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VHDL Model in Xilinx ISIM | Cypress Semiconductor

VHDL Model in Xilinx ISIM

Summary: 1 Reply, Latest post by aju on 17 Nov 2011 11:13 PM PST
Verified Answers: 0
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davekepley's picture
1 post

I am attempting to simulate a cy62157ev30 interface coded in verilog and using the VHDL model provided by Cypress.  I will attach an image of the module (mobl_512kx16) waveform in simulation.  I am not sure what I am doing or if it is a software problem with the simulator, but I would appreciate it if someone could look at the timing (behavioral logic) and see if I am doing something wrong -- this is a write cycle...   I am not sure why the data_skew is undefined.


aju's picture
Cypress Employee
14 posts


Can you please open a Support case on for this issue. This will ensure a faster response and more personalized level of support.



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