Power Down mode in MoBL SRAM | Cypress Semiconductor
Power Down mode in MoBL SRAM
I am using a CY62157ESL MoBL SRAM connected to a Xilinx Virtex-5 FPGA. There will be a power down condition when the FPGA is not powered and the SRAM is powered by 2.5V. I need to have a very low, known current draw by the SRAM in this mode. I am buffering the CE_N pin to ensure a VCC level. What should I do with the other pins. The data sheet implies they all need to be at the VSS or VCC rails, so do I need to use a resistor at each pin to ensure this. I could put 60K resistors to the FPGA 2.5V, which would pull down the pins in the power down mode. What is recommended?