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ASYNC SRAM: Address pin mapping | Cypress Semiconductor

ASYNC SRAM: Address pin mapping

Summary: 1 Reply, Latest post by cledwith on 15 Apr 2014 04:53 PM PDT
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lsen's picture
Cypress Employee
22 posts

For your ASYNC SRAM, the datasheet doesn't identify address bit numbers (all address pins are identified as just "A"). what is the address bit number to package pin number mapping?


Since the ASYNC devices doesn't have an internal burst counter, the address numbering for Async SRAM's does not matter. 

The pins can be connected in any way such that the routing is made simple. 

The following link has the details-

cledwith's picture
4 posts


I'm about to upgrade (and increase) a memory in one of my boards.

I'm using a CY7C199D-10VXI (32Kx8) and I want to increase the memory to 64Kx8, but I can't found it, so I decide to use a CY7C1009D-10VXI (128Kx8).

If I want to modify the board the less possible, I'll need to not take care of the numbers of the addres, because both memory seems to have almost the same pin configuration but with very different address lines.

Do I have total freedom to change the address of this new memory ? I really think that it is ok, and when I read this post I confirmed it. But because the data sheet is numbering the addres, I want to be really sure.

Apart from that, why there is no any SRAM memory with 64Kx8 ?

Best Regards,


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