Static timing analysis - Cypress.com Forums http://www.cypress.com/? Re: Static timing analysis http://www.cypress.com/?rID=57937 Another interesting aspect is: when I change the device to a PSoC3 the timing analyse runs fine!

Bob

 

 

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Thu, 05 Jan 2012 10:14:07 -0600
Re: Static timing analysis http://www.cypress.com/?rID=57927 This look really strange. When I open the timing analysis result (just double click on the 'notice list' entry, one can see that the error lies within the counter component. dclk1 is connected to the count input, and CyBUS_CLK comes from the clock input.

The 'ClockBlock' component mentioned in the warning seems to be something PSoC creator internal. I don't find any component containing it...

 I was able to solve this by syncing both clock and count input of the counter component, though this seems unnecessary. Both are derived from the same clock (at least I tested it that way - have them both generated from MASTER_CLK). Seems like a routing bug to me...

 

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Thu, 05 Jan 2012 07:32:13 -0600
Re: Static timing analysis http://www.cypress.com/?rID=57910 Hi Bob.

 

Find attached.

 

 

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Thu, 05 Jan 2012 02:51:33 -0600
Re: Static timing analysis http://www.cypress.com/?rID=57874 I re-built your project, but I didn't get the error. And my Counter-module (v2.10) is watermaked with "Prototype".

Can you please strip down your project, build, clean, archive (minimal) and finally upload your project to have a look at it.

Bob

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Wed, 04 Jan 2012 11:33:26 -0600
Re: Static timing analysis http://www.cypress.com/?rID=57867 Hi

I have implemented the SYNC block as per the previous recomendations and I have no build errors but a timing violation warning which is affecting the way my PWM modules are being cloocked and hence run. The warning is as below and find attached the Static Timing analysis log.

 

Warning-1350: Path(s) exist between clocks ClockBlock/dclk_1 and CyBUS_CLK, but the clocks are not synchronous to each other: (ClockBlock/dclk_1, \Counter:CounterUDB:sC16:counterdp:u1\/ci)

The static timing analyzer reported a warning. See the warning message for details. Additional information may be available in the timing report file.

 

Any idea on how i can get over this?

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Wed, 04 Jan 2012 07:49:39 -0600
Re: Static timing analysis http://www.cypress.com/?rID=57866 Hi

I have implemented the SYNC block as per the previous recomendations and I have no build errors but a timing violation warning which is affecting the way my PWM modules are being cloocked and hence run. The warning is as below and find attached the Static Timing analysis log.

 

Warning-1350: Path(s) exist between clocks ClockBlock/dclk_1 and CyBUS_CLK, but the clocks are not synchronous to each other: (ClockBlock/dclk_1, \Counter:CounterUDB:sC16:counterdp:u1\/ci)

The static timing analyzer reported a warning. See the warning message for details. Additional information may be available in the timing report file.

 

Any idea on how i can get over this?

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Wed, 04 Jan 2012 07:46:57 -0600
Re: Static timing analysis http://www.cypress.com/?rID=57801 What BOB has told is absolutely correct. 

You can as well read this blog post by Brad Budlong to better understand the need for a SYNC component, http://www.cypress.com/?rID=48686&cache=0  . 

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Mon, 02 Jan 2012 00:49:01 -0600
Re: Static timing analysis http://www.cypress.com/?rID=57782 That's a rarther easy one:

Sync is a three terminal module: a clock to synchronize with (inyour case should be the bus-clock,

a clock signal to synchronize (dont know the name here)

an output resulting in a synchronized clock which you should connect to your module(s)

So: the Sync-Module is placed BETWEEN the unsynchronized signal and the module where the unsynchronized signal was originally connected to.

Still need an example?

Happy New Year!

Bob

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Sun, 01 Jan 2012 04:46:12 -0600
Re: Static timing analysis http://www.cypress.com/?rID=57781 Hi

 

 Do you have any example project how the sync can be implemented. I have looked on the site and i seem not to find anything.

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Sun, 01 Jan 2012 03:55:11 -0600
Re: Static timing analysis http://www.cypress.com/?rID=57765 Hi Maduna,

 

The Clock Summary Section shows that frequency violation has occurred in CyBUS_CLK.

Did you use the "Sync" component available under the "System" section in the component catalog?

It can be used to synchronize the clock to bus clock.

 

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Sat, 31 Dec 2011 07:01:07 -0600