ADC SAR low SPS issue - Forums Re: ADC SAR low SPS issue Muxing is the way to go. Primary concern with a mux is when channel is changed to allow mux

output to settle. This is because of mux Ron x Cstray and Cgd and Cgs charge injection into output

of mux from gate switch signal.

Also use of one SAR conserves Pdiss, code space, and resources for other uses.

Here is a generalized ap note on switches and muxes -

Regards, Dana.


Tue, 12 Jun 2012 05:06:38 -0600
Re: ADC SAR low SPS issue In free-running mode, that will not work as you expect. Use the triggered mode an set up a PWM or timer to trigger your ADC with the right frequency. When done, use the EOC with an interrupt to get woken up to retrieve the converted value or use a DMA to store them wherever you like, because at low conversion frequencies you'll waste all your MIPS when you poll for the result ready.



Tue, 12 Jun 2012 04:39:09 -0600
Re: ADC SAR low SPS issue I also have the same problem.I really want to use low SPS,but in Free Running Mode it seems can't realize.

Mon, 11 Jun 2012 21:30:24 -0600
Re: ADC SAR low SPS issue It is saver to do the following with the current counter

if (++currentCounter >= 100)
  currentCounter = 0;

Thu, 10 Nov 2011 18:01:07 -0600
Re: ADC SAR low SPS issue You can use a fast ADC for slow sampling. Your ADC just finished faster.
Here is a simple c program to do this.
Note: You should consider what to do before the first 100 samples were
read. But that's is another problem.

void timer_interrupt (void)
 // interrupt every 3.3ms */
 /* all ADC are triggered mode */
 read ADC1;
 save reading to ADC1_data[counter];
 start ADC1 conversion;

 read ADC2;
 save reading to ADC2_data[counter];
 start ADC2 conversion;
 read ADC3;
 save reading to ADC3_data[counter];
 start ADC3 conversion;

 if (++currentCounter == 100)
  currentCounter = 0;


/* global variable */
uint8 currentCounter = 0;

void main(void)
 uint8 oldCounter = 0;

 /* init routine */
 while (1)
  if (oldCounter != currentCounter)
   oldCounter = currentCounter;
   /* do the averaging here */

Thu, 10 Nov 2011 16:41:58 -0600
Re: ADC SAR low SPS issue  


Hi all,

Thanks, for the replies. The reason to use a low SPS is that I want to fill a continuous buffer (FIFO type) with the result of the ADC, so I can apply a filter to it. And due to limitation of the resources in the design (there won’t be enough memory to fill the buffer for let say 30 sec at 55k SPS) I want to reduce the SPS rate. I do not need the high SPS, and I need 3 channels. I prefer not to use MUX for switching between the channels, and use 100% of the ADCs available in the PSoC 5 instead (2 SAR ADC and 1 delta Sigma (DS) ADC). I read that multiplexing would cause me a lot of troubles if I use it on a DS ADC.  So the final configuration would be 3 ADCs (running at low rate – I need only about 100 SPS from each – my signal is between 5 and 15 Hz, but could go higher if I have to) filling 3 FIFO buffers. Due to limitations in the PSoC 5 architecture, I cannot use 3 DFB because I have only one DFB with 2 channels, and multiplexing may not work with the DFB. So I will apply software low pass filters on each buffer before continuing with the signal processing.

I can still put a timer and trigger an interrupt every 10 ms and get the result from the ADC. I am not sure how "correct" this approach would be.

Another approach would be to use a variable (double or long int) and sum the output of the ADC at 55k SPS. Then every 10 ms to get the result and divide it to 550 or so, and thus getting an average of this samples. this average would be my input for the FIFO buffer.

Either approach will take some processing and developing time, I usually prefer simplistic approach.

Could you please advise on this! Any help would be greatly appreciable.



Thu, 10 Nov 2011 11:30:06 -0600
Re: ADC SAR low SPS issue Hi Stoyan,


Is there any specific reason why you want to sample at 300 SPS?

Are you using interrupt after every conversion to read the ADC data? If so, you can sample it at any higher permissible rate and give a 300Hz clock to "soc" terminal of the component. For this, the "Sample Mode" should be set to "Triggered".


Connecting an external clock of 5.4kHz to the ADC component might not be a good idea.

Tue, 08 Nov 2011 04:23:11 -0600
Re: ADC SAR low SPS issue Don't use the ADC in continous mode, just do a AD conversion every 3.3mS

Mon, 07 Nov 2011 23:26:30 -0600