How To Debug a Verilog component which uses Cypress "extensions" - Cypress.com Forums http://www.cypress.com/? Re: How To Debug a Verilog component which uses Cypress "extensions" http://www.cypress.com/?rID=48801 Hi Robert,

 

As Gautam told, it is not so easy to debug codes written in Verilog. But you can take out those signals and use Status registers externally to see the functionality. But if it is more of timing issues, then better use Modelsim to simulate.

 

Regards,

Kishore.

]]>
Tue, 15 Feb 2011 11:23:10 -0600
Re: How To Debug a Verilog component which uses Cypress "extensions" http://www.cypress.com/?rID=48646 Hi Robert,

 

The files with .v extension can be tested on simulators like Modelsim.

But the Datapath implementation which is used in the creation of components like UART cannot be tested on the simulators. Equivalent verilog code can be written to perform the datapath's operation which can be simulated.

Test bench has to be written to provide the inputs and necessary clock.

Other freeware such as ICARUS can also be used for the purpose of simulation. Do make sure that the syntax of the verilog code matches with that of the standard.

 

If Debugging of the verilog code can be done, then a symbol can be created for the component, with required pins. The project containing this component can be executed in "debug" mode and output can be probed from the pins on the oscilloscope.

Control Register data can be used as clock by toggling appropriately. 

 

Regards,

dasg

]]>
Tue, 01 Feb 2011 06:31:59 -0600