Missing SPI Bit - Cypress.com Forums http://www.cypress.com/? Re: Missing SPI Bit http://www.cypress.com/?rID=47357 The SPI Master component does not work properly. I spent a _whole lot of time_ debugging this with an oscilloscope, and finally made my own SPI master with Verilog. However, that component could not write into a Control Register! I will try DMA next. Anyway, I suggest that you try older versions of the SPIM. At least I was able to get some functionality out of v1.20.


Below are some bugs I have discovered:

SPI Master v2.0

1) The reset-input has no functionality
- I/O-reset is not possible, control register reset is not possible:
Error: mpr.M0093: The datapath, \SPIM:sR16:Dp:u0\, is using the routed reset feature which is not available in this revision of the device. (App=cydsfit)
- The prototyping platform (001) reset button will reset the SPI Master but also render all control registers unwriteable.

2) The UI setting for the internal clock does nothing, the SPI output clock is always 12MHz. This problem can be bypassed by writing directly to the clock divide register with SPIM_IntClock_SetDivider(). However, only a few divider values are accepted.

3) The component writes some garbage to the bus (a single 1-bit if I remember correctly) before the first actual word gets transferred. The prototyping platform (001) reset button removes this malfunction, but also renders all control registers unwriteable.

4) Consecutive bus writes with no delay in between them do not work. This problem can in some cases be avoided by using a longer wordlength, i.e., writing two or more words on one bus cycle.

SPI Master v1.20

1) RX and TX buffer sizes larger than 4 do not work.

Tue, 07 Dec 2010 13:45:09 -0600