Important specifications:

Supply Voltage: 5V

Accuracy: +/-0.25%

Total error band: +/-2% FSS

Sensor Operation:

This sensor has an amplified and temperature compensated output and is driven by a voltage supply. The output curve and equation are shown below.

Design:

The design is very simple as both amplification and temperature compensation are done within PSoC.  Resolution should be 1/1000th of full scale, hence a 10-bit ADC is required. The sensor output voltage goes to 90% of the supply voltage, so the ADC range should be vssa vdda. The ADC should operate with the rail-rail buffer enabled. Sensor output is ratiometric and the ADC reference should be Vdda/4.

PSoC Top Design and ADC configuration:

Although not as many analog resources are required when interfacing a pressure sensor with an amplified output, integrating a sensor with other PSoC features such as capsense, segment LCD drive and communication protocols, etc, will lower overall system costs.

Conclusion:

PSoC3 and PSoC 5LP can sense pressure accurately while reducing BOM cost and board space by integrating the analog front-end, ADC, reference and MCU. PSoC ADC inputs can be multiplexed with many inputs (limited only by the GPIO count) allowing interfacing to multiple pressure sensors or other analog sensors. The PSoC Creator design environment makes it easier for you to design and debug, reducing the design time and your time to market.

By Praveen Sekar

Supply current = 1.5 mA

Pressure Range:  0 -15 psi (Gage)

Sensitivity (max): 10 mV / psi

Sensitivity (min): 5 mV / psi

Temp error - span (max): 0.5 % FSS

Offset (max): 2 mV

Temperature error - offset: 0.5% FSS

Specified temp range: -40 to 125 °C

Bridge resistance (max): 6.4 k (50°C)

Accuracy: +/-0.1 % FSS BFSL

Sensor Operation:

The sensor is a piezo-resistive sensor excited by a current and has an output voltage proportional to the pressure and the current. The output voltage has a 50% tolerance and the sensor provides a gain set resistor to calibrate it to 1%. When the sensor is excited by proper current excitation levels specified in the datasheet, the temperature coefficient of span and offset will cause only a very small error in the final measurement (temperature compensated).

Design:

The design requires an excitation current of 1.5mA and an ADC to measure the output voltage. With a bridge resistance of 6.4k (max) and excitation current of 1.5mA (current level prescribed in the datasheet for proper temperature compensation), the load voltage of the current source is 9.6V. This means PSoC IDAC cannot directly be used for supplying bridge current because of very high load voltage. To limit external components and get maximum value out of PSoC we can use circuit below.

By controlling the V_GS of this circuit, the I_D can be controlled. V_GS is controlled by changing the current of the sinking IDAC. R_B ensures the IDAC output voltage is within compliance and optimum. The current sense resistor (0.1%), R_SENS,aids in setting the current to 1.5mA. The voltage across R_SENS is read by PSoC ADC (0.2%) and the IDAC current is adjusted until I_D becomes 1.5mA. With this circuit, we can ensure that the current is accurate to 0.3%. A current accuracy of 2% is the requirement so the temperature error due to offset and span are within datasheet limits.

Sensor Common mode output voltage:

With this design the sensor common mode output voltage is given by;

(1.5 * 6.4)/2 + 0.150 /2 + (1.5mA * 0.05)/2 = 4.8 + 0.075 + 0.0375 = 4.91 V

Here, 1.5mA is the sensor current, 6.4k is the max bridge resistance and 0.150 V is the maximum span, 0.05 is the sense resistance.

The sensor common mode voltage is very high to directly feed into PSoC. The ADC with input buffer can accommodate only to within 200 mV of Vdda. The ADC without buffer can t be used because it has low input impedance. The PGA can allow input voltage all the way to the voltage rail, but we ll be limiting the design to supplies with very strict tolerance levels. This is not desirable as various designers might want flexibility in their power supply design (at least support 5% supplies).

Hence to lower the common mode voltage we can use a charge pump that generates a negative voltage. The generated voltage is about -3V using a negative charge pump. The ripple voltage (of <10%) on the charge pump output doesn t have a major effect as long as we set the ADC input sampling frequency as an integral multiple of the ripple frequency (the charge pump clock frequency).

ADC input range:

The sensor span is 150mV (max). The ADC input range should be > +/- 0.256V.  

Resolution:

Resolution required in 1/1000^th of full scale. At minimum span of 75mV, we require 75uV of voltage resolution. At 15-bit level, the ADC resolution is 64uV. With a gain of 4, the ADC resolution is < 16uV.

At +/-1.024V range, we require 15-bit resolution

At +/-0.256V range, we require 13-bit resolution

Reference:

This measurement requires an absolute reference. The final pressure accuracy depends on the reference accuracy, therefore the internal 1.024 V reference is a good choice.

The ADC has four channels:

0.  Sense resistance channel: This channel is used to set the current to 1.5mA

1.  Sensor Channel: Senses the sensor output

2, 3.  Calibration channels: Measures the gain set resistance for calibration

The IDAC has two channels:

1. Passes current through the calibration resistance

2. Passes current through the sensor

The ADC configuration for the pressure sensing channel is shown below.

Pressure Equation:

The pressure is computed from the measured voltage using the following equation.

P = A* (V_o / S_i) * P_r

P Pressure (in psi)

V₀ Bridge output voltage in mV

S_i Span of pressure sensor output in mV

P_r Rated Pressure (in psi)

A I/1.5. I is the actual current flowing into the pressure sensor

Calibrations required:

Span Calibration:

The Span of the pressure sensor is calibrated using the gain set resistance provided in the sensor. Using the gain set resistance, r, the span can be calibrated. The gain set resistance is trimmed such that when it s used in conjunction with a differential amplifier, it ll give a 2V span. Working the equations back, you can find that the gain set resistance.

r = (2 * Rf * Si)/ (So Si)

Here, Rf is feedback resistor of the differential amplifier, Si is the span of the pressure sensor output (differential amplifier input) and So is the span at the differential amplifier output. By looking at the datasheet of the part, Rf and So can be found. For MEAS 1210, Rf = 100k and S₀ = 2V.  By measuring r, we can find the span,

S_i = 2/(1 + (200/r))

Performance measures:

Offset:

The sensor has a 2mV offset (max). This can be calibrated out to zero.

Span error:

The gain set resistor can provide an interchangeability accuracy of 1%. In addition, the gain set resistor can be found with 0.1% accuracy only (limited by calibration resistor accuracy. If the calibration resistor is very accurate (0.01%) or calibrated, then the span error will be 1%.

Temperature Error offset:

This has a maximum error of 0.5% FS. This is 0.075 psi.

Temperature Error span:

This has a maximum error of 0.5% FS. This is 0.075psi.

Pressure non-linearity + hysteresis:

Together they contribute 0.15% FS. This is 0.022 psi.

Signal Chain:

Offset error:

The offset error of PSoC ADC is <100uV, which can be cancelled by Correlated Double Sampling (CDS).

Offset drift:

Offset drift of PSoC is 0.55uV/°C. At 50°C, this is 11uV. It is 1/7^th of minimum resolution (0.015psi). It can be cancelled by Correlated Double Sampling (CDS).

Gain error:

PSoC ADC s calibrated accuracy is 0.2%. There are 2 measurements, 1 voltage measurement and 1 current measurement (current set to 1.5mA). This can contribute to 0.4% error in total.

Gain drift:

Drift is 50 ppm/°C. For 25°C change, it ll be 0.125%.

List of all errors:

PSoC Value:

Apart from integrating the analog front end, ADC, 0.1% precision reference, Op-Amp, IDAC and the MCU and providing a separate channel for accurate temperature measurement, PSoC can integrate miscellaneous features suchascapsense, segment LCD drive and communications protocols. Designing with PSoC creator reduces the design time considerably. The BOM cost and board size can also be significantly reduced.

In the next part we ll see how to interface unamplified compensated pressure sensor with PSoC3.

By Praveen Sekar

www.cypress.com/go/programming

Many customers choose to purchase PSoC devices through a Cypress partnered distributor. These distributors will often support programming services for customers. Customers will be able to purchase devices and have those devices programmed prior to delivery or manufacturing. Since our distributors provide these programming services we have ensured that we are working with mutual third party programming companies in order to ensure timely support for our customers. Distributors often support multiple programming vendors for their programming services. We work to ensure that we have qualified at least one programming vendor for each of the Cypress distributors.

www.cypress.com/?app=distiInventory&source=buy

If one has questions or requires additional device support please file a tech support case so that your request can be expedited.

www.cypress.com/go/support

Supply voltage = 5V

Pressure Range:  0 -15 psi (Gage)

Sensitivity (max): 6.9 mV / psi (25°C)

Sensitivity (min): 3.3 mV / psi (25°C)

Temp Coefficient of sensitivity (max): -3.8 %

Offset: 35.6 mV (50°C)

Temperature coefficient of offset: 1.5%

Specified temp range: -40 to 125 °C

Bridge resistance (max): 5.9 k (50°C)

Accuracy: +/-0.25 % FSS BFSL

Sensor operation:

This type of pressure sensor is a piezo-resistive sensor (Wheatstone s bridge) driven by a voltage supply. The bridge output voltage is directly proportional to the applied pressure and the supply voltage. The primary sources of error to be factored in while designing with this type of sensor is the sensor offset error, span error and temperature coefficient of span and offset (since the sensor is temperature uncompensated, temperature coefficient of span and offset play a major role in the final error).

Design:

The design parameters of concern are the ADC resolution, input range and reference.

ADC input range:

This parameter is dependent on the maximum voltage output, V₀, from the pressure sensor. At 5V supply and using the maximum offset and sensitivity possible, we get;

V₀ (max) = 6.9 * 15 + 35.6 = 139.1 mV

ADC input range should be greater than +/-0.256 V.

Resolution:

1/1000^th of the full scale resolution is sufficient in pressure sensing applications.

Pressure resolution = 15 psi/1000 = 0.015 psi

Voltage resolution = 49.543 mV/1000 = 49.543uV

This requires a 16-bit ADC in +/-1.024V range or 14-bit ADC in +/-0.256V range.

Reference:

A ratiometric reference should be used in this case. Hence PSoC reference should be configured for internal vdda/4 , where vdda = 5 volts.

PSoC Creator Top Design:

The ADC has three channels, one for sensing pressure and the other two used for temperature measurement. The RTD temperature is measured as described in AN70698.  ADC configuration for the pressure sensing channel is shown below.

Note that +/-Vref/4 range can also be used for this configuration in 14-bit mode.

Pressure Equation:

From the measured ADC voltage, the pressure is calculated from the equation below;

P = (V_o / S) * P_r

P Pressure (in psi)

V₀ Bridge output voltage in mV

S Span in mV

P_r Rated Pressure (in psi)

Calibrations required:

Room Temperature calibration:

Since span has a very high tolerance, we have to calibrate span before using it. Pressure sensor offset should also be calibrated before use.

Offset Calibration:

Offset of the pressure sensor has to be corrected by giving a zero pressure input and measuring the ADC output voltage, V_off.

V_off  = V_offp + V_offs

V_offp Pressure sensor offset

V_offs signal chain offset

Span/Gain Calibration:

The span of the pressure sensor is calibrated by applying a full scale pressure input to the pressure sensor and measuring the ADC output voltage, V_fs.

S = V_fs

(Where S is the Span)

By doing span calibration we are calibrating both the span error of the sensor and gain error of the ADC.

Temperature calibration:

Both the pressure sensor offset and span varies with temperature and they have to be calibrated. But the sensor datasheet doesn t provide information on the span or offset calibration. It provides only the limits of the error. If the characteristic curve is found by experiment, we can correct for both span and offset temperature coefficient accurately.

List of all errors:

*Note:  Assumes calibration source has zero error.

ADC INL and the sensor non-linearity are the only factors that can t be calibrated and will affect the final measurement.

PSoC Value:

Apart from integrating the analog front end, ADC and the MCU, providing a separate channel for accurate temperature measurement, PSoC can integrate miscellaneous features suchascapsense, segment LCD drive and communications protocols. Designing with PSoC creator can reduce the design time considerably. The BOM cost and board size can also be significantly reduced.

In the next part we ll see how to interface unamplified compensated pressure sensor with PSoC3.

By Praveen Sekar

In this four part series, piezo-resistive pressure sensing basics and the PSoC circuits for three types of pressure sensors will be examined. The first part covers piezo-resistive pressure sensor basics and introduces three categories of pressure sensors

Piezo-resistive Pressure sensor basics

 A piezo resistive pressure sensor has a silicon diaphragm whose resistance depends on its tension. The diaphragm undergoes tension whenever there is a pressure. It can be modelled by a Wheatstone s bridge where all the resistors change with pressure. When pressure is applied to the diaphragm, resistance of the two arms (diametrically opposite to each other) increases and the resistance of the other two arms decreases.

 Pressure sensor equations

 The change in resistance can be converted to voltage by voltage or current excitation. The equations involved in voltage and current excitation are shown below.

Voltage Excitation Mode:

In this case, the Wheatstone s bridge is excited by a voltage. Span is defined as the bridge output voltage for rated pressure (full pressure). Span( S) is given by

S = V * R/R

R Change in resistance for rated pressure

R - Bridge resistance

V Excitation voltage

R = P * P_s

P Rated Pressure

P_s Pressure sensitivity (Change in resistance for unit change in pressure)

P_s = R * k

k - Normalized pressure sensitivity i.e. Pressure sensitivity for 1ohm resistor

S = V * P * k

Span is independent of bridge resistance. The temperature coefficient of span primarily results from the temperature coefficient of pressure sensitivity which is dependent on the diaphragm material.

Current excitation:

In this case, the bridge is excited by a current source. In this case span is given by,

S = I * R * P * k

Where I is the excitation current.

In this case, the span depends on the current source and bridge resistance.  

The temperature coefficient of span results from the temperature coefficient of resistance and the temperature coefficient of pressure sensitivity.  By proper design, the two can be made close to each other. Hence current excited pressure sensors have the design advantage of tweaking the process parameters so as to reduce the effect of temperature on span.

Pressure sensor types

The pressure sensor span is generally around 50-150mV. Depending on whether the pressure sensor output is amplified and on whether the pressure sensor is compensated for temperature variations of span and offset, we can have the following categories of pressure sensors

1. Unamplified uncompensated pressure sensors
2. Unamplified compensated pressure sensors
3. Amplified pressure sensors/transmitters.

The next three parts explains interfacing each type of pressure sensor with PSoC and the system performance measures.

By Praveen Sekar

Anyway, it is impossible for your microcontroller to always have every serial interface that may come along.  For example, I read about a string of 50 Christmas lights that had red, green, and blue LEDs in each bulb and here comes the best part, each bulb is addressable.  Yes, you can control each individual bulb for color and intensity, four bits for each color (red, green, and blue) and 8 bits for intensity.  Of course the string of lights came with its own controller that could generate 12 different patterns, but I wanted to create my own patterns.  With a little Google searching I found that someone had already hacked the asynchronous protocol and bit-banged an IO port to control the lights with some microcontroller.  Nobody had actually created hardware to make this easier or less CPU intensive, you know why? Because nobody else used a PSoC3 or PSoC5 with their powerful UDBs!  Yes a PSoC3/5 can bit bang with the best of them, but why bother when you have extremely flexible hardware, plus bit banging is so 90's. 

The protocol was a 26-bit packet with one start and three stop bits. Each data bit was divided into three 10uS periods.  The first period is always low, the second period was low if the data was a 1 and high if the data bit was a 0 .  The last period is always high.  See images below for bit and packet formats.

The packet format is pretty straight forward with the address, brightness level and three colors packed into 26 bits.  See figure below.

I had a choice, be lazy and use a 32-bit wide shifter or use a single 8-bit wide shifter with a slightly more complicated state machine. The 32-bit wide implementation would be easier but would be a bit wasteful in hardware.  The 8-bit wide implementation would take a bit longer, but much more efficient. I choose to go with the 8-bit wide design.  One other nice feature in the UDBs, is that you can create two 4 byte FIFOs for data flowing into or out of an interface.  This turned out to be perfect since it took 4 bytes to transfer the full 26-bit packet.

The string of lights is 50 bulbs long and if you want to update all the bulbs at one time, it would take 200 bytes (50 bulbs * 4 bytes per packet). Since you don t want the processor to just sit and wait for an interface to move data, DMA is the perfect solution. This way I was able to update the entire string using DMA with almost no CPU overhead!  Where the other guys are wasting their CPU cycles toggling bits, the CPU in the PSoC could concentrate on generating cool interactive patterns, converting DMX commands to the light string format, or any other task.  What is even better, I could implement 8 of these interfaces in a single PSoC3 or PSoC5 at the same time.  

Making this interface into a PSoC Creator component, provides a way to setup all the hardware and DMA with a single start command as with all Creator components.  More APIs are added to generate cool lighting patters.  The video below is an example of version 1.0 controlling three strings of light on my house.

This second video shows four strings on the floor in our lunch room.

This third video demonstrates yet another use for the lights.

Just think of the possibilities interfacing a string of lights to anything that can be measured with a PSoC!

Here are a few other images of the actual box the string came in, the string that I modified, my interface board, and a close up view of one of the bulbs.

Stay tuned for an upcoming video with the details of what it took to make the lighting component and how easy it is to interface the string with the Cypress PSoC3 First Touch Kit.

Mark Hastings

I2C, I2S, LIN, SM Bus, SPDIF, SPI, UART, Counters, CRC generator, Glitch filter, Quadrature Decoder, Shift register, Timer, Logic gates, Flops, Digital multiplexers and de-multiplexers, control and status registers, etc. 

You get the picture, but what is currently in the library is by no means the limit of what can be created.  Recently I sent an email to our application and field application engineers and asked what they had created with UDBs.  Here is a list of some of the components people have created with PSoC UDBs.

• 60Hz Grid Lock PLL
• Numerically Controlled Oscillator (Used for DDS)
• Forward Error Correction (FEC) decoder
• No clock stretch I2C slave
• Simple components (8bit adder, PWM, digital compares etc )
• Complex Counters 
• ADC mux sequencers
• Holiday Light controller
• Square root calculator
• First order IIR filter
• Hardware state machines
• Delta sigma modulator
• UDB discrete Fourier transform
• Byte packer (sticks two 12-bit values into 3 bytes for RF transmission)
• 7-Segment Display controller
• Remote control servo controller
• Manchester Encoder/Decoder
• 1-Wire communication interface
• ClipDetect,  Monitors 16-bit audio and over rides output if value exceeds a certain limit.
• Audioclkgen,  Creates a factional N reference for the on-chip PLL.  Used in digital audio designs.

Notice that this list contains some pretty weird stuff that you would never find standard in any microcontroller.  You won t even find most this stuff in the standard PSoC Creator library, yet!  The point is, that it doesn t matter.  You can create your own  custom interface or component, that makes your project unique without adding extra external glue logic or a CPLD.

Cypress does have a Community Components page where people can post any component they have created.  Unfortunately it has been a very well kept secret until now.  Do yourself a favor and check out the Community Components page.

Also, if you want to get more training on creating components, read the app notes I mentioned above or look at the community components guidelines on this this page.

If you have created a cool component (or even a weird one), don t be afraid to share it with the Cypress community for your 15 minutes of fame. 

By Mark Hastings

It used to be with creating host applications for a computer, you only needed to create one application for Windows. In today's world, operating systems such as Mac OS X and Linux are growing in popularity. Additionally, mobile devices running Android are increasing in numbers with the continuous  production of smart phones and tablets. With so many different operating systems available, the need for cross platform functionality is ever so more important.

What if I told you there was a way to develop a PSoC 3 or PSoC 5 application to easily stream general data across USB and provide the foundation for cross platform functionality?  Using the Human Interface Device (HID) class makes this possible. Yes, the same class that is used for mice and keyboards is breaking free from the stereotype that it is limited to a device that requires some form of human interface, such as a button press, to function.

The truth is that the HID protocol provides the perfect foundation to shuttle data back and forth between a PSoC and computer, in applications where high speed data transfer is not required. Best of all is that implementing a generic HID on PSoC is easy to do and creating Graphical User Interfaces (GUIs) on various operating systems such as Windows, Mac OS X, and Linux is fairly straightforward.  AN82072: PSoC 3 / PSoC 5 USB General Data Transfer with Standard OS Drivers will guide you through all the steps required to do so. You will have your PSoC streaming data to a host operating system of your choice in no time! 

You can download this application note from the following link.
AN82072 - PSoC® 3 / PSoC 5 USB General Data Transfer with Standard OS Drivers

By Robert Murphy

1.       SMBus and PMBus

These complete Cypress power supervision portfolio for PSoC 3 and PSoC 5, by adding SMBus and PMBus slave communication capability to PSoC. Learn more about PSoC Power Supervision solution at http://www.cypress.com/go/PowerSupervision.

2.       Debouncer

This is probably going to be the most-used component out of all six new releases because it is the easiest and best way to debounce and edge-detect switch inputs to your system, without using your CPU.

3.        Glitch Filter

The hardware glitch filter removes unwanted pulses from a digital signal, and is a frequently used function in digital designs. The Glitch Filter v2.0 is a complete re-design from its previous version which was available as a PSoC Creator concept component.

For more information on switch-debouncing and glitch-filtering, see AN60024.

4.       RTD Calculator

5.       Thermistor Calculator

6.       Thermocouple Calculator

These three new components add easy-to-implement temperature-sensing capability to PSoC Creator s component library. Find out more about temperature-sensing with PSoC 3 and PSoC 5 through the suite of application notes available:

·         AN70698 - Temperature Measurement with RTDs

·         AN66477 - Temperature Measurement with Thermistor

·         AN75511 - Temperature Measurement with Thermocouples

In addition, you may be interested in:

·         AN60590 - Temperature Measurement Using Diode

·         AN65977 - Creating an Interface to a TMP05/TMP06 Digital Temperature Sensor

CP4 also provides an update to the I2C Master/Multi-Master/Slave component, with the addition of an I2C bus multiplexing feature, besides for some minor tweaks.

I have already installed CP4 on my system especially for the debouncer. Many of you may want one or more of these new components, or the more robust I2C. To get all of these, please download Component Pack 4.

The Constants component is a very simple way to display constants used by the firmware on the schematic.  Also this allows you to change firmware parameters without changing actual source code.  I have created an example component that allows the user to assigns names and values to up to four constants.  The component consists of just a symbol and a header file. Below is what the component would look like on the schematic.  The four constants have already been assigned names, DEBUG, LOOP, DELAY, and COUNT, as well as values.

Figure 1 Example Project Constants Component

The configuration is very simple.  The user simply assigns a name and value.  The header file is automatically generated.  The constants defined below will have the instance name pre-pended on the name.  For example, the LOOP constant name will be MyConstants_LOOP .

Figure 2 Configuration dialog of Project Constants Component

The generated header file would look like this using the configuration in Figure 2.

 #defineMyConstants_DEBUG   0

#defineMyConstants_LOOP   100

#defineMyConstants_DELAY   95

#defineMyConstants_COUNT   5

 

The constants can then be used throughout the firmware, just by including the MyConstants.h header file.  Below is an example of a code snippet that makes use of the constants provided in MyConstants.h.

 for(i = 0; i < MyConstants_LOOP; i++)

{

      LCD_Position(1,5);  
   
      LCD_PrintHexUint8(i);

      CyDelay(MyConstants_DELAY);

}

   

The same concept could be used for user created components for a specific application. For example a project phase component that displays on the schematic whether the project is in the release or debug phase.  The header file would contain the #define statements for the different mode.

Figure 3 Project Phase Component

Other similar components can easily be generated by the user, with just some simple basic knowledge of how to create components. For example if you wanted a waveform generator to change the waveform without changing code.

Figure 4 Application Mode Example

The header file would contain the following:

 #defineAppMode_Mode     2

#defineAppMode_SINE     0

#defineAppMode_SQUARE   1

#defineAppMode_TRIANGLE 2

 

The firmware would look at the AppMode_Mode constant to determine which waveform to generate, requiring no code changes.

This is just one simple trick to make a project more flexible and easier to change its operation without editing code.  It is also a good way to demo an application to a customer.  The user can then try different operations without editing code.  The MyConst component is generic and can be used with any project.  The ProjectPhase and AppMode components can easily be created by the user in a matter of minutes.

By Mark Hastings

Do you want to use the Programmable Logic Device (PLD) capability of PSoC, and don t know where to start? Or need to create your own custom digital components in PSoC Universal Digital Blocks (UDBs)? Then look no further.

AN82250: PSoC® 3 and PSoC 5 Implementing Programmable Logic Designs An Introduction provides you with an ideal start towards digital mastery with PSoC UDBs. By introducing the PLD architecture, and then walking through an example project, AN82250 teaches you how to create Verilog components in PSoC Creator. For those interested in advanced features of PSoC PLDs and PSoC Creator, these are touched upon in the additional reading material in the appendices.

This application note is actually the second of a three-part series of application notes written to help you learn and exploit PSoC s powerful digital capabilities. This series begins with the introductory AN81623: Digital Design Best Practices, continues with the PLD-centric AN82250, and culminates with the datapath-focused AN81256: Designing PSoC Creator Components With UDB Datapaths.

After reading AN82250, you will be able to implement moderately complex PLD-based components in PSoC Creator. AN82250 also provides a good gateway to building more complex Datapath-based designs dealt with in AN82156. So what are you waiting for? Download AN82250 now!

By Antonio De Lima Fernandes

AN82156 - Designing PSoC Creator Components With UDB Datapaths

Have you ever wondered how PSOC Creator manages to pack so much functionality into its components? Chances are the component uses the UDBs in PSoC 3 and PSoC 5 to perform calculations, comparisons, and data management.  The "secret sauce" in the UDBs is the datapath - a configurable 8-bit ALU designed to offload tasks from the CPU. The datapaths, when chained together across UDBs and/or combined with PLD logic, are powerful tools to have at your disposal. Understanding how to use them is an essential part of creating optimized PSoC 3 and PSoC 5 solutions.

AN82156 explains how the datapaths work and teaches you how to develop PSoC Creator components that use the UDB datapaths. It contains step-by-step instructions for creating your first datapath component. The appendices also review the Datapath Configuration Tool and the Verilog code it generates.

If you are planning to create a custom component, you should become familiar with the datapath and the advantages it can offer. AN82156, its example projects, and related on-demand training videos are available today from the Cypress.com website.

AN82156 Landing Page:

• AN82156 - Designing PSoC Creator Components With UDB Datapaths  

On-Demand Videos:

• PSoC Creator 210: Intro to Datapath Components
• PSoC Creator 211: Datapath Computation
• PSoC Creator 212: Datapath FIFOs
• PSoC Creator 213: Multi-Byte Datapath Components
• PSoC Creator 214: Datapath API Generation
   

By Greg Reynolds

 

Trimming simply means adjusting register values to achieve better accuracy be it for offset of a comparator or the frequency of a clock. For clocks, trimming means calibration with respect to a higher accuracy reference clock.

In the example project associated with the application note (schematic shown above), the IMO is trimmed with a 32 kHz crystal as reference and the ILO is trimmed with the IMO as reference. This enables the IMO to achieve near MHz crystal accuracy (±0.05%) at kHz crystal cost. The ILO performance is also considerably improved with a post-trim accuracy of ±6.5% with respect to the IMO. This means that the respective trim components improve ILO accuracy by a factor of 16, and the IMO accuracy by up to a factor of 140. Moreover, the accuracy can be easily verified on the character LCD (an example is shown below) with a simple API call to check IMO and ILO errors!

I really enjoyed developing these two components. Once you program the example project on the PSoC, zap it with freeze-spray or a heat gun and have fun watching the component correct the IMO and ILO frequencies!

In conclusion, having an accurate MHz clock is important for a wide range of applications, and particularly for high-speed communication. An accurate kHz clock also has many applications, especially in low power modes when MHz clocks are switched off.

The IMO and ILO Trim components really enhance the already-flexible clocking structure in PSoC 3 & PSoC 5, and I hope that they help you out in your specific applications as well. You can download the application note and the components at AN80248's landing page.

By Antonio De Lima Fernandes

To help you learn about and effectively use the UDBs, we're launching a series of new application notes that cover the topic in great detail. The first one, AN81623, PSoC 3/5 Digital Design Best Practices, is intended to introduce designers, especially firmware engineers, to the field of digital design and how it is done with PSoC 3/5.  Forthcoming application notes will give detailed instruction on the use of PLDs, datapaths and other UDB features.

AN81623 gives a brief introduction to digital hardware design theory and then describes the digital subsystem in PSoC 3 and PSoC 5. It also describes best practices for digital design using PSoC Creator, and shows how to use static timing analysis (STA) report files.

So this application note should help you more effectively use the digital components available to you right now - Counter, Timer, PWM, Shift Register, Quadrature Decoder, and more.  And with the Lookup Table (LUT) component you should easily be able to build simple state machines. Then watch for more advanced application notes, coming soon, that will show how to implement your own complex digital designs in the PSoC 3/5 UDBs.

To download this new application note "Digital Design Best Practices" click on this link, AN81623.

By Mark Ainsworth

The second project, 2_WaveDAC8_TwoWaves shows how you can alternate between two waveforms and easily switch right at the end of each wave.  The project schematic is rather simple, and the source code can t get much simpler.

Project source code.

This is the waveform output, notice it is not just a simple sinewave.

The third project "3_WaveDAC8_UART_FSL" shows how to generate a simple FSK output when you combine the WaveDAC8 and UART components.  Note the simplicity of the schematic below.  By changing the two clocks you can generate any two frequencies you want.

The scope screen shot below shows the output of the UART and the WaveDAC8 output.

Again the code can t get much simpler to send out Hello World .

The forth project was probably the most fun.  Who doesn t enjoy dialing their phone with their own custom made PSoC controlled DTMF dialer.   This project used two WaveDAC8 components, a couple of counters, an opamp to buffer the DAC outputs, and a single clock.

This project demonstrates another cool feature of PSoC.  Since the WaveDAC8 component uses standard internal DACs to generate the output,  connecting the two DAC outputs together is not a problem.  When the DAC is in the voltage DAC mode, it is simply a current DAC with an internal resistor.  Now the coolest thing about this project is that it gives you a good chance to use that FFT feature in your digital scope.  I had the DTMF dialer project dial the sequence 159D which causes all of the eight tones to be exercised.  Using the Tek MSO 2024 FFT mode I can see the frequency spectrum of the output, cool eh?

You can find the full application note, example projects, and WaveDAC8 component library on the AN69133 Application Note web page. The application note contains details about the design of the WaveDAC8 and information on sampling theory.

So just remember, although the WaveDAC8 maybe pretty, it has some brains as well.  Since it does all it's work with DMA, it does not require any of the valuable PSoC 3 or PSoC 5 CPU cycles.

By Mark Hastings

• The update includes:
• A description of the updates to the PSoC Creator 2.1 ECO interface.
• Descriptions of ECO performance metrics, and how to measure them.
• An "Advanced Topics" section for ECO experts.
• A table of recommended MHz resonators with manufacturer specifications, reccomended configurations and typical performance metrics. (Shown below)

Check it out now, and let us know what you think in the comments!

By Max Kingsbury

The following is an actual screen shot of the Analog Device Viewer/Editor.  If you look close, note that all the resources used, including routes are highlighted.  You can click on the nets on the right or the graphical routes on the left to examine the nets and routes.

Example Circuit

Below is an example circuit and the analog viewer s representation.  Note how AMux_1 consist of the light blue traces.  It is easy to understand just how the signals are routed and exactly the resources used to create the circuit, no more guess work!

Lock down signals and component placements graphically

Many of you at times wish you could easily lock down blocks that are used for a specific component implementation.  You may have learned to use the constraints editor but found it a real pain trying to remember the syntax.  I know I did.  Now you can graphically lock down or move blocks right in the analog editor.  I can almost hear the cheers in the background from you seasoned users.

Analog Mux and Simulation

Ever asked yourself I wonder exactly how my analog mux is implemented?   I know I have.  Now you can go into the tool and connect the analog mux one channel at a time and see the actual signal path.  No more laying awake at night wondering if your signal took AGL[6] or AGL[7] on its way home to the ADC.

View analog switch names, registers, and masks.

This feature is for the real hard core guys that want to know the actual register and mask to control each analog switch.  Now just by hovering over a switch you can get all that information.  No more digging into that big 1000+ page document to try and figure out how to control that one switch.

Measure typical route resistance with an Ohm Meter

This is another cool tool.  The Ohm Meter tool lets you measure the route resistance between any two endpoints of a signal.  Of course the measurement is not exact, but it gives you a ballpark number of what to expect. ( Please ignore the significant digits of the ohm meter reading in the figure below, it has been rounded off in the current version.)

Toggle analog switches interactively in the debugger

This feature is really powerful.  While in the debugger, you can view the state of almost any switch.  The only ones you can t monitor is the state of any switch that is controlled by hardware, such as the hardware mux.  All other analog switches that are part of a route, or controlled by software can be examined interactively.  So each time you halt the operation in the debugger, you can actually view the current state of the switches.  But wait, there s more!  You can actually toggle the state of each switch as well.  This means you can debug any route you want and interactively see what happens when you open or close a switch.  I often use a spare route and pin to internally probe signals.  Yes you heard me, this allows you to probe internal nodes while the chip is running.  If you don t like this feature, you shouldn t call yourself an engineer!

Set breakpoints when a switch opens or closes

OK one more amazing feature.  Just think of being able to click on an analog switch and set a breakpoint when that switch opens, closes, or just changes states.  Yes not kidding!  I dare you to find another vender s tool and MCU that will let you do that!

I hope this was just enough information to give you a taste of some of the new features in PSoC Creator 2.1.  So don t delay, go download PSoC Creator 2.1 and play with some of the new analog debug and design features.   If this isn t enough there are even more features to help you get your design to market faster.  You can download the new feature packed PSoC Creator 2.1 here.  So don t delay, go checkout all the good stuff!

By Mark Hastings

AN77900 is available on the Cypress website today, contains:

• An introduction to the low-power features of the PSoC 3/5 devices.
• Information on reducing power consumption in Active and Alternate Active modes.
• Examples, tips, and tricks for success with the Sleep and Hibernate low-power modes, including example code.
• Descriptions and explanations of the registers and API associated with low-power operation.
• Step-by-step instructions for performing accurate power measurements using the Cypress DVK boards.

Example projects for both the PSoC 3 and PSoC 5 are also included with the application note:

• Low-power modes and wakeup source examples for PSoC 3.
• Low-power modes and wakeup source examples for PSoC 5.
• A simple example project with no low-power optimizations.
• The same simple example using low-power techniques.

In addition to the application note and example projects, we're pleased to be able to provide you with a spreadsheet that can be used to perform rough "back of the napkin" type estimates for the average power consumption and battery life of your design. The spreadsheet lets you use up to ten different PSoC 3/5 configurations, with selectable settings for various subsystems and components. Based upon those configurations, the spreadsheet will calculate the average power consumption and show an estimated battery life.

AN77900 is a good starting point for anyone who wants to become more familiar with the PSoC 3/5 low-power features. As with all our documentation, we're happy to hear back from you regarding any additional topics that you'd like to see covered in this application note.

By Greg Reynolds

For more information about 8051 Code Optimization, see application note AN60630.

By Mark Ainsworth

Placing code in RAM using GCC

Gcc supports the use of the __attribute__ keyword which allows you to apply special attributes to your code.  There are many attributes you can apply; the one we are interested in is section .

The section attribute places code in a specific memory section as defined in the cm3gcc.ld file.  RAM is defined as the .data section.  So, for example, if you wanted to place a function in RAM the code for the function prototype would look like this:

void foo (void) __attribute__ ((section(".data")));

This method can be used for variables as well.

Interrupt Example

A great use of this feature is to place interrupt handlers in RAM for faster execution time.  If you define your own ISRs you can do this by placing __attribute__ ((section .data ))) after the ISR prototype like a normal function declaration.

If you are using the Cypress generated ISR code you can add a declaration statement to the section of code at the top of the .c file which is provided for the user to include modules and declare variables.

Here is an example:

// place interrupt in SRAM to improve speed

externCY_ISR_PROTO(isr_1_Interrupt) __attribute__ ((section(".data")));

for an isr named isr_1.

Linker Warning

When you place code into the .data section you will get the following warning:

Warning: ignoring changed section attributes for .data

This is because the .data section does not, by default, expect to have code attributes associated with it.  In this case you can ignore the warning, because you intend to add attributes to the .data section.  Even though the warning indicates that the linker is ignoring your attribute, it will still place your code in RAM.  You can verify this in the map file by checking which section your code has been placed in.

To clear this warning you would need to modify the cm3gcc.ld file.  The best approach would be to add a custom section located in RAM for you code.  However, since this is Creator generated source code, changes you make to this file will be overwritten when generating the project APIs.

RAM vs Flash execution

The following table provides some sample data taken to show the code execution speed from flash vs RAM.  There is about a 30 % improvement in execution time when executing out of RAM vs flash.  This data was taken by toggling a pin in an ISR with a varying amount of code, measured in bytes.  The Cortex M3 was running at 24 MHz. There was no difference in the time it took to get into the interrupt.

By Keith Mikoleit

To configure the PSoC 3 and 5 ECO for use with a ceramic resonator, simply use the PSoC Creator Design Wide Resources interface to configure the oscillator as you normally would, then add the following lines in your main.c initialization code:

/* Configure MHz XTAL */

/* Turn automatic gain control off (AGC not necessary for resonators */

CY_SET_REG8(CYREG_FASTCLK_XMHZ_CSR, 0x05);

/* Set the XTAL feedback and watchdog voltages to a reasonable value */

CY_SET_REG8(CYREG_FASTCLK_XMHZ_CFG1, 0x55)

Also, be sure to check out AN54439 - PSoC® 3 and PSoC 5 External Oscillator to learn more about using PSoC 3 and 5's powerful ECO circuit.

Max Kingsbury

Applications Engineer

 For more information, see the Code Example "CapSense® Button and Slider Example - PSoC® 3 / PSoC 5".

By Jaya Kathuria

For more information on PSoC production programming and programming in general please see the following web page for more details:

www.cypress.com/go/programming

If one needs additional device support please file a tech support case so that your request can be expedited.

www.cypress.com/go/support

AN73503 USB HID Bootloader provides a complete USB HID Bootloader solution for PSoC3 and PSoC5. The App Note explains,

• Procedure to create a USB Bootloader project

• Procedure to create a USB Bootloadable project

• Create your own Graphical User Interface (GUI) to Bootload via USB

Each of the above is explained with a working example. A precompiled stand alone GUI is also available with the application note that can be used to perform Bootloading. This App Note can be used as a starting point to develop your own USB Bootloader GUI and add additional features as desired.

• GPIO Pin Basics physical structure, internal routing, startup and low-power behavior.
• GPIO Pins and PSoC Creator using APIs, placing pin component symbols and macros, manual pin assignment.
• API and Register Reference component API, per-pin API, GPIO registers, nonvolatile latches.
• Examples, Tips, and Tricks a dozen examples from Hello World to controlling analog switching with hardware.

Application note AN72382 is a great starting point for anyone looking to become more familiar with the possibilities available when using PSoC 3 and PSoC 5 GPIO pins. The examples include step-by-step instructions and sample code that can be integrated into your project.

The resistance of an RTD varies with temperature in the following manner.

Once we find the resistance of the RTD, the temperature can be found using (inverse of) the above equations. But finding the inverse equation is very math intensive. The optimal approach is to determine the polynomial fit to find resistance from temperature. Using a higher order polynomial is computation intensive while using a lower order polynomial may not yield accurate results. AN70698 Temperature Measurement with RTDs provides a PSoC Creator Component for RTD where you can easily choose an appropriate polynomial based on your temperature range and accuracy required.

The PSoC Creator Component solves one part of the puzzle: converting the measured resistance accurately to temperature. The bigger part is finding the resistance accurately. AN70698 discusses the pros and cons of some circuits commonly used for measuring resistance and describes a method (shown below) where the resistance can be measured accurately using PSoC3/PSoC5 s IDAC, 20-bit delta sigma ADC and one precise external resistance.

The application note lists all significant sources of error so you know beforehand what accuracy to expect at a certain temperature.

Note(*): This error indicates the worst-case limit. The actual temperature error will be much lower, depending on the INL at that point. In most cases, the error will be < 0.1 °C.

Integrated 20-bit Delta Sigma ADC and IDAC combined with the RTD component simplifies designing with RTDs and gives you an experience no other design platform provides. PSoC3/PSoC5 also provides direct segment LCD drive for displaying temperature and a host of communication peripherals (I2C, SPI, UART, USB, SMBus, PMBus) for inter-IC communication or communication to a PC for data logging.

PSoC 3 Implementation

Figure below shows the overall block diagram for implementation of the Li-ion battery charger with a PSoC 3 device. The implementation is broken down into three blocks:

• Battery parameter measurement
• Charging algorithm
• External current control

Additionally, a protection block is provided for additional features related to the battery protection. The external current control can be either linear or switching type of implementation. For more information on each of these blocks and the components used, and detailed information about their implementation using PSoC 3, please refer AN73648 PSoC3 Single Cell Lithium Ion Battery Charger. The application note also provides a PSoC Creator project, which includes a charge display tool and demonstrates Li-ion battery charging.

MiniProg3 is used during the prototype stage of application development to program and debug PSoC 3 or PSoC 5 target devices on a development board. Third-party programmers are used for production programming of PSoC 3 or PSoC 5 in large numbers. Those programmers are used after the design is completed and the application goes for mass production. In addition, custom-developed host programmers, such as external microcontrollers, can perform in-system programming of PSoC 3 or PSoC 5 devices.

The application note AN73054 - PSoC® 3 / PSoC 5 Programming Using an External Microcontroller (HSSP) will enable in the rapid development of in-system programmers by providing a portable, modular C code that can be easily ported to any host programmer development platform with minimal changes. The following are the broad changes required while porting the code to a specific host programmer.

• SWD physical layer routines to access (read, write) the programming pins. These routines will have to be modified based on the method of accessing  an I/O pin state in the host programmer
• The method of getting the data to be programmed to the target PSoC 3/5. Some host programmers might use the on-chip memory to store the data to be programmed; other host programmers might use a communication interface like USB, SPI to get the programming data

Refer to the application note AN73054 - PSoC® 3 / PSoC 5 Programming Using an External Microcontroller (HSSP) for complete details on creating an in-system programming solution for PSoC 3/5. The example project provided with the application note uses a PSoC 5 as a host programmer to program the target PSoC 3/5 device.

Segment LCDs are available in two forms - segment LCD glass and the segment LCD module, which comes with inbuilt driver. Many times, it is difficult to get all the required display features on a LCD module. One possibility is to use a custom LCD glass and an external driver. But this increases the cost of the system. Cypress PSoC chip can do segment LCD glass drive besides executing some other major tasks with its configurable digital/analog hardware and with its 8-bit MCU. It integrates multiple functions of the system within a single chip offering significant BOM savings.

Segment LCD Drive in PSoC 1

PSoC Designer provides SLCD user module (UM) that can directly drive a multiplexed segment LCD. The SLCD UM has the following features:

• Drives LCD with ½ bias
• Supports 2, 3, and 4 common LCD
• 30 150 Hz refresh rate
• Supports Type A waveform
• Contrast control Feature

Support for Numeric (7 segment), alphanumeric (14 and 16 segment) and special symbols

SLCD is a firmware based module where the CPU generates the ½ bias waveforms by configuring the pins and associated registers. To time the refresh events, periodic interrupts are generated to the CPU using a timer. This timer is embedded within the module.

SLCD module provides two unique techniques to drive the LCD:

1.     AMUX Drive

2.     GPIO Direct Drive

www.cypress.com/go/psocdesigner

PSoC Designer 5.2 is a minor release and will coexist with existing PSoC Designer 4.4, 5.0 and 5.1 installations.

The PSoC Designer 5.2 release has added the notable new features:

• Updated ImageCraft compiler
• Boot.tpl update to support custom code merge sections
• Support for CY8C20xx6L Device Family
• New SmartLED User Module
  • CY8C20xx6L Devices Only
• New CSDe User Module
  • CY8C20xx6L Devices Only
• Ovation ONS II LP Device Support
• Update to PowerPSoC SREG Sleep settings
• LINS user module support on new CY8C29xxx Automotive Devices
• New Wireless-NL User Module for all Encore II devices
• Update to SmartSense_EMC User Module
• Update to ADC10 and CSDADC User Modules
• New Device Package Support for CY7C638xx devices
• Co-existence with past PSoC Designer releases

We are also pleased to announce the PSoC Designer Youtube page. The Designer Team will post new videos announcing new features and walk users through example projects. Currently we have a tutorial walkthrough for “Your First PSoC Designer Project.” This video can be found directly on the Youtube channel or linked on the PSoC Designer landing age.

http://www.youtube.com/user/PSoCDesigner
http://www.cypress.com/go/psocdesigner

Thank you and Cypress appreciates your continued support of PSoC Designer.

Hilo has released their software update, revision V3.06B, which contains the qualified PSoC 5 support. Prior to programming any Cypress PSoC 5 devices the distributor or vendor must update to the latest revision of software from Hilo.

The following table details the Hilo adapter Support

Hilo Systems currently supports the device listed above and will add additional Marketing Part Numbers and support the entire PSoC 5 family.

For more information on PSoC production programming and programming in general please see the following web page for more details:

www.cypress.com/go/programming

If one needs additional device support please file a tech support case so that your request can be expedited.

www.cypress.com/go/support

Elnec Systems currently supports the device listed above and will add the remaining PSoC 5 device support before the end of the quarter 2011.

For more information on PSoC production programming and programming in general please see the following web page for more details:  

www.cypress.com/go/programming

If one needs additional device support please file a tech support case so that your request can be expedited.

www.cypress.com/go/support

PSoC Programmer 3.13.4 Release:

We are pleased to announce the release of PSoC Programmer 3.13.4 which is available at the following web page:

www.cypress.com/go/psocprogrammer  

PSoC Programmer 3.13.4 provides the following updates:

Defect fixes to support Ovation II devices

• Updated PSoC 3 and GEN4 device support list
• Supports PSoC Designer and PSoC Creator releases

For more information on the software update please see the PSoC Programmer release notes and user guide linked on the PSoC Programmer web page.

Unique Features of PSoC 3 and PSoC 5 Interrupts

PSoC 3 and PSoC 5 provide the following enhanced interrupt features that are not supported by the other traditional microcontrollers:

• Configurable Interrupt Vector Address: In PSoC 3 and PSoC 5, you can dynamically configure the interrupt vector address. The CPU execution can be directly branched to any ISR code when the interrupt occurs. In traditional microcontrollers, the interrupt vector address is fixed for each interrupt line. Typically, a JUMP instruction is placed in that fixed address to branch the CPU execution to the actual ISR code. This unique feature reduces the interrupt execution latency in PSoC 3 and PSoC 5 compared to the traditional microcontrollers.

• Flexible Interrupt Sources:In traditional microcontrollers, the interrupt source is fixed for each interrupt line. PSoC 3 and PSoC 5, give you the flexibility to choose the interrupt source for each interrupt line. This flexible architecture enables any digital signal to be configured as an interrupt source.

Interrupt Support in PSoC Creator

PSoC Creator supports interrupts by providing them as a component. The Interrupt component is available under the System tab in the Component Catalog window as shown infigure below. Each instance of the interrupt component is an interrupt line. The interrupt source should be connected to the interrupt component in the schematic.

For more information on interrupts in PSoC3 and PSoC5, please refer Application note AN54460 PSoC3 and PSoC5 Interrupts, which introduces you to the interrupt architecture, and explains the support for interrupts in the PSoC Creator Software, the development tool for PSoC 3 and PSoC 5. Advanced interrupt concepts such as handling re-entrant functions and fixed function interrupts are also explained in detail. Code examples are provided to explain the different use cases of interrupts. Please access the application note webpage for document and zip file containing the example projects.

The DMA can be very useful in applications that require ADC data buffering and allows the CPU to do other tasks simultaneously.  The Delta-Sigma ADC has programmable resolutions from 8-bits to 20-bits. This ADC output is available in 32-bit format consisting of four 8-bit registers: OUTSAMP, OUTSAMPM, OUTSAMPH, and OUTSAMPS registers. The OUTSAMPS register gives sign extension of the data if OUTSAMPH is read as a 16-bit register. In the default ADC configuration, the output is aligned to the least significant bit (LSB). Hence for an n bit resolution, the ADC result is always available in the least n bits starting from OUTSAMP.

8-Bit ADC Data Buffering Using DMA

For 8-bit ADC data buffering, the contents of OUTSAMP register should be moved to memory buffer on each EoC (End of Conversion) signal. The ADC generates an EoC signal at the end of each conversion, which can be used as the DMA channel trigger to buffer the ADC data. The block diagram illustrating 8-bit transfer is as follows.

AN61102 PSoC3 and PSoC5 ADC Data Buffering using DMA provides a detailed example project implementing the above block diagram. The application note also explains basics of 16-bit, and 20-bit Delta-Sigma ADC data buffering using DMA with example projects. The 20-bit example project accompanying this application note demonstrates problems with data buffering using DMA and how to tackle this using multiple DMA channels. The application note also includes an example project on 12-bit SAR ADC data buffering for PSoC 5 device.

Please access the application note webpage to download the document and zip file containing the example projects. Note that these are all updated to work with PSoC Creator 2.0, the latest edition of our PSoC Creator software.

The DMA with the help of Transaction Descriptors (TD) can move data from a source to destination at very high speeds. The TDs can be chained together to perform complex data transfers. The following diagram illustrates a simple data transfer using DMA.

The key features of PSoC® 3 and PSoC® 5 DMA are:

• 24 DMA channels
• Each channel has one or more Transaction Descriptors (TDs) to configure channel behavior. Up to 128 total TDs can be defined
• TDs can be dynamically updated
• Eight levels of priority per channel
• Any digitally routable signal, the CPU, or another DMA channel, can trigger a transaction
• Each channel can generate up to two interrupts per transfer
• Transactions can be stalled or canceled
• Supports transaction size of infinite or 1 to 64k bytes
• TDs may be nested and/or chained for complex transactions

Please refer AN52705 - PSoC® 3 and PSoC 5 - Getting Started with DMAfor information on different ways to configure the DMA channel and TD to perform data transfers. The application note also has example projects and a brief video.

By Kaushik Subramanian

Figure 1: I2C Hardware Block

The HW block is a serial to parallel processor designed to interface the PSoC 1 to an I²C bus. The HW block takes the burden off the CPU by providing support for HW detection of I²C status and generation of I²C signals.

EzI2Cs

The first user module to consider is the EzI2Cs UM. The EzI2Cs UM operates exclusively as a slave; there is no master version of EzI2C. The EzI2Cs UM is a firmware layer on top of the I²C hardware block. It requires minimal user knowledge of how the I²C bus works by allowing you to setup a data structure in user code, and exposing that structure to the I²C master. All I²C transactions happen in the background through interrupts. You need not worry about any of the I²C functionality once the user module is started in the main code.

I2CHW

This user module is a firmware layer on top of the I²C HW bloc and can be used as a slave, master, or multi-master slave. Unlike EzI2Cs, this user module requires more designer interaction. Status bits must be checked to see if an I²C transaction occurred. The main firmware also needs to check for error conditions on a transaction. Finally, user code must clear the status bits that are set.

For a detailed overview of the I2C block in PSoC1 and example usage of the user modules described above, please refer application note AN50987 - Getting Started with I2C in PSoC® 1.

Hysteresis comparator in PSoC1 can be implemented using either of the following types of analog blocks:

1.    Continuous time (CT) analog block

2.    Switched capacitor (SC) analog block

The CT block in PSoC1 includes an opamp and a resistor array. This makes the analog block useful for functions such as programmable gain amplifier (PGA) and comparators. The SC block of PSoC1 includes an opamp with a switched capacitor network around it. This architecture is useful in the design of integrator, differentiator, filter, amplifier, DAC and comparator.

Hysteresis Comparator using SC Block

The COMP user module in PSoC Designer can be used to design hysteresis comparators using the CT block. It is also possible to make an SC block comparator with the hysteresis. The SC block comparator s threshold level is determined by the ratio of two internal capacitors. This produces a comparator with the hysteresis that:

• Has no external components
• Allows the hysteresis thresholds to be easily changed in firmware

Figure below shows an SC block configured as a programmable threshold comparator.

AN2108 PSoC1 Impementing Hysteresis Comparators describes a detailed example to show how SC blocks can be used for such a design in PSoC1. In addition, two other design examples are also shown, along with commented firmware projects:

Design 1 shows a hysteresis comparator implementation using a CT block and external resistors. This architecture allows precise setting of the hysteresis.

Design 2 shows a unique technique to implement a comparator with independently controllable hysteresis thresholds.

Please access the application note webpage to download the document and zip file containing the example projects.  

A view before:

Creator 2.0 with anotation components:

Checkout www.cypress.com/go/creator for more cool stuff about Creator 2.0!

Elnec has released their software update, revision V2.83n/11.2011, which contains the qualified PSoC 3 support. Prior to programming any Cypress PSoC 3 devices the distributor or vendor must update to the latest revision of software from Elnec.

The following table details the Elnec adapter Support

 
Elnec Systems supports all PSoC 3 marketing part numbers.

For more information on PSoC production programming and programming in general please see the following web page for more details:

www.cypress.com/go/programming 

Cypress has qualified 48-QFN, 48-SSOP, 68-QFN, and 100-TQFP devices from RPM Systems for programming PSoC3 devices.

RPM Systems has released their software update, revision V 1.17.4, which contains the qualified PSoC 3 support. Prior to programming any Cypress PSoC 3 devices the distributor or vendor must update to the latest revision of software from RPM Systems.

RPM Systems supports all PSoC 3 marketing part numbers.

For more information on PSoC production programming and general programming please see the following web page for more details:

www.cypress.com/go/programming 

Interrupts and Dynamic Reconfiguration

Dynamic reconfiguration allows digital and analog blocks to be shared between different user modules, performing different functions at different times. This requires designers to handle interrupts differently from normal PSoC usage and choose the ISR to execute, based on which user module is loaded at any given time. For example, a digital block may share functionality between a Timer and SPI user module. Each of these UMs have a unique interrupt service routine, however, they share the same interrupt vector.

Therefore, the interrupt vector must be routed to the ISR for the user module that is loaded when the interrupt occurs. It is best to place user modules in such a way that the number of shared interrupt vectors is minimized.

The code excerpt below is taken from the interrupt vector table located in boot.asm file.

org   2Ch    ;PSoC Block DCB03 Interrupt Vector

ljmp  Dispatch_INTERRUPT_11

reti

Normally this interrupt vector would have jumped to a routine with a name specific to the user module. The vector now jumps to a routine called Dispatch_INTERRUPT_11 instead of the user module s ISR. This interrupt handler consecutively checks each configuration that shares the block to determine the active one. When it finds the active configuration, it jumps to the appropriate ISR for the loaded user module. If many configurations share the same block, this function may take longer to execute. This also causes different interrupts to have different latencies.

For more information about setting up dynamic reconfiguration in PSoC along with an example project, please refer AN2104 Dynamic Reconfiguration using PSoC Designer.

For more information on how to use the WaveDAC8 component and download the example projects, go to the AN69133 page.

By Mark Hastings

Disable Analog Block References

PSoC Analog Blocks have individual power-down settings that are controlled by the firmware. The Analog Block References can be disabled  by a  write to the PWR bits [2:0] of the  ARF_CR register, similar to the code below:

ARF_CR &= 0xf8; //Turn off analog reference

Disable CT/SC Blocks

The continuous time (CT) blocks are powered down individually with a write to each ACBxxCRy or ACExxCRy register corresponding to the block s column. The switch capacitor (SC) blocks are similarly controlled by the ASCxxCRy or ASDxxCRy registers. The example below shows how to disable the CT and SC blocks for column zero.

ACB00CR2 &= 0xfc; // Disable CT Block

ASC10CR3 &= 0xfc; // Disable typeC SC block

ASD20CR3 &= 0xfc; // Disable typeD SC block

The CT blocks can remain in operation because they do not require a clock source. However, the SC blocks do not operate because there is no clock source for the switches.

Application Note AN47310 PSoC1 Power Savings Using Sleep Mode provides an overview of PSoC1 sleep mode basics and information on power-saving methods, and other sleep related considerations.

This video is a short tutorial on how to use the EzI2C Slave Component for PSoC 3 and PSoC 5.

 To download the example project see the code example CE56296

By Rajiv Badiger

 For more information on PSoC3 interrupts, see application note AN54460

By Vivek Shankar

Hilo Systems has released their software update, revision V3.06, which contains the qualified PSoC 3 support. Prior to programming any Cypress PSoC 3 devices the distributor or vendor must update to the latest revision of software from Hilo Systems.

The following table details the PSoC 3 device package and the respective Hilo Systems adapter.

Hilo Systems will be adding additional marketing part number support through the rest of the year. The following is a list of Marketing Part Numbers currently supported by Hilo Systems:

CY8C3245LTI-139

CY8C3246LTI-162

CY8C3446AXI-099

CY8C3446LTI-073

CY8C3446PVI-076

CY8C3866AXI-040

CY8C3866LTI-030

CY8C3866LTI-068

CY8C3866PVI-021

CY8CTMA395-LTI-00

CY8CTMA395-LTI-01

For more information on PSoC production programming and programming in general please see the following web page for more details:

www.cypress.com/go/programming 

1. Bootloader host: It can be a PC or an embedded host capable of communicating with the target device.
2. Bootloader: This is a piece of code that resides in the target device and capable of communicating with the host, re-flashing the device and handing control to the application. The bootloader is usually factory programmed onto the device.
3. Bootloadable project: This is the actual application in the target device. It can be changed using the bootloader.

• PSoC3/PSoC5 bootloader allows you to reconfigure both hardware resources as well as firmware.
• The bootloader is created as a separate project. The bootloadable project is linked to the bootloader project using the dependency option in PSoC Creator IDE.
• You can build your own custom communication interface for bootloading.
• A typical PSoC3 I2C bootloader project only consumes 7 kB of flash.
• It is possible to protect the security settings of the bootloader flash to prevent any accidental rewrites to the bootloader itself.
• PSoC3/PSoC5 bootloaders are fail-safe. The bootloadable project checksum is validated during power-up. When the checksum is invalid, the bootloader will wait for a valid image to be bootloaded. This is useful in situations where power fails during bootloading.

• Single signal conveys the data and clock information
• Self synchronization

• When the MOSI is “low”, the XORed output follows the clock. Hence there is a transition from low to high (rising edge = ‘0’).
• When the MOSI is “high”, the XORed output is an inverted version of clock. Hence there is a transition from high to low (falling edge = ‘1’).

• An XOR Gate – Used to derive the Clock which in turn triggers the Delay unit.
• A Delay Unit – Produces a delay of 3/4^th bit period.
• A D Flip-Flop – Used to hold the Serial data out.

• Simplicity in designing of the encoder - Just an SPI Master with an XOR Gate are the only requirements.
•  Implementation of Decoder in Hardware – Manchester decoder uses a D Flip-Flop and an XOR which are implemented in hardware. The PWM Component has to be initialized at the beginning of code. Then, no CPU intervention is required for its further operation.

To observe memory in the XDATA space, use the following in the watch window: 

*((char*)0x01yyy)

Where YYYY is a 2 byte address. This limits the addressable range for XDATA to 64KB. The char designator restricts it to a single byte, which for most debugging purposes is sufficient.

*Note: There are no spaces in the name.

Other observable memory locations:

The address spaces are limited based on address type through the watch window (Keil limit), and everything must be addressed via the 24 bit address.

XDATA: 0x01YYYY    64k limit

DATA:  0x0000YY    128 byte limit

CODE:  0xFFYYYY    64k limit

PDATA: 0xFE00YY    256 byte limit

Other types: Char is not the only allowable type. For larger values (16 and 32 bit) you can also use int and long:

*((int*)0x01YYYY)

*((long*)0x01YYYY)

Be aware though, Keil is a big endian compiler, so it will interpret memory differently than if you read it out of the memory window. For example:

In the memory map:

0x7000   0x7001   0x7002    0x7003

FE           00            00             1F

The result of the watch window:

Watch window expressions:

You can also create interesting expressions in the watch window:

In the memory map:
0x4690    0x4691
77        02

(int)(*((char*)0x014690)+(*((char*)0x014691)<<8))

This generates the following value -> 0x0277

   
For PSoC 5 (GCC), there are no memory restrictions for PSoC 5 so the entire register space can be accessed in the debugger.

The same techniques apply for PSoC 5 when setting up watch variables for memory locations, although the compiler is little endian oriented, so the int and long values will look different from PSoC 3 to PSoC 5 for the same value:

In the memory map:
0x7000    0x7001    0x7002     0x7003
FE        00        00         07

The result of the watch window:

 Quick Reference (PSoC 3):

XDATA: *((char*)0x01YYYY)

*Limited to 64 KB, no spaces in name

CODE: *((char*)0xFFYYYY)

*Limited to 64 KB, no spaces in name

DATA: *((char*)0x0000YY)

*Limited to 128 B, no spaces in name


Quick Reference (PSoC 5):

ALL MEMORY: *((char*)0xYYYYYYYY)


* no spaces in name

By Chris Keeser

Over the last couple of years I have been asked several questions about the reference system in PSoC3 and PSoC5.  The common assumption is that when you place a Vref component in your schematic and set the reference to 1.024 volts, you will get 1.024 volts +/-0.1% at room temperature. Unfortunately this is not true.  What you will actually get is a voltage that is not exactly 1.024 volts, but with an offset of several mVolts.  But the PSoC datasheet says that the Vref is trimmed to within +/- 1mV, what's the deal? To understand this, you need to first understand the PSoC3/5 Reference Tree.  Below is a simplified version. 



Notice that on the upper left hand side there is a bandgap voltage reference that generates about 1.2 volts.  Its output is buffered then fed into a resistor network to create a voltage near 1.024 volts.  This output is connected to the input of several reference buffers that drive different analog blocks including comparators, opamps, the DelSig ADC (Upper Right), and the SC/CT blocks.  During calibration, the output of the DelSig ADC’s reference buffer is measured to get exactly 1.024 volts +/- 0.1%, while the bandgap voltage is adjusted.  This means that only the DelSig ADC’s reference is the only true calibrated reference.  The input to the other reference buffers may be off by several mVolts to start with.  Each reference buffer will also have its own input offset as well.  If the input offset of all the references buffers were the same, then all the references would match, but this is unlikely.  The input offset of all the buffers will most likely vary from buffer to buffer.  This is why a reference may not be exactly 1.024 volts and why references will not all be the same. 

By Mark Hastings

By Chris Keeser

For more information on how to implement and use correlated double sampling, see Cypress application note AN66444 for PSoC 3 and PSoC 5 or  AN2226 for PSoC 1.

By Archana Yarlagadda

Another option is to use a hardware mux to select the feedback resistor.  This allows you to select a reference other than Vss.  In the diagram below, the VDAC8 is used to generate the reference voltage which is then buffered with another opamp.  The disadvantage for this design, is that to maintain gain accuracy the resistors should be as large as possible to wash out the affect of the analog mux switch resistance.  Each analog switch in the hardware analog mux is about 200 ohms, so the external resistors should be above 10K or more. The gain for this option is the same as the first, it provides 2^N gain combinations where N is the number of pins and resistors used for gain control.

A third topology eliminates the issue with switch resistance.  The analog mux is used to select the tap point along a string of external series resistors.  Since the current through the mux switches is just that of the opamp input, the 200 ohm switch resistance can be ignored.  The disadvantage, is that one pin is required for each gain setting you want to select, therefore using more pins.  As with the other two options the gain can be controlled purely with digital signals.

 

If we add a window comparator to one of theses examples, a simple AGC (Automatic Gain Control) can be implemented.  The LUT in this example  uses the comparator outputs to determine if the gain should be increased, decreased, or remained the same.

This is just another example of the flexibility of PSoC3 and 5.  This example makes use of two of my favorite components, the opamp and the LUT.  I am sure many of you can come up with even more cool examples mixing analog and digital components to make a better super component.

Mark Hastings

Heading up the Wirtz basin.

Up the narrows to Headlee Pass

From Headlee pass just another 1500 vertical feet to the Vesper Peak Summit.

Getting closer...

I made it.

The view from the top of Vesper Peak

Now the big question, where am I going to pack all that electronics stuff around next weekend?

Mark

So you might say “so what?”  This means we can actually put two VDACs in parallel and not violate the law of parallel voltage sources.  In the diagram below you can see that two parallel VDACs in parallel really look like a single IDAC with double the current output with a 2K load to Vss.  The 2K resistor is the result of two 4K resistors in parallel.

If each of the VDACs (VDAC8_1 and VDAC8_2) generate a separate waveform and the VDAC outputs are connected, we simply get the average of those two signals.  Take a look at the scope image below where the two upper traces are the two individual VDAC output. The third signal on the bottom is the output of these two signals when the DACs are connected in parallel.

Just to have a bit more fun, do you remember when you learned about Fourier series?  I remember how cool I thought it was the first time we looked at the FFT of a square wave and learned the relationship of the harmonics to input square wave.  Looking at just the first four harmonics we get the equation below.

We then had to write a program to prove this and display it graphically.  With PSoC you can prove it just by connecting four VDAC8s in parallel.  As you can see in the image below, the upper four sine waves are averaged together to create the pseudo square at the bottom.  Wish I had a PSoC back in school about 30 years ago.

This is just a handy trick when you need to average two or more individual signals in hardware and don’t want to use any external components.

Note:  VDACs can be used to generate periodic waveforms by making use of RAM/ROM lookup tables that are transferred to the VDAC either with the CPU or with DMA.
 

Mark Hastings

• The structure of the VDACs
• Simple usage examples are given
• On chip buffering of the VDAC output for driving loads with higher current demands (less than 20 mA)

By Chris Keeser

By Greg Reynolds

By Greg Reynolds

For more details on the PSoC 3 architecture and a simple starter project, see the Cypress AN54181 web page.

By Ross Fosler

For more details on the PSoC 3 architecture and a simple starter project, see the Cypress AN54181 web page.

By Ross Fosler

By Ross Fosler

By Stuart Owen

For more information on cool ways to make use of SIO pins, see Cypress application note AN60580.

By Pavan Vibhute

For more information on using DMA with PSoC® 3 and PSoC 5, see Cypress Application Note AN52705.

By Kannan Sadasivam

Cypress is continuing to host weekly webinars for PSoC.  These webinars are presented by the PSoC experts, our Applications Team.  

This week's webinar is on Thursday, June 9th at 9:00am PDT.  The topic is on low power designs with PSoC 3 and PSoC 5.  You can access the webinar from this link.  In case anyone has problems with the link, they can always access the meeting by going to http://cypress.webex.com and entering meeting number 498 741 435.  These are VoIP meetings, so all you need is speakers or headphones.

We've had positive feedback on these webinars to date, so I hope you can join.

For more PCB layout tips, see application note AN57821.

By Mark Hastings

 For more information on AM modulation and demodulation using PSoC3 or PSoc5, see application note AN62582.

By Anup Mohan

 For more informaton using DMA with the ADC in PSoC3 or PSoC5, see application note AN61102.

By Kannan Sadasivam

 For more infomation on using the CAN Bus with PSoC3 or PSoC5, see application note AN52701.

By  Anup Mohan

For more information on using USB bulk transfers with PSoC3 or PSoC5, see application note AN56377.

By Robert Murphy

For more information about PSoC 3 and PSoC 5 bootloader, see application note AN60317.

By Mark Ainsworth

 For more information on increating DAC resolution for PSoC 3 and PSoC 5, see application note AN64275.

By Mark Hastings

For more information on the PSoC 3 and PSoC 5 external kHz crystal oscillator, see application note AN54439.

By Max Kingsbury

For more information on the PSoC 3 and PSoC 5 external crystal oscillator, see application note AN54439.

By Max Kingsbury

Robert Murphy - "PSoC Does"

For more information about USB Peripheral Basic, see application note AN57294.

 For more information about the PSoC 3 and PSoC 5 I2C Bootloader, see application note AN60317.

Mark Ainsworth

For more information about the internal analog routing in PSoC3 and PSoC5, see application note AN58827.

By Rajiv Vasanth Badiger

Feel free to comment and let us know what you would like to see and what you like or dislike.  We will do our best to respond to your requests in a timely fashion. 

PSoC Rocks my friends!!

Mark Hastings
 

Mark Hastings

The entire code for this project is shown below.

/* ========================================
 * MyFirstvoltMeter
 *
 * Simple project to read a voltage between
 * 0 and 1 volts and display it on an LCD.
 *
 * ========================================
*/
#include
#include

void main()
{
    int32 adcResult;
    float adcVolts;
    char  tmpStr[25];
   
    ADC_Start();  /* Initialize components */
    LCD_Start();
   
    LCD_Position(0,0);    /* Display message */
    LCD_PrintString("PSoC VoltMeter");
   
    ADC_StartConvert();   /* Start ADC conversions */

    for(;;)  /* Loop forever */
    {
       if(ADC_IsEndConversion(ADC_RETURN_STATUS) != 0)  /* Check for result */
       {
          adcResult = ADC_GetResult32() ;               /* Get Reading     */
          adcVolts = ADC_CountsTo_Volts( adcResult) ;   /* Convert to volts */
          sprintf(tmpStr,"%+1.3f volts", adcVolts);     /* Create a formatted string */
          
          LCD_Position(1,0);                            /* Display on LCD */
          LCD_PrintString(tmpStr);
       }
    }
}