Application Notes - Cypress.com http://www.cypress.com/?app=search&searchType=advanced&keyword%3D%26rtID%3D76%26id%3D64%26applicationID%3D0%26l%3D0 AN5042 - Migrating from Cypress FLEx18 / FLEx36® / FLEx72™ Dual-Port SRAMs to FullFlex Dual-Port SRAMs http://www.cypress.com/?rID=12654 Introduction

Cypress's FLEx18 / FLEx36® / FLEx72™ portfolio of highdensity, high-performance synchronous Dual-Port SRAMs can operate at speeds up to 167 MHz. In the fast growing data communications market, the bandwidth requirements have increased. Cypress addresses these demands with its FullFlex Dual-Port SRAMs, which can operate up to 200 MHz.

 

FLEx18: CYD01S18V/ CYD02S18V/ CYD04S18V/ CYD09S18V

FLEx36: CYD02S36V/36VA

FLEx72: CYD04S72V/CYD09S72V/CYD18S72V
 

FullFlex x 18: CYD36S18V18, CYD18S18V18, CYD09S18V18

FullFlex x 36: CYD02S36V18, CYD09S36V18, CYD18S36V18, CYD36S36V18

FullFlex x 72: CYD09S72V18, CYD18S72V18, CYD36S72V18

Package:

256-ball FBGA 17mm x 17mm
484-ball FBGA 23mm x 23mm

Package:

256-ball FBGA 17mm x 17mm
484-ball FBGA 23mm x 23mm
  • Power Supply 3.3V
  • Single I/O Standard
    • LVTTL(3.3V)


     
  • Upto 167MHz in pipelined mode
  • Pipelined mode of operation
  • Burst Counter, Mask & Counter Wrap around features
  • Retransmit functionality achieved using counter increment feature
  • Collision Detection
    • BUSY signal
  • Power Supply 1.8V or 1.5V
  • Four selectable I/O standards
    • LVTTL (3.3V)
    • Extended HSTL (1.4V to 1.9V)
    • 2.5V LVCMOS
    • 1.8V LVCMOS
  • Upto 200MHz in pipelined mode
  • Selectable Pipeline or Flow-Through mode
  • Burst Counter, Mask & Counter Wrap around features
  • Dedicated Retransmit feature (with RT# pin) enabling repeated access to the same block of memory
  • Collision Detection
    • BUSY signal
    • Readable register to store collision address
    • Busy Address Readback
  • Echo Clocks for reliable data transfer at high speeds
  • Variable Impedance Matching (VIM)
]]> Thu, 07 Feb 2013 00:37:50 -0600 AN43593 - Storage Capacitor (V<sub>CAP</sub>) Options for Cypress nvSRAM http://www.cypress.com/?rID=12769 Introduction

The nvSRAM architecture uses a one-to-one pairing of a nonvolatile bit and a fast SRAM bit in each memory cell. During normal operation, the IC behaves exactly as a standard fast asynchronous SRAM and is easy to interface with the microprocessor or microcontroller. When IC power is disrupted or lost, the event is detected and all the SRAM bits are saved into the nonvolatile part (within 8 ms) using the stored energy in a small capacitor (VCAP). This operation is called AutoStore and is described in more detail in the next section. When power is restored, data is automatically recalled from the nonvolatile part to SRAM on power restore and this operation is called Power Up RECALL (Hardware RECALL).
 

]]> Mon, 04 Feb 2013 05:39:23 -0600 AN58815 - Advantages of 65 nm Technology over 90 nm Technology QDR® Family of SRAMs http://www.cypress.com/?rID=40217
The 65nm technology QDR family  of  devices  offers significant advantages over the 90nm  technology  family. 
This application note describes these  advantages and provides guidelines to migrate from 90nm to 65nm devices. 
 
The advantages of the 65nm Technology devices are as follows and is described in detail in this application note:
 
  • Faster Operating Frequencies
  • Lower Power Consumption
  • Improved Data Valid Window
  • Improved Signal Integrity
  • Lower Input and Output Capacitances
 
]]> Thu, 17 Jan 2013 05:25:09 -0600 AN70630 - Event Data Recorder with Controller Area Network using PSoC® 3 and nvSRAM http://www.cypress.com/?rID=58300 Introduction

Systems that rely on electronic subsystems for their functionality use EDRs to store information about system status as it evolves after a critical event occurs. A critical event typically stops the system from functioning.

An EDR, such as the one described in this application note, monitors communication among electronic subsystems (controller area network nodes) and records all or selected information. Moreover, an EDR can store information collected and processed locally from various sensors.

The following table indicates the PSoC devices, PSoC Creator versions, compilers, and development kits that will work with this application note project:


Project
Device
PSoC Creator
Version
Development Kit
CY8CKIT-xxx
Compiler
Architecture
Silicon
Revision
V2.0
V2.1 SP1
V2.2
001
DVK
030/050
DVK
003/014
FTK
Keil
GCC
RVDS
MDK

AN70630.zip
Prod
YES
YES
NO*
YES
YES
NO
YES
N/A
N/A
N/A
Prod
NO
NO
NO
NO
NO
NO
N/A
NO
NO
NO
Prod
NO
NO
NO
NO
NO
NO
N/A
NO
NO
NO
*Note: This project is currently being updated for PSoC Creator 2.2 compatibility. A new version will be posted here by mid February, 2013.

Refer to Migrating CY8CKIT-001 DVK project to CY8CKIT 030/ 050.

The project associated with this application note can be downloaded from the ‘Related Files’ section below.

]]> Thu, 20 Dec 2012 23:51:49 -0600 AN6081 - Interfacing 90-nm Cypress Asynchronous SRAMs in Legacy Systems http://www.cypress.com/?rID=12711 Click here to download Application Note (PDF File)

Cypress's 90nm technology Asynchronous SRAMs have best-in-class specifications in speed and power making them an ideal choice as memories in a wide variety of applications today.

The application note below discusses how they are suited for present generation processors and controllers while Cypress' older generation SRAMs (250nm and 350nm) are a good fit for interfacing with legacy processors and controllers. The 90nm technology 5V devices are pin compatible with their older technology counterparts. The reason for Cypress continuing to support end users with older generations SRAMs is because of their increased VOH levels that ensure compliance with CMOS VIH levels of legacy processors and microcontrollers. While both generations of SRAM's have the same industry standard VOH spec, the difference in actual VOH levels enable Cypress to support processors of older and present generations, reiterating Cypress' commitment as the #1 supplier in the industry.

Please see the illustrations and the application note below for details.

Processor receiving data from SRAM on a read operation:

 

]]> Wed, 19 Dec 2012 02:29:55 -0600 AN69061 - Design, Manufacturing, and Handling Guidelines for Cypress Wafer-Level Chip Scale Packages (WLCSP) http://www.cypress.com/?rID=50506 AN69061 provides guidelines for using the Cypress wafer-level chip scale package (WLCSP) on Flexible Printed Circuits (FPC) and rigid Printed Circuit Boards (PCB).

]]> Fri, 14 Dec 2012 00:52:04 -0600 AN80555 - 72-Mbit RH QDR®II+ Interface Controller Implementation Details http://www.cypress.com/?rID=69649 Introduction

RH QDR®II+ Memory Controller contains the logic necessary to read from and write to RH QDRII+ SRAM memory. Its primary function involves synchronizing the Single Data Rate SDR (System Logic) and the Double Data Rate DDR (RH QDRII+ memory) data domains.

]]> Sun, 02 Dec 2012 23:23:38 -0600 AN44517 - Design Recommendation for Battery Backed SRAMs Using Cypress MoBL® SRAMs http://www.cypress.com/?rID=12710 Battery Backed SRAM's (BBSRAM's), also called NVRAM's by system designers, are an important part of applications that require any kind of data backup in the event of a power failure. The block diagram below illustrates a simple FPGA/microcontroller-based application that contains a shared memory bus (Flash memory SRAM), a supervisor chip and a battery. In the event of a power failure, the battery-supervisor combination acts as a power backup for the SRAM, to ensure its contents are undisturbed. The supervisor chip places the SRAM in disable mode (standby) to reduce power consumption and extend battery life. This ensures data integrity and power savings.

The attached Application Note discusses Design Considerations that need to be taken into account when using Cypress MoBL SRAM's in these battery backed applications.

]]> Fri, 23 Nov 2012 01:12:16 -0600 AN54908 - Accelerated Neutron SER Testing and Calculation of Terrestrial Failure Rates http://www.cypress.com/?rID=38369
This application note describes the accelerated neutron testing procedure and test conditions, which are applied during device qualification for Cypress SRAM devices. This application note covers Synchronous SRAM, Asynchronous SRAM, More Battery Life™ MoBL® SRAM as well as Nonvolatile SRAM (nvSRAM). This Application note does not contain the SER data for any of the SRAMs. The derived accelerated Neutron failure rates are listed in the individual data sheets for Synchronous SRAMs. For other families, SER data can be availed by raising a request on Cypress’ customer care portal. ]]> Fri, 02 Nov 2012 04:01:31 -0600 AN43380 - HSB Operation in nvSRAMs http://www.cypress.com/?rID=12770 Introduction

Cypress’ nonvolatile synchronous random access memory (nvSRAM) cell integrates a fast speed SRAM cell and a SONOS (Silicon-Oxide-Nitride-Oxide-Silicon) based nonvolatile cell into a single nvSRAM cell. The nvSRAM combines the best features of SRAM and EEPROM and makes it the fastest and the most reliable nonvolatile memory solution in the industry. The SRAM is read from and written to it an infinite number of times, while independent nonvolatile data resides in the nonvolatile elements.

This application note explains the HSB# pin internal architecture and its behavior during the device operation.

]]> Wed, 03 Oct 2012 07:34:17 -0600 AN6068 - Replacing MRAM with Cypress nvSRAM http://www.cypress.com/?rID=12773 These differences should be taken into consideration while designing a PCB to use either a MRAM or the high performance nvSRAM on the same socket without making any PCB layout changes.

Introduction

Cypress offers a family of high-speed, high performance nvSRAM. The nvSRAM technology combines the performance characteristics of a high-speed SRAM with that of a nonvolatile cell. The other similar nonvolatile solution is the Magnetoresistive RAM (MRAM) in which magnetic polarization is used to store information permanently. This application note discusses about designing applications hardware with alternative part options to use either MRAM or nvSRAM on the same socket without any hardware redesign.

]]> Wed, 03 Oct 2012 07:06:43 -0600 AN6022 - A Comparison between nvSRAMs and BBSRAMs http://www.cypress.com/?rID=35449 With lead-free initiatives being implemented globally, nvSRAMs have become a popular choice for NVRAM selection. The nvSRAM is a single monolithic solution when compared to a multiple component solution. nvSRAM can easily replace the BBSRAM with the following benefits:

  • Lower Cost
  • Higher reliability
  • Smaller board space and lower height
  • Improved manufacturing
  • RoHS compliance
  • Higher Performance

This application note outlines the BBSRAM and nvSRAM memory architecture and comparison of their features. More...

Fig: Board Space Comparison between 4 Mbit Cypress nvSRAM and BBSRAM

4 Mbit nvSRAM in 44-pin TSOP-II package         4 Mbit BBSRAM in 32-pin Encapsulated package (740 mil extended)

(No battery, RoHS compliant)                                (Battery inside)

]]> Thu, 27 Sep 2012 04:14:35 -0600 AN69702 - 72-Mbit RHQDRII+&trade; Power Modes http://www.cypress.com/?rID=51728 High speed source synchronous semiconductor devices rely on clock synthesis circuits (DLL- Delay Lock Loop / PLL – Phase Lock Loop) to mitigate on die clock skews. The 72-Mbit RHQDRII™+ SRAM uses a DLL to ensure output data and echo clocks (Strobe) are edge aligned and de-skewed with respect to the source clock. However, all DLLs/PLLs require a certain number of clock cycles to attain “lock” during which the device will not reliably operate. This application note discusses the required steps necessary to effectively transition between maximum performance and power saving modes with proper DLL operation.

]]> Tue, 25 Sep 2012 07:24:02 -0600 AN64574 - Designing with Serial Peripheral Interface (SPI) nvSRAM http://www.cypress.com/?rID=47470 The SPI nvSRAM is a slave SPI device and requires an SPI master controller to access nvSRAM in a system. This application note provides a few key design considerations and firmware tips to guide the users designing with SPI nvSRAM. An associated project for PSoC® 1 and a library component for PSoC 3 are also provided as an example project, which demonstrates SPI nvSRAM access by a standard SPI master controller.

]]> Tue, 25 Sep 2012 03:20:42 -0600 AN4011 - Choosing The Right Cypress Synchronous SRAM http://www.cypress.com/?rID=13042 Cypress currently manufactures several major synchronous SRAM architectures. The purpose of this application note is to provide a means to determine which architecture is right for a particular application. In so doing, a brief description will be supplied concerning each architecture and each will be contrasted by address/data relationships and significant performance characteristics. 

The table below shows the architecture comparison for the different options:                                                                            


Parameter
Std. Sync
NoBLTM
DDR-II/DDR-II+
QDRTM-II/ QDRTM-II+

Data Rate
Single
Single
Double
Double

Data Bus
Common I/O
Common I/O
Common and Separate I/O
Separate I/O

VDD
3.3V/2.5V
3.3V/2.5V
1.8V
1.8V

VDDQ
LVTTL 3.3V/2.5V
LVTTL 3.3V/3.5V
HSTL (1.5V/1.8V)
HSTL (1.5V/1.8V)

Clock Frequency
250 MHz
250 MHz
333 MHz / 550 MHz
333 MHz / 550 MHz
]]> Mon, 24 Sep 2012 05:59:52 -0600 AN1090 - NoBL&trade;: The Fast SRAM Architecture http://www.cypress.com/?rID=12879 Introduction

Processors in high-performance communication equipments and networking applications demand highspeed memories. The type of memory required is determined by the system architecture, the application, and the processor used. System performance suffers if the memory sub-system cannot satisfy the processor requirements.

This application note describes the Cypress NoBL SRAMs architecture designed to improve memory sub-system performance.

.

]]> Fri, 21 Sep 2012 01:53:17 -0600 AN46982 - PLL Considerations in QDRII/II+/DDRII/II+SRAMS http://www.cypress.com/?rID=53503 Introduction

QDRTM SRAM family of devices has a phase-locked loop (PLL) within the device to synchronize the output data to the input clocks thereby enabling the device to operate at higher frequencies.

QDR-II/II+/DDR-II/II+ devices can be operated with PLL enabled or PLL disabled. This application note provides an overview of the operation of the device when the PLL is disabled.

]]> Fri, 21 Sep 2012 01:47:32 -0600 AN4065 - QDR&trade;-II, QDR-II+, DDR-II, and DDR-II+ Design Guide http://www.cypress.com/?rID=12889 Cypress Quad Data RateTM-II (QDRTM-II),QDR-II+, DDR-II, and DDR-II+ SRAMs address the high-bandwidth requirements for communication and data storage applications. The purpose of this application note is to assist designers in using the QDR-II, QDR-II+, DDR-II, and DDR-II+ SRAM devices. It includes guidelines on clocking and termination techniques for the QDR-II, QDR-II+, DDR-II, and DDR-II+ SRAM devices.

 

(Clocking Strategy for QDR-II+ using Echo Clocks CQ and CQ#)

]]> Fri, 21 Sep 2012 01:39:56 -0600 AN42468 - On-Die Termination for QDR&trade;II+/DDRII+ SRAMs http://www.cypress.com/?rID=12890 ODT has the following advantages:

  • Improves signal integrity by having termination closer to the device inputs
  • Simplifies board routing
  • Saves board space by eliminating external resistors
  • Reduces cost involved in using external termination resistors

For ODT-enabled QDRII+ and DDRII+ SRAMs, ODT is offered on the following input signals:

  • Input clocks (K and Kb clocks)
  • Data input signals
  • Control signals (Byte Write Select signals)

The figure below shows the ODT implementation for Cypress QDRII+/DDRII+ SRAMs:

  

Clicking on the link below provides a tool which enables calculation of the Idd current for desired frequency, total Power consumption and Junction temperature for Sync SRAMs

http://www.cypress.com/?docID=23984

Please refer to the respective product datasheets to get the Vdd voltage and  Idd current used in the formula.

]]> Tue, 11 Sep 2012 06:02:05 -0600 AN66311 - Timing Recommendation for Byte Enables and Chip Enables in MoBL® SRAMs http://www.cypress.com/?rID=48325 This Application note explains a particular timing condition in SRAM accesses that could cause an unexpected behavior of the device. The condition involves Address lines and Chip Enable or Byte Enable lines. A workaround is also suggested in the application note. A brief pictorial representation is shown below; please read the application note for a detailed explanation.


]]> Tue, 11 Sep 2012 01:57:23 -0600 AN61546 - Non Volatile Static Random Access Memory (nvSRAM) Real Time Clock (RTC) Design Guidelines and Best Practices http://www.cypress.com/?rID=45439

(Note: Either Capacitor or Battery should be connected for RTC backup.)

]]> Mon, 27 Aug 2012 08:13:47 -0600 AN6017 - Differences in Implementation of 65 nm QDR™II/DDRII and QDRII+/DDRII+ Memory Interfaces http://www.cypress.com/?rID=12892 This application note covers the differences in implementation of 65 nm QDRII/DDRII devices and QDRII+/DDRII+ Memory Interfaces. More

 

This document describes the following:
  • Description of the QDRII+/DDRII+ devices
  • Differences between QDRII/DDRII and QDRII+/DDRII+ functionality and timing
  • Design changes that need to be considered by system designers when migrating from QDRII/DDRII to QDRII+/DDRII+ devices

 

The table below outlines the differences between the QDRII/DDRII and QDRII+/DDRII+ SRAMs

Differences between QDRII / DDRII and QDRII+ / DDRII+

  QDR II / DDRII QDRII+ / DDRII+ Remark
Frequency (PLL enabled)-65nm technology device

120 MHz ~ 333 MHz

 120 MHz ~ 550 MHz Burst of 2 QDRII+/DDRII+ support 333
MHz and Burst of 4 QDRII+/DDRII+
support 550 MHz as highest frequency.
Organization x8, x9, x18, x36 x18, x36 -
VDD 1.8 V ± 0.1 V 1.8 V ± 0.1 V -
VDDQ 1.8 V ± 0.1 V or 1.5 V ± 0.1 V 1.8 V ± 0.1 V or 1.5 V ± 0.1 V -
Read latency 1.5 clocks 2.0 & 2.5 clocks QDRII+/DDRII+ read latency is not user selectable. Offered as two different devices.
Input clocks Single ended (K,K#) Single ended     (K,K#) -
Output clocks (C,C#) Yes No -
ODT (On-Die Termination) No Offered in ODT and Non ODT versions -
A0 (DDR B2) Yes No -
A0, A1 (DDR B4) Yes No -
Echo clock number 1 Pair 1 Pair Echo clocks are single ended
PKG 165 ball FBGA 165 ball FBGA -
Individual byte write (BW0#, BW1#) Yes Yes -

 

]]> Thu, 23 Aug 2012 04:40:58 -0600 AN6023 - NonVolatile SRAM (nvSRAM) Basics http://www.cypress.com/?rID=35116

Cypress offers a family of high speed, high performance Nonvolatile Static Random Access Memory (nvSRAM) products that combine the performance characteristics of a high speed SRAM with the reliability of SONOS (Silicon-Oxide-Nitride-Oxide-Silicon) nonvolatile cell. The SRAM data is retained in the nonvolatile elements that are integrated with each SRAM cell. Cypress nvSRAMs ensure secure storage of data by automatically storing the SRAM data to the nonvolatile cells on power down using charge from a capacitor connected to the VCAP pin.

This application note describes the nvSRAM block diagram and its basic operations using a parallel nvSRAM as example. More...

The audio visual tutorial below provides an introduction to the nvSRAM architecture & its functionality.

 

]]> Thu, 16 Aug 2012 00:09:12 -0600 AN53313 - Real Time Clock Calibration in Cypress nvSRAM http://www.cypress.com/?rID=38165 The nvSRAM Real Time Clock (RTC) is driven by a crystal oscillator with a nominal frequency of 32.768 kHz. The standard 32.768 kHz crystals have a frequency tolerance of ±20 ppm at +25°C, and a nonlinear temperature drift of -0.036 ppm/°C2. The ppm error due to tolerance or temperature drift at a constant temperature can be fixed using the nvSRAM RTC Calibration circuit.

This application note discusses the operation and usage of the nvSRAM RTC Calibration circuit to maintain precise time by compensating for ppm variations. More...

]]> Wed, 15 Aug 2012 23:38:41 -0600 AN4017 - Understanding Temperature Specifications: An Introduction http://www.cypress.com/?rID=12896 The following application note is intended to give the reader a basic understanding of the temperature specifications found in Cypress's product datasheets. There are many factors that affect the thermal operation of a device. This application note provides the reader with enough background to understand the thermal parameters and temperature specifications of the device.   

This document describes the various thermal parameters namely Ambient Temperature (Ta), Case Temperature (Tc), Junction Temperature(Tj), Thermal Resistance, Power Dissipation etc.

Details on calculating Junction Temperature are provided in this application note.

Clicking on the link below provides a tool which enables calculation of the I/O Switching Current (Iddq) for desired frequency, Total Power Consumption and Junction Temperature for Sync SRAMs

http://www.cypress.com/?docID=23984

Please refer to the respective product datasheets to get the Vdd voltage and Idd current used in the formula.

]]> Wed, 08 Aug 2012 23:16:56 -0600 AN15979 - Soft Errors in nvSRAM http://www.cypress.com/?rID=12761 Introduction

The Soft Error Rate (SER) of advanced CMOS devices is higher than all other reliability mechanisms combined together. So it becomes necessary for the high-speed memory architectures to counter the effect of soft errors. The Cypress nvSRAM with its unique architecture and special features such as Software STORE and Software RECALL can correct soft errors on the fly. This capability combined with Cypress’s intense SER test methodology makes nvSRAM one of the most reliable memory devices against the soft errors.

]]> Thu, 26 Jul 2012 04:41:00 -0600 AN1044 - Understanding Asynchronous FIFOs (with Self-Paced Training Module) http://www.cypress.com/?rID=12682 The architecture, features & expansion logic of Cypress’s Asynchronous are discussed in this application note. The document also includes a brief note on the common FIFO problems and their solutions. More...

The content of the application note has been captured in a training module. This audio visual tutorial provides an introduction to FIFO architecture & its functionality. It explains the features of asynchronous FIFOs such as flags, retransmit functionality & expansion logic. It also briefly discusses the applications of Asynchronous FIFOs.


Training Module: View Download


]]> Thu, 26 Jul 2012 02:13:00 -0600 AN1042 - Understanding Synchronous FIFOs (with Self-Paced Training Module) http://www.cypress.com/?rID=12689 This application note provides a general introduction to the features & functionality of Cypress’s Synchronous FIFOs. It includes a brief discussion on Cypress’s portfolio of Synchronous FIFOs and their applications. More...

The content of the application note has also been captured in a training module. This audio visual tutorial provides an introduction to FIFO architecture & its functionality. It also explains basic FIFO features such as flags, expansion logic, timing specifications and some additional features specific to Synchronous FIFOs. A brief introduction to Cypress’s portfolio of Synchronous FIFOs & its applications is also included.

Training Module: View Download


]]> Fri, 29 Jun 2012 09:47:34 -0600 AN1043 - Understanding Synchronous Dual Port RAMs (with Self-Paced Training Module) http://www.cypress.com/?rID=12642 This application note discusses the architecture and functionality of synchronous dual port SRAMs. It covers the expansion configurations of these devices and also includes a brief note on the applications of synchronous dual port SRAMs. More...

To improve user experience, the content of this application note has been captured in a training module. This introductory audio visual tutorial covers basics of Dual Port SRAM operation, types of Dual Ports(Asynchronous & Synchronous), and in the later sections focuses on the features and functionality of Synchronous Dual port SRAMs. A brief introduction to Cypress’s Fullflex™ family of Synchronous Dual Port SRAMs is also included.

Training Module: View Download

 

]]> Fri, 29 Jun 2012 03:24:42 -0600 AN52433 - Advantages of Serial Peripheral Interface (SPI) nvSRAM over SPI EEPROM in Metering Applications http://www.cypress.com/?rID=44467 Cypress’s serial peripheral interface(SPI) nvSRAM nonvolatile memory technology has significant advantages when compared to conventional SPI EEPROM solutions. This technology is aimed at designers and architects of the latest ‘smart’ electrical energy meters.The nonvolatile memory is a critical component in such a meter. It stores valuable energy consumption and environmental data (such as suspicious physical changes which may signify an attempt to tamper with the meter) over time.

The smart meter uploads stored information over the network that links it to the supply infrastructure. In pursuit of reduced energy consumption and efficient electric energy use, different metrics of energy consumption (active power, reactive power, apparent power, sometimes both imported and exported) are recorded at fine granularity. More...

]]> Tue, 26 Jun 2012 00:57:49 -0600 AN55663 - Migrating from CY14E256L/STK14C88 to CY14E256LA http://www.cypress.com/?rID=38980 This application note provides information for migrating from CY14E256L/STK14C88 parts to the CY14E256LA.

Cypress CY14E256LA is a 5 V, 256 Kbit (32 K x 8) nvSRAM in 0.13 u technology. It is a pin to pin functional equivalent of CY14E256L/STK14C88 (0.8 u) and is a drop in replacement in most AutoStore applications. However, in an existing AutoStore inhibit application, the circuit would require change in routing of power to the VCC pin and a firmware change to disable AutoStore.

This application note highlights the differences between the CY14E256L/STK14C88 and the CY14E256LA and the parameters of significance that must be considered while migrating.

]]> Mon, 18 Jun 2012 04:35:22 -0600 AN55662 - Migrating from STK14C88-3 to CY14B256LA http://www.cypress.com/?rID=38981

This application note provides information for migrating from STK14C88-3 parts to the CY14B256LA.

Cypress CY14B256LA is a 3 V, 256 Kbit (32 K x 8) nvSRAM in 0.13 u technology. It is a pin to pin functional equivalent of STK14C88-3 (0.8 u) and is a drop in replacement in most AutoStore applications. However, in an existing AutoStore inhibit application, the circuit would require change in routing of power to the VCC pin and a firmware change to disable AutoStore.

This application note highlights the differences between the STK14C88-3 and the CY14B256LA and the parameters of significance that must be considered while migrating. ]]> Mon, 18 Jun 2012 04:33:21 -0600 AN72389 - Migrating from CY14B101P/CY14B512P/CY14B256P to CY14B101PA/CY14B512PA/CY14B256PA http://www.cypress.com/?rID=56908 Cypress CY14B101PA is a 3 V, 1 Mbit (128 K x 8) serial (SPI) nvSRAM with Real Time Clock (RTC) in 0.13 u technology. It is a pin to pin replacement for CY14B101P and has enhanced features such as lower power, 104 MHz operation and Back up power fail flag. Because of these enhancements there are a few differences in parameters which should be considered by users while migrating from the older part.

This application note highlights the differences between the CY14B101P and the CY14B101PA and lists the parameters of significance that must be considered while migrating. These differences and considerations are applicable for the CY14B512PA (3 V, 64 K x 8, 512 Kbit) and CY14B256PA (3 V, 32 K x 8, 256 Kbit) serial (SPI) nvSRAMs with RTC, which are the replacement parts for CY14B512P and CY14B256P devices, respectively.

]]> Mon, 18 Jun 2012 04:29:29 -0600 AN55661 - Migrating from CY14B256L/STK14D88 to CY14B256LA http://www.cypress.com/?rID=38985 This application note provides details for migrating from the CY14B256L/STK14D88 parts to the CY14B256LA.

Cypress CY14B256LA is a 3 V, 256 Kbit (32 K x 8) nvSRAM in 0.13 u technology. This part is a pin to pin functional equivalent of CY14B256L/STK14D88 (0.25 u) and is superior in endurance and data retention. However, the older technology part has a lower capacitor range for VCAP and hence applications using lower values of capacitor would need a capacitor change when migrating to the newer technology part.

This application note highlights the differences between the CY14B256L/STK14D88 and the CY14B256LA and the parameters of significance that must be considered while migrating.

]]> Wed, 13 Jun 2012 03:31:28 -0600 AN68174 - Migrating from Serial Peripheral Interface (SPI) EEPROM to SPI nvSRAM http://www.cypress.com/?rID=51194 Serial SPI EEPROM devices were frequently used in the past for nonvolatile storage of data. However, their low writing speed and limited endurance cycle causes bottleneck when used in designs that need frequent write updates to the nonvolatile memory at the bus speed. Many system designers have tried to solve endurance problems by using wear-leveling techniques to increase effective endurance cycles at the cost of increasing EEPROM density and software overheads. Other designers have taken a buffer memory approach in which the system saves data only at power down or power fail conditions using a reliable backup power source. Both of these approaches have been proven to be expensive solutions because of increased BOM cost, board area, processor I/O usage, design complexity, and software overheads.

 This application note provides design guidelines for migrating from SPI EEPROM to SPI nvSRAM. More...

]]> Tue, 12 Jun 2012 01:40:26 -0600 AN5036 - Interfacing Cypress MoBL® Asynchronous Dual-Port to TI OMAP1710 Multimedia Processor http://www.cypress.com/?rID=12669 Interfacing Cypress MoBL Asynchronous Dual-Port to TI OMAP1710 Multimedia Processor

The Texas Instruments OMAP1710 Multimedia Processor is a low-power, highly-integrated hardware and software platform designed to meet the application processing needs of next-generation embedded devices.The OMAPTM platform enables OEMs and ODMs to quickly bring to market devices featuring rich user interfaces, high-processing performance, and long battery life through the maximum flexibility of a fully-integrated mixed-processor solution.The OMAP1710 is primarily targeted at mobile communications applications using WLAN802.11x, Bluetooth, GSM, GPRS, EDGE, CDMA and other proprietary wireless standards. The processor provides video and image processing (MPEG, JPEG, etc.), advanced speech/audio processing, graphics and video acceleration, generalized web access and data processing.The OMAP1710 Multimedia Processor supports External Memory Interface (EMIF) that readily connects to Cypress asynchronous Dual-Ports. This application note describes the wiring, EMIF register settings, and other design considerations for connecting the OMAP1710 Multimedia Processor to the 1/4 Mb Cypress MoBL(TM) Dual-Port (CYDM256A16-55). The same design can be used in interfacing the OMAP1710 Multimedia Processor to other Cypress MoBL Dual-Ports in the x16 configuration, such as the CYDM128A16 and CYDM064A16.

]]> Wed, 09 May 2012 01:18:24 -0600 AN13842 - Recommended Usage of Byte Enables in Standby Mode for 90 nm x16 MoBL® SRAM Devices http://www.cypress.com/?rID=12875 Recommended usage of Byte enables (BHE and BLE) in standby mode, for the following Cypress 90 nm x16 MoBL® SRAM devices is being discussed in AN13842.

  • 1 Mbit (CY62126EV30)
  • 2 Mbit (CY62136EV30, CY62137EV30, CY62136FV30, CY62137FV30, CY62137FV18)
  • 4 Mbit (CY62146E, CY62146EV30, CY62147EV30, CY62147EV18)
  • 8 Mbit (CY62157E, CY62157EV30, CY62157EV18)
  • 16 Mbit (CY62167E18, CY62167EV30, CY62167E)


The figures below illustrate the trigger condition that could cause an unexpected behavior and the recommended workaround. For a detailed explanation, please refer to the attached application note and contact www.cypress.com/support if you have any questions.

 

                                 Trigger Condition                                                                        Workaround

]]> Tue, 10 Apr 2012 06:37:20 -0600 AN55659 - Migrating from CY14B101L/STK14CA8 to CY14B101LA http://www.cypress.com/?rID=38983 Introduction

Cypress CY14B101LA is a 3 V, 1 Mbit (128 K x 8) nvSRAM in 0.13 micron technology. This part is functionally equivalent to CY14B101L/STK14CA8 (0.25 µ) and is intended as a drop in replacement. (STK14CA8 is the Simtek part number for CY14B101L.) This application note highlights the differences between the CY14B101L/STK14CA8 and the CY14B101LA and the parameters that must be considered while migrating.
 

]]> Mon, 26 Mar 2012 05:46:12 -0600 Implementing Interprocessor Communication Using Cypress MoBL(R) Dual-Ports and the Mailbox Registers - AN5074 http://www.cypress.com/?rID=12668
The Cypress Semiconductor MoBL(R) dual-ports provide an ultra low-power, high-bandwidth, flexible solution for the intercommunication of two processing elements. The MoBL dual-port removes the necessity for processing elements to communicate with a protocol such as I2C, SPI or UART. In addition, the MoBL dual-port provides a way to interconnect processing elements with different clock frequencies, bus widths, I/O voltages, and at bandwidths in excess of 400 Mbit/s. ]]> Thu, 27 Oct 2011 15:09:33 -0600 AN5075 - Migrating from Cypress CYDMxxxAxx MoBL(R) Dual-Ports to CYDMxxxBxx MoBL Dual-Ports http://www.cypress.com/?rID=51171 The Cypress CYDMxxxAxx and CYDMxxxBxx MoBL® Dual-Ports are high-speed, low-power interconnects that provide two independent ports with simultaneous read/write access to the shared memory core. Both devices have full asynchronous operation and on-chip arbitration logic. The devices also offer features such as the Input Read Registers (IRR) and Output Drive Registers (ODR).  

 


]]> Tue, 10 May 2011 10:26:43 -0600 AN5093 - Cypress MoBL(R) Dual-Port 100-Ball VFBGA Printed Circuit Board (PCB) Layout Guidelines http://www.cypress.com/?rID=51164 MoBL® Dual-Port is a specialty memory product offered by Cypress Semiconductor targeted for handheld applications. It provides a flexible processor interconnect solution that is low-power and high-bandwidth.

]]> Tue, 10 May 2011 07:08:06 -0600 Interfacing Cypress MoBL&reg; Asynchronous Dual- Port to TI OMAP2420 Multimedia Processor - AN5056 http://www.cypress.com/?rID=48515 Tue, 25 Jan 2011 03:55:26 -0600