USB has long been the interface of choice between PCs and their peripherals. However, many legacy PCs still use an RS232 serial interface— in some cases referred to as a UART interface—to communicate with their peripherals.

Cypress’s USB-to-UART Bridge Controller enables seamless connectivity between USB and UART devices. It is a low-power, single-chip, plug-and-play solution that is easy to design and reuses existing application software and firmware—accelerating time to market.

Standard 8051 Interrupts:

• IE0(INT0): External Interrupt0
• IE1(INT1): External Interrupt1
• RI_0 & TI_0: USART1 Interrupt
• TF0: Timer0 Overflow
• TF1: Timer1 Overflow

Additional EZ-USB interrupts:

• TF2: Timer2 Overflow
• PF1: Wake up pin(WU2)
• RI_1 & TI_1: UART 1 Transmit and receive
• USBINT(INT2): USB specific Interrupt
• I2CINT(INT3): I2C Bus Interrupt
• IE4(INT4): External Interrupt 4
• IE5(INT5): External Interrupt 5
• IE6(INT6): External Interrupt 6
   

For more, see pdf.

Introduction

Cypress's EZ-USB® FX3 is the next-generation USB 3.0 peripheral controller, providing integrated and flexible features. FX3 has a fully configurable, parallel, general programmable interface called GPIF II, which can connect to any processor, ASIC, or FPGA. It provides easy and glue less connectivity to popular interfaces, such as asynchronous SRAM, asynchronous and synchronous address data multiplexed interfaces, and parallel ATA. FX3 has an embedded 32-bit ARM926EJ-S microprocessor for powerful data processing and for building custom applications. It implements an architecture that enables 375-MBps data transfer from GPIF II to the USB interface. 

Cypress's FLEx18 / FLEx36® / FLEx72™ portfolio of highdensity, high-performance synchronous Dual-Port SRAMs can operate at speeds up to 167 MHz. In the fast growing data communications market, the bandwidth requirements have increased. Cypress addresses these demands with its FullFlex Dual-Port SRAMs, which can operate up to 200 MHz.

The video describes the case of using a DMA to buffer ADC data. Buffering of 20 bit ADC data is taken as an example and discussed. The video also gives a preview of the project implementing the 20 bit data buffering and explains the DMA configuration in code.

The following table indicates the PSoC devices, PSoC Creator versions, compilers, and development kits that will work with this application note project:

*Refer to Migrating CY8CKIT-001 DVK project to CY8CKIT 030/ 050. 

Notes:

1. Click on AN84741 - PSoC® 5 to PSoC 5LP Migration Guide to learn differences between PSoC 5 and PSoC 5LP.
2. Click on AN77835 - PSoC® 3 to PSoC 5LP Migration Guide to learn differences between PSoC 3 and PSoC 5LP.
3. For PSoC 5 project and related document, please download file AN61102_Archive.zip.

Projects associated with this application note can be downloaded from the ‘Related Files’ section below. For your convenience, we have provided projects that are compatible with the two most recent versions of PSoC Creator:

• AN61102.zip is used with PSoC Creator 2.1 SP1
• AN61102_Archive.zip is used with PSoC Creator 2.1/2.0

The project’s default settings may not be compatible with your device or kit, and you may need to change your project settings. For more information, see:

EZ-USB® FX3 is the next generation USB 3.0 peripheral controller, providing highly integrated and flexible features that enable developers to add USB 3.0 functionality to a wide range of applications.

FX3 supports several boot options including booting over I2C, SPI, USB, Synchronous ADMux and Asynchronous SRAM interfaces. This application note describes the details of the different booting options for FX3.

The default state of the FX3 IOs during boot are also documented. The Appendix describes the step-wise sequence for testing the different boot modes using the FX3 DVK.

Introduction

USB is so commonplace that it has almost completely replaced other communication methods between peripheral devices and a PC. This holds true both for general-purpose devices, such as flash drives and mice, and special-purpose devices for specific applications. According to the standard USB 2.0 specification, USB peripherals do not communicate directly with one another; they may communicate only with a USB host, which fully controls data traffic on the bus. The Cypress EZ-USB FX3 with integrated high-speed USB host controller, along with the USB function and On-The-Go (OTG) capabilities accomplishes two things: It retains the device functions and allows embedded systems to act as a USB host.

The TMP05 Digital Temperature Sensor Interface Component is a building block for thermal management applications. It enables designers using PSoC 3 to quickly and easily interface with Analog Devices’ TMP05 or TMP06 digital temperature sensors through a simple, serial 2-wire digital interface. The sensors can be daisy-chained together, minimizing I/O requirements on the controller. For more details on the specific functions of the TMP05 Digital Temperature Sensor Interface Component, refer to the component datasheet.

Notes:

1. Click on AN84741 - PSoC® 5 to PSoC 5LP Migration Guide to learn differences between PSoC 5 and PSoC 5LP.
2. For PSoC 5 project and related document, please download file AN65977_Archive.zip.

Projects associated with this application note can be downloaded from the 'Related Files' section below. For your convenience, we have provided projects that are compatible with the two most recent versions of PSoC Creator:

• AN65977.zip is used with PSoC Creator 2.1 SP1
• AN65977_Archive.zip is used with PSoC Creator 2.1/2.0

The project’s default settings may not be compatible with your device or kit, and you may need to change your project settings. For more information, see:

The nvSRAM architecture uses a one-to-one pairing of a nonvolatile bit and a fast SRAM bit in each memory cell. During normal operation, the IC behaves exactly as a standard fast asynchronous SRAM and is easy to interface with the microprocessor or microcontroller. When IC power is disrupted or lost, the event is detected and all the SRAM bits are saved into the nonvolatile part (within 8 ms) using the stored energy in a small capacitor (VCAP). This operation is called AutoStore and is described in more detail in the next section. When power is restored, data is automatically recalled from the nonvolatile part to SRAM on power restore and this operation is called Power Up RECALL (Hardware RECALL).
 

Sleep mode is used to reduce a PSoC’s average current consumption by entering a low-power state, whenever the CPU and other internally clocked functions are not needed. Sleep mode is most useful for battery-powered systems, but it is applicable to any design.

The document AN66477 - PSoC® 3 and PSoC 5 Temperature Measurement with Thermistor is currently being reviewed and updated to support the new Thermistor Component available in PSoC Creator 2.1. The updated application note is expected by 11/30/2012. The below abstract describes what this application note covers. If you have an immediate need for this document, please click here to create a technical support case requesting this material. 

Please note that the Thermistor Component is now provided in PSoC Creator 2.1. Please access the Thermistor Component Datasheet for features and configuration details. 

AN66477 Abstract:

AN66477 explains how to measure temperature with a thermistor using PSoC® 3 or PSoC 5LP®. This application note describes the PSoC Creator™ Thermistor Calculator Component, which simplifies the math-intensive resistance-to-temperature conversion. In addition, we discuss a PSoC Creator thermistor measurement project.

1. Click on AN84741 - PSoC® 5 to PSoC 5LP Migration Guide to learn differences between PSoC 5 and PSoC 5LP.
2. Click on AN77835 - PSoC® 3 to PSoC 5LP Migration Guide to learn differences between PSoC 3 and PSoC 5LP.

General-purpose input and output (GPIO) is a very critical part of any microcontroller unit (MCU) as they form the bridge between the external world and the MCU. The type and nature of this external world bridge depends on the end application. For instance, an ADC requires a GPIO to be an analog pin whereas an I2C or SPI digital communication block requires the same GPIO to be digital. In order to properly setup this external world bridge, you need to know not only the end application but also the GPIO system of the MCU that is used. PSoC like any other controller has its own GPIO system. This application note discusses the application specific parameters of the GPIO system. Detailed technical overview of the system can be found in the respective device technical reference manual (TRM) under General Purpose I/O chapter of PSoC Core section.
 

1. Click on AN84741 - PSoC® 5 to PSoC 5LP Migration Guide to learn differences between PSoC 5 and PSoC 5LP.

An FX2LP™-FPGA interface is implemented to add High-Speed USB connectivity for FPGA based applications, such as data acquisition, industrial control and monitoring, and image processing. The FX2LP acts in Slave-FIFO mode and the FPGA acts as the master. This Application Note also gives a sample FX2LP firmware for Slave-FIFO implementation and a sample VHDL and Verilog project for FPGA implementation.

 

In addition, this application note walks you through an example project for PSoC 5LP. Through this project example, PSoC Creator is introduced. The first part of the project guides you on how to blink an LED like a typical MCU. In the second part you develop a "breathing" LED using the Programmable-System-On-Chip concept.

An additional bonus project is included with this application note that takes a design example a little farther than simply blinking LEDs. The bonus project uses some of the mixed signal functionality of PSoC 5LP to create an ambient light/dark detector using one of the LEDs on the CY8CKIT-050 demonstration board. 

The following table indicates the PSoC devices, PSoC Creator versions, compilers, and development kits that will work with this application note project:

*Refer to Migrating CY8CKIT-001 DVK project to CY8CKIT 030/050.

1. Click on AN84741 - PSoC® 5 to PSoC 5LP Migration Guide to learn differences between PSoC 5 and PSoC 5LP.
2. For PSoC 5 project and related document, please download file AN77759_Archive.zip.
3. Click on AN77835, PSoC 3 to PSoC 5LP Migration Guide. to learn differences between PSoC 3 and PSoC 5LP

Projects associated with this application note can be downloaded from the 'Related Files' section below. For your convenience, we have provided projects that are compatible with the two most recent versions of PSoC Creator:

• AN77759.zip is used with PSoC Creator 2.1 SP1
• AN77759_Archive.zip is used with PSoC Creator 2.1/2.0

The project’s default settings may not be compatible with your device or kit, and you may need to change your project settings. For more information, see:

The following table indicates the PSoC devices, PSoC Creator versions, compilers, and development kits that will work with this application note project:

Refer to Migrating CY8CKIT-001 DVK project to CY8CKIT 030/ 050.

Introduction

PSoC® 3 and PSoC 5LP have a powerful clocking system. This system offers the flexibility and performance to suit the needs of most embedded applications. It is comprised of clock sources and a clock distribution network. The clock sources available are the internal main oscillator (IMO), external crystal oscillators (ECO) and internal low-speed oscillator (ILO). This application note describes the IMO and ILO as well a method to improve their accuracy through run-time calibration.

The following table indicates the PSoC devices, PSoC Creator versions, compilers, and development kits that will work with this application note project:

Notes:

1. Click on AN84741 - PSoC® 5 to PSoC 5LP Migration Guide to learn differences between PSoC 5 and PSoC 5LP.
2. Click on AN77835 - PSoC® 3 to PSoC 5LP Migration Guide to learn differences between PSoC 3 and PSoC 5LP.
3. For PSoC 5 project and related document, please download file AN80248_Archive.zip.

Projects associated with this application note can be downloaded from the 'Related Files' section below. For your convenience, we have provided projects that are compatible with the two most recent versions of PSoC Creator:

• AN80248.zip is used with PSoC Creator 2.1 SP1
• AN80248_Archive.zip is used with PSoC Creator 2.1/2.0

The project’s default settings may not be compatible with your device or kit, and you may need to change your project settings. For more information, see:

Introduction

The EZ-USB FX2LP is an excellent solution if you want to a high-performance high-speed USB to a design. In applications similar to a TV dongle, an MPEG2-TS to USB Bridge is critical. The EZ-USB FX2LP not only takes care of glueless logic, but also makes it easier for the designer to complete the design. This application note addresses the hardware connections and example firmware required to implement the MPEG2-TS interface using the Slave FIFO mode.

现在在中国 !!

今日本語で !!  

Introduction

   Cypress's Programmable System-on-Chip (PSoC®) integrates a microcontroller with programmable analog and digital peripherals. Because you can configure the resources of a PSoC, you can develop a device that is customized and tuned for your application. Moreover, as the needs of the application change during development and in production, you can reconfigure the device to adapt to these new requirements with minimal effort.   
   

Getting Started with PSoC 1 - Part 1 - Architecture and System Resources

Getting Started with PSoC 1 - Part 2 - Digital Subsystem

Getting Started with PSoC 1 - Part 3 - Analog architecture

Getting Started with PSoC 1 - Part 4 - My first PSoC Designer Project

CAN (Controller Area Network) is a serial communication protocol developed by Robert Bosch GmbH in the early 1980s. This protocol was initially developed for automotive applications to communicate between subsystems without a central control. CAN is also being adopted in areas such as embedded systems (CANOpen) and factory automation (DeviceNet). CAN was standardized by ISO in 2003 (ISO 11898-1:2003).

This application note introduces the basic concepts of CAN protocol and demonstrates how CAN bus communication can be implemented using PSoC® 3 and PSoC 5LP (hereafter referred to as PSoC). Four code examples are included with this application note. Examples 1 and 2 together illustrate a simplex communication between two PSoCs. Examples 3 and 4 together demonstrate the Remote Transmission Request (RTR) feature of CAN.

The video talks about how to transmit and receive messages using CAN controller available in PSoC3.

The following table indicates the PSoC devices, PSoC Creator versions, compilers, and development kits that will work with this application note project:

*Refer to Migrating CY8CKIT-001 DVK project to CY8CKIT 030/ 050.

1. Click on AN84741 - PSoC® 5 to PSoC 5LP Migration Guide to learn differences between PSoC 5 and PSoC 5LP.
2. Click on AN77835 - PSoC® 3 to PSoC 5LP Migration Guide to learn differences between PSoC 3 and PSoC 5LP.
3. For PSoC 5 project and related document, please download file AN52701_Archive.zip.

Projects associated with this application note can be downloaded from the ‘Related Files’ section below. For your convenience, we have provided projects that are compatible with the two most recent versions of PSoC Creator:

• AN52701.zip is used with PSoC Creator 2.1 SP1
• AN52701_Archive.zip is used with PSoC Creator 2.1/2.0

The project’s default settings may not be compatible with your device or kit, and you may need to change your project settings. For more information, see:

Introduction

The DMA controller (DMAC) in PSoC 3 and PSoC 5LP can transfer data from a source to a destination with no CPU intervention. This allows the CPU to handle other tasks while the DMA does data transfers, thereby achieving a „multiprocessing‟ environment.

The PSoC DMA Controller (DMAC) is highly flexible – it can seamlessly transfer data between memory and on chip peripherals including ADCs, DACs, Filter, USB, UART, and SPI. There are 24 independent DMA channels.

 The following video gives the user a brief description of how to use the DMA on PSoC3 and the different parameters related to it:

The following table indicates the PSoC devices, PSoC Creator versions, compilers, and development kits that will work with this application note project:

 *Refer to Migrating CY8CKIT-001 DVK project to CY8CKIT 030/ 050. 

1. Click on AN84741 - PSoC® 5 to PSoC 5LP Migration Guide to learn differences between PSoC 5 and PSoC 5LP.
2. For PSoC 5 project and related document, please download file AN52705_Archive.zip.

Projects associated with this application note can be downloaded from the ‘Related Files’ section below. For your convenience, we have provided projects that are compatible with the two most recent versions of PSoC Creator:

• AN52705.zip is used with PSoC Creator 2.1 SP1
• AN52705_Archive.zip is used with PSoC Creator 2.1/2.0

The project’s default settings may not be compatible with your device or kit, and you may need to change your project settings. For more information, see:

In this application note, we use a CY3660 Development Kit (DVK) to demonstrate wireless data exchange between two enCoRe™ V LV devices each using the WirelessUSB™-LP Radio. The CY3660 DVK includes two enCoRe V LV development boards, each with a WirelessUSB-LP radio. With the PSoC® Designer™ projects attached to this application, we configure one board for data transmission and the second board for data reception.

PSoC® 1 - Getting Started with SPI

PSoC 1, PSoC 3, and PSoC 5LP are all true programmable embedded system-on-chips that integrate configurable analog, programmable digital, memory, and a central processor on a single chip.

PSoC contains a processor, but it is not an MCU. The name PSoC (Programmable-System-on-Chip) defines its true identity. AN54181 introduces the Programmable-System-on-Chip concept with specific emphasis on PSoC 3. Here, you learn about PSoC 3 and what it can do for you and your projects. It also introduces PSoC Creator™, a powerful IDE development tool for PSoC 3 and PSoC 5LP.

The following video gives brief introduction for PSoC3:

The following video guides how to create projects using PSoC3:

The following table indicates the PSoC devices, PSoC Creator versions, compilers, and development kits that will work with this application note project:

*Refer to Migrating CY8CKIT-001 DVK project to CY8CKIT 030/050. 

1. Click on AN84741 - PSoC® 5 to PSoC 5LP Migration Guide to learn differences between PSoC 5 and PSoC 5LP.
2. Click on AN77835 - PSoC® 3 to PSoC 5LP Migration Guide to learn differences between PSoC 3 and PSoC 5LP.
3. For PSoC 5 project and related document, please download file AN54181_Archive.zip.

Projects associated with this application note can be downloaded from the ‘Related Files’ section below. For your convenience, we have provided projects that are compatible with the two most recent versions of PSoC Creator:

• AN54181.zip is used with PSoC Creator 2.1 SP1
• AN54181_Archive.zip is used with PSoC Creator 2.1/2.0.

The project’s default settings may not be compatible with your device or kit, and you may need to change your project settings. For more information, see:

To get introduced to basics of PSoC 3 and PSoC 5LP Bootloader please refer  AN73854 - PSoC® 3 and PSoC 5LP - Introduction to Bootloaders. If you intend to learn how to develop I2C Bootloader for PSoC 3 and PSoC 5LP,  AN60317 - PSoC® 3/PSoC 5LP I2C Bootloader  should get you going. 

Since the projects involve the use of USB component, in case of PSoC 5LP it is mandatory to use an external 24 MHz crystal.

The Bootloader GUI provided with this App Note has been tested to work on full-fledged Windows operating system only.
The GUI is not tested and not guaranteed to work on Virtual machines.
 

*Refer to Migrating CY8CKIT-001 DVK project to CY8CKIT 030/ 050. 

Notes:

1. Click on AN84741 - PSoC® 5 to PSoC 5LP Migration Guide to learn differences between PSoC 5 and PSoC 5LP.
2. Click on AN77835 - PSoC® 3 to PSoC 5LP Migration Guide to learn differences between PSoC 3 and PSoC 5LP.
3. For PSoC 5 project and related document, please download file AN73503_Archive.zip.

Projects associated with this application note can be downloaded from the ‘Related Files’ section below. For your convenience, we have provided projects that are compatible with the two most recent versions of PSoC Creator:

• AN73503.zip is used with PSoC Creator 2.1 SP1
• AN73503_Archive.zip is used with PSoC Creator 2.1/2.0

The project’s default settings may not be compatible with your device or kit, and you may need to change your project settings. For more information, see:

Introduction

HX2VL is the next-generation family of high-performance, low-power USB 2.0 hub controllers. The HX2VL has integrated upstream and downstream transceivers, a USB serial interface engine (SIE), USB hub control and repeater logic, and transaction translator (TT) logic. The HX2VL portfolio has Single-TT and Multi-TT versions, lowcost options with high performance.

Introduction

System cooling is a critical task in any high performance electronic system. As circuit miniaturization continues, increasing demands are placed on system designers to improve the efficiency of their thermal management designs. Usually thermal management is done by forced convection. In forced convection the heat dissipation is increased by moving the air inside and around the heat source. This can be easily accomplished using Brushless DC (BLDC) based fans. The speed of these fans depends on DC voltage across these fans.

Introduction

This application note focuses on an RF-based remote control device operating over the 2.4-GHz ISM (industrial, scientific, and medical) band. Because it uses Cypress’s proprietary WirelessUSB-NL radio, the device overcomes the following shortcomings of IR-based remote control:

• line-of-sight pointing
• limited operating angles
• short transmission range
• reflection problems
• high current consumption

PSoC® 3 and PSoC 5LP (hereafter referred to as PSoC) are more than just microcontrollers. With PSoC you can integrate the functions of a microcontroller, complex programmable logic device (CPLD) and high-performance analog with unmatched flexibility. This saves cost, board space, power and development time.

This application note introduces the PLDs in the PSoC Universal Digital Block (UDB), and then teaches how to use them by creating PSoC Creator components. It is an effective first step in porting complex programmable logic device (CPLD) functionality to PSoC. After reading this application note, you should be familiar with PSoC PLDs, and be able to create your own custom Verilog-based components using PSoC Creator™.

* Refer to Migrating CY8CKIT-001 DVK project to CY8CKIT 030/ 050.

Notes:

1. Click on AN84741 - PSoC® 5 to PSoC 5LP Migration Guide to learn differences between PSoC 5 and PSoC 5LP.
2. For PSoC 5 project and related document, please download file AN82250_Archive.zip.

Projects associated with this application note can be downloaded from the 'Related Files' section below. For your convenience, we have provided projects that are compatible with the two most recent versions of PSoC Creator:

• AN82250.zip is used with PSoC Creator 2.1 SP1
• AN82250_Archive.zip is used with PSoC Creator 2.1/2.0

The project’s default settings may not be compatible with your device or kit, and you may need to change your project settings. For more information, see:

*Refer to Migrating CY8CKIT-001 DVK project to CY8CKIT 030/ 050.

1. Click on AN84741 - PSoC® 5 to PSoC 5LP Migration Guide to learn differences between PSoC 5 and PSoC 5LP.
2. Click on AN77835 - PSoC® 3 to PSoC 5LP Migration Guide to learn differences between PSoC 3 and PSoC 5LP.
3. For PSoC 5 project and related document, please download file AN77900_Archive.zip.

Projects associated with this application note can be downloaded from the 'Related Files' section below. For your convenience, we have provided projects that are compatible with the two most recent versions of PSoC Creator:

• AN77900.zip is used with PSoC Creator 2.1 SP1
• AN77900_Archive.zip is used with PSoC Creator 2.1/2.0

The project’s default settings may not be compatible with your device or kit, and you may need to change your project settings. For more information, see:

Systems that rely on electronic subsystems for their functionality use EDRs to store information about system status as it evolves after a critical event occurs. A critical event typically stops the system from functioning.

An EDR, such as the one described in this application note, monitors communication among electronic subsystems (controller area network nodes) and records all or selected information. Moreover, an EDR can store information collected and processed locally from various sensors.

The following table indicates the PSoC devices, PSoC Creator versions, compilers, and development kits that will work with this application note project:

Refer to Migrating CY8CKIT-001 DVK project to CY8CKIT 030/ 050.

The project associated with this application note can be downloaded from the ‘Related Files’ section below.

Overview

Cypress EZ-USB FX2LP™ is one of the most popular programmable high-speed USB controllers in the industry. This application note has two parts.

Host application: This application is built on the Microsoft Visual C# 2008 platform. The application communicates to BULK IN and BULK OUT endpoints of  FX2LP™ using the interfaces given by CyUSB.dll. The CyUSB.dll, in-turn communicates internally with the Cypress USB driver CyUSB.sys, for talking to these endpoints.

Target firmware: This describes related firmware residing on target, which transfers the data sent from the host application on BULK OUT endpoint to the BULK IN endpoint, for sending it back to the host application in loopback fashion.

Overview

AN70486 describes a host application built on the Microsoft Visual C++ 2008 platform that uses CyUSB.dll to communicate with Cypress USB driver, CyUSB.sys. The host application communicates with the BULK IN and BULK OUT endpoints of FX2LP, using the interfaces provided by the APIs of CyUSB.dll. The CyUSB.dll in-turn communicates internally with Cypress USB driver (CyUSB.sys), for talking to these endpoints. This host application implements the transfer only with devices that pass the particular VID/PID identification. The example device used in this application note is the Bulkloop device. The firmware that is attached along with this application note causes a loop back of data inside the device. Thus this host application, with the attached Bulkloop device, demonstrates the loopback of data.

Cypress's 90nm technology Asynchronous SRAMs have best-in-class specifications in speed and power making them an ideal choice as memories in a wide variety of applications today.

The application note below discusses how they are suited for present generation processors and controllers while Cypress' older generation SRAMs (250nm and 350nm) are a good fit for interfacing with legacy processors and controllers. The 90nm technology 5V devices are pin compatible with their older technology counterparts. The reason for Cypress continuing to support end users with older generations SRAMs is because of their increased V_OH levels that ensure compliance with CMOS V_IH levels of legacy processors and microcontrollers. While both generations of SRAM's have the same industry standard V_OH spec, the difference in actual V_OH levels enable Cypress to support processors of older and present generations, reiterating Cypress' commitment as the #1 supplier in the industry.

Please see the illustrations and the application note below for details.

Processor receiving data from SRAM on a read operation:

Introduction

Have you maxed out your CPU bandwidth? PSoC 3 and PSoC 5LP UDBs can lighten the load on your CPU by creating intelligent custom peripherals. The datapaths in those UDBs can be used to create sophisticated multiprocessor-based designs.

Many PSoC customers have experience writing HDL code for CPLDs or FPGAs. PSoC 3 and PSoC 5LP support Verilog for PLDs. However, PSoC 3 and PSoC 5LP PLDs are smaller than full-fledged CPLDs or FPGAs, and many designs are too large for PSoC 3 and PSoC 5LP. PSoC’s unique datapath modules remove this obstacle by integrating one or more small 8-bit processors into PLD-based designs.

1. Click on AN84741 - PSoC® 5 to PSoC 5LP Migration Guide to learn differences between PSoC 5 and PSoC 5LP.
2. Click on AN77835 - PSoC® 3 to PSoC 5LP Migration Guide to learn differences between PSoC 3 and PSoC 5LP.
3. For PSoC 5 project and related document, please download file AN82156_Archive.zip.

Projects associated with this application note can be downloaded from the 'Related Files' section below. For your convenience, we have provided projects that are compatible with the two most recent versions of PSoC Creator:

• AN82156.zip is used with PSoC Creator 2.1 SP1
• AN82156_Archive.zip is used with PSoC Creator 2.1/2.0

The project’s default settings may not be compatible with your device or kit, and you may need to change your project settings. For more information, see:

The following table provides the list of devices, the supported Creator version, Development kit and Compiler for this application note project:

*Refer to Migrating CY8CKIT-001 DVK project to CY8CKIT 030/ 050.

1. Click on AN84741 - PSoC® 5 to PSoC 5LP Migration Guide to learn differences between PSoC 5 and PSoC 5LP.
2. Click on AN77835 - PSoC® 3 to PSoC 5LP Migration Guide to learn differences between PSoC 3 and PSoC 5LP.
3. For PSoC 5 project and related document, please download file AN58726_Archive.zip.

Projects associated with this application note can be downloaded from the ‘Related Files’ section below. For your convenience, we have provided projects that are compatible with the two most recent versions of PSoC Creator:

• AN58726.zip is used with PSoC Creator 2.1 SP1
• AN58726_Archive.zip is used with PSoC Creator 2.1/2.0

The project’s default settings may not be compatible with your device or kit, and you may need to change your project settings. For more information, see:

Below are some of videos demonstrating  how to impliment bulk transfers and vendor commands which are discussed in this application note.

The following table indicates the PSoC devices, PSoC Creator versions, compilers, and development kits that will work with this application note project:

*Refer to Migrating CY8CKIT-001 DVK project to CY8CKIT 030/ 050. 

Notes:

1. Click on AN84741 - PSoC® 5 to PSoC 5LP Migration Guide to learn differences between PSoC 5 and PSoC 5LP.
2. For PSoC 5 project and related document, please download file AN56377_Archive.zip.

Projects associated with this application note can be downloaded from the ‘Related Files’ section below. For your convenience, we have provided projects that are compatible with the two most recent versions of PSoC Creator:

• AN56377.zip is used with PSoC Creator 2.1 SP1
• AN56377_Archive.zip is used with PSoC Creator 2.1/2.0

The project’s default settings may not be compatible with your device or kit, and you may need to change your project settings. For more information, see:
Information on application note projects compatible with PSoC Creator 1.0 SP2
PSoC® 3 and PSoC 5 AN/CE project file naming convention and usage

If instead of PSoC 3 you want to migrate a PSoC 5 design to PSoC 5LP, please see AN84741, PSoC 5 to PSoC 5LP Migration Guide, instead of this application note.

The PSoC 3 and PSoC 5LP devices are designed for easy migration from PSoC 3 to PSoC 5LP. Although there are some differences such as the CPU cores, the programmable analog, programmable digital, programmable routing, pin functions, and other features are quite similar. Furthermore, the PSoC Creator IDE handles a lot of the migration issues for you, automatically. Often, migrating a PSoC Creator design is as simple as specifying a new part then rebuilding the project.

If, instead of PSoC 5, you want to migrate from a PSoC 3 design to PSoC 5LP, see AN77835, PSoC 3 to PSoC 5LP Migration Guide.

The PSoC 5 and PSoC 5LP devices are designed for easy migration from PSoC 5 to PSoC 5LP. Although there are some differences such as additional features in PSoC 5LP, the programmable analog, programmable digital, programmable routing, pin functions, and other features are quite similar. Furthermore, the PSoC Creator IDE handles a lot of the migration issues for you, automatically. Often, migrating a PSoC Creator design is as simple as specifying a new part and then rebuilding the project.

There are generally two types of PLC systems: high-bandwidth (video, audio, and so on) and low-bandwidth (command and control). This application note describes how to implement a low-bandwidth, half-duplex PLC solution with the PSoC 5LP family of devices.

The following table indicates the PSoC devices, PSoC Creator versions, compilers, and development kits that will work with this application note project:

1. Click on AN84741 - PSoC® 5 to PSoC 5LP Migration Guide to learn differences between PSoC 5 and PSoC 5LP.
2. For PSoC 5 project and related document, please download file AN76458_Archive.zip.

Projects associated with this application note can be downloaded from the 'Related Files' section below. For your convenience, we have provided projects that are compatible with the two most recent versions of PSoC Creator:

• AN76458.zip is used with PSoC 5LP and PSoC Creator 2.1 SP1
• AN76458_Archive.zip is used with PSoC 5 and PSoC Creator 2.1/2.1 SP1.

The project’s default settings may not be compatible with your device or kit, and you may need to change your project settings. For more information, see:

The application note describes the three modes in which the TMP05/06 sensors can be interfaced followed by sample projects interfacing the sensors with a CY8C28xxx device through a simple, serial 2-wire digital interface. After reading the application note, a designer should be able to use the project attached to interface any PSoC 1 to TMP05 and TMP06 sensors in all the three modes described.

This application note assumes that the reader is familiar with PSoC 1, PSoC Designer IDE and programming in C.

For PSoC® 3 based implementation of TMP05/06 sensor interface refer - AN65977
 

This video explains briefly how to implement amplitude modulation (AM) and demodulation using PSoC3 or PSoC 5LP controller.

The following table indicates the PSoC devices, PSoC Creator versions, compilers, and development kits that will work with this application note project:

*Refer to Migrating CY8CKIT-001 DVK project to CY8CKIT 030/ 050. 

1. Click on AN84741 - PSoC® 5 to PSoC 5LP Migration Guide to learn differences between PSoC 5 and PSoC 5LP.
2. Click on AN77835 - PSoC® 3 to PSoC 5LP Migration Guide to learn differences between PSoC 3 and PSoC 5LP.
3. For PSoC 5 project and related document, please download file AN62582_Archive.zip.

Projects associated with this application note can be downloaded from the ‘Related Files’ section below. For your convenience, we have provided projects that are compatible with the two most recent versions of PSoC Creator:

• AN62582.zip is used with PSoC Creator 2.1 SP1
• AN62582_Archive.zip is used with PSoC Creator 2.1/2.0

The project’s default settings may not be compatible with your device or kit, and you may need to change your project settings. For more information, see:

This AN also talks about the method to reduce the 3^rd and 5^th harmonics by using a dead band PWM generator and a band-pass filter.

In order to be able to understand the functionality better, following pre-readings are suggested:

AN2168: Understanding switched capacitor filters - Discusses how low pass, band pass and notch filters can be implemented using switched capacitor blocks.

KB Article: Generation of non-overlapping signals using dead band PWM generator.

Introduction

Temperature measurements typically use one of four sensors: thermocouple, thermistor, diode, and resistance temperature detector (RTD). The primary criteria for choosing a sensor are cost, accuracy, and temperature range. Although they are more expensive than other sensor types, RTDs have the best temperature accuracy. Calibrated platinum RTDs can achieve accuracy of >0.02 °C in the -200 °C to 850 °C range.

The following table indicates the PSoC devices, PSoC Creator versions, compilers, and development kits that will work with this application note project:
 

* Refer to Migrating CY8CKIT-001 DVK project to CY8CKIT 030/ 050.

Notes:

1. Click on AN84741 - PSoC® 5 to PSoC 5LP Migration Guide to learn differences between PSoC 5 and PSoC 5LP.
2. Click on AN77835 - PSoC® 3 to PSoC 5LP Migration Guide to learn differences between PSoC 3 and PSoC 5LP.
3. For PSoC 5 project and related document, please download file AN70698_Archive.zip.

Projects associated with this application note can be downloaded from the 'Related Files' section below. For your convenience, we have provided projects that are compatible with the two most recent versions of PSoC Creator:

• AN70698.zip is used with PSoC Creator 2.1 SP1
• AN70698_Archive.zip is used with PSoC Creator 2.1/2.0

The project’s default settings may not be compatible with your device or kit, and you may need to change your project settings. For more information, see:

*Refer to Migrating CY8CKIT-001 DVK project to CY8CKIT 030/ 050.

1. Click on AN84741 - PSoC® 5 to PSoC 5LP Migration Guide to learn differences between PSoC 5 and PSoC 5LP.
2. Click on AN77835 - PSoC® 3 to PSoC 5LP Migration Guide to learn differences between PSoC 3 and PSoC 5LP.
3. For PSoC 5 project and related document, please download file AN75111_Archive.zip.

Projects associated with this application note can be downloaded from the 'Related Files' section below. For your convenience, we have provided projects that are compatible with the two most recent versions of PSoC Creator:

• AN75111.zip is used with PSoC Creator 2.1 SP1
• AN75111_Archive.zip is used with PSoC Creator 2.1/2.0

The project’s default settings may not be compatible with your device or kit, and you may need to change your project settings. For more information, see:

Please contact Innovatech Switching Power India Pvt. Ltd. to buy evaluation boards shown in this applicaiton note. Please refer http://ispipl.com/contact_us for more information.

The video demonstrates a PowerPSoC based battery charger and LED controller for standalone solar electric systems.

PowerPSoC product family provides a highly integrated platform for designing intelligent LED driver circuits that can be used in small form factors such as MR-16. This application note describes the design of a DMX512-enabled LED driver circuit for MR-16 using PowerPSoC. The application note also gives a top level description of the MR-16 fixture and the LED driver board reference design. It also briefly explains the board bring up and operation procedure. The application has an associated code example, which has sample firmware for multicolor lamps and tunable white light systems with DMX512 interface using PowerPSoC. A brief descirpion of the code example is also included in the applicaiton note.

PowerPSoC(R) - Designing LED Driver Circuits For MR-16 Lamps With DMX-512 Interface

Because PSoC 1 offers billions of configuration options, the PSoC device must be properly initialized after reset to fulfill its potential. The PSoC Designer boot process performs these necessary initialization tasks before entering main to provide an optimal working environment. This application note explains the device initialization procedure, but this document is not required reading for users of PSoC 1 or the PSoC Designer integrated development environment (IDE). The information is for users seeking a deeper understanding of PSoC and PSoC Designer initialization before main is executed.

PSoC® 1 Boot Process from Reset to Main

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Several common debugging techniques are described to help you solve common problems, such as stack overflow and memory corruption. A troubleshooting guide is included. 

Introduction

The purpose of this application note is to introduce the hardware and software debugger elements available in PSoC 1 and to describe several common debugging techniques.

The primary hardware elements of the debugging system are an In-Circuit-Emulator (ICE) and a debug pod with an on chip debugger (OCD) enabled PSoC 1 device. Those elements, and instructions on configuring and using them, are described in the Debugging Hardware portion of this application note.

PSoC 1 Getting Started Debugging - Part 1

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Introduction

When designing with the PSoC 1 family of microcontrollers, you use PSoC Designer and its highlevel interface to configure the PSoC, including the analog architecture. In addition to placing and configuring the individual user modules (building blocks), several global analog parameters also require configuration. Understanding these global parameters and the overall analog architecture is important, especially when a design consists of several analog user modules that are affected by these settings.
 

In the following videos, Dave implements Analog to Digital converters in a project and shows the tools he'll be using for designing robust analog-output sensor signal paths.

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The focus of the application note is on features specific to the ImageCraft compiler that can be modified to optimize code. General code optimization techniques for C language are only handled briefly in this application note.

This application note is for PSoC1 M8C CPU.

For PSoC3 8051 CPU, please see AN60630 - PSoC® 3 - 8051 Code Optimization

For PSoC5 ARM Cortex-M3 CPU, please see ARM Documentation

Segment LCDs are available in two forms - segment LCD glass and the segment LCD module, which comes with inbuilt driver. Many times, it is difficult to get all the required display features on a LCD module. One possibility is to use a custom LCD glass and an external driver. But this increases the cost of the system. Cypress PSoC chip can do segment LCD glass drive besides executing some other major tasks with its configurable digital/analog hardware and with its 8-bit MCU. It integrates multiple functions of the system within a single chip offering significant BOM savings.

To assist in design development, PSoC Designer provides SLCD user module. It supports following features:

• Multiplexed LCD glass drive, 1/2 bias
• 2, 3 and 4 common LCD drive
• 30Hz to 150Hz refresh rate
• Type A waveform
• Contrast control 

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The source code provided can be easily ported to any microntroller used as the host in the system. However, the application note does not describe the programming protocol. For details on programming protocol, please refer to the following documents:

• PSoC1 – Device programming specifications (AN2026A) – ISSP programming specifications for following device families: CY8C21x23, CY8C21x34, CY8C23x33, CY8C24x23A, CY8C27x43, CY8CTMG110, CY8CTST110

• PSoC1 – Device programming specifications (AN2026B) – ISSP programming specifications for following device families: CY8C21x45, CY8C22x45, CY8C24x94, CY8C28xxx, CY8C29x66, CY8CTST120, CY8CTMA120, CY8CTMG120, CY7C64215

You can find the complete list of PSoC programmer hardware, software, documentation and 3^rd party vendor relationships here: General PSoC Programming.

The app note explains each parameter under the Global Resources, the relevance of each parameter to the operation of the device, points to remember while configuring these parameters, registers that affect the parameters, and code snippets to change these parameters during runtime.

This Application Note outlines a simple, almost all-hardware method for detecting FSK signals using the analog signal processing capabilities of the PSoC 1 device. It describes circuits and signal processing techniques for demodulation. This signal processing technique is readily applicable to caller ID and several modem standards but it is not a complete modem; it does not include the phone line or other interfaces; it also does not include the data processing code.

A separate project is included and outlined in the Appendix A to simplify testing of the demodulator.

In order to be able to understand the implementation, following pre-readings are suggested:

AN2041: Understanding switched capacitor blocks – Explains the operation of switched capacitor blocks, and provides practical examples for their use.

AN2168: Understanding switched capacitor filters - Discusses how low pass, band pass and notch filters can be implemented using switched capacitor blocks.

KB Article: Implementation of a full wave rectifier and low pass filtering using all hardware technique.

The thermocouple (TC) is a voltage output device that measures the temperature difference between the sensor tip and a reference junction (called the cold junction). This is a relative measurement and to be accurate, the reference lead temperature must also be known. Type K thermocouples have an average output of approximately 40.7 μV/°C. This output is approximately linear.

Correlated Double Sampling (CDS) provides a means to efficiently subtract offset and remove drift, and low frequency noise from this sensitive measurement. This technique works just as well for differential measurements such as pressure sensors and load cells.

Reading the following application notes will aid in better understanding of this application note:

AN74170 – PSoC 1 Analog structure and configuration with PSoC Designer - Discusses in detail about the architecture of analog blocks in PSoC 1 and how they can be configured to implement a particular functionality.

AN2224 – Lower noise continuous time signal processing - Provide an introduction to semiconductor noise phenomena and specifics on PSoC noise parameters.

AN2219 – Selecting Analog Ground and reference - Describes the internal ground and reference settings in detail and how they can be routed at the output to provide a reference.
 

PSoC 1 - Correlated Double Sampling Video

This video presents low noise signal processing in PSoC® 1 through the use of Correlated Double Sampling (CDS) to reduce errors due to offset, drift, and low frequency noise.