Application Notes - Cypress.com http://www.cypress.com/?app=search&searchType=advanced&keyword%3D%26rtID%3D76%26id%3D1933%26applicationID%3D0%26l%3D0 AN76458 - PSoC® 5LP Powerline Communication Solution http://www.cypress.com/?rID=64581 Powerline communication (PLC) provides a mechanism to exchange data over existing powerlines. The primary benefit of PLC over most other communication methods is that there are no infrastructure costs (i.e. no new wires) to install a PLC-enabled system.

There are generally two types of PLC systems: high-bandwidth (video, audio, and so on) and low-bandwidth (command and control). This application note describes how to implement a low-bandwidth, half-duplex PLC solution with the PSoC 5LP family of devices.

The following table indicates the PSoC devices, PSoC Creator versions, compilers, and development kits that will work with this application note project:


Project
Device
PSoC Creator
Version
Development Kit
CY8CKIT-xxx
Compiler
Architecture
Silicon
Revision
  V2.1 SP1 / V2.1
V2.0
001
DVK
030/050
DVK
003/014
FTK
Keil
GCC
RVDS
MDK

AN76458.zip
Prod
YES
NO
NO
NO
NO
N/A
YES
YES
YES

Notes:

  1. Click on AN84741 - PSoC® 5 to PSoC 5LP Migration Guide to learn differences between PSoC 5 and PSoC 5LP.
  2. For PSoC 5 project and related document, please download file AN76458_Archive.zip.

Projects associated with this application note can be downloaded from the 'Related Files' section below. For your convenience, we have provided projects that are compatible with the two most recent versions of PSoC Creator:

  • AN76458.zip is used with PSoC 5LP and PSoC Creator 2.1 SP1
  • AN76458_Archive.zip is used with PSoC 5 and PSoC Creator 2.1/2.1 SP1.

The project’s default settings may not be compatible with your device or kit, and you may need to change your project settings. For more information, see:

Information on application note projects compatible with PSoC Creator 1.0 SP2
PSoC® 3 and PSoC 5 AN/CE project file naming convention and usage
]]> Mon, 17 Dec 2012 19:57:04 -0600 AN62792 - Updating Field Firmware With PLC http://www.cypress.com/?rID=46688 Once a system is deployed to the field, it may require updates in the future to either add features or fix issues in the application. If the systems are connected on a communication bus, updates can be performed over this bus. This application note describes the concept of field updates to systems that use Cypress’ Powerline communication (PLC) solution and explains how to write application code such that it can be remotely updated using the Powerline link. The attached code examples contain transmitter side firmware that sends out user application code over Powerline, and receiver side firmware that receives data over Powerline and reconfigures itself to the new application. 

]]> Wed, 12 Dec 2012 02:17:41 -0600 AN60685 - PLC - Interfacing the Cypress Powerline Communication Solution to CyFi Low-Power RF Module http://www.cypress.com/?rID=46713 In a majority of homes, electrical power is divided into multiple phases, with appliances distributed across these phases. When using Cypress’ PLC solution, a phase coupler is required for the Powerline packets from nodes in one phase to pass through to nodes on the other phase. This application note describes the use of Cypress’ CyFi technology to build a phase coupler that bridges the two phases using a wireless link. It describes the hardware interface between the Artaflex CyFi module and CY8CPLC20 device and the firmware code for the PLC device that accomplishes this application. The code example for the CY8CPLC20 device is attached.

]]> Wed, 12 Dec 2012 02:16:06 -0600 AN62769 - Encrypted Data Communication Using Cypress PLC Solution http://www.cypress.com/?rID=45490 This application note describes the implementation of an AES-128 encryption algorithm for the Cypress Powerline Communication (PLC) Solution. The associated project can be used to encrypt, transmit, receive, and decrypt the data.

]]> Wed, 12 Dec 2012 02:14:26 -0600 AN54416 - Using CY8CPLC20 in Powerline Communication (PLC) Applications http://www.cypress.com/?rID=37951 The application note also includes a spreadsheet to estimate the power consumption by CY8CPLC20 and focuses on four code examples. The first provides steps to develop an example project to communicate between two nodes on the powerline. The second discusses how to develop a UART Host interface for CY8CPLC20. The third discusses how to develop an I2C Host interface for CY8CPLC20. The fourth shows how to use CY8CPLC20 with average low power consumption of <50mW.

]]> Wed, 12 Dec 2012 02:12:24 -0600 AN52478 - Designing an External Host Application for Cypress's Powerline Communication IC CY8CPLC10 http://www.cypress.com/?rID=37956 Introduction

The Cypress PLC family is a single chip solution for powerline communication (PLC). It has a robust FSK modem with a user-friendly powerline network protocol. Cypress’s PLC solution and a simple powerline coupling circuit create low-cost communication interface using the existing power lines.
 
]]> Tue, 11 Dec 2012 20:55:59 -0600 AN58825 - PLC - Powerline Communication Debugging Tools http://www.cypress.com/?rID=41082 Powerlines are a widely available communication medium all over the world for Powerline Communication (PLC) technology. The pervasiveness of powerlines also makes it difficult to predict the characteristics and operation of PLC products. Because of the variable quality of powerlines around the world, implementing robust communication over powerline has been an engineering challenge for years. This application note describes these challenges, explains how to identify the cause for poor PLC performance, and provides solutions to ensure successful communication.

]]> Mon, 10 Dec 2012 20:41:35 -0600 AN60934 - PLC/PowerPSoC - High Brightness LED Control with Powerline Communication Interface http://www.cypress.com/?rID=43202 Cypress’ PowerPSoC devices are highly integrated programmable power controllers that can be used in LED driver circuits to create smart LED lighting applications. In order to exploit the flexibility and intelligence of these systems, there is now a need for an advanced communication interface between the light switch and the lighting fixture. This application note describes how to add a Powerline communication interface using Cypress’ PLC solution to PowerPSoC based LED driver circuits. The attached code example for PowerPSoC interfaces with CY8CPLC10 device, receives color information sent over the Powerline, and drives up to four LED channels in the circuit.

]]> Mon, 10 Dec 2012 20:41:04 -0600 AN55427 - Cypress Powerline Communication Board Design Analysis http://www.cypress.com/?rID=38366

Cypress’ Powerline Communication (PLC) devices (CY8CPLC10, CY8CPLC20 and CY8CLED16P01) provide a secure and reliable solution that integrates a Powerline PHY modem and Powerline optimized network protocol with CSMA into single device. These devices work with an external Powerline coupling circuit and power supply, which may need to be designed to meet certain compliance standards and specifications. This application note describes the design of these circuits and provides an overview of the commonly encountered compliance specifications along with guidelines on selection of critical components necessary to meet these specifications. 

]]> Mon, 10 Dec 2012 20:38:43 -0600 AN58717 - PLC - LED Lighting Control using Powerline Communication http://www.cypress.com/?rID=40641 The CY8CLED16P01 device provides a robust solution to implement Powerline Communication (PLC) for command and control applications with LED lighting. This application note describes the design of an intelligent lighting system using CY8CLED16P01 that allows RGB LED control over Powerline and automatic node discovery of new light fixtures connected to the Powerline network. The attached code examples contain receiver firmware (LED fixture side) that can be tested on the CY3276 or CY3277 PLC kits and master firmware (control side) that can be tested on CY3274 or CY3275 kits. Also included is a GUI that can be installed on a PC and used as master side control for RGB lighting.

In this video it is shown, how Cypress's Powerline Communication solution can be used to control LED lighting.

]]> Mon, 10 Dec 2012 20:37:25 -0600 AN62487 - Cypress Powerline Communication (PLC) Repeater Implementation http://www.cypress.com/?rID=44468 All Powerline Communication (PLC) implementations are limited by distance between nodes and the loading on the network. Cypress has developed a repeater algorithm that can overcome this limitation and makes it possible to reach any node on the network, provided there is at least one node present in range of every other node. This enables the design of a robust PLC solution especially in conditions that require high security and reliability. This application note explains the Cypress repeater algorithm which is implemented in the attached code example on CY8CPLC20 device. 

]]> Fri, 07 Dec 2012 07:09:08 -0600 AN1161 - HOTLink® Jitter Characteristics http://www.cypress.com/?rID=13024 This application note describes the basics of jitter in transmission systems and, using HOTLink™ as the example, shows how it can be analyzed and measured. Specific characterization data is presented to allow system integrators to understand the parameters needed to improve the reliability of their systems.

]]> Wed, 09 Nov 2011 04:39:36 -0600 AN1184 - Frequently Asked Questions about HOTLink® http://www.cypress.com/?rID=12747 How far can HOTLink communicate over various media?

HOTLink has no intrinsic distance limit. The two issues that determine the distances over which data can be sent using HOTLink are: (1) the choice of interconnect media (plastic or glass fiber-optic cable, coaxial cable, twisted-pair cable, etc.); and (2) the jitter that accumulates or is injected while the data is in transit over the selected media.

]]> Wed, 02 Nov 2011 02:38:33 -0600 AN1057 - TAXITM to Cypress CY7C9689A HOTLink® Transceiver Conversion Series: 1. System Parallel Interface http://www.cypress.com/?rID=12732 The Cypress CY7C9689A TAXI-compatible HOTLink® Transceiver facilitates point-to-point data communication over high-speed serial links. Systems built with the CY7C9689A are directly compatible with legacy systems made using AMD TAXI chip devices. The CY7C9689A HOTLink Transceiver is functionally equivalent to an AMD AM7968 TAXI transmitter and AM7969 receiver pair, with numerous technology enhancements and extensions.

]]> Wed, 02 Nov 2011 02:28:34 -0600 AN1032 - Using Decoupling Capacitors http://www.cypress.com/?rID=12873 Network analysis is used to prove that the conventional recommendation of using widely spaced values can, in many circumstances, cause less than ideal operation. Simpler, more reliable designs will often result from following the design guidelines of this note. 

]]> Fri, 21 Oct 2011 05:02:41 -0600 AN1162 - HOTLink® Design Considerations http://www.cypress.com/?rID=13025 The HOTLink™ family of data communications products provides a simple and low-cost solution to high-speed data transmission. While these products are easy to use, the methods used to connect them to high-speed serial interfaces are often not intuitive. This document provides a basic level of explanation of the parallel and serial interface characteristics, and provides some cookbook solutions for interfacing them to different types of parts and media.

]]> Thu, 20 Oct 2011 02:01:29 -0600 AN1055 - Termination and Biasing of HOTLink IITM High-Speed Serial I/O http://www.cypress.com/?rID=12749 This application note is one of a series of design considerations for the use of the HOTLinkII device. Its purpose is to aid in the design of circuits used to connect the serial high-speed inputs and outputs of the CYP15G0401DX Quad HOTLinkII. It discusses high-speed circuit termination techniques and the required DC-biasing for the serial drivers and receivers used in the HOTLinkII device.

]]> Wed, 19 Oct 2011 07:28:55 -0600 AN35159 - TAXI™ to Cypress CY7C9689 HOTLink® Transceiver Conversion Series: 2 Serial Interface http://www.cypress.com/?rID=12741 The Cypress CY7C9689 HOTLink(R) Transceiver integrates all the functions necessary to create TAXI(TM)-compatible bidirectional data communication links. Systems built with the CY7C9689 are directly compatible with legacy systems made using AMD(TM) TAXIchip(TM) devices. The CY7C9689 HOTLink Transceiver is functionally equivalent to an AMD AM7968 TAXI tranmitter and AM7969 receiver pair, with numerous technology enhancements and extensions.

]]> Wed, 12 Oct 2011 04:09:55 -0600 AN4059 - Clocking Options When Using HOTLink II&trade; Devices in HD-SDI Video Applications http://www.cypress.com/?rID=12999 The HOTLink II(TM) family of physical layer (PHY) devices is a point-to-point or point-to-multipoint communications building block that provide serialization, deserialization, selectable 8B/10B encoding/decoding and framing functions. The family of devices are used in both SD (Standard Definition) and HD (High Definition) SDI (Serial Digital Interface) applications, i.e. SMPTE 259M-CD (270 and 360 Mbps), and SMPTE 292M (1.485 and 1.485/1.001 Gbps). This application note discusses the various clocking options that can be used in these applications when using the HOTLink II device. The application note focuses on HD-SDI applications at the 1.485 Gbps data rate, but can equally be applied in SD- and HD-SDI 1.485/1.001 Gbps environments by simply substituting the appropriate frequency for REFCLKx, via a clock oscillator or VCXO.

]]> Tue, 11 Oct 2011 08:44:15 -0600 AN1130 - Interfacing the CY7B923 and CY7B933 (HOTLink®) to Clocked FIFOs http://www.cypress.com/?rID=12731 This application note considers the interface issues between the Cypress CY7B923/933(HOTLink)transmitter/receiver and Cypress Clocked FIFOs.This note is divided into two sections:HOTLink Transmitter-Clocked FIFO interfaces, and HOTLink Receiver-Clocked FIFO interfaces.The transmitter interface section provides a simple design example that uses a state machine to control the HOTLink-FIFO interface.A state transition diagram for the controller is provided.Critical path timing analysis is then discussed for this design example.The derived critical path equations and their critical datasheet parameters are provided and explained.A timing diagram is shown to help illustrate these critical timing relationships.

The HOTLink Receiver-FIFO interface section also includes a simple design example.A simple state machine controls this interface.The state machine addresses design issues such as reframing the serial data,BIST(Built-In Self-Test), and programming clocked FIFOs.These issues are discussed in detail.A state transition diagram is included.Critical path timing equations are derived and the advantages of pipelining the interface are discussed.Timing waveforms are shown to help illustrate the critical timing relationships.

]]> Tue, 11 Oct 2011 08:29:20 -0600 AN1089 - Parallel Cyclic Redundancy Check (CRC) for HOTLink® http://www.cypress.com/?rID=12729 This note discusses using CRC codes to insure data integrity over high-speed serial links, such as Fibre Channel, ESCON and other standards supported by Cypress's CY7B923 and CY7B933 HOTLink devices.It also shows why parity is not useful and then describes the most common CRC codes(CRC-16 and CRC-32) used in high-speed communications systems.

]]> Tue, 11 Oct 2011 08:14:39 -0600 AN1077 - Replacing Wire with Inexpensive Plastic Fiber Solutions http://www.cypress.com/?rID=12727 This application note will show how to make a data link capable of sustained operation at 15.5 mybtes/sec over 50 meters using a combination of HOTLink transmitter/receiver parts with H-P optical devices and inexpensive plastic optical fiber. Full schematics part list and operational information are included.

]]> Tue, 11 Oct 2011 07:05:52 -0600 AN1125 - Interfacing the CYS25G0101DX to Differential LVPECL http://www.cypress.com/?rID=12866 This application note demonstrates how to connect the single-ended interface of CY25G0101DX to the differential LVPECL device. This application note also provides simple calculation formulas to help users to calculate the values of the termination circuitry.

]]> Tue, 11 Oct 2011 06:18:56 -0600 AN1038 - Upgrade Your TAXI–275 with HOTLink® http://www.cypress.com/?rID=12742 This application note will explain how to upgrade TAXI-275 (AM79168/AM79169) devices with the HOTLink (CY7B923/CY7B933) devices from Cypress Semiconductor. It will aid in the migration of TAXI-275 designs to the HOTLink architecture. This note begins with an introduction to HOTLink and then gives advantages of HOTLink and replacement suggestions for the TAXI-275 devices.

]]> Tue, 11 Oct 2011 06:14:27 -0600 AN17004 - Decoupling Guidelines for the CYS25G0101DX OC-48 SONET Transceiver http://www.cypress.com/?rID=12868 This application note gives some decoupling guidelines, loop-filter requirements, and CM_SER pin requirements for the CYS25G0101DX OC-48 SONET Transceiver.

]]> Tue, 04 Oct 2011 04:20:44 -0600 AN1047 - Understanding Bit-Error-Rate with HOTLink&reg; http://www.cypress.com/?rID=12726 This application note explains the concept of an error rate for serial interfaces. Causes of errors in both optical and copper based interfaces are explained. BER floor plots of data rate vs. distance are included for a copper media type.

]]> Thu, 15 Sep 2011 07:49:04 -0600 AN1027 - Using High-Speed Serial Links to Supplement Parallel Data Buses http://www.cypress.com/?rID=12758 AN1027 discusses using the high speed serial link as a solution to replace parallel data using HOTLink®.

]]> Mon, 20 Jun 2011 05:16:38 -0600 AN014 - Channel Bonding with HOTLink II Transceiver http://www.cypress.com/?rID=12738 The HOTLink II™ family of devices are point-to-point or point-to-multipoint communications building block that provide serialization, deserialization and framing functions. They can transport serial data at rates between 0.2 and1.5 Gigabits per second (Gbps) per channel and are compatible with communication standards such as Gigabit Ethernet, Fibre Channel, SMPTE-259M, SMPTE-292M, DVB-ASI and ESCON®.

]]> Tue, 17 May 2011 09:26:58 -0600 Power Consumption of HOTLink II (TM) Family of Devices - AN027 http://www.cypress.com/?rID=13023 This application note illustrates the power consumed by any device in the HOTLink II(TM) family for a given operating frequency and configuration. Apart from illustrating the power consumption for different devices, the application note also discusses the instructions for the Cypress HOTLink II(TM) Power Estimation Graphical User Interface (GUI). The GUI can be downloaded from http://www.cypress.com/?rID=14430 under Software & Drivers.

]]> Fri, 13 May 2011 00:00:00 -0600 Configuring the HOTLink II(TM) CYP15G0403DXB - AN067 http://www.cypress.com/?rID=12739 This application note focuses on the benefits of independent clocking of CYP(V)15G0403DXB and how each channel of the device can be configured independently to operate at a different protocol. It shows the configuration settings required for four different protocols: Fiber Channel, ESCON, Gigabit Ethernet and DVB-ASI.

]]> Thu, 12 May 2011 09:14:30 -0600 Guidelines for Selecting Reference Clock Input of the HOTLink II(TM) Device in Datacom Applications - AN5076 http://www.cypress.com/?rID=13001 The purpose of this application note is to analyze one of the contributors of jitter in the serial output, namely the phase noise present in the reference source. The bit-rate clock that clocks the shift register is a multiple of the reference clock. Hence, a portion of the jitter on the reference clock is transferred to the serial bit rate clock which in turn translates to jitter at the serial data output.

This document presents phase noise of nine sample crystal oscillators for which the HOTLink II(TM) serial data output meets the jitter specifications for serial output jitter.

]]> Thu, 12 May 2011 09:11:33 -0600 Guidelines for Selecting the Reference Clock Input of the HOTLink II Device in SMPTE SDI Video Applications - AN5073 http://www.cypress.com/?rID=13003 The purpose of this application note is to analyze one of the contributors of jitter in the serial output, namely the phase noise present in the reference source. The bit-rate clock that clocks the shift register is a multiple of the reference clock. Hence, a portion of the jitter on the reference clock is transferred to the serial bit rate clock which in turn translates to jitter at the serial data output.

This application note presents the phase noise of five sample clock sources for which the HOTLink II(TM) serial data output meets the SMPTE jitter specifications for both alignment and timing jitter.

]]> Thu, 12 May 2011 09:08:11 -0600 Frequently Asked Questions About the CYP(V)15G0403DXB Device - AN060_B http://www.cypress.com/?rID=12756 The following are Frequently Asked Questions (FAQs) by customers who are evaluating CYP(V)15G0403DXB devices. The CYP(V)15G0403DXB is a member of Cypress's High-Speed Frequency Agile HOTLink II. product family. Within the device, all four channels can simultaneously operate at different data rates and transmit different types of data. The only difference between the CYP15G0403DXB and the CYV15G0403DXB devices is that the latter satisfies SMPTE 259M and SMPTE 292M pathological test requirements per SMPTE EG 34-1999.

]]> Fri, 06 May 2011 00:00:00 -0600 Jitter Generation and Jitter Tolerance of Independent Channel HOTLink II(TM) Devices for Datacom Applications - AN5077 http://www.cypress.com/?rID=13002 Fri, 06 May 2011 00:00:00 -0600 AN17006 - High Speed Serial Simulation with HOTLink II™ http://www.cypress.com/?rID=12670 The HOTLink II™ family of devices are point-to-point or point-to-multipoint communication building blocks, providing encoding, serialization, deserialization, and decoding at high speed and are compatible with many communication standards. A HOTLink II device is a frequency agile transceiver with the ability of the serial links to transport data at a rate between 0.2 and 1.5 Gigabits per second (Gbps) per channel. ]]> Tue, 22 Mar 2011 18:46:42 -0600 Configuring the Independent Channel HOTLink II(TM) Device for Digital VideoTransport http://www.cypress.com/?rID=13008 Thu, 17 Feb 2011 04:31:47 -0600 HOTLink(R) CY7B923/CY7B933 to HOTLink II(TM) Migration - AN1160 http://www.cypress.com/?rID=13028 This application note discusses how to migrate from HOTLink-based designs to HOTLink II-based designs. While most designs can be converted from HOTLink to HOTLink II, applications that use the device at signaling rates of less than 200 Mbaud cannot be migrated. The scope of this application note is limited to device configuration, although some information on device operation is covered as necessary. The Quad HOTLink II Transceiver (CYP15G0401DXB) is used to illustrate how to migrate your design and one of the channels is used to show how to interface the HOTLink device to the HOTLink II devices.

]]> Wed, 16 Feb 2011 00:00:00 -0600 SD-SDI and HD-SDI Checkfield Testing on HOTLink II(TM) Transceivers for SMPTE Pathological Conditions - AN084 http://www.cypress.com/?rID=13013 The HOTLink II(TM) family of physical layer (PHY) devices is a point-to-point or point-to-multipoint communications building block that provides serialization, deserialization, optional 8B/10B encoding/decoding and framing functions. It can transport serial data at rates from 195 Mbps to 1.5 Gbps per channel and is compliant with communication standards such as SMPTE 259M, SMPTE 292M, DVB-ASI, Gigabit Ethernet, Fibre Channel and ESCON(R).

]]> Wed, 16 Feb 2011 00:00:00 -0600 Crosstalk Analysis of the Quad Independent Channel HOTLink II(TM) Device - AN4047 http://www.cypress.com/?rID=13027 The HOTLink II(TM) family of physical layer (PHY) devices is a point-to-point or point-to-multipoint communications building block that provides serialization, deserialization, optional 8B/10B encoding/decoding and framing functions. The quad independent channel device is a member of this frequency agile family that can support serial data rates between 195 and 1.5 Gbps per channel. Within this device, all four channels can simultaneously operate at different data rates and transmit different types of data. In order to provide this flexible feature, each channel has its own transmit and receive Phase-Locked Loops (PLLs).

]]> Mon, 14 Feb 2011 00:00:00 -0600 HD-SDI and SD-SDI SMPTE Jitter Performance of the Independent Channel HOTLinkII(TM) Transceiver in a System - AN5004 http://www.cypress.com/?rID=13015 The HOTLink II(TM) family of physical layer (PHY) devices is a point-to-point or point-to-multipoint communications building block that provides serialization, deserialization, optional 8B/10B encoding/decoding and framing functions. It can transport serial data at rates from 195 Mbps to 1.5 Gbps per channel and is compliant to digital video standards such as SMPTE 259M, SMPTE 292M and DVB-ASI.

]]> Mon, 14 Feb 2011 00:00:00 -0600 Driving Teradyne FR4 and GETEK Backplanes with the HOTLink II(TM) Transceivers - AN072 http://www.cypress.com/?rID=48470 Fri, 21 Jan 2011 05:25:11 -0600 Connecting CY7B951/CY7B952 to 3.3V Framers - AN1226 http://www.cypress.com/?rID=12864 This application note describes how to connect the 5-V PECL outputs of the CY7B951 or CY7B952 to 3.3-V PECL inputs, and also how to connect the 5-V PECL inputs of the CY7B951 or CY7B952 to 3.3-V PECL outputs of some framer chips.

]]> Thu, 20 Jan 2011 09:43:59 -0600 Interfacing the HOTLink II(TM) Transceiver with the 3.3V Gennum GS1524 Equalizer and GS1528 Cable Driver for Digital Video - AN080 http://www.cypress.com/?rID=12757 Tue, 18 Jan 2011 00:26:02 -0600 CY7B952 Layout Recommendation - AN1239 http://www.cypress.com/?rID=12865

This document provides a layout recommendation for the CY7B952 clock and data recovery chip.

]]> Thu, 25 Nov 2010 03:27:00 -0600 AN1025 - Using HOTLink® with Long Copper Cables http://www.cypress.com/?rID=13026 While "Driving Copper Cables with HOTLink" describes how to operate HOTLink with copper media, this application note discusses the additional problems that must be considered when driving very long cables. The design of equalization networks to increase the operational length of a copper interconnect is also covered.

]]> Wed, 07 Apr 2010 12:54:58 -0600