PSoC workshops are getting really popular! Tomorrow I am headed to Cal Poly San Luis Obispo to advise some students on their PSoC projects and attend the winter career fair.

Hope your year is going well so far!

C. U. Around

2. Upgrading Embedded Design Firmware via USB (By Rakesh Reddy) – http://www.eetimes.com/design/other/4026877/Upgrading-Embedded-Design-Firmware-via-USB
This goes a little deeper into the embedded design with USB for those who are not satisfied with the first article above!

3. Common USB Development Mistakes – You Don’t Have To Make Them All Yourself! – (By Steve Kolokowsky and Trevor Davis) http://uk.farnell.com/images/en/ede/pdf/usb_dev_mistake.pdf
This is a very handy article for embedded designers starting off with USB

4.  USB Technology: Multi-TT Hub Goes Head-to-Head With Single-TT – (By Patrick Schmid for Tom’s Hardware) - http://www.tomshardware.com/reviews/usb-technology,677.html
Don’t go by the title. Most of us have used a USB hub at some point in our lives. This article – written back in 2003, gives a good understanding on how a USB hub works!

5. Increase the USB performance of your handset design (By Steve Kolokowsky) - http://www.eetimes.com/design/other/4016183/Increase-the-USB-performance-in-your-handset-design?pageNumber=1
Now that 90% of world’s handset devices (>1.3Billion handsets sold every year) have a USB port, most popularly used for charging and data transfer – this article written in 2006 is very much ahead of its time.

6. Making USB Flash Drives Secure (By Anant Jhawar)  - http://embeddeddsp.embedded.com/columns/technicalinsights/225402174?printable=true
Great read on how the most common USB device around (the flash drives / USB sticks / thumb drives – or whatever you call them J ) can be made more scure

8. USB3.0 – The Next-Generation Interconnect (By Ashwini Govindaraman)
http://electronicdesign.com/article/digital/usb_3_0_the_next_generation_interconnect.aspx
Good article on some of the basics of USB3.0

I'm writing after a long hiatus! Feels like a first entry. Need to keep this moving at a more constant rate. Thank you all for being patient!!

Here is the link (bookmark it!): http://www.cypress.com/go/programming

Perhaps most importantly we maintain a table of production programming solutions for all parts. Here is a snapshot summary of that information (there is more detail on the web).

As we extend the list of supported programmer tools we ll post a message to this forum and update the table on the web so you can always have an accurate and up-to-date record of your PSoC programming choices.

Happy Programming!

Watching a brief walkthrough video can be a big help in conquering the PSoC Designer learning curve. Join Ganesh Raja and see how easy it is to build your first project:

http://www.cypress.com/?rID=70468

The upgrade program for the CY8CKIT-001 and CY8CKIT-010 to PSoC 5LP silicon will be coming in the first weeks of January. Look for an announcement at that time.  

The PSoC 3 (CY8CKIT-001, CY8CKIT-003) upgrade program will end January 4^th, 2013.  I would like to thank everyone who participated over the last two years for trying out our new silicon. I hope you had an excellent upgrade experience. If you haven't yet had a chance to upgrade your system, you still have a few days.  We are taking upgrade requests through the end of the day on January 4^th. You just need to fill out a short form on the PSoC Kit Upgrade Program website.

The team here at Cypress wants you to have the best experience possible with PSoC.  That's why we offer free kit upgrades to production silicon or new silicon (look for a PSoC 5 to PSoC 5LP upgrade program coming soon).  We strongly believe being an early adopter shouldn't penalize you.  We will continue to offer these kit upgrades to production silicon and new key silicon. The PSoC 3 kit upgrade program was highly successful with just under a thousand total kits upgraded over the last two years and we hope that all PSoC 5 customers will use the kit upgrade program to try out the PSoC 5LP.  

Although I wish everyone could come visit us in our Seattle office where we make PSoC, your programmable solution on a chip, it's a bit cold and grey this time of year.  Instead, virtually visit us at PSoC World 2012 on Dec 12 & 13.  I think you'll really enjoy the technical sessions, inspiring keynotes and a chance to chat with me and the whole PSoC team all from the comfort of your home or desk.  I'm most looking forward to the PSoC pannel discussion between several of our customers, a university professor and a PSoC expert from Arrow all moderated by Dan Byers, Senior Director of World Wide FAEs.  I think the discussion will be lively to say the least.

Tom Lantzsch, the EVP of Strategy for ARM, is discussing intelligence everywhere and the pervasive nature both of ARM processors and the fundamental shift in products for increasing technology at lower and less expensive price points.  He also brings up some great thought provoking concepts on energy conservation and low power.

If you're an engineer who likes wine, you need to check out Cypress's CEO, T.J. Rodgers' keynote on the science and technology he's introducing to wine-making in his vineyard near the mountains of Santa Cruz, California and at the University of California at Davis.  T.J. is an engineer's engineer and brings measurement, a knowledge of organic chemistry and fun electronics to everything he does and wine is no exception. 

If you need more convincing, check out the following:

• Watch the Sneak Peak with real session content
• Take a look at the Agenda
• Read the personal invitation John Weil, Director of PSoC Marketing and Applications, sent to the ARM community
• Meet Alan Hawse, Executive Vice President of Software, in his PSoC Creator Commercial

Important specifications:

Supply Voltage: 5V

Accuracy: +/-0.25%

Total error band: +/-2% FSS

Sensor Operation:

This sensor has an amplified and temperature compensated output and is driven by a voltage supply. The output curve and equation are shown below.

Design:

The design is very simple as both amplification and temperature compensation are done within PSoC.  Resolution should be 1/1000th of full scale, hence a 10-bit ADC is required. The sensor output voltage goes to 90% of the supply voltage, so the ADC range should be vssa vdda. The ADC should operate with the rail-rail buffer enabled. Sensor output is ratiometric and the ADC reference should be Vdda/4.

PSoC Top Design and ADC configuration:

Although not as many analog resources are required when interfacing a pressure sensor with an amplified output, integrating a sensor with other PSoC features such as capsense, segment LCD drive and communication protocols, etc, will lower overall system costs.

Conclusion:

PSoC3 and PSoC 5LP can sense pressure accurately while reducing BOM cost and board space by integrating the analog front-end, ADC, reference and MCU. PSoC ADC inputs can be multiplexed with many inputs (limited only by the GPIO count) allowing interfacing to multiple pressure sensors or other analog sensors. The PSoC Creator design environment makes it easier for you to design and debug, reducing the design time and your time to market.

By Praveen Sekar

Supply current = 1.5 mA

Pressure Range:  0 -15 psi (Gage)

Sensitivity (max): 10 mV / psi

Sensitivity (min): 5 mV / psi

Temp error - span (max): 0.5 % FSS

Offset (max): 2 mV

Temperature error - offset: 0.5% FSS

Specified temp range: -40 to 125 °C

Bridge resistance (max): 6.4 k (50°C)

Accuracy: +/-0.1 % FSS BFSL

Sensor Operation:

The sensor is a piezo-resistive sensor excited by a current and has an output voltage proportional to the pressure and the current. The output voltage has a 50% tolerance and the sensor provides a gain set resistor to calibrate it to 1%. When the sensor is excited by proper current excitation levels specified in the datasheet, the temperature coefficient of span and offset will cause only a very small error in the final measurement (temperature compensated).

Design:

The design requires an excitation current of 1.5mA and an ADC to measure the output voltage. With a bridge resistance of 6.4k (max) and excitation current of 1.5mA (current level prescribed in the datasheet for proper temperature compensation), the load voltage of the current source is 9.6V. This means PSoC IDAC cannot directly be used for supplying bridge current because of very high load voltage. To limit external components and get maximum value out of PSoC we can use circuit below.

By controlling the V_GS of this circuit, the I_D can be controlled. V_GS is controlled by changing the current of the sinking IDAC. R_B ensures the IDAC output voltage is within compliance and optimum. The current sense resistor (0.1%), R_SENS,aids in setting the current to 1.5mA. The voltage across R_SENS is read by PSoC ADC (0.2%) and the IDAC current is adjusted until I_D becomes 1.5mA. With this circuit, we can ensure that the current is accurate to 0.3%. A current accuracy of 2% is the requirement so the temperature error due to offset and span are within datasheet limits.

Sensor Common mode output voltage:

With this design the sensor common mode output voltage is given by;

(1.5 * 6.4)/2 + 0.150 /2 + (1.5mA * 0.05)/2 = 4.8 + 0.075 + 0.0375 = 4.91 V

Here, 1.5mA is the sensor current, 6.4k is the max bridge resistance and 0.150 V is the maximum span, 0.05 is the sense resistance.

The sensor common mode voltage is very high to directly feed into PSoC. The ADC with input buffer can accommodate only to within 200 mV of Vdda. The ADC without buffer can t be used because it has low input impedance. The PGA can allow input voltage all the way to the voltage rail, but we ll be limiting the design to supplies with very strict tolerance levels. This is not desirable as various designers might want flexibility in their power supply design (at least support 5% supplies).

Hence to lower the common mode voltage we can use a charge pump that generates a negative voltage. The generated voltage is about -3V using a negative charge pump. The ripple voltage (of <10%) on the charge pump output doesn t have a major effect as long as we set the ADC input sampling frequency as an integral multiple of the ripple frequency (the charge pump clock frequency).

ADC input range:

The sensor span is 150mV (max). The ADC input range should be > +/- 0.256V.  

Resolution:

Resolution required in 1/1000^th of full scale. At minimum span of 75mV, we require 75uV of voltage resolution. At 15-bit level, the ADC resolution is 64uV. With a gain of 4, the ADC resolution is < 16uV.

At +/-1.024V range, we require 15-bit resolution

At +/-0.256V range, we require 13-bit resolution

Reference:

This measurement requires an absolute reference. The final pressure accuracy depends on the reference accuracy, therefore the internal 1.024 V reference is a good choice.

The ADC has four channels:

0.  Sense resistance channel: This channel is used to set the current to 1.5mA

1.  Sensor Channel: Senses the sensor output

2, 3.  Calibration channels: Measures the gain set resistance for calibration

The IDAC has two channels:

1. Passes current through the calibration resistance

2. Passes current through the sensor

The ADC configuration for the pressure sensing channel is shown below.

Pressure Equation:

The pressure is computed from the measured voltage using the following equation.

P = A* (V_o / S_i) * P_r

P Pressure (in psi)

V₀ Bridge output voltage in mV

S_i Span of pressure sensor output in mV

P_r Rated Pressure (in psi)

A I/1.5. I is the actual current flowing into the pressure sensor

Calibrations required:

Span Calibration:

The Span of the pressure sensor is calibrated using the gain set resistance provided in the sensor. Using the gain set resistance, r, the span can be calibrated. The gain set resistance is trimmed such that when it s used in conjunction with a differential amplifier, it ll give a 2V span. Working the equations back, you can find that the gain set resistance.

r = (2 * Rf * Si)/ (So Si)

Here, Rf is feedback resistor of the differential amplifier, Si is the span of the pressure sensor output (differential amplifier input) and So is the span at the differential amplifier output. By looking at the datasheet of the part, Rf and So can be found. For MEAS 1210, Rf = 100k and S₀ = 2V.  By measuring r, we can find the span,

S_i = 2/(1 + (200/r))

Performance measures:

Offset:

The sensor has a 2mV offset (max). This can be calibrated out to zero.

Span error:

The gain set resistor can provide an interchangeability accuracy of 1%. In addition, the gain set resistor can be found with 0.1% accuracy only (limited by calibration resistor accuracy. If the calibration resistor is very accurate (0.01%) or calibrated, then the span error will be 1%.

Temperature Error offset:

This has a maximum error of 0.5% FS. This is 0.075 psi.

Temperature Error span:

This has a maximum error of 0.5% FS. This is 0.075psi.

Pressure non-linearity + hysteresis:

Together they contribute 0.15% FS. This is 0.022 psi.

Signal Chain:

Offset error:

The offset error of PSoC ADC is <100uV, which can be cancelled by Correlated Double Sampling (CDS).

Offset drift:

Offset drift of PSoC is 0.55uV/°C. At 50°C, this is 11uV. It is 1/7^th of minimum resolution (0.015psi). It can be cancelled by Correlated Double Sampling (CDS).

Gain error:

PSoC ADC s calibrated accuracy is 0.2%. There are 2 measurements, 1 voltage measurement and 1 current measurement (current set to 1.5mA). This can contribute to 0.4% error in total.

Gain drift:

Drift is 50 ppm/°C. For 25°C change, it ll be 0.125%.

List of all errors:

PSoC Value:

Apart from integrating the analog front end, ADC, 0.1% precision reference, Op-Amp, IDAC and the MCU and providing a separate channel for accurate temperature measurement, PSoC can integrate miscellaneous features suchascapsense, segment LCD drive and communications protocols. Designing with PSoC creator reduces the design time considerably. The BOM cost and board size can also be significantly reduced.

In the next part we ll see how to interface unamplified compensated pressure sensor with PSoC3.

By Praveen Sekar

www.cypress.com/go/programming

Clicking the link above will take you to a page detailing the software and hardware you need to program your PSoC. You'll also find programming specifications and a list of our 3^rd party programming vendors. In short, it's everything you need to handle programming from your first prototype to high volume manufacturing.

Supply voltage = 5V

Pressure Range:  0 -15 psi (Gage)

Sensitivity (max): 6.9 mV / psi (25°C)

Sensitivity (min): 3.3 mV / psi (25°C)

Temp Coefficient of sensitivity (max): -3.8 %

Offset: 35.6 mV (50°C)

Temperature coefficient of offset: 1.5%

Specified temp range: -40 to 125 °C

Bridge resistance (max): 5.9 k (50°C)

Accuracy: +/-0.25 % FSS BFSL

Sensor operation:

This type of pressure sensor is a piezo-resistive sensor (Wheatstone s bridge) driven by a voltage supply. The bridge output voltage is directly proportional to the applied pressure and the supply voltage. The primary sources of error to be factored in while designing with this type of sensor is the sensor offset error, span error and temperature coefficient of span and offset (since the sensor is temperature uncompensated, temperature coefficient of span and offset play a major role in the final error).

Design:

The design parameters of concern are the ADC resolution, input range and reference.

ADC input range:

This parameter is dependent on the maximum voltage output, V₀, from the pressure sensor. At 5V supply and using the maximum offset and sensitivity possible, we get;

V₀ (max) = 6.9 * 15 + 35.6 = 139.1 mV

ADC input range should be greater than +/-0.256 V.

Resolution:

1/1000^th of the full scale resolution is sufficient in pressure sensing applications.

Pressure resolution = 15 psi/1000 = 0.015 psi

Voltage resolution = 49.543 mV/1000 = 49.543uV

This requires a 16-bit ADC in +/-1.024V range or 14-bit ADC in +/-0.256V range.

Reference:

A ratiometric reference should be used in this case. Hence PSoC reference should be configured for internal vdda/4 , where vdda = 5 volts.

PSoC Creator Top Design:

The ADC has three channels, one for sensing pressure and the other two used for temperature measurement. The RTD temperature is measured as described in AN70698.  ADC configuration for the pressure sensing channel is shown below.

Note that +/-Vref/4 range can also be used for this configuration in 14-bit mode.

Pressure Equation:

From the measured ADC voltage, the pressure is calculated from the equation below;

P = (V_o / S) * P_r

P Pressure (in psi)

V₀ Bridge output voltage in mV

S Span in mV

P_r Rated Pressure (in psi)

Calibrations required:

Room Temperature calibration:

Since span has a very high tolerance, we have to calibrate span before using it. Pressure sensor offset should also be calibrated before use.

Offset Calibration:

Offset of the pressure sensor has to be corrected by giving a zero pressure input and measuring the ADC output voltage, V_off.

V_off  = V_offp + V_offs

V_offp Pressure sensor offset

V_offs signal chain offset

Span/Gain Calibration:

The span of the pressure sensor is calibrated by applying a full scale pressure input to the pressure sensor and measuring the ADC output voltage, V_fs.

S = V_fs

(Where S is the Span)

By doing span calibration we are calibrating both the span error of the sensor and gain error of the ADC.

Temperature calibration:

Both the pressure sensor offset and span varies with temperature and they have to be calibrated. But the sensor datasheet doesn t provide information on the span or offset calibration. It provides only the limits of the error. If the characteristic curve is found by experiment, we can correct for both span and offset temperature coefficient accurately.

List of all errors:

*Note:  Assumes calibration source has zero error.

ADC INL and the sensor non-linearity are the only factors that can t be calibrated and will affect the final measurement.

PSoC Value:

Apart from integrating the analog front end, ADC and the MCU, providing a separate channel for accurate temperature measurement, PSoC can integrate miscellaneous features suchascapsense, segment LCD drive and communications protocols. Designing with PSoC creator can reduce the design time considerably. The BOM cost and board size can also be significantly reduced.

In the next part we ll see how to interface unamplified compensated pressure sensor with PSoC3.

By Praveen Sekar

See you there!

In this four part series, piezo-resistive pressure sensing basics and the PSoC circuits for three types of pressure sensors will be examined. The first part covers piezo-resistive pressure sensor basics and introduces three categories of pressure sensors

Piezo-resistive Pressure sensor basics

 A piezo resistive pressure sensor has a silicon diaphragm whose resistance depends on its tension. The diaphragm undergoes tension whenever there is a pressure. It can be modelled by a Wheatstone s bridge where all the resistors change with pressure. When pressure is applied to the diaphragm, resistance of the two arms (diametrically opposite to each other) increases and the resistance of the other two arms decreases.

 Pressure sensor equations

 The change in resistance can be converted to voltage by voltage or current excitation. The equations involved in voltage and current excitation are shown below.

Voltage Excitation Mode:

In this case, the Wheatstone s bridge is excited by a voltage. Span is defined as the bridge output voltage for rated pressure (full pressure). Span( S) is given by

S = V * R/R

R Change in resistance for rated pressure

R - Bridge resistance

V Excitation voltage

R = P * P_s

P Rated Pressure

P_s Pressure sensitivity (Change in resistance for unit change in pressure)

P_s = R * k

k - Normalized pressure sensitivity i.e. Pressure sensitivity for 1ohm resistor

S = V * P * k

Span is independent of bridge resistance. The temperature coefficient of span primarily results from the temperature coefficient of pressure sensitivity which is dependent on the diaphragm material.

Current excitation:

In this case, the bridge is excited by a current source. In this case span is given by,

S = I * R * P * k

Where I is the excitation current.

In this case, the span depends on the current source and bridge resistance.  

The temperature coefficient of span results from the temperature coefficient of resistance and the temperature coefficient of pressure sensitivity.  By proper design, the two can be made close to each other. Hence current excited pressure sensors have the design advantage of tweaking the process parameters so as to reduce the effect of temperature on span.

Pressure sensor types

The pressure sensor span is generally around 50-150mV. Depending on whether the pressure sensor output is amplified and on whether the pressure sensor is compensated for temperature variations of span and offset, we can have the following categories of pressure sensors

1. Unamplified uncompensated pressure sensors
2. Unamplified compensated pressure sensors
3. Amplified pressure sensors/transmitters.

The next three parts explains interfacing each type of pressure sensor with PSoC and the system performance measures.

By Praveen Sekar

This is a great opportunity to take a short break from finals and attend the virtual show of shows.

You can register by clicking here: PSoC World

See you there - there will be a few academic goodies on the show.

Until then,

C. U. A.round

This is a great opportunity to take a short break from finals and attend the virtual show of shows.

You can register by clicking here: PSoC World

See you there - there will be a few academic goodies on the show.

Until then,

C. U. A.round

Anyway, it is impossible for your microcontroller to always have every serial interface that may come along.  For example, I read about a string of 50 Christmas lights that had red, green, and blue LEDs in each bulb and here comes the best part, each bulb is addressable.  Yes, you can control each individual bulb for color and intensity, four bits for each color (red, green, and blue) and 8 bits for intensity.  Of course the string of lights came with its own controller that could generate 12 different patterns, but I wanted to create my own patterns.  With a little Google searching I found that someone had already hacked the asynchronous protocol and bit-banged an IO port to control the lights with some microcontroller.  Nobody had actually created hardware to make this easier or less CPU intensive, you know why? Because nobody else used a PSoC3 or PSoC5 with their powerful UDBs!  Yes a PSoC3/5 can bit bang with the best of them, but why bother when you have extremely flexible hardware, plus bit banging is so 90's. 

The protocol was a 26-bit packet with one start and three stop bits. Each data bit was divided into three 10uS periods.  The first period is always low, the second period was low if the data was a 1 and high if the data bit was a 0 .  The last period is always high.  See images below for bit and packet formats.

The packet format is pretty straight forward with the address, brightness level and three colors packed into 26 bits.  See figure below.

I had a choice, be lazy and use a 32-bit wide shifter or use a single 8-bit wide shifter with a slightly more complicated state machine. The 32-bit wide implementation would be easier but would be a bit wasteful in hardware.  The 8-bit wide implementation would take a bit longer, but much more efficient. I choose to go with the 8-bit wide design.  One other nice feature in the UDBs, is that you can create two 4 byte FIFOs for data flowing into or out of an interface.  This turned out to be perfect since it took 4 bytes to transfer the full 26-bit packet.

The string of lights is 50 bulbs long and if you want to update all the bulbs at one time, it would take 200 bytes (50 bulbs * 4 bytes per packet). Since you don t want the processor to just sit and wait for an interface to move data, DMA is the perfect solution. This way I was able to update the entire string using DMA with almost no CPU overhead!  Where the other guys are wasting their CPU cycles toggling bits, the CPU in the PSoC could concentrate on generating cool interactive patterns, converting DMX commands to the light string format, or any other task.  What is even better, I could implement 8 of these interfaces in a single PSoC3 or PSoC5 at the same time.  

Making this interface into a PSoC Creator component, provides a way to setup all the hardware and DMA with a single start command as with all Creator components.  More APIs are added to generate cool lighting patters.  The video below is an example of version 1.0 controlling three strings of light on my house.

This second video shows four strings on the floor in our lunch room.

This third video demonstrates yet another use for the lights.

Just think of the possibilities interfacing a string of lights to anything that can be measured with a PSoC!

Here are a few other images of the actual box the string came in, the string that I modified, my interface board, and a close up view of one of the bulbs.

Stay tuned for an upcoming video with the details of what it took to make the lighting component and how easy it is to interface the string with the Cypress PSoC3 First Touch Kit.

Mark Hastings

I2C, I2S, LIN, SM Bus, SPDIF, SPI, UART, Counters, CRC generator, Glitch filter, Quadrature Decoder, Shift register, Timer, Logic gates, Flops, Digital multiplexers and de-multiplexers, control and status registers, etc. 

You get the picture, but what is currently in the library is by no means the limit of what can be created.  Recently I sent an email to our application and field application engineers and asked what they had created with UDBs.  Here is a list of some of the components people have created with PSoC UDBs.

• 60Hz Grid Lock PLL
• Numerically Controlled Oscillator (Used for DDS)
• Forward Error Correction (FEC) decoder
• No clock stretch I2C slave
• Simple components (8bit adder, PWM, digital compares etc )
• Complex Counters 
• ADC mux sequencers
• Holiday Light controller
• Square root calculator
• First order IIR filter
• Hardware state machines
• Delta sigma modulator
• UDB discrete Fourier transform
• Byte packer (sticks two 12-bit values into 3 bytes for RF transmission)
• 7-Segment Display controller
• Remote control servo controller
• Manchester Encoder/Decoder
• 1-Wire communication interface
• ClipDetect,  Monitors 16-bit audio and over rides output if value exceeds a certain limit.
• Audioclkgen,  Creates a factional N reference for the on-chip PLL.  Used in digital audio designs.

Notice that this list contains some pretty weird stuff that you would never find standard in any microcontroller.  You won t even find most this stuff in the standard PSoC Creator library, yet!  The point is, that it doesn t matter.  You can create your own  custom interface or component, that makes your project unique without adding extra external glue logic or a CPLD.

Cypress does have a Community Components page where people can post any component they have created.  Unfortunately it has been a very well kept secret until now.  Do yourself a favor and check out the Community Components page.

Also, if you want to get more training on creating components, read the app notes I mentioned above or look at the community components guidelines on this this page.

If you have created a cool component (or even a weird one), don t be afraid to share it with the Cypress community for your 15 minutes of fame. 

By Mark Hastings

http://www.engineeringtv.com/video/Cypress-Semiconductor-PSoC-T-56

If you are a Cypress design partner and you would like to show case your PSoC based products in our show contact us at designpartners@cypress.com

It used to be with creating host applications for a computer, you only needed to create one application for Windows. In today's world, operating systems such as Mac OS X and Linux are growing in popularity. Additionally, mobile devices running Android are increasing in numbers with the continuous  production of smart phones and tablets. With so many different operating systems available, the need for cross platform functionality is ever so more important.

What if I told you there was a way to develop a PSoC 3 or PSoC 5 application to easily stream general data across USB and provide the foundation for cross platform functionality?  Using the Human Interface Device (HID) class makes this possible. Yes, the same class that is used for mice and keyboards is breaking free from the stereotype that it is limited to a device that requires some form of human interface, such as a button press, to function.

The truth is that the HID protocol provides the perfect foundation to shuttle data back and forth between a PSoC and computer, in applications where high speed data transfer is not required. Best of all is that implementing a generic HID on PSoC is easy to do and creating Graphical User Interfaces (GUIs) on various operating systems such as Windows, Mac OS X, and Linux is fairly straightforward.  AN82072: PSoC 3 / PSoC 5 USB General Data Transfer with Standard OS Drivers will guide you through all the steps required to do so. You will have your PSoC streaming data to a host operating system of your choice in no time! 

You can download this application note from the following link.
AN82072 - PSoC® 3 / PSoC 5 USB General Data Transfer with Standard OS Drivers

By Robert Murphy

1.       SMBus and PMBus

These complete Cypress power supervision portfolio for PSoC 3 and PSoC 5, by adding SMBus and PMBus slave communication capability to PSoC. Learn more about PSoC Power Supervision solution at http://www.cypress.com/go/PowerSupervision.

2.       Debouncer

This is probably going to be the most-used component out of all six new releases because it is the easiest and best way to debounce and edge-detect switch inputs to your system, without using your CPU.

3.        Glitch Filter

The hardware glitch filter removes unwanted pulses from a digital signal, and is a frequently used function in digital designs. The Glitch Filter v2.0 is a complete re-design from its previous version which was available as a PSoC Creator concept component.

For more information on switch-debouncing and glitch-filtering, see AN60024.

4.       RTD Calculator

5.       Thermistor Calculator

6.       Thermocouple Calculator

These three new components add easy-to-implement temperature-sensing capability to PSoC Creator s component library. Find out more about temperature-sensing with PSoC 3 and PSoC 5 through the suite of application notes available:

·         AN70698 - Temperature Measurement with RTDs

·         AN66477 - Temperature Measurement with Thermistor

·         AN75511 - Temperature Measurement with Thermocouples

In addition, you may be interested in:

·         AN60590 - Temperature Measurement Using Diode

·         AN65977 - Creating an Interface to a TMP05/TMP06 Digital Temperature Sensor

CP4 also provides an update to the I2C Master/Multi-Master/Slave component, with the addition of an I2C bus multiplexing feature, besides for some minor tweaks.

I have already installed CP4 on my system especially for the debouncer. Many of you may want one or more of these new components, or the more robust I2C. To get all of these, please download Component Pack 4.

http://www.cypress.com/?rID=70468

Also, don't miss episode 2 of PSoC Today's continuing series on PSoC Designer 5.3:

http://www.cypress.com/?rID=70509

The Constants component is a very simple way to display constants used by the firmware on the schematic.  Also this allows you to change firmware parameters without changing actual source code.  I have created an example component that allows the user to assigns names and values to up to four constants.  The component consists of just a symbol and a header file. Below is what the component would look like on the schematic.  The four constants have already been assigned names, DEBUG, LOOP, DELAY, and COUNT, as well as values.

Figure 1 Example Project Constants Component

The configuration is very simple.  The user simply assigns a name and value.  The header file is automatically generated.  The constants defined below will have the instance name pre-pended on the name.  For example, the LOOP constant name will be MyConstants_LOOP .

Figure 2 Configuration dialog of Project Constants Component

The generated header file would look like this using the configuration in Figure 2.

 #defineMyConstants_DEBUG   0

#defineMyConstants_LOOP   100

#defineMyConstants_DELAY   95

#defineMyConstants_COUNT   5

 

The constants can then be used throughout the firmware, just by including the MyConstants.h header file.  Below is an example of a code snippet that makes use of the constants provided in MyConstants.h.

 for(i = 0; i < MyConstants_LOOP; i++)

{

      LCD_Position(1,5);  
   
      LCD_PrintHexUint8(i);

      CyDelay(MyConstants_DELAY);

}

   

The same concept could be used for user created components for a specific application. For example a project phase component that displays on the schematic whether the project is in the release or debug phase.  The header file would contain the #define statements for the different mode.

Figure 3 Project Phase Component

Other similar components can easily be generated by the user, with just some simple basic knowledge of how to create components. For example if you wanted a waveform generator to change the waveform without changing code.

Figure 4 Application Mode Example

The header file would contain the following:

 #defineAppMode_Mode     2

#defineAppMode_SINE     0

#defineAppMode_SQUARE   1

#defineAppMode_TRIANGLE 2

 

The firmware would look at the AppMode_Mode constant to determine which waveform to generate, requiring no code changes.

This is just one simple trick to make a project more flexible and easier to change its operation without editing code.  It is also a good way to demo an application to a customer.  The user can then try different operations without editing code.  The MyConst component is generic and can be used with any project.  The ProjectPhase and AppMode components can easily be created by the user in a matter of minutes.

By Mark Hastings

PSoC 3, PSoC 5 and PSoC Creator are finalists for EDN magazine's Innovation Awards. Vote at: http://bit.ly/bUkQhb . PSoC Rocks! #psoc

Heading to UNCC tomorrow for PSoC 3 workshops Friday and Saturday. If you are already going to IEEE South East CON come by and check us out.

Cheers

Read more about Starter Designs in the Release Notes of PSoC Creator 2.1

Do you want to use the Programmable Logic Device (PLD) capability of PSoC, and don t know where to start? Or need to create your own custom digital components in PSoC Universal Digital Blocks (UDBs)? Then look no further.

AN82250: PSoC® 3 and PSoC 5 Implementing Programmable Logic Designs An Introduction provides you with an ideal start towards digital mastery with PSoC UDBs. By introducing the PLD architecture, and then walking through an example project, AN82250 teaches you how to create Verilog components in PSoC Creator. For those interested in advanced features of PSoC PLDs and PSoC Creator, these are touched upon in the additional reading material in the appendices.

This application note is actually the second of a three-part series of application notes written to help you learn and exploit PSoC s powerful digital capabilities. This series begins with the introductory AN81623: Digital Design Best Practices, continues with the PLD-centric AN82250, and culminates with the datapath-focused AN81256: Designing PSoC Creator Components With UDB Datapaths.

After reading AN82250, you will be able to implement moderately complex PLD-based components in PSoC Creator. AN82250 also provides a good gateway to building more complex Datapath-based designs dealt with in AN82156. So what are you waiting for? Download AN82250 now!

By Antonio De Lima Fernandes

AN82156 - Designing PSoC Creator Components With UDB Datapaths

Have you ever wondered how PSOC Creator manages to pack so much functionality into its components? Chances are the component uses the UDBs in PSoC 3 and PSoC 5 to perform calculations, comparisons, and data management.  The "secret sauce" in the UDBs is the datapath - a configurable 8-bit ALU designed to offload tasks from the CPU. The datapaths, when chained together across UDBs and/or combined with PLD logic, are powerful tools to have at your disposal. Understanding how to use them is an essential part of creating optimized PSoC 3 and PSoC 5 solutions.

AN82156 explains how the datapaths work and teaches you how to develop PSoC Creator components that use the UDB datapaths. It contains step-by-step instructions for creating your first datapath component. The appendices also review the Datapath Configuration Tool and the Verilog code it generates.

If you are planning to create a custom component, you should become familiar with the datapath and the advantages it can offer. AN82156, its example projects, and related on-demand training videos are available today from the Cypress.com website.

AN82156 Landing Page:

• AN82156 - Designing PSoC Creator Components With UDB Datapaths  

On-Demand Videos:

• PSoC Creator 210: Intro to Datapath Components
• PSoC Creator 211: Datapath Computation
• PSoC Creator 212: Datapath FIFOs
• PSoC Creator 213: Multi-Byte Datapath Components
• PSoC Creator 214: Datapath API Generation
   

By Greg Reynolds

 

On the right side of the window, you can see the pinout and list of supported user modules for the selected device.

Note for power users: if you know a portion of the MPN for the device you want to use, you can also just type it in the Find box in the top of the window, and the list will filter live as you type. You can also right-click a device in the catalog to add it to your favorites. These two methods are the quickest ways to select your device.

Application note "AN73212 - Debugging with PSoC1" provides all the information required to debug a PSoC1 project.

Happy Debugging!

Tired of clicking on one interconnect row after another, trying to get all your signals to where they need to go? With Designer 5.3, you're done with that! Just shift+click on a block port and a number of glowing, golden lines will show you all the possible destinations. A second click on one of those highlighted locations and you're done! This works on analog routes as well as digital routes, block-to-block or block-to-pin. This will make Designer quicker for your new engineers to learn, and make life easier for the veteran users.

A final note: If you like the control of personally routing your signals, have no fear! We haven't removed any of the existing manual routing features.

The tall building in the center is the new Hyatt. My hotel is forward and to the right (you cannot see it really).

You are looking into Wan Chai on Hong Kong Island in the background.

Moving to a more directly Southern view. Looking at the famous Victoria Peak behind the Central area of Hong Kong Island

Trimming simply means adjusting register values to achieve better accuracy be it for offset of a comparator or the frequency of a clock. For clocks, trimming means calibration with respect to a higher accuracy reference clock.

In the example project associated with the application note (schematic shown above), the IMO is trimmed with a 32 kHz crystal as reference and the ILO is trimmed with the IMO as reference. This enables the IMO to achieve near MHz crystal accuracy (±0.05%) at kHz crystal cost. The ILO performance is also considerably improved with a post-trim accuracy of ±6.5% with respect to the IMO. This means that the respective trim components improve ILO accuracy by a factor of 16, and the IMO accuracy by up to a factor of 140. Moreover, the accuracy can be easily verified on the character LCD (an example is shown below) with a simple API call to check IMO and ILO errors!

I really enjoyed developing these two components. Once you program the example project on the PSoC, zap it with freeze-spray or a heat gun and have fun watching the component correct the IMO and ILO frequencies!

In conclusion, having an accurate MHz clock is important for a wide range of applications, and particularly for high-speed communication. An accurate kHz clock also has many applications, especially in low power modes when MHz clocks are switched off.

The IMO and ILO Trim components really enhance the already-flexible clocking structure in PSoC 3 & PSoC 5, and I hope that they help you out in your specific applications as well. You can download the application note and the components at AN80248's landing page.

By Antonio De Lima Fernandes

To help you learn about and effectively use the UDBs, we're launching a series of new application notes that cover the topic in great detail. The first one, AN81623, PSoC 3/5 Digital Design Best Practices, is intended to introduce designers, especially firmware engineers, to the field of digital design and how it is done with PSoC 3/5.  Forthcoming application notes will give detailed instruction on the use of PLDs, datapaths and other UDB features.

AN81623 gives a brief introduction to digital hardware design theory and then describes the digital subsystem in PSoC 3 and PSoC 5. It also describes best practices for digital design using PSoC Creator, and shows how to use static timing analysis (STA) report files.

So this application note should help you more effectively use the digital components available to you right now - Counter, Timer, PWM, Shift Register, Quadrature Decoder, and more.  And with the Lookup Table (LUT) component you should easily be able to build simple state machines. Then watch for more advanced application notes, coming soon, that will show how to implement your own complex digital designs in the PSoC 3/5 UDBs.

To download this new application note "Digital Design Best Practices" click on this link, AN81623.

By Mark Ainsworth

Professor Renji Mikami

View of Tokyo from Cypress Japan office

I will be presenting a PSoC workshop at TALE 2012 being held at Hong Kong Polytechnic on Monday.

Until Then,

C. U. Around

The second project, 2_WaveDAC8_TwoWaves shows how you can alternate between two waveforms and easily switch right at the end of each wave.  The project schematic is rather simple, and the source code can t get much simpler.

Project source code.

This is the waveform output, notice it is not just a simple sinewave.

The third project "3_WaveDAC8_UART_FSL" shows how to generate a simple FSK output when you combine the WaveDAC8 and UART components.  Note the simplicity of the schematic below.  By changing the two clocks you can generate any two frequencies you want.

The scope screen shot below shows the output of the UART and the WaveDAC8 output.

Again the code can t get much simpler to send out Hello World .

The forth project was probably the most fun.  Who doesn t enjoy dialing their phone with their own custom made PSoC controlled DTMF dialer.   This project used two WaveDAC8 components, a couple of counters, an opamp to buffer the DAC outputs, and a single clock.

This project demonstrates another cool feature of PSoC.  Since the WaveDAC8 component uses standard internal DACs to generate the output,  connecting the two DAC outputs together is not a problem.  When the DAC is in the voltage DAC mode, it is simply a current DAC with an internal resistor.  Now the coolest thing about this project is that it gives you a good chance to use that FFT feature in your digital scope.  I had the DTMF dialer project dial the sequence 159D which causes all of the eight tones to be exercised.  Using the Tek MSO 2024 FFT mode I can see the frequency spectrum of the output, cool eh?

You can find the full application note, example projects, and WaveDAC8 component library on the AN69133 Application Note web page. The application note contains details about the design of the WaveDAC8 and information on sampling theory.

So just remember, although the WaveDAC8 maybe pretty, it has some brains as well.  Since it does all it's work with DMA, it does not require any of the valuable PSoC 3 or PSoC 5 CPU cycles.

By Mark Hastings

• The update includes:
• A description of the updates to the PSoC Creator 2.1 ECO interface.
• Descriptions of ECO performance metrics, and how to measure them.
• An "Advanced Topics" section for ECO experts.
• A table of recommended MHz resonators with manufacturer specifications, reccomended configurations and typical performance metrics. (Shown below)

Check it out now, and let us know what you think in the comments!

By Max Kingsbury

http://www.cypress.com/go/psocdesignerfaq

http://www.youtube.com/watch?v=GrbbYZXRaqs&context=C3ea8e43ADOEgsToPDskJu3ydARmtq8n9dWhPWGn7L

Cypress Semiconductor has completed the JTAG programming qualification for Goepel Electronic (http://www.goepel.com/). The qualification covered all electrical requirements, algorithm support, and verification of multiple device packages. Cypress has qualified the 48-SSOP, 48-QFN, 68-QFN, and 100-TQFP packages.

The vendor has released their software update, CASCON GALAXY 4.6.0a 1266 and VarioTAP model libraries, which contains JTAG programming support for the entire PSoC 3 device family. All testing was conducted on the SCAN FLEX SFX/ASL1149 programmer. Prior to programming PSoC 3 devices via JTAG or through a JTAG chain, users will need to ensure they have the latest Cypress supporting software via Goepel and the correct Goepel JTAG programmers.

For more information on device programming capabilities and software pricing contact the Goepel Sales office:
For more information on PSoC programming, visit the PSoC programming landing page.
If you need additional device support please file a tech support case.

The following is an actual screen shot of the Analog Device Viewer/Editor.  If you look close, note that all the resources used, including routes are highlighted.  You can click on the nets on the right or the graphical routes on the left to examine the nets and routes.

Example Circuit

Below is an example circuit and the analog viewer s representation.  Note how AMux_1 consist of the light blue traces.  It is easy to understand just how the signals are routed and exactly the resources used to create the circuit, no more guess work!

Lock down signals and component placements graphically

Many of you at times wish you could easily lock down blocks that are used for a specific component implementation.  You may have learned to use the constraints editor but found it a real pain trying to remember the syntax.  I know I did.  Now you can graphically lock down or move blocks right in the analog editor.  I can almost hear the cheers in the background from you seasoned users.

Analog Mux and Simulation

Ever asked yourself I wonder exactly how my analog mux is implemented?   I know I have.  Now you can go into the tool and connect the analog mux one channel at a time and see the actual signal path.  No more laying awake at night wondering if your signal took AGL[6] or AGL[7] on its way home to the ADC.

View analog switch names, registers, and masks.

This feature is for the real hard core guys that want to know the actual register and mask to control each analog switch.  Now just by hovering over a switch you can get all that information.  No more digging into that big 1000+ page document to try and figure out how to control that one switch.

Measure typical route resistance with an Ohm Meter

This is another cool tool.  The Ohm Meter tool lets you measure the route resistance between any two endpoints of a signal.  Of course the measurement is not exact, but it gives you a ballpark number of what to expect. ( Please ignore the significant digits of the ohm meter reading in the figure below, it has been rounded off in the current version.)

Toggle analog switches interactively in the debugger

This feature is really powerful.  While in the debugger, you can view the state of almost any switch.  The only ones you can t monitor is the state of any switch that is controlled by hardware, such as the hardware mux.  All other analog switches that are part of a route, or controlled by software can be examined interactively.  So each time you halt the operation in the debugger, you can actually view the current state of the switches.  But wait, there s more!  You can actually toggle the state of each switch as well.  This means you can debug any route you want and interactively see what happens when you open or close a switch.  I often use a spare route and pin to internally probe signals.  Yes you heard me, this allows you to probe internal nodes while the chip is running.  If you don t like this feature, you shouldn t call yourself an engineer!

Set breakpoints when a switch opens or closes

OK one more amazing feature.  Just think of being able to click on an analog switch and set a breakpoint when that switch opens, closes, or just changes states.  Yes not kidding!  I dare you to find another vender s tool and MCU that will let you do that!

I hope this was just enough information to give you a taste of some of the new features in PSoC Creator 2.1.  So don t delay, go download PSoC Creator 2.1 and play with some of the new analog debug and design features.   If this isn t enough there are even more features to help you get your design to market faster.  You can download the new feature packed PSoC Creator 2.1 here.  So don t delay, go checkout all the good stuff!

By Mark Hastings

I recommend installing 2.1 today (http://www.cypress.com/go/psoccreator) and trying it out. Remember that you can still do breaking moves by presssing the Control key when you move things around (and there is a Tools->Options parameter to reverse the behavior if you prefer it the other way around).

Happy wobbling!

The early access program has ended as there is no need for it any more. PSoC Creator 2.1 is now officially available for download to all customers! The wait is over and we highly recommend for all users to upgrade to this new version. Many of you have asked us for rubber banding or flexible wires, which ever you prefer. We listened to your input and improved PSoC Creator in many places. It is easier to use than ever before, performance of components has significantly increased and it can be installed in parallel to Creator 2.0. If you are close to production or just want to be extra cautious, just keep Creator 2.0 for now until you have verified there are no problems.

No let us have some fun with the new version of PSoC Creator.

The new component of this release is:
     Digital Filter Block (DFB) Assembler
The updated and improved components of this release are:
     USB FS adds support for communication with an external MIDI device
     SPI master adds a high speed mode, doubling the max. baudrate to 18 Mbps

Detailed release notes; download requires to be logged in with your Cypress account

The fast option for a component update using the Update Manager takes approx. 2 Minutes with a high-speed internet connection.
You can find the Update Manager under: All Programs - Cypress - Cypress Update Manager
This program will guide you through the component update process.

The development kits are once again the CY8CKIT-030, CY8KIT-050 and CY8CKIT-001 kits. Check out the Cypress Store for details on the kits. Please register with the Cypress Developer Community (CDC), if you haven't done so already, and start posting new topics on the PSoC 3 and PSoC 5 forums

Share your thoughts, ask your questions, win a develoment kit!  Be an active member of the CDC.

The PSoC Fan Controller Component can control up to 16 independent 4-wire DC fans. Because the design is done in hardware, the cooling system will run even when the CPU is in a sleep mode or better even, the CPU can handle other real-time critical events while the fans are controlled via a hardware control loop.

AN77900 is available on the Cypress website today, contains:

• An introduction to the low-power features of the PSoC 3/5 devices.
• Information on reducing power consumption in Active and Alternate Active modes.
• Examples, tips, and tricks for success with the Sleep and Hibernate low-power modes, including example code.
• Descriptions and explanations of the registers and API associated with low-power operation.
• Step-by-step instructions for performing accurate power measurements using the Cypress DVK boards.

Example projects for both the PSoC 3 and PSoC 5 are also included with the application note:

• Low-power modes and wakeup source examples for PSoC 3.
• Low-power modes and wakeup source examples for PSoC 5.
• A simple example project with no low-power optimizations.
• The same simple example using low-power techniques.

In addition to the application note and example projects, we're pleased to be able to provide you with a spreadsheet that can be used to perform rough "back of the napkin" type estimates for the average power consumption and battery life of your design. The spreadsheet lets you use up to ten different PSoC 3/5 configurations, with selectable settings for various subsystems and components. Based upon those configurations, the spreadsheet will calculate the average power consumption and show an estimated battery life.

AN77900 is a good starting point for anyone who wants to become more familiar with the PSoC 3/5 low-power features. As with all our documentation, we're happy to hear back from you regarding any additional topics that you'd like to see covered in this application note.

By Greg Reynolds

AN78646 - Integrated Power Manager using PSoC® 1

AN78692 - PSoC® 1 - Intelligent Fan Controller

AN78737 - PSoC® 1 - Temperature Sensing Solution using a TMP05/TMP06 Digital Temperature Sensor

AN78920 - PSoC® 1 Temperature Measurement Using Diode

Power Monitor The Power Monitor is used to monitor the voltage and current for up to 32 DC-DC power converters.

To download the full installation file of Creator with the new Component Pack or check out the release notes, visit the dedicated landing page.

The kit upgrade program allows customers who own development kits with PSoC 3 ES2 silicon to get new kits with production version PSoC 3 silicon at no cost. The kits that qualify include:  PSoC 3 First Touch Kit (FTK), PSoC Processor Module Kit,  and PSoC Development kit (DVK).

Also, Customers who wish to perform Power Cycle programming but have the MiniProg3 revision *A (CY8CKIT-002) can upgrade to the MiniProg3 revision *B for free.

More details on the upgrade program..

I was also fortunate enough to visit the summer palace while in Beijing

The 17 Arch bridge on lake Kunming

And of course the golden arches ;<)

C. U. Around

What kind of bird brain decides to build a nest on an engine block?

C. U. Around

What defines the FIR filter? A two part introduction into coefficient values from our Filter Wiz Kendall.
1. Analyze your FIR filter
2. Synthesize your FIR filter. 

If you want to tap deeper into the brain of a Filter Wiz, check out Kendall's Filter Blog

This brief video shows how a PSoC based solution can control temperature and fans without the CPU even running.

MCUs CAN'T. PSoC CAN interview at the ARM booth during Design West in San Jose, 2012 as posted on Youtube.

http://www.cypress.com/?rID=58117

For more information about 8051 Code Optimization, see application note AN60630.

By Mark Ainsworth

http://www.cypress.com/?rID=57555

C. U. in St. Louis

         or

C. U. Around

Execercise to the User:

1. Set the ASign parameter of the SCBlock to "Positive" and observe the result
2. Set the ACap value to 8, 24 and 31 and observe the result.
3. Set the Polarity of the Comparator to Negative and observe the result.

For more details about Switched Capacitor blocks, refer below application note.

AN2041 - Understanding PSoC 1 Switched Capacitor Analog Blocks

The project file for the video may be found below.

PSoC Designer Project - Precision Rectifier

Placing code in RAM using GCC

Gcc supports the use of the __attribute__ keyword which allows you to apply special attributes to your code.  There are many attributes you can apply; the one we are interested in is section .

The section attribute places code in a specific memory section as defined in the cm3gcc.ld file.  RAM is defined as the .data section.  So, for example, if you wanted to place a function in RAM the code for the function prototype would look like this:

void foo (void) __attribute__ ((section(".data")));

This method can be used for variables as well.

Interrupt Example

A great use of this feature is to place interrupt handlers in RAM for faster execution time.  If you define your own ISRs you can do this by placing __attribute__ ((section .data ))) after the ISR prototype like a normal function declaration.

If you are using the Cypress generated ISR code you can add a declaration statement to the section of code at the top of the .c file which is provided for the user to include modules and declare variables.

Here is an example:

// place interrupt in SRAM to improve speed

externCY_ISR_PROTO(isr_1_Interrupt) __attribute__ ((section(".data")));

for an isr named isr_1.

Linker Warning

When you place code into the .data section you will get the following warning:

Warning: ignoring changed section attributes for .data

This is because the .data section does not, by default, expect to have code attributes associated with it.  In this case you can ignore the warning, because you intend to add attributes to the .data section.  Even though the warning indicates that the linker is ignoring your attribute, it will still place your code in RAM.  You can verify this in the map file by checking which section your code has been placed in.

To clear this warning you would need to modify the cm3gcc.ld file.  The best approach would be to add a custom section located in RAM for you code.  However, since this is Creator generated source code, changes you make to this file will be overwritten when generating the project APIs.

RAM vs Flash execution

The following table provides some sample data taken to show the code execution speed from flash vs RAM.  There is about a 30 % improvement in execution time when executing out of RAM vs flash.  This data was taken by toggling a pin in an ISR with a varying amount of code, measured in bytes.  The Cortex M3 was running at 24 MHz. There was no difference in the time it took to get into the interrupt.

By Keith Mikoleit

Six years back, I was an Applications Engineer handling broadcast video customers who were using Cypress HOTLink family of SERDES devices in broadcast video networks. I loved going to the NAB show (http://www.nabshow.com) since the entire food chain of the industry (from component vendors to content creators) gather to show case their latest technology related to broadcast video.  

One of the video applications where the new Cypress EZ-USB FX3 differentiates itself is Broadcast Video. The FX3 device is a very efficient and cost-effective way to deliver uncompressed HD video from a professional broadcast studio network to a PC-host via a SuperSpeed USB3.0 link. USB3.0 is a straightforward way to bring in uncompressed HD video from the studio network into a PC-host without a lot of hardware. For example, the Cypress EZ-USB FX3 can used in conjunction with FPGAs to bridge between other studio-video formats like SD-SDI and HD-SDI to USB3.0.

At NAB 2012 (http://www.nabshow.com) held from April 16-19^th, Nuvation, a platinum design partner certified for Cypress EZ-USB FX3 will be showcasing new USB 3.0 technology based on Cypress Semiconductor s new EZ-USB FX3 device.  The NAB show is a large convention of the entire video broadcast industry held yearly at Las Vegas. Nuvation s demonstration will show uncompressed HD video being sent into a PC for display and processing at high speeds over a USB 3.0 link.  This lightweight design showcases both a cost-effective and high throughput architecture that allows high-end video transport. Stop by Nuvation s booth N3536 at NAB 2012 to see this demonstration running live.

If you have any questions on this topic please contact designpartners@cypress.com

Thanks,

Palani

Also note that because we are translating the page weekly, the topmost posts may sometimes be in English, waiting until the next translation pass.

To configure the PSoC 3 and 5 ECO for use with a ceramic resonator, simply use the PSoC Creator Design Wide Resources interface to configure the oscillator as you normally would, then add the following lines in your main.c initialization code:

/* Configure MHz XTAL */

/* Turn automatic gain control off (AGC not necessary for resonators */

CY_SET_REG8(CYREG_FASTCLK_XMHZ_CSR, 0x05);

/* Set the XTAL feedback and watchdog voltages to a reasonable value */

CY_SET_REG8(CYREG_FASTCLK_XMHZ_CFG1, 0x55)

Also, be sure to check out AN54439 - PSoC® 3 and PSoC 5 External Oscillator to learn more about using PSoC 3 and 5's powerful ECO circuit.

Max Kingsbury

Applications Engineer

 For more information, see the Code Example "CapSense® Button and Slider Example - PSoC® 3 / PSoC 5".

By Jaya Kathuria

This video shows how a thermal managament application may be implemented using PSoC 1. 

More information on the kits used may be found in the below links.

CY8CKIT-001 PSoC Platform Development Kit

CY8CKIT-036 Thermal Management Expansion Board

The project used in the demo may be found below.

PSoC Designer Project - Thermal Management

Unfortunately, there is no such thing as an ideal converter in the real world, where systems have to contend with errors that are introduced into the system and affect the ADC s output. The most important errors are offset and gain errors.  

Refer graph below.  This is a plot of an 8 bit ADC with a range of +2.5V.  X axis denotes the input voltage and Y axis denotes the ADC counts.  The blue line is the ideal ADC output. The red line is the actual ADC output.  Notice the actual output is shifted from the ideal.  This shift is called the offset error.

 
All operational amplifiers have a finite offset voltage at the input.  This offset voltage gets added to the input signal, gets amplified by the amplifier s gain and manifests at the output.  Apart from the amplifier stage, the ADC also has its own offset voltage which adds to the system error.  Offset error is an additive error and can be easily removed from the system.

Graph below is the plot of the same 8 bit ADC with the +2.5V range.  Note that the slope of the actual output is now different from the slope of the ideal output.  This shift in slope is called the gain error.

 
These errors may be removed from a system using many calibration techniques like:

• Correlated Double Sampling
• Two-point Calibration
• Gain calibration using external reference. 

PSoC 1, with its flexible analog resources and routing makes it very easy to implement all of the above calibration techniques.  Depending upon the application, one or more of these methods can be combined to achieve maximum accuracy.
Recently, I, with my friend and colleague Pushek Madaan, wrote an article on this topic in EETimes.  The article may be found in the following link.

Calibrating Amplifiers and ADCs in SoCs

The article in PDF format and the PSoC Designer projects for the Correlated Double Sampling and Two-point calibration technique are attached here in this post.

Happy Signal Conditioning!!

Calibrating Amplifiers and ADCs in SoCs - PDF Article

PSoC Designer Project - CDS Calibration

PSoC Designer Project - Two Point Calibration

http://www.cypress.com/?rID=60521