Algorithm

The approach we'll use for a square root algorithm is essentially a guess-and-check. To calculate the square root of N, we will continue to make a guess (let's call it root) until that guess is as close to sqrt(N) as possible without going over. At each guess, we will be checking if (root + Delta)² <= N, where Delta gets progressively smaller until it is beyond the precision of our data type. If (root + Delta)² is smaller than N, we will add Delta to root to get closer to our final answer. To do this intelligently (and efficiently on hardware), we will use powers of 2: Delta = 2^{n/2 - 1}, 2^{n/2 - 2},.., 2, 1, where n is the maximum number of bits in any N we want our algorithm to handle. For you computer-sciency types, we are essentially performing a binary search of the solution space of our problem. This gives us a first cut of our algorithm:

Try #1

Many of you have probably used the Character LCD component or User Module in PSoC Creator and PSoC Designer.  It is a handy device that provides a simple and quick way to display information.  The only problem is that it has one little flaw, it must be connected to sequential pins on a single port.  Sometimes, depending on the design and package you are using, you may have the extra GPIOs but they are spread across multiple ports.  Well after today this is no longer a problem.  I posted a new component on our Community Components page.  I bet many of you didn t even know we had such a page.  This page is a place where users can download their own custom components for everyone to use.  There are already several components there worth taking a look at, even a couple by yours truly.  For Cypress employees, it is a way to get a cool prototype component out to customers without going through a very long internal process.

You can download this new CharLCDmp (Character LCD Multi-Port) component at this location.  This component is 100% software compatible with the original Character LCD.  Below is a picture of the new component (on the right) next to the original component.  The most noticeable thing you might notice is the pins are no longer hidden. 

Two other less noticeable features is that there are only 6 pins instead of 7, and the code size is a little smaller.  So what is the catch you might ask?  Well as you probably know nothing is for free in this world, but the downside isn t that bad.  The original component uses the R/W signal so it can poll the status through one of the data ports, for optimal speed.  The CharLCDmp, doesn t poll the status bit, but instead uses a standard command delay to make sure everything works OK.  Although this makes the LCD a little slower, you can still update the display much faster than the LCD or your eyes can respond.  Since none of the signals now had to be bidirectional, I was able to take advantage of one of the real cool features of the newer generation of PSoCs.  A Control Register from the UDBs is used to drive all the signals.  Since PSoC is able to route the signals from the Control Register to the pins, it really doesn t matter where you put the pins.  The internal software just has to deal with the Control Register where the signals are always aligned perfectly.  Below is an example circuit showing the connection between the CharLCDmp component and the real LCD module.  Notice the annotation LCD component that is included in this library.

I hope this simple component will come in handy, it already has on my workbench playing with a yet to be released PSoC and development board, more about that later.  I ll try to keep these posts a little more frequent from now on. 

By Mark Hastings

Important specifications:

Supply Voltage: 5V

Accuracy: +/-0.25%

Total error band: +/-2% FSS

Sensor Operation:

This sensor has an amplified and temperature compensated output and is driven by a voltage supply. The output curve and equation are shown below.

Design:

The design is very simple as both amplification and temperature compensation are done within PSoC.  Resolution should be 1/1000th of full scale, hence a 10-bit ADC is required. The sensor output voltage goes to 90% of the supply voltage, so the ADC range should be vssa vdda. The ADC should operate with the rail-rail buffer enabled. Sensor output is ratiometric and the ADC reference should be Vdda/4.

PSoC Top Design and ADC configuration:

Although not as many analog resources are required when interfacing a pressure sensor with an amplified output, integrating a sensor with other PSoC features such as capsense, segment LCD drive and communication protocols, etc, will lower overall system costs.

Conclusion:

PSoC3 and PSoC 5LP can sense pressure accurately while reducing BOM cost and board space by integrating the analog front-end, ADC, reference and MCU. PSoC ADC inputs can be multiplexed with many inputs (limited only by the GPIO count) allowing interfacing to multiple pressure sensors or other analog sensors. The PSoC Creator design environment makes it easier for you to design and debug, reducing the design time and your time to market.

By Praveen Sekar

Supply current = 1.5 mA

Pressure Range:  0 -15 psi (Gage)

Sensitivity (max): 10 mV / psi

Sensitivity (min): 5 mV / psi

Temp error - span (max): 0.5 % FSS

Offset (max): 2 mV

Temperature error - offset: 0.5% FSS

Specified temp range: -40 to 125 °C

Bridge resistance (max): 6.4 k (50°C)

Accuracy: +/-0.1 % FSS BFSL

Sensor Operation:

The sensor is a piezo-resistive sensor excited by a current and has an output voltage proportional to the pressure and the current. The output voltage has a 50% tolerance and the sensor provides a gain set resistor to calibrate it to 1%. When the sensor is excited by proper current excitation levels specified in the datasheet, the temperature coefficient of span and offset will cause only a very small error in the final measurement (temperature compensated).

Design:

The design requires an excitation current of 1.5mA and an ADC to measure the output voltage. With a bridge resistance of 6.4k (max) and excitation current of 1.5mA (current level prescribed in the datasheet for proper temperature compensation), the load voltage of the current source is 9.6V. This means PSoC IDAC cannot directly be used for supplying bridge current because of very high load voltage. To limit external components and get maximum value out of PSoC we can use circuit below.

By controlling the V_GS of this circuit, the I_D can be controlled. V_GS is controlled by changing the current of the sinking IDAC. R_B ensures the IDAC output voltage is within compliance and optimum. The current sense resistor (0.1%), R_SENS,aids in setting the current to 1.5mA. The voltage across R_SENS is read by PSoC ADC (0.2%) and the IDAC current is adjusted until I_D becomes 1.5mA. With this circuit, we can ensure that the current is accurate to 0.3%. A current accuracy of 2% is the requirement so the temperature error due to offset and span are within datasheet limits.

Sensor Common mode output voltage:

With this design the sensor common mode output voltage is given by;

(1.5 * 6.4)/2 + 0.150 /2 + (1.5mA * 0.05)/2 = 4.8 + 0.075 + 0.0375 = 4.91 V

Here, 1.5mA is the sensor current, 6.4k is the max bridge resistance and 0.150 V is the maximum span, 0.05 is the sense resistance.

The sensor common mode voltage is very high to directly feed into PSoC. The ADC with input buffer can accommodate only to within 200 mV of Vdda. The ADC without buffer can t be used because it has low input impedance. The PGA can allow input voltage all the way to the voltage rail, but we ll be limiting the design to supplies with very strict tolerance levels. This is not desirable as various designers might want flexibility in their power supply design (at least support 5% supplies).

Hence to lower the common mode voltage we can use a charge pump that generates a negative voltage. The generated voltage is about -3V using a negative charge pump. The ripple voltage (of <10%) on the charge pump output doesn t have a major effect as long as we set the ADC input sampling frequency as an integral multiple of the ripple frequency (the charge pump clock frequency).

ADC input range:

The sensor span is 150mV (max). The ADC input range should be > +/- 0.256V.  

Resolution:

Resolution required in 1/1000^th of full scale. At minimum span of 75mV, we require 75uV of voltage resolution. At 15-bit level, the ADC resolution is 64uV. With a gain of 4, the ADC resolution is < 16uV.

At +/-1.024V range, we require 15-bit resolution

At +/-0.256V range, we require 13-bit resolution

Reference:

This measurement requires an absolute reference. The final pressure accuracy depends on the reference accuracy, therefore the internal 1.024 V reference is a good choice.

The ADC has four channels:

0.  Sense resistance channel: This channel is used to set the current to 1.5mA

1.  Sensor Channel: Senses the sensor output

2, 3.  Calibration channels: Measures the gain set resistance for calibration

The IDAC has two channels:

1. Passes current through the calibration resistance

2. Passes current through the sensor

The ADC configuration for the pressure sensing channel is shown below.

Pressure Equation:

The pressure is computed from the measured voltage using the following equation.

P = A* (V_o / S_i) * P_r

P Pressure (in psi)

V₀ Bridge output voltage in mV

S_i Span of pressure sensor output in mV

P_r Rated Pressure (in psi)

A I/1.5. I is the actual current flowing into the pressure sensor

Calibrations required:

Span Calibration:

The Span of the pressure sensor is calibrated using the gain set resistance provided in the sensor. Using the gain set resistance, r, the span can be calibrated. The gain set resistance is trimmed such that when it s used in conjunction with a differential amplifier, it ll give a 2V span. Working the equations back, you can find that the gain set resistance.

r = (2 * Rf * Si)/ (So Si)

Here, Rf is feedback resistor of the differential amplifier, Si is the span of the pressure sensor output (differential amplifier input) and So is the span at the differential amplifier output. By looking at the datasheet of the part, Rf and So can be found. For MEAS 1210, Rf = 100k and S₀ = 2V.  By measuring r, we can find the span,

S_i = 2/(1 + (200/r))

Performance measures:

Offset:

The sensor has a 2mV offset (max). This can be calibrated out to zero.

Span error:

The gain set resistor can provide an interchangeability accuracy of 1%. In addition, the gain set resistor can be found with 0.1% accuracy only (limited by calibration resistor accuracy. If the calibration resistor is very accurate (0.01%) or calibrated, then the span error will be 1%.

Temperature Error offset:

This has a maximum error of 0.5% FS. This is 0.075 psi.

Temperature Error span:

This has a maximum error of 0.5% FS. This is 0.075psi.

Pressure non-linearity + hysteresis:

Together they contribute 0.15% FS. This is 0.022 psi.

Signal Chain:

Offset error:

The offset error of PSoC ADC is <100uV, which can be cancelled by Correlated Double Sampling (CDS).

Offset drift:

Offset drift of PSoC is 0.55uV/°C. At 50°C, this is 11uV. It is 1/7^th of minimum resolution (0.015psi). It can be cancelled by Correlated Double Sampling (CDS).

Gain error:

PSoC ADC s calibrated accuracy is 0.2%. There are 2 measurements, 1 voltage measurement and 1 current measurement (current set to 1.5mA). This can contribute to 0.4% error in total.

Gain drift:

Drift is 50 ppm/°C. For 25°C change, it ll be 0.125%.

List of all errors:

PSoC Value:

Apart from integrating the analog front end, ADC, 0.1% precision reference, Op-Amp, IDAC and the MCU and providing a separate channel for accurate temperature measurement, PSoC can integrate miscellaneous features suchascapsense, segment LCD drive and communications protocols. Designing with PSoC creator reduces the design time considerably. The BOM cost and board size can also be significantly reduced.

In the next part we ll see how to interface unamplified compensated pressure sensor with PSoC3.

By Praveen Sekar

Supply voltage = 5V

Pressure Range:  0 -15 psi (Gage)

Sensitivity (max): 6.9 mV / psi (25°C)

Sensitivity (min): 3.3 mV / psi (25°C)

Temp Coefficient of sensitivity (max): -3.8 %

Offset: 35.6 mV (50°C)

Temperature coefficient of offset: 1.5%

Specified temp range: -40 to 125 °C

Bridge resistance (max): 5.9 k (50°C)

Accuracy: +/-0.25 % FSS BFSL

Sensor operation:

This type of pressure sensor is a piezo-resistive sensor (Wheatstone s bridge) driven by a voltage supply. The bridge output voltage is directly proportional to the applied pressure and the supply voltage. The primary sources of error to be factored in while designing with this type of sensor is the sensor offset error, span error and temperature coefficient of span and offset (since the sensor is temperature uncompensated, temperature coefficient of span and offset play a major role in the final error).

Design:

The design parameters of concern are the ADC resolution, input range and reference.

ADC input range:

This parameter is dependent on the maximum voltage output, V₀, from the pressure sensor. At 5V supply and using the maximum offset and sensitivity possible, we get;

V₀ (max) = 6.9 * 15 + 35.6 = 139.1 mV

ADC input range should be greater than +/-0.256 V.

Resolution:

1/1000^th of the full scale resolution is sufficient in pressure sensing applications.

Pressure resolution = 15 psi/1000 = 0.015 psi

Voltage resolution = 49.543 mV/1000 = 49.543uV

This requires a 16-bit ADC in +/-1.024V range or 14-bit ADC in +/-0.256V range.

Reference:

A ratiometric reference should be used in this case. Hence PSoC reference should be configured for internal vdda/4 , where vdda = 5 volts.

PSoC Creator Top Design:

The ADC has three channels, one for sensing pressure and the other two used for temperature measurement. The RTD temperature is measured as described in AN70698.  ADC configuration for the pressure sensing channel is shown below.

Note that +/-Vref/4 range can also be used for this configuration in 14-bit mode.

Pressure Equation:

From the measured ADC voltage, the pressure is calculated from the equation below;

P = (V_o / S) * P_r

P Pressure (in psi)

V₀ Bridge output voltage in mV

S Span in mV

P_r Rated Pressure (in psi)

Calibrations required:

Room Temperature calibration:

Since span has a very high tolerance, we have to calibrate span before using it. Pressure sensor offset should also be calibrated before use.

Offset Calibration:

Offset of the pressure sensor has to be corrected by giving a zero pressure input and measuring the ADC output voltage, V_off.

V_off  = V_offp + V_offs

V_offp Pressure sensor offset

V_offs signal chain offset

Span/Gain Calibration:

The span of the pressure sensor is calibrated by applying a full scale pressure input to the pressure sensor and measuring the ADC output voltage, V_fs.

S = V_fs

(Where S is the Span)

By doing span calibration we are calibrating both the span error of the sensor and gain error of the ADC.

Temperature calibration:

Both the pressure sensor offset and span varies with temperature and they have to be calibrated. But the sensor datasheet doesn t provide information on the span or offset calibration. It provides only the limits of the error. If the characteristic curve is found by experiment, we can correct for both span and offset temperature coefficient accurately.

List of all errors:

*Note:  Assumes calibration source has zero error.

ADC INL and the sensor non-linearity are the only factors that can t be calibrated and will affect the final measurement.

PSoC Value:

Apart from integrating the analog front end, ADC and the MCU, providing a separate channel for accurate temperature measurement, PSoC can integrate miscellaneous features suchascapsense, segment LCD drive and communications protocols. Designing with PSoC creator can reduce the design time considerably. The BOM cost and board size can also be significantly reduced.

In the next part we ll see how to interface unamplified compensated pressure sensor with PSoC3.

By Praveen Sekar

In this four part series, piezo-resistive pressure sensing basics and the PSoC circuits for three types of pressure sensors will be examined. The first part covers piezo-resistive pressure sensor basics and introduces three categories of pressure sensors

Piezo-resistive Pressure sensor basics

 A piezo resistive pressure sensor has a silicon diaphragm whose resistance depends on its tension. The diaphragm undergoes tension whenever there is a pressure. It can be modelled by a Wheatstone s bridge where all the resistors change with pressure. When pressure is applied to the diaphragm, resistance of the two arms (diametrically opposite to each other) increases and the resistance of the other two arms decreases.

 Pressure sensor equations

 The change in resistance can be converted to voltage by voltage or current excitation. The equations involved in voltage and current excitation are shown below.

Voltage Excitation Mode:

In this case, the Wheatstone s bridge is excited by a voltage. Span is defined as the bridge output voltage for rated pressure (full pressure). Span( S) is given by

S = V * R/R

R Change in resistance for rated pressure

R - Bridge resistance

V Excitation voltage

R = P * P_s

P Rated Pressure

P_s Pressure sensitivity (Change in resistance for unit change in pressure)

P_s = R * k

k - Normalized pressure sensitivity i.e. Pressure sensitivity for 1ohm resistor

S = V * P * k

Span is independent of bridge resistance. The temperature coefficient of span primarily results from the temperature coefficient of pressure sensitivity which is dependent on the diaphragm material.

Current excitation:

In this case, the bridge is excited by a current source. In this case span is given by,

S = I * R * P * k

Where I is the excitation current.

In this case, the span depends on the current source and bridge resistance.  

The temperature coefficient of span results from the temperature coefficient of resistance and the temperature coefficient of pressure sensitivity.  By proper design, the two can be made close to each other. Hence current excited pressure sensors have the design advantage of tweaking the process parameters so as to reduce the effect of temperature on span.

Pressure sensor types

The pressure sensor span is generally around 50-150mV. Depending on whether the pressure sensor output is amplified and on whether the pressure sensor is compensated for temperature variations of span and offset, we can have the following categories of pressure sensors

1. Unamplified uncompensated pressure sensors
2. Unamplified compensated pressure sensors
3. Amplified pressure sensors/transmitters.

The next three parts explains interfacing each type of pressure sensor with PSoC and the system performance measures.

By Praveen Sekar

Anyway, it is impossible for your microcontroller to always have every serial interface that may come along.  For example, I read about a string of 50 Christmas lights that had red, green, and blue LEDs in each bulb and here comes the best part, each bulb is addressable.  Yes, you can control each individual bulb for color and intensity, four bits for each color (red, green, and blue) and 8 bits for intensity.  Of course the string of lights came with its own controller that could generate 12 different patterns, but I wanted to create my own patterns.  With a little Google searching I found that someone had already hacked the asynchronous protocol and bit-banged an IO port to control the lights with some microcontroller.  Nobody had actually created hardware to make this easier or less CPU intensive, you know why? Because nobody else used a PSoC3 or PSoC5 with their powerful UDBs!  Yes a PSoC3/5 can bit bang with the best of them, but why bother when you have extremely flexible hardware, plus bit banging is so 90's. 

The protocol was a 26-bit packet with one start and three stop bits. Each data bit was divided into three 10uS periods.  The first period is always low, the second period was low if the data was a 1 and high if the data bit was a 0 .  The last period is always high.  See images below for bit and packet formats.

The packet format is pretty straight forward with the address, brightness level and three colors packed into 26 bits.  See figure below.

I had a choice, be lazy and use a 32-bit wide shifter or use a single 8-bit wide shifter with a slightly more complicated state machine. The 32-bit wide implementation would be easier but would be a bit wasteful in hardware.  The 8-bit wide implementation would take a bit longer, but much more efficient. I choose to go with the 8-bit wide design.  One other nice feature in the UDBs, is that you can create two 4 byte FIFOs for data flowing into or out of an interface.  This turned out to be perfect since it took 4 bytes to transfer the full 26-bit packet.

The string of lights is 50 bulbs long and if you want to update all the bulbs at one time, it would take 200 bytes (50 bulbs * 4 bytes per packet). Since you don t want the processor to just sit and wait for an interface to move data, DMA is the perfect solution. This way I was able to update the entire string using DMA with almost no CPU overhead!  Where the other guys are wasting their CPU cycles toggling bits, the CPU in the PSoC could concentrate on generating cool interactive patterns, converting DMX commands to the light string format, or any other task.  What is even better, I could implement 8 of these interfaces in a single PSoC3 or PSoC5 at the same time.  

Making this interface into a PSoC Creator component, provides a way to setup all the hardware and DMA with a single start command as with all Creator components.  More APIs are added to generate cool lighting patters.  The video below is an example of version 1.0 controlling three strings of light on my house.

This second video shows four strings on the floor in our lunch room.

This third video demonstrates yet another use for the lights.

Just think of the possibilities interfacing a string of lights to anything that can be measured with a PSoC!

Here are a few other images of the actual box the string came in, the string that I modified, my interface board, and a close up view of one of the bulbs.

Stay tuned for an upcoming video with the details of what it took to make the lighting component and how easy it is to interface the string with the Cypress PSoC3 First Touch Kit.

Mark Hastings

I2C, I2S, LIN, SM Bus, SPDIF, SPI, UART, Counters, CRC generator, Glitch filter, Quadrature Decoder, Shift register, Timer, Logic gates, Flops, Digital multiplexers and de-multiplexers, control and status registers, etc. 

You get the picture, but what is currently in the library is by no means the limit of what can be created.  Recently I sent an email to our application and field application engineers and asked what they had created with UDBs.  Here is a list of some of the components people have created with PSoC UDBs.

• 60Hz Grid Lock PLL
• Numerically Controlled Oscillator (Used for DDS)
• Forward Error Correction (FEC) decoder
• No clock stretch I2C slave
• Simple components (8bit adder, PWM, digital compares etc )
• Complex Counters 
• ADC mux sequencers
• Holiday Light controller
• Square root calculator
• First order IIR filter
• Hardware state machines
• Delta sigma modulator
• UDB discrete Fourier transform
• Byte packer (sticks two 12-bit values into 3 bytes for RF transmission)
• 7-Segment Display controller
• Remote control servo controller
• Manchester Encoder/Decoder
• 1-Wire communication interface
• ClipDetect,  Monitors 16-bit audio and over rides output if value exceeds a certain limit.
• Audioclkgen,  Creates a factional N reference for the on-chip PLL.  Used in digital audio designs.

Notice that this list contains some pretty weird stuff that you would never find standard in any microcontroller.  You won t even find most this stuff in the standard PSoC Creator library, yet!  The point is, that it doesn t matter.  You can create your own  custom interface or component, that makes your project unique without adding extra external glue logic or a CPLD.

Cypress does have a Community Components page where people can post any component they have created.  Unfortunately it has been a very well kept secret until now.  Do yourself a favor and check out the Community Components page.

Also, if you want to get more training on creating components, read the app notes I mentioned above or look at the community components guidelines on this this page.

If you have created a cool component (or even a weird one), don t be afraid to share it with the Cypress community for your 15 minutes of fame. 

By Mark Hastings

It used to be with creating host applications for a computer, you only needed to create one application for Windows. In today's world, operating systems such as Mac OS X and Linux are growing in popularity. Additionally, mobile devices running Android are increasing in numbers with the continuous  production of smart phones and tablets. With so many different operating systems available, the need for cross platform functionality is ever so more important.

What if I told you there was a way to develop a PSoC 3 or PSoC 5 application to easily stream general data across USB and provide the foundation for cross platform functionality?  Using the Human Interface Device (HID) class makes this possible. Yes, the same class that is used for mice and keyboards is breaking free from the stereotype that it is limited to a device that requires some form of human interface, such as a button press, to function.

The truth is that the HID protocol provides the perfect foundation to shuttle data back and forth between a PSoC and computer, in applications where high speed data transfer is not required. Best of all is that implementing a generic HID on PSoC is easy to do and creating Graphical User Interfaces (GUIs) on various operating systems such as Windows, Mac OS X, and Linux is fairly straightforward.  AN82072: PSoC 3 / PSoC 5 USB General Data Transfer with Standard OS Drivers will guide you through all the steps required to do so. You will have your PSoC streaming data to a host operating system of your choice in no time! 

You can download this application note from the following link.
AN82072 - PSoC® 3 / PSoC 5 USB General Data Transfer with Standard OS Drivers

By Robert Murphy

1.       SMBus and PMBus

These complete Cypress power supervision portfolio for PSoC 3 and PSoC 5, by adding SMBus and PMBus slave communication capability to PSoC. Learn more about PSoC Power Supervision solution at http://www.cypress.com/go/PowerSupervision.

2.       Debouncer

This is probably going to be the most-used component out of all six new releases because it is the easiest and best way to debounce and edge-detect switch inputs to your system, without using your CPU.

3.        Glitch Filter

The hardware glitch filter removes unwanted pulses from a digital signal, and is a frequently used function in digital designs. The Glitch Filter v2.0 is a complete re-design from its previous version which was available as a PSoC Creator concept component.

For more information on switch-debouncing and glitch-filtering, see AN60024.

4.       RTD Calculator

5.       Thermistor Calculator

6.       Thermocouple Calculator

These three new components add easy-to-implement temperature-sensing capability to PSoC Creator s component library. Find out more about temperature-sensing with PSoC 3 and PSoC 5 through the suite of application notes available:

·         AN70698 - Temperature Measurement with RTDs

·         AN66477 - Temperature Measurement with Thermistor

·         AN75511 - Temperature Measurement with Thermocouples

In addition, you may be interested in:

·         AN60590 - Temperature Measurement Using Diode

·         AN65977 - Creating an Interface to a TMP05/TMP06 Digital Temperature Sensor

CP4 also provides an update to the I2C Master/Multi-Master/Slave component, with the addition of an I2C bus multiplexing feature, besides for some minor tweaks.

I have already installed CP4 on my system especially for the debouncer. Many of you may want one or more of these new components, or the more robust I2C. To get all of these, please download Component Pack 4.

The Constants component is a very simple way to display constants used by the firmware on the schematic.  Also this allows you to change firmware parameters without changing actual source code.  I have created an example component that allows the user to assigns names and values to up to four constants.  The component consists of just a symbol and a header file. Below is what the component would look like on the schematic.  The four constants have already been assigned names, DEBUG, LOOP, DELAY, and COUNT, as well as values.

Figure 1 Example Project Constants Component

The configuration is very simple.  The user simply assigns a name and value.  The header file is automatically generated.  The constants defined below will have the instance name pre-pended on the name.  For example, the LOOP constant name will be MyConstants_LOOP .

Figure 2 Configuration dialog of Project Constants Component

The generated header file would look like this using the configuration in Figure 2.

 #defineMyConstants_DEBUG   0

#defineMyConstants_LOOP   100

#defineMyConstants_DELAY   95

#defineMyConstants_COUNT   5

 

The constants can then be used throughout the firmware, just by including the MyConstants.h header file.  Below is an example of a code snippet that makes use of the constants provided in MyConstants.h.

 for(i = 0; i < MyConstants_LOOP; i++)

{

      LCD_Position(1,5);  
   
      LCD_PrintHexUint8(i);

      CyDelay(MyConstants_DELAY);

}

   

The same concept could be used for user created components for a specific application. For example a project phase component that displays on the schematic whether the project is in the release or debug phase.  The header file would contain the #define statements for the different mode.

Figure 3 Project Phase Component

Other similar components can easily be generated by the user, with just some simple basic knowledge of how to create components. For example if you wanted a waveform generator to change the waveform without changing code.

Figure 4 Application Mode Example

The header file would contain the following:

 #defineAppMode_Mode     2

#defineAppMode_SINE     0

#defineAppMode_SQUARE   1

#defineAppMode_TRIANGLE 2

 

The firmware would look at the AppMode_Mode constant to determine which waveform to generate, requiring no code changes.

This is just one simple trick to make a project more flexible and easier to change its operation without editing code.  It is also a good way to demo an application to a customer.  The user can then try different operations without editing code.  The MyConst component is generic and can be used with any project.  The ProjectPhase and AppMode components can easily be created by the user in a matter of minutes.

By Mark Hastings

Do you want to use the Programmable Logic Device (PLD) capability of PSoC, and don t know where to start? Or need to create your own custom digital components in PSoC Universal Digital Blocks (UDBs)? Then look no further.

AN82250: PSoC® 3 and PSoC 5 Implementing Programmable Logic Designs An Introduction provides you with an ideal start towards digital mastery with PSoC UDBs. By introducing the PLD architecture, and then walking through an example project, AN82250 teaches you how to create Verilog components in PSoC Creator. For those interested in advanced features of PSoC PLDs and PSoC Creator, these are touched upon in the additional reading material in the appendices.

This application note is actually the second of a three-part series of application notes written to help you learn and exploit PSoC s powerful digital capabilities. This series begins with the introductory AN81623: Digital Design Best Practices, continues with the PLD-centric AN82250, and culminates with the datapath-focused AN81256: Designing PSoC Creator Components With UDB Datapaths.

After reading AN82250, you will be able to implement moderately complex PLD-based components in PSoC Creator. AN82250 also provides a good gateway to building more complex Datapath-based designs dealt with in AN82156. So what are you waiting for? Download AN82250 now!

By Antonio De Lima Fernandes

AN82156 - Designing PSoC Creator Components With UDB Datapaths

Have you ever wondered how PSOC Creator manages to pack so much functionality into its components? Chances are the component uses the UDBs in PSoC 3 and PSoC 5 to perform calculations, comparisons, and data management.  The "secret sauce" in the UDBs is the datapath - a configurable 8-bit ALU designed to offload tasks from the CPU. The datapaths, when chained together across UDBs and/or combined with PLD logic, are powerful tools to have at your disposal. Understanding how to use them is an essential part of creating optimized PSoC 3 and PSoC 5 solutions.

AN82156 explains how the datapaths work and teaches you how to develop PSoC Creator components that use the UDB datapaths. It contains step-by-step instructions for creating your first datapath component. The appendices also review the Datapath Configuration Tool and the Verilog code it generates.

If you are planning to create a custom component, you should become familiar with the datapath and the advantages it can offer. AN82156, its example projects, and related on-demand training videos are available today from the Cypress.com website.

AN82156 Landing Page:

• AN82156 - Designing PSoC Creator Components With UDB Datapaths  

On-Demand Videos:

• PSoC Creator 210: Intro to Datapath Components
• PSoC Creator 211: Datapath Computation
• PSoC Creator 212: Datapath FIFOs
• PSoC Creator 213: Multi-Byte Datapath Components
• PSoC Creator 214: Datapath API Generation
   

By Greg Reynolds

 

Application note "AN73212 - Debugging with PSoC1" provides all the information required to debug a PSoC1 project.

Happy Debugging!

Trimming simply means adjusting register values to achieve better accuracy be it for offset of a comparator or the frequency of a clock. For clocks, trimming means calibration with respect to a higher accuracy reference clock.

In the example project associated with the application note (schematic shown above), the IMO is trimmed with a 32 kHz crystal as reference and the ILO is trimmed with the IMO as reference. This enables the IMO to achieve near MHz crystal accuracy (±0.05%) at kHz crystal cost. The ILO performance is also considerably improved with a post-trim accuracy of ±6.5% with respect to the IMO. This means that the respective trim components improve ILO accuracy by a factor of 16, and the IMO accuracy by up to a factor of 140. Moreover, the accuracy can be easily verified on the character LCD (an example is shown below) with a simple API call to check IMO and ILO errors!

I really enjoyed developing these two components. Once you program the example project on the PSoC, zap it with freeze-spray or a heat gun and have fun watching the component correct the IMO and ILO frequencies!

In conclusion, having an accurate MHz clock is important for a wide range of applications, and particularly for high-speed communication. An accurate kHz clock also has many applications, especially in low power modes when MHz clocks are switched off.

The IMO and ILO Trim components really enhance the already-flexible clocking structure in PSoC 3 & PSoC 5, and I hope that they help you out in your specific applications as well. You can download the application note and the components at AN80248's landing page.

By Antonio De Lima Fernandes

To help you learn about and effectively use the UDBs, we're launching a series of new application notes that cover the topic in great detail. The first one, AN81623, PSoC 3/5 Digital Design Best Practices, is intended to introduce designers, especially firmware engineers, to the field of digital design and how it is done with PSoC 3/5.  Forthcoming application notes will give detailed instruction on the use of PLDs, datapaths and other UDB features.

AN81623 gives a brief introduction to digital hardware design theory and then describes the digital subsystem in PSoC 3 and PSoC 5. It also describes best practices for digital design using PSoC Creator, and shows how to use static timing analysis (STA) report files.

So this application note should help you more effectively use the digital components available to you right now - Counter, Timer, PWM, Shift Register, Quadrature Decoder, and more.  And with the Lookup Table (LUT) component you should easily be able to build simple state machines. Then watch for more advanced application notes, coming soon, that will show how to implement your own complex digital designs in the PSoC 3/5 UDBs.

To download this new application note "Digital Design Best Practices" click on this link, AN81623.

By Mark Ainsworth

The second project, 2_WaveDAC8_TwoWaves shows how you can alternate between two waveforms and easily switch right at the end of each wave.  The project schematic is rather simple, and the source code can t get much simpler.

Project source code.

This is the waveform output, notice it is not just a simple sinewave.

The third project "3_WaveDAC8_UART_FSL" shows how to generate a simple FSK output when you combine the WaveDAC8 and UART components.  Note the simplicity of the schematic below.  By changing the two clocks you can generate any two frequencies you want.

The scope screen shot below shows the output of the UART and the WaveDAC8 output.

Again the code can t get much simpler to send out Hello World .

The forth project was probably the most fun.  Who doesn t enjoy dialing their phone with their own custom made PSoC controlled DTMF dialer.   This project used two WaveDAC8 components, a couple of counters, an opamp to buffer the DAC outputs, and a single clock.

This project demonstrates another cool feature of PSoC.  Since the WaveDAC8 component uses standard internal DACs to generate the output,  connecting the two DAC outputs together is not a problem.  When the DAC is in the voltage DAC mode, it is simply a current DAC with an internal resistor.  Now the coolest thing about this project is that it gives you a good chance to use that FFT feature in your digital scope.  I had the DTMF dialer project dial the sequence 159D which causes all of the eight tones to be exercised.  Using the Tek MSO 2024 FFT mode I can see the frequency spectrum of the output, cool eh?

You can find the full application note, example projects, and WaveDAC8 component library on the AN69133 Application Note web page. The application note contains details about the design of the WaveDAC8 and information on sampling theory.

So just remember, although the WaveDAC8 maybe pretty, it has some brains as well.  Since it does all it's work with DMA, it does not require any of the valuable PSoC 3 or PSoC 5 CPU cycles.

By Mark Hastings

• The update includes:
• A description of the updates to the PSoC Creator 2.1 ECO interface.
• Descriptions of ECO performance metrics, and how to measure them.
• An "Advanced Topics" section for ECO experts.
• A table of recommended MHz resonators with manufacturer specifications, reccomended configurations and typical performance metrics. (Shown below)

Check it out now, and let us know what you think in the comments!

By Max Kingsbury

Cypress Semiconductor has completed the JTAG programming qualification for Goepel Electronic (http://www.goepel.com/). The qualification covered all electrical requirements, algorithm support, and verification of multiple device packages. Cypress has qualified the 48-SSOP, 48-QFN, 68-QFN, and 100-TQFP packages.

The vendor has released their software update, CASCON GALAXY 4.6.0a 1266 and VarioTAP model libraries, which contains JTAG programming support for the entire PSoC 3 device family. All testing was conducted on the SCAN FLEX SFX/ASL1149 programmer. Prior to programming PSoC 3 devices via JTAG or through a JTAG chain, users will need to ensure they have the latest Cypress supporting software via Goepel and the correct Goepel JTAG programmers.

For more information on device programming capabilities and software pricing contact the Goepel Sales office:
For more information on PSoC programming, visit the PSoC programming landing page.
If you need additional device support please file a tech support case.

The early access program has ended as there is no need for it any more. PSoC Creator 2.1 is now officially available for download to all customers! The wait is over and we highly recommend for all users to upgrade to this new version. Many of you have asked us for rubber banding or flexible wires, which ever you prefer. We listened to your input and improved PSoC Creator in many places. It is easier to use than ever before, performance of components has significantly increased and it can be installed in parallel to Creator 2.0. If you are close to production or just want to be extra cautious, just keep Creator 2.0 for now until you have verified there are no problems.

No let us have some fun with the new version of PSoC Creator.

The new component of this release is:
     Digital Filter Block (DFB) Assembler
The updated and improved components of this release are:
     USB FS adds support for communication with an external MIDI device
     SPI master adds a high speed mode, doubling the max. baudrate to 18 Mbps

Detailed release notes; download requires to be logged in with your Cypress account

The fast option for a component update using the Update Manager takes approx. 2 Minutes with a high-speed internet connection.
You can find the Update Manager under: All Programs - Cypress - Cypress Update Manager
This program will guide you through the component update process.

The development kits are once again the CY8CKIT-030, CY8KIT-050 and CY8CKIT-001 kits. Check out the Cypress Store for details on the kits. Please register with the Cypress Developer Community (CDC), if you haven't done so already, and start posting new topics on the PSoC 3 and PSoC 5 forums

Share your thoughts, ask your questions, win a develoment kit!  Be an active member of the CDC.

The PSoC Fan Controller Component can control up to 16 independent 4-wire DC fans. Because the design is done in hardware, the cooling system will run even when the CPU is in a sleep mode or better even, the CPU can handle other real-time critical events while the fans are controlled via a hardware control loop.

AN77900 is available on the Cypress website today, contains:

• An introduction to the low-power features of the PSoC 3/5 devices.
• Information on reducing power consumption in Active and Alternate Active modes.
• Examples, tips, and tricks for success with the Sleep and Hibernate low-power modes, including example code.
• Descriptions and explanations of the registers and API associated with low-power operation.
• Step-by-step instructions for performing accurate power measurements using the Cypress DVK boards.

Example projects for both the PSoC 3 and PSoC 5 are also included with the application note:

• Low-power modes and wakeup source examples for PSoC 3.
• Low-power modes and wakeup source examples for PSoC 5.
• A simple example project with no low-power optimizations.
• The same simple example using low-power techniques.

In addition to the application note and example projects, we're pleased to be able to provide you with a spreadsheet that can be used to perform rough "back of the napkin" type estimates for the average power consumption and battery life of your design. The spreadsheet lets you use up to ten different PSoC 3/5 configurations, with selectable settings for various subsystems and components. Based upon those configurations, the spreadsheet will calculate the average power consumption and show an estimated battery life.

AN77900 is a good starting point for anyone who wants to become more familiar with the PSoC 3/5 low-power features. As with all our documentation, we're happy to hear back from you regarding any additional topics that you'd like to see covered in this application note.

By Greg Reynolds

Power Monitor The Power Monitor is used to monitor the voltage and current for up to 32 DC-DC power converters.

To download the full installation file of Creator with the new Component Pack or check out the release notes, visit the dedicated landing page.

The kit upgrade program allows customers who own development kits with PSoC 3 ES2 silicon to get new kits with production version PSoC 3 silicon at no cost. The kits that qualify include:  PSoC 3 First Touch Kit (FTK), PSoC Processor Module Kit,  and PSoC Development kit (DVK).

Also, Customers who wish to perform Power Cycle programming but have the MiniProg3 revision *A (CY8CKIT-002) can upgrade to the MiniProg3 revision *B for free.

More details on the upgrade program..

What defines the FIR filter? A two part introduction into coefficient values from our Filter Wiz Kendall.
1. Analyze your FIR filter
2. Synthesize your FIR filter. 

If you want to tap deeper into the brain of a Filter Wiz, check out Kendall's Filter Blog

This brief video shows how a PSoC based solution can control temperature and fans without the CPU even running.

MCUs CAN'T. PSoC CAN interview at the ARM booth during Design West in San Jose, 2012 as posted on Youtube.

Execercise to the User:

1. Set the ASign parameter of the SCBlock to "Positive" and observe the result
2. Set the ACap value to 8, 24 and 31 and observe the result.
3. Set the Polarity of the Comparator to Negative and observe the result.

For more details about Switched Capacitor blocks, refer below application note.

AN2041 - Understanding PSoC 1 Switched Capacitor Analog Blocks

The project file for the video may be found below.

PSoC Designer Project - Precision Rectifier

Placing code in RAM using GCC

Gcc supports the use of the __attribute__ keyword which allows you to apply special attributes to your code.  There are many attributes you can apply; the one we are interested in is section .

The section attribute places code in a specific memory section as defined in the cm3gcc.ld file.  RAM is defined as the .data section.  So, for example, if you wanted to place a function in RAM the code for the function prototype would look like this:

void foo (void) __attribute__ ((section(".data")));

This method can be used for variables as well.

Interrupt Example

A great use of this feature is to place interrupt handlers in RAM for faster execution time.  If you define your own ISRs you can do this by placing __attribute__ ((section .data ))) after the ISR prototype like a normal function declaration.

If you are using the Cypress generated ISR code you can add a declaration statement to the section of code at the top of the .c file which is provided for the user to include modules and declare variables.

Here is an example:

// place interrupt in SRAM to improve speed

externCY_ISR_PROTO(isr_1_Interrupt) __attribute__ ((section(".data")));

for an isr named isr_1.

Linker Warning

When you place code into the .data section you will get the following warning:

Warning: ignoring changed section attributes for .data

This is because the .data section does not, by default, expect to have code attributes associated with it.  In this case you can ignore the warning, because you intend to add attributes to the .data section.  Even though the warning indicates that the linker is ignoring your attribute, it will still place your code in RAM.  You can verify this in the map file by checking which section your code has been placed in.

To clear this warning you would need to modify the cm3gcc.ld file.  The best approach would be to add a custom section located in RAM for you code.  However, since this is Creator generated source code, changes you make to this file will be overwritten when generating the project APIs.

RAM vs Flash execution

The following table provides some sample data taken to show the code execution speed from flash vs RAM.  There is about a 30 % improvement in execution time when executing out of RAM vs flash.  This data was taken by toggling a pin in an ISR with a varying amount of code, measured in bytes.  The Cortex M3 was running at 24 MHz. There was no difference in the time it took to get into the interrupt.

By Keith Mikoleit

To configure the PSoC 3 and 5 ECO for use with a ceramic resonator, simply use the PSoC Creator Design Wide Resources interface to configure the oscillator as you normally would, then add the following lines in your main.c initialization code:

/* Configure MHz XTAL */

/* Turn automatic gain control off (AGC not necessary for resonators */

CY_SET_REG8(CYREG_FASTCLK_XMHZ_CSR, 0x05);

/* Set the XTAL feedback and watchdog voltages to a reasonable value */

CY_SET_REG8(CYREG_FASTCLK_XMHZ_CFG1, 0x55)

Also, be sure to check out AN54439 - PSoC® 3 and PSoC 5 External Oscillator to learn more about using PSoC 3 and 5's powerful ECO circuit.

Max Kingsbury

Applications Engineer

This video shows how a thermal managament application may be implemented using PSoC 1. 

More information on the kits used may be found in the below links.

CY8CKIT-001 PSoC Platform Development Kit

CY8CKIT-036 Thermal Management Expansion Board

The project used in the demo may be found below.

PSoC Designer Project - Thermal Management

Unfortunately, there is no such thing as an ideal converter in the real world, where systems have to contend with errors that are introduced into the system and affect the ADC s output. The most important errors are offset and gain errors.  

Refer graph below.  This is a plot of an 8 bit ADC with a range of +2.5V.  X axis denotes the input voltage and Y axis denotes the ADC counts.  The blue line is the ideal ADC output. The red line is the actual ADC output.  Notice the actual output is shifted from the ideal.  This shift is called the offset error.

 
All operational amplifiers have a finite offset voltage at the input.  This offset voltage gets added to the input signal, gets amplified by the amplifier s gain and manifests at the output.  Apart from the amplifier stage, the ADC also has its own offset voltage which adds to the system error.  Offset error is an additive error and can be easily removed from the system.

Graph below is the plot of the same 8 bit ADC with the +2.5V range.  Note that the slope of the actual output is now different from the slope of the ideal output.  This shift in slope is called the gain error.

 
These errors may be removed from a system using many calibration techniques like:

• Correlated Double Sampling
• Two-point Calibration
• Gain calibration using external reference. 

PSoC 1, with its flexible analog resources and routing makes it very easy to implement all of the above calibration techniques.  Depending upon the application, one or more of these methods can be combined to achieve maximum accuracy.
Recently, I, with my friend and colleague Pushek Madaan, wrote an article on this topic in EETimes.  The article may be found in the following link.

Calibrating Amplifiers and ADCs in SoCs

The article in PDF format and the PSoC Designer projects for the Correlated Double Sampling and Two-point calibration technique are attached here in this post.

Happy Signal Conditioning!!

Calibrating Amplifiers and ADCs in SoCs - PDF Article

PSoC Designer Project - CDS Calibration

PSoC Designer Project - Two Point Calibration

The partner solution of this month is developed and supported by one of our design and module partners, Redpine Signals. The RS-CY8C001-220X Wi-Fi Expansion Board Kit (EBK) is an expansion board that is designed to work with the Cypress PSoC3® and PSoC5® development kits that have an expansion connector CY8CKIT-001 (PSoC3/5), CY8CKIT-030 (PSoC3) and CY8CKIT-050 (PSoC5). It allows you to jump start your PSoC Designs that requires Wi-Fi (wireless) connectivity with an easy-to-use Wi-Fi component for Cypress's PSoC Creator , or altering sample projects provided with this kit. The Redpine Wi-Fi module present in this kit simply connects to PSoC3/5 devices using a serial interface (UART or SPI). The FCC certified Wi-Fi module present on this kit runs a TCP/IP stack and contains RF front end also, thereby offloading the entire WiFi interface to the module, which leads to quicker development cycles. The expansion board kit and the Wi-Fi module (for production purposes) are available for sale from Redpine Signals (through their distributors, Arrow and Future Electronics). The PSoC Creator component is also available for download along with example projects at the Redpine Signals Website (http://www.redpinesignals.com/cypress/psoc).

Features:

• Expansion board designed to work with the Cypress PSoC3® and PSoC5® development kits that have an expansion connector
• Based on the Redpine Signals Connect-io-n module - RS9110-N-11-22
• Fully self-contained IEEE 802.11bgn based wireless device server
• Includes all the protocol and configurations functions for WLAN connectivity in Open and Secure modes of operation
• Payload data through Serial Interface and SPI
• Terminates TCP and UDP connections, and offers transparent serial modem functionality
• Integrated antenna, frequency reference and low-frequency clock
• Ultra-low-power operation with power-save modes
• Ad-hoc and infrastructure modes for maximum deployment flexibility
• Single supply 3.1 to 3.6V operation

Would like to know your thoughts on how you would use Wi-Fi in your embedded designs. Top 3 ideas will receive a dev kit of your choice.

For more information on collateral, please visithttp://www.cypress.com/?rID=54643.

For more details on other Design Partner Solutions visit www.cypress.com/?app=search&searchType=advanced&keyword=&rtID=432&id=0&applicationID=0&l=0

For more details on the Design Partner Program visit: www.cypress.com/?id=1088&source=home_support

Feel free to drop in any questions to designpartners@cypress.com

Thanks,

Palani

http://www.eetimes.com/electrical-engineers/education-training/courses/4237731/Wizard-Filters-for-all-using-the-built-in-hardware-digital-filter-in-a-programmable-SoC

It's really too short a piece to carry any in-depth (or even in-shallow) technical perspective, but it was fun to do, and whetted my appetite for other forays into this format.  Let me know what you think!  best / Kendall

http://www.analog-eetimes.com/en/now-synthesize-your-fir-filters-using-high-school-algebra.html?cmp_id=71&news_id=222903141

and see just how easy it can be to make an FIR filter that has notches where you want them to be, not scattered randomly by some mystery filter design process.  Check out my 'null hypothesis'!  best / Kendall

In this Product How-To article Mark Saunders describes a new methodology for doing firmware development for the Cypress Arm-based Programmable SoCs, using the company s PSoC Creator in combination with Arm s uVision IDE.

This time, I am talking about the mechanics of using the µVision IDE to develop firmware for a design made in PSoC Creator. I'm just out to prove the point that you really can do it I suppose.

You can download PSoC Creator 2.0 from our website for free and you can get an evaluation of the µVision IDE from ARM so there go your excuses... go on, download a bit of software and see how easy it is to split hardware design from firmware development on configurable platforms like PSoC.

Some noteworthy components of this release are:
     emFile FAT File System for SD Cards
     emWin Graphics Library
     Resistive Touch for use with emWin
     IIR (Biquad) support added to the Filter component

You probably got prompted by Cypress Update Manager already to perform an update and download the Component Pack 1

If your settings allow the Update Manager to prompt you just once a month or never, you can also start the Cypress Update Manager manually.
You can find the Update Manager under: All Programs - Cypress - Cypress Update Manager
This program will guide you through the component update process.

http://www.analog-eetimes.com/en/analyze-fir-filters-using-high-school-algebra.html?cmp_id=71&news_id=222903041

Dust off that high school algebra about polynomials and start digging!  The second part will be along in a few weeks' time!  best - Kendall

AN73503 USB HID Bootloader provides a complete USB HID Bootloader solution for PSoC3 and PSoC5. The App Note explains,

• Procedure to create a USB Bootloader project

• Procedure to create a USB Bootloadable project

• Create your own Graphical User Interface (GUI) to Bootload via USB

Each of the above is explained with a working example. A precompiled stand alone GUI is also available with the application note that can be used to perform Bootloading. This App Note can be used as a starting point to develop your own USB Bootloader GUI and add additional features as desired.

• GPIO Pin Basics physical structure, internal routing, startup and low-power behavior.
• GPIO Pins and PSoC Creator using APIs, placing pin component symbols and macros, manual pin assignment.
• API and Register Reference component API, per-pin API, GPIO registers, nonvolatile latches.
• Examples, Tips, and Tricks a dozen examples from Hello World to controlling analog switching with hardware.

Application note AN72382 is a great starting point for anyone looking to become more familiar with the possibilities available when using PSoC 3 and PSoC 5 GPIO pins. The examples include step-by-step instructions and sample code that can be integrated into your project.

PSoC 3 Implementation

Figure below shows the overall block diagram for implementation of the Li-ion battery charger with a PSoC 3 device. The implementation is broken down into three blocks:

• Battery parameter measurement
• Charging algorithm
• External current control

Additionally, a protection block is provided for additional features related to the battery protection. The external current control can be either linear or switching type of implementation. For more information on each of these blocks and the components used, and detailed information about their implementation using PSoC 3, please refer AN73648 PSoC3 Single Cell Lithium Ion Battery Charger. The application note also provides a PSoC Creator project, which includes a charge display tool and demonstrates Li-ion battery charging.

Hint: Datasheets for all components can be opened directly within PSoC Creator. If you select the component, a preview window shows a link to the datasheet underneath the component list.

A Happy   New   Year from the PSoC Team

This guide is targeted at advanced users of PSoC Creator

MiniProg3 is used during the prototype stage of application development to program and debug PSoC 3 or PSoC 5 target devices on a development board. Third-party programmers are used for production programming of PSoC 3 or PSoC 5 in large numbers. Those programmers are used after the design is completed and the application goes for mass production. In addition, custom-developed host programmers, such as external microcontrollers, can perform in-system programming of PSoC 3 or PSoC 5 devices.

The application note AN73054 - PSoC® 3 / PSoC 5 Programming Using an External Microcontroller (HSSP) will enable in the rapid development of in-system programmers by providing a portable, modular C code that can be easily ported to any host programmer development platform with minimal changes. The following are the broad changes required while porting the code to a specific host programmer.

• SWD physical layer routines to access (read, write) the programming pins. These routines will have to be modified based on the method of accessing  an I/O pin state in the host programmer
• The method of getting the data to be programmed to the target PSoC 3/5. Some host programmers might use the on-chip memory to store the data to be programmed; other host programmers might use a communication interface like USB, SPI to get the programming data

Refer to the application note AN73054 - PSoC® 3 / PSoC 5 Programming Using an External Microcontroller (HSSP) for complete details on creating an in-system programming solution for PSoC 3/5. The example project provided with the application note uses a PSoC 5 as a host programmer to program the target PSoC 3/5 device.

Segment LCDs are available in two forms - segment LCD glass and the segment LCD module, which comes with inbuilt driver. Many times, it is difficult to get all the required display features on a LCD module. One possibility is to use a custom LCD glass and an external driver. But this increases the cost of the system. Cypress PSoC chip can do segment LCD glass drive besides executing some other major tasks with its configurable digital/analog hardware and with its 8-bit MCU. It integrates multiple functions of the system within a single chip offering significant BOM savings.

Segment LCD Drive in PSoC 1

PSoC Designer provides SLCD user module (UM) that can directly drive a multiplexed segment LCD. The SLCD UM has the following features:

• Drives LCD with ½ bias
• Supports 2, 3, and 4 common LCD
• 30 150 Hz refresh rate
• Supports Type A waveform
• Contrast control Feature

Support for Numeric (7 segment), alphanumeric (14 and 16 segment) and special symbols

SLCD is a firmware based module where the CPU generates the ½ bias waveforms by configuring the pins and associated registers. To time the refresh events, periodic interrupts are generated to the CPU using a timer. This timer is embedded within the module.

SLCD module provides two unique techniques to drive the LCD:

1.     AMUX Drive

2.     GPIO Direct Drive

How do I create a Bootloader?

What's the communication going on between my host and my target?

These and many other questions are handled in the updated Application Note AN60317. It describes how to add an I2C bootloader to a PSoC® 3 / PSoC 5 project. It also discusses how to use the PC based bootloader host program provided with PSoC Creator. Finally the application note illustrates how to create your own embedded bootloader host. Each of these is explained with examples.

The DMA can be very useful in applications that require ADC data buffering and allows the CPU to do other tasks simultaneously.  The Delta-Sigma ADC has programmable resolutions from 8-bits to 20-bits. This ADC output is available in 32-bit format consisting of four 8-bit registers: OUTSAMP, OUTSAMPM, OUTSAMPH, and OUTSAMPS registers. The OUTSAMPS register gives sign extension of the data if OUTSAMPH is read as a 16-bit register. In the default ADC configuration, the output is aligned to the least significant bit (LSB). Hence for an n bit resolution, the ADC result is always available in the least n bits starting from OUTSAMP.

8-Bit ADC Data Buffering Using DMA

For 8-bit ADC data buffering, the contents of OUTSAMP register should be moved to memory buffer on each EoC (End of Conversion) signal. The ADC generates an EoC signal at the end of each conversion, which can be used as the DMA channel trigger to buffer the ADC data. The block diagram illustrating 8-bit transfer is as follows.

AN61102 PSoC3 and PSoC5 ADC Data Buffering using DMA provides a detailed example project implementing the above block diagram. The application note also explains basics of 16-bit, and 20-bit Delta-Sigma ADC data buffering using DMA with example projects. The 20-bit example project accompanying this application note demonstrates problems with data buffering using DMA and how to tackle this using multiple DMA channels. The application note also includes an example project on 12-bit SAR ADC data buffering for PSoC 5 device.

Please access the application note webpage to download the document and zip file containing the example projects. Note that these are all updated to work with PSoC Creator 2.0, the latest edition of our PSoC Creator software.

Figure 1: I2C Hardware Block

The HW block is a serial to parallel processor designed to interface the PSoC 1 to an I²C bus. The HW block takes the burden off the CPU by providing support for HW detection of I²C status and generation of I²C signals.

EzI2Cs

The first user module to consider is the EzI2Cs UM. The EzI2Cs UM operates exclusively as a slave; there is no master version of EzI2C. The EzI2Cs UM is a firmware layer on top of the I²C hardware block. It requires minimal user knowledge of how the I²C bus works by allowing you to setup a data structure in user code, and exposing that structure to the I²C master. All I²C transactions happen in the background through interrupts. You need not worry about any of the I²C functionality once the user module is started in the main code.

I2CHW

This user module is a firmware layer on top of the I²C HW bloc and can be used as a slave, master, or multi-master slave. Unlike EzI2Cs, this user module requires more designer interaction. Status bits must be checked to see if an I²C transaction occurred. The main firmware also needs to check for error conditions on a transaction. Finally, user code must clear the status bits that are set.

For a detailed overview of the I2C block in PSoC1 and example usage of the user modules described above, please refer application note AN50987 - Getting Started with I2C in PSoC® 1.

Hysteresis comparator in PSoC1 can be implemented using either of the following types of analog blocks:

1.    Continuous time (CT) analog block

2.    Switched capacitor (SC) analog block

The CT block in PSoC1 includes an opamp and a resistor array. This makes the analog block useful for functions such as programmable gain amplifier (PGA) and comparators. The SC block of PSoC1 includes an opamp with a switched capacitor network around it. This architecture is useful in the design of integrator, differentiator, filter, amplifier, DAC and comparator.

Hysteresis Comparator using SC Block

The COMP user module in PSoC Designer can be used to design hysteresis comparators using the CT block. It is also possible to make an SC block comparator with the hysteresis. The SC block comparator s threshold level is determined by the ratio of two internal capacitors. This produces a comparator with the hysteresis that:

• Has no external components
• Allows the hysteresis thresholds to be easily changed in firmware

Figure below shows an SC block configured as a programmable threshold comparator.

AN2108 PSoC1 Impementing Hysteresis Comparators describes a detailed example to show how SC blocks can be used for such a design in PSoC1. In addition, two other design examples are also shown, along with commented firmware projects:

Design 1 shows a hysteresis comparator implementation using a CT block and external resistors. This architecture allows precise setting of the hysteresis.

Design 2 shows a unique technique to implement a comparator with independently controllable hysteresis thresholds.

Please access the application note webpage to download the document and zip file containing the example projects.  

Interrupts and Dynamic Reconfiguration

Dynamic reconfiguration allows digital and analog blocks to be shared between different user modules, performing different functions at different times. This requires designers to handle interrupts differently from normal PSoC usage and choose the ISR to execute, based on which user module is loaded at any given time. For example, a digital block may share functionality between a Timer and SPI user module. Each of these UMs have a unique interrupt service routine, however, they share the same interrupt vector.

Therefore, the interrupt vector must be routed to the ISR for the user module that is loaded when the interrupt occurs. It is best to place user modules in such a way that the number of shared interrupt vectors is minimized.

The code excerpt below is taken from the interrupt vector table located in boot.asm file.

org   2Ch    ;PSoC Block DCB03 Interrupt Vector

ljmp  Dispatch_INTERRUPT_11

reti

Normally this interrupt vector would have jumped to a routine with a name specific to the user module. The vector now jumps to a routine called Dispatch_INTERRUPT_11 instead of the user module s ISR. This interrupt handler consecutively checks each configuration that shares the block to determine the active one. When it finds the active configuration, it jumps to the appropriate ISR for the loaded user module. If many configurations share the same block, this function may take longer to execute. This also causes different interrupts to have different latencies.

For more information about setting up dynamic reconfiguration in PSoC along with an example project, please refer AN2104 Dynamic Reconfiguration using PSoC Designer.

• AN237: Migrating from 8051 to Cortex Microcontrollers
• AN234: Migrating from PIC Microcontrollers to Cortex-M3

Disable Analog Block References

PSoC Analog Blocks have individual power-down settings that are controlled by the firmware. The Analog Block References can be disabled  by a  write to the PWR bits [2:0] of the  ARF_CR register, similar to the code below:

ARF_CR &= 0xf8; //Turn off analog reference

Disable CT/SC Blocks

The continuous time (CT) blocks are powered down individually with a write to each ACBxxCRy or ACExxCRy register corresponding to the block s column. The switch capacitor (SC) blocks are similarly controlled by the ASCxxCRy or ASDxxCRy registers. The example below shows how to disable the CT and SC blocks for column zero.

ACB00CR2 &= 0xfc; // Disable CT Block

ASC10CR3 &= 0xfc; // Disable typeC SC block

ASD20CR3 &= 0xfc; // Disable typeD SC block

The CT blocks can remain in operation because they do not require a clock source. However, the SC blocks do not operate because there is no clock source for the switches.

Application Note AN47310 PSoC1 Power Savings Using Sleep Mode provides an overview of PSoC1 sleep mode basics and information on power-saving methods, and other sleep related considerations.

Signing off! Have a Merry Christmas and a Happy New Year.

By the way, I know that a lot of you have expressed interest in participating in the ARM Cortex M3 PSoC5 Design Challenge. If you have not submitted your entries. The deadline is coming soon (January 17, 2011). For more details: http://www.cypress.com/go/challenge

Palani

We will have a booth at the expo, which is open to the public (and free!) on September 27th and 28th.  We have some exciting new stuff to announce, so keep an eye out for upcoming press releases.

I'll be at the show both days, working the booth.  We'll be demonstrating some of the coolest applications PSoC can do.  If you are in the Boston are those days, please stop in and say hi!  We'll be in booth #400.  You can learn more about ESC Boston here: esc.eetimes.com/boston/

http://www.analog-europe.com/en/sample-multiple-channels-simultaneously-with-a-single-adc.html?cmp_id=71&news_id=222902424

http://www.analog-eetimes.com/en/a-fast-settling-bias-voltage-filter-with-high-ripple-rejection.html?cmp_id=71&news_id=222901909

Oh, and for another trick to help reduce the size of low-frequency gain rolloff caps in compact audio circuits, see my article in Linear Audio (www.linearaudio.net ; you actually have to pay money for it and get a paper version, how retro!  But well worth it.)

Keep on filtering!

If you've ever designed a high order analog active filter from a cascade of 'biquad' sections, you'll probably have discovered how important it is both to get those sections in the right order and to get the individual gains set properly.  It's the only way to avoid premature overload (sometimes hard to detect when it occurs internally) and excessive build-up of noise.

It seems like many digital filter designers are unaware that the issues of hidden overload and noise build-up apply just as much to digital IIR filter cascades as they do to analog filters.  In fact, although the output noise power of an analog filter falls with reducing cutoff frequency, that of a digital filter actually increases!  It's to do with the magnification of the inevitable quantization of the filter calculations, and I'll put a Filter Wizard piece out on the web on that soon.

These days, the presumption is that you'll have enough spare bits both above and below your working dynamic range that you can completely ignore this.  But these bits aren't free, either in area or power consumption.  In practical, commercially viable systems, you often have to push the hardware you can afford close to its theoretical limits to get the job done.  The PSoC3/5 DFB is a 24bit fixed-point engine, but you should still use such capacity wisely to have a chance of achieving respectable performance in your application.

So, I've put a lot of effort into ensuring that the IIR filters that the next Creator FILT component will generate are carefully sequenced and gain-adjusted to get the best (or close to the best, at least!) dynamic range possible, for any given response shape and cut-off frequency.  Low-frequency filters in particular benefit from this.  Internal safety margins are set to permit the worst case digital input signals - signals that are highly unlikely to originate from any physical system through a sampling process.  DC offset buildup - sometimes a problem with carelessly implemented IIR filter code - has been eliminated.  So, if you want to use any of the IIR filter types that we'll be supporting in the next release, please do use the Creator internal routines to do the design.  Don't assume that because you paid $10k for the math package you use, that it will do a better job - because it quite possibly won't!

The PSoC 3 is in full production NOW.

You can order or sample the following 11 marketing part numbers on www.cypress.com/go/psoc. The rest of the part numbers will be open in the next few month by stages.

11 x parts for a new year of 2011!!

After Phase 1, we'll pick the top 100 submission.  Those chosen will advance to Phase 2 and receive a free PSoC 5 Development Kit for their design.  If you haven't already submitted a design abstract, I hope you consider doing so now that you have an extra few weeks.

For more information, visit www.cypress.com/go/challenge.

There are four devices currently available:

• CY8C3866AXI-040ES3
• CY8C3866LTI-030ES3
• CY8C3866LTI-068ES3
• CY8C3866PVI-021ES3

Get'em while they're hot!

Meanwhile, for the last few days I've been in San Francisco at the 129th Convention of the Audio Engineering Society, catching up with the latest technology and product trends in high quality and professional audio. Seeing the wide spread of equipment on show at the associated exhibition brought home just how useful our new PSoC3 devices will be in this space. Of course, all the micro guys can do a mix of buttons, lights and displays. But the programmable digital hardware of PSoC3 will give it a real edge for people who are doing custom signal and control interfaces, which abound in pro audio.

Audio amplification has always been a favourite subject of mine, and I'm also struck by what a good supervisory and control processor for amplifiers that PSoC3 will make. The flexible analogue capability can be deployed for voltage and current monitoring (of the amp and the psu), power device safe area protection and thermal management, and control of internal bias currents and voltages. Novel switchmode and hybrid power supply architectures can be developed and optimized for the particular application. Programmable logic enables no-code protection interlocks, and you can use the CAN bus to form a network between multiple amplifiers to ensure synchronized performance in high channel count systems. And for many applications, the audio signal processing, routing and management possible with UDB and DFB support will be more than sufficient.

All in all, I think this is a really exciting application and close to my heart, and I hope many of you out there will take up your DVK and your copy of PSoC Creator and develop something wonderful in the audio amplifier space!

The PSoC® Expansion Board Kit For iPhone & iPod Accessories speeds up your development of accessories tremendously by offering both a hardware development kit and a pre-developed and tested software component that takes care of 2-way communication with the iPod or iPhone device. Drag and drop the component in PSoC Creator and start developing with the development kit. The kit and the component are available only to licensees of Apple's Made for iPod program, through Apple’s authorized Made for iPod component distributor. For more information on the Made for iPod program, visit http://developer.apple.com/programs/ipod

My friend and colleague, Leon Tan, explains the benefits of this development in an elegant video at http://www.cypress.com/?rID=40218. If you are type who likes iPhone applications, he also demonstrates a cool iPhone Application that shows our development kit communicating in both directions to the iPod or iPhone device.

If you are in the design community and are thinking about or you have thought about development of accessories for iPod or iPhone you are at the right place.

-Palani

But that comment also took me back to when I was a young, green engineer, designing an antialiasing filter module for a particular customer.  It turned out that the customer also needed some gain in the signal path.  "No problem, boss!", I said, "I can incorporate that in the filter".  "Kendall," he replied, "you don't understand.  That's his job.  He's got to be able to contribute something to the project or he'll get the sack".  The particular moral of that story, brought up to date, is that when you design something with PSoC3, you should really try to do something yourself, rather than just take a completely engineered example circuit provided by us (or by one of your colleagues).

And sometimes, the idea that every single component can be internal to the device is too good to be true.  I've designed quite a few active filters to run on PSoC3's analogue blocks, and they require a sprinkling of external passive components - something extra for you to add, that might differentiate your solution from someone else's.  Just recently, I've spread my wings a little, thinking what cool things could be done if you allowed for instance one external transistor.  Now that transistors are available in such tiny packages (SOT-1123 is the smallest I've seen so far, at 1x0.6mm), they take up negligible extra space and cost.  So I'm thinking of running a little 'just add one transistor" contest, to see what people can come up with.  OK, and a two transistor one as well...

And in a funny way, that's why PSoC3 is related to cake, and not just by the daft pun in the blog title.  Take the classic marketing tale of Betty Crocker cake mixes.  They got far greater engagement from their customers when they adjusted the mix formulation so that you needed to complete it by the addition of an egg.  If the whole thing came out of a packet, housewives felt rather disenfranchised from their cooking territory.  So, I'm a great fan of designing things where it's almost all done for you, but you still need to flex a few brain cells to actually get it to work out.  You actually feel like you've done something then.

My daughter gave me another example that came right out of left field.  Making a cake out of cake mix (with or without an egg) is somehow rather conventional in comparison.  Why not make your cake - or your next electronic product - out of something completely unexpected.  Meet the Ice Cream Muffin:

Ingredients: one tub of good ice cream, any flavour you want; same-sized tub of self-raising flour

Method: soften ice-cream slightly; beat in flour until mixture is smooth; bake in a medium oven until cooked.

Just as easy as a cake mix, more 'programmable', more interesting, less expected... The moral: PSoC3 might well be a solution to your problem, even if at first glance the packet seems to say something completely different.  Right, now I'm going to bake some Caramel Chew-Chew muffins for the PSoC3 team!  Happy PieSe-of-Caking - Kendall

My family were skeptical about this claim, and demanded further explanation.  With calculus off-limits in a car full of artists, and the simultaneous requirement to concentrate on the driving, I think I pulled it off - but I decided not to push my luck by setting any homework questions...

Reflecting on this later, I realized that, with a periodic modulation of the tyre tread, the frequency at which tread blocks are passing a particular point in space is being frequency-modulated, and with a unit modulation index.  The tread blocks in contact with the asphalt aren't moving at all relative to it, while the ones at the topmost part of the tyre are passing at twice the rate that an unrolled piece of tyre tread strapped to the car would do.  The tread blocks travel an approximately cycloidal path; points on the tyre's sidewall that are closer to the axis travel on a smoother curve (a curtate cycloid) that tends towards being a sinewave as you get nearer to the axis.

Does this have a PSoC3 connection?  Well, there's some interest in creating quadrature clock oscillators using the Digital Filter Block.  This will use a well-known technique - see for instance Lyons - but I'm interested in adapting the technique so that the processor can actually run on the varying clock that it creates.  Looking back on my weekend tyre experience, I now see that the equations that fall out of that look very like the parametric equations for a cycloid.  This tells us how to modify the process to correct the modulation non-linearity.

So next time you see a beat-up old truck doing something unusual on the highway, ask yourself - what does this tell me about my project?  Happy treading!  best - Kendall

• On Demand Modules
• Application Notes
• Product Brochures
• Technical Reference Manuals
• Datasheets
• Developer Kits
• Software Download

The latest, fresh out-of-oven PSoC 5 product collaterals are available to dowload as well. Enjoy!!

http://www.eet-china.com/resource/index.do?sponsorId=1000002900
 

http://blogs.arm.com/arm-events/cypress-psoc-5-device-development-board-availability-milestone-achieved/

When combining stop-frame animation with live performance, the live footage is back-projected a frame at a time behind the animated models.  Their small incremental movements are rephotographed together with the 'live' backdrop.  When the resulting shots are played back, you get the illusion of animated models 'acting' in perfect sync with the live cast of the movie.

As I was watching this, it occurred to me that there are significant parallels between this sort of approach and the common use of sampled data techniques in signal processing these days.  The 'live' footage is obtained by sampling the analogue dynamics of the actors at typically 24 frames per second.  When it's replayed in the cinema, our persistence of vision acts as a lowpass reconstruction filter.  We don't see the jerkiness of the sudden shot-to-shot changes, just an impression of the original dynamics (falsified occasionally by aliasing, but that's another story...).

We can do the same sort of thing in a mixed-signal processing engine like PSoC3.  The example that came to my mind was creating a little digital synthesiser to 'play along' with an incoming audio signal.  Imagine singing into a microphone which is driving PSoC3's main ADC, set to sample your analogue warblings (Bernard Herrmann's great score for the film, perhaps?) at say 48kHz/16bit.  We can make a little programmable digital oscillator running on the Digital Filter Block, combined with some envelope shaping and a little 70's synth-rock filter.  For the 20.8us that each input sample is sitting there - the equivalent of the film frame - the program running on PSoC3 is acting as a little stop-motion animator, making numerous small changes to parameters of another new sound.

Then we mix them together and send them back out - perhaps up the USB interface to your PC where you're re-recording this.  The result - a live actor (you) and a stop-motion skeleton with a sharp sword and a bad attitude (well, here's hoping the synth sounds that good), acting together in perfect sync!

Think about what other cool things you can do with PSoC3 that are  analogous (or should that be digitalogous?) to Ray Harryhausen's masterful animation.  Happy sampling! - Kendall

 

Stay classy my PSoC brethren.   

In order to introduct the new CapSensePlus technology enabled by PSoC, I partnered with my college product manager in China, Arden Li, to deliver two webinars: one in English, and one in Chinese. You can register the English webinar through this link.

Welcome to join the discussion and discover the fun of CapSensePlus!

With no external driver required, the “Segment LCD Driver” is the first user module that truly enables the easy-to-use and command-and-control development tool for low cost LCD segment direct drive with PSoC 1 with no external components required. This user module (SLCD) applies to all the PSoC 1 families.

Features include:

• Multiplexed -1/2 bias supported
• 2, 3, and 4 common LCD drive
• 30-150 Hz refresh rate
• LCD Drive technique using analog MUX bus
• Option of 1/2 bias to be generated externally or internally
• Supports Type A waveform only
• Contrast Control
  

Yes, it is simple

A wizard is available in PSoC Designer to shoot for "skill barrier."After the wizard is complete and the project is built, constants for all displays with corresponding IDs are available in the SLCD.inc and SLCD.h files. There are three main sections (shown with additional color coding in the figure) of the SLCD Wizard:

1. LCD Specification: Specify the number of common lines and segment lines, add or remove numeric or alphanumeric displays, and add or remove digits to or from a display.
   
2. Segment-Common Mapping Table: Maps segments and symbols to commons according to the LCD specification.
   
3. Pin Assignment: Assigns the bias pin, and common and segment lines to PSoC pins and sets group size for displays.
   

Try it in the latest PSoC Designer release: http://www.cypress.com/?rID=41083
Here are all the tranings available for PSoC Designers: http://www.cypress.com/?rID=40543

It's the result of a lot of work from the A-team (A for Audio, natch), including some Universal Digital Block magic from my Cypress co-blogger PSoC Sensei.  We're still cleaning up the PSoC Creator components for public consumption, so they won't be part of the distributed software for a while.  But eventually, you'll be able to drag-and-drop USB audio into your Creator schematics as easily as an op-amp or a NAND gate.  Is that cool, or what?

Next step is to get the built-in Digital Filter Block integrated and enabled.  We've got a 10-band-per-channel stereo graphic equalizer (yes, Old School, I know...) running, and it looks like we should be able to double the band count.  I got that general biquad ordering algorithm working that I blogged about last time.  So I'm looking forward to doing some high-order arbitrary bandpass filters for the comms applications people are asking about.  I'm also quite stimulated by a request from a correspondent who's trying to do a massively parallel bank of very narrow bandpass filters and detectors.  So much to do, so little time.  Actually, that can't be true, because little times imply large bandwidth, and I certainly don't have enough of that!

Oh, and we now have an email address: filterwizard@cypress.com gets you straight through (subject to our spam filters, of course).  Happy Filtering! - Kendall

Last week, we had our world-wide FAE Conference here at the factory in San Jose.  During one of the meetings, we showed our new ePSG (written about in a previous blog post).  It was a controversy immediately.  Within seconds people questioned our claim that the device could support 12 UARTs, or 28 PWMs.

During the meeting, I decided to prove them wrong.  I quietly loaded up PSoC Creator on my laptop and started working on a couple of new projects.  Needless to say, I was able to prove both of the claims.  I figured it was worth sharing the results with you.

12 UARTs in a Single PSoC 3 Device
Here is my working design that contains 12 UARTs.  I was able to build it and route it.  You can see the build report too.

Just to provided that this worked, here is the build report.

28 PWMs in a Single PSoC 3 Device
Everyone said it's impossible.  I had to prove them wrong.  Below is a working design that has 28 8-bit PWMs.  PSoC Creator schematic is below.

Once again, here is the build report.

We're really just starting to lear everything that can be done with the UDBs.  Of course, if you don't like our components, you can go off and write your own in Verilog.  And with the coming release of PSoC Creator Beta 5, we'll offer a Datapath Configuration Tool, that will really let you unleash the power of a UDB in your own custom component.