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Overview:
USB is the most successful peripheral interconnect and is heavily adopted in consumer electronics and PC peripherals. USB 3.0 is the next revolution in the wired USB market. The primary goal of USB 3.0 is to keep the same ease of use and flexibility that users have become comfortable with, but at a much higher data rate of 5Gbps. The other major goal of the USB 3.0 specification is the power management which is very important for "Sync & Go" applications that need to maintain long battery life.

USB 3.0 is expected to begin shipping as discrete silicon in 2009, and broad deployment of USB 3.0-enabled products is expected in 2011.

In this webinar, geared towards demystifying USB3.0 for engineers, we will cover the following:

    * USB 3.0 and why it is relevant?
    * USB 3.0 Architecture and Benefits
    * USB 3.0 vs USB2.0 Comparison
    * Early Applications and usage models

Presenters:
Hans van Antwerpen
Hans is a VP of Technical Staff at Cypress and a member of Cypress's CTO group. Hans leads the architecture definition of Cypress's USB3 products and is Cypress's delegation lead to USB-IF & DWG. Hans held positions as senior scientist, chief architect and manager on software and digital hardware programs. Hans holds a M.Sc. in Mathematics from the University of Eindhoven, The Netherlands. Hans is an expert on USB, Software and SoC architecture and design, real-time embedded systems, CPU/DSP/SoC architecture, component reuse and audio and video processing.

Ashwini Govindaraman
Ashwini is a Product Marketing Manager at Cypress's USB New Product Development group. Ashwini drives the strategy and roadmap of Cypress's USB 3.0 products in addition to engaging with key customers. Ashwini has held positions at National Semiconductor, Texas Instruments and Dust Networks in various engineering roles. Ashwini holds a B.E in Electrical and Electronics from Birla Institute of Technology and Science, Pilani, India and is currently an MBA student at the Wharton school, University of Pennsylvania.

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Overview:
How many embedded projects have you worked on that successfully transitioned between project lifecycle phases without major rework of system designs, bill of materials, layouts, etc.?

If you're answer is less than 100%, then you must attend this webinar and open your mind to a new methodology for embedded design that will save you countless hours, dollars and headaches.

In this webinar we'll explore the embedded design challenges you face on a day-to-day basis and how you can overcome them with true system-level programmability, as exemplified by Cypress's PSoC® programmable system-on-chip architectures and the PSoC CreatorTM development software.

We'll explore how you can apply a system-level programmable design methodology to your embedded designs today. This methodology allows you to:

    * Adapt to change
    * Get to market faster
    * Deal with analog complexities
    * Protect your design IP


At the end of the webinar there will be a detailed Q&A period to address your own applications and designs and ways to easily integrate such a programmable design methodology into your business processes today.

Presenters:
Jim Davis
Jim Davis is a Product Marketing Manager for PSoC programmable system-on-chip devices at Cypress Semiconductor. Since joining Cypress in 2008, he has held positions in global and product marketing for the company's wireless and PSoC solutions. Before joining Cypress, Jim served 8-years in the US Air Force as a communications officer. He holds a Masters of Software Engineering from the University of Maryland University College, Adelphia, MD and a Bachelor of Science in Computer Science from the US Air Force Academy, Colorado Springs, CO.

Robert Jania
Robert Jania is a Product Marketing Manager for Programmable System-on-Chip (PSoC) devices at Cypress Semiconductor. Since joining Cypress in 2004, he has held positions in product marketing, business development, and technical marketing for the company's PSoC, USB, and Clocking devices. He holds a Bachelor of Science degree in Computer Engineering from the University of Illinois at Urbana-Champaign.


Moderator:
David Blaza
David Blaza holds the position of Vice President, Events for TechInsights. David has over 20 years of sales, marketing and media experience in the technology sector working for companies as diverse as IBM Europe, Motorola, Mars Electronics, ChipCenter and CMP Media. David built his early career selling new technology into emerging applications; this included selling one of the first voice mail systems installed in the UK and private wireless data systems in the US. After moving into technology media in 1994, David sold some of the earliest versions of internet ads on the EETimes.com website and led the CMP Electronics Group web sales initiatives. The internet boom of 1998 lured David away from CMP to an electronics industry content and commerce website called ChipCenter but returned when this company was acquired by CMP in 2001. David was named Publisher of Embedded Systems Design magazine in late 2005, Vice President and Publisher of EE Times in 2008, and currently leads the Embedded Systems portfolio with a specific focus on the ESC event franchise. David lives in Northern California and is a graduate of the University of Bradford, England (BS, Materials Science) and the University of Stirling, Scotland (MS in Economics & Technology).

Webinar Date: June 09, 2010
Status: Available On-demand

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Overview:

A signal chain, or signal-processing chain, is a common term you have probably heard before used to describe a series of signal-conditioning components in a mixed-signal design that are used for analog signal acquisition, processing, and control.

So, what the heck is a programmable signal chain?...

A Programmable Signal Chain is a modern design methodology for implementing signal chains using programmable analog integrated with programmable digital logic and high-performance CPUs to provide unique and easy-to-implement solutions to common design challenges in mixed-signal embedded design.

• Adapt to change easier
• Get to market faster
• Deal with analog complexity
• Protect your design IP

Presenters:

Matt Branda is the Marketing Director for PSoC programmable system-on-chip devices at Cypress Semiconductor. Since joining Cypress in 2000, he has held positions in various product marketing and business development roles for the company's USB, wireless and PSoC solutions. Matt holds a Bachelors of Electrical Engineering from Rensselaer Polytechnic Institute in Troy, New York.

Mark Hastings is an Applications Engineer MTS for PSoC Programmable System-on-Chip at Cypress Semiconductor. Since joining Cypress in 1998, he worked with the first Cypress USB microcontrollers, and then in 2001 joined Cypress MicroSystems working on PSoC. Mark first worked on developing content (libraries of pre-configured analog and digital peripherals) for PSoC 1, PSoC 3, and PSoC 5, with a focus on analog. In 2009 he took a position in the PSoC applications team focused on expanding the analog capabilities and applications of Cypress's PSoC portfolio. Mark holds a Bachelors of Electrical Engineering from Washington State University.

Cypress Semiconductor Corporation

Cypress delivers high-performance, mixed-signal, programmable solutions that provide customers with rapid time-to-market and exceptional system value. Cypress offerings include the flagship PSoC® programmable system-on-chip families and derivatives such as PowerPSoC® solutions for high-voltage and LED lighting applications, CapSense® touch sensing and TrueTouch™ solutions for touchscreens. Cypress is the world leader in USB controllers, including the high-performance West Bridge™ solution that enhances connectivity and performance in multimedia handsets. Cypress is also a leader in high-performance memories and programmable timing devices. Cypress serves numerous markets including consumer, mobile handsets, computation, data communications, automotive, industrial and military. Cypress trades on the Nasdaq Global Select Market under the ticker symbol CY. Visit Cypress online at www.cypress.com.