PSoC Designer is Cypress' feature-rich integrated development environment (IDE) for Cypress's PSoC (Programmable System-on-Chip) dynamically reconfigurable mixed-signal controllers. PSoC Designer offers embedded designers much faster time-to-market and design change flexibility. Try PSoC Designer today!

This online training module first looks at the register map and configuration files used with PSoC User Modules. Then, the module will walk through how to implement dynamic reconfiguration, which allows you to reuse resources in PSoC and maximize PSoC's integration value proposition.

**Exam reference: The reference to the exam is only applicable to Cypress distributors and sales reps. To receive CYU credit, Cypress distributors and sales reps should access this course from the Cypress University Learning Management site.

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PSoC Designer is Cypress' feature-rich integrated development environment (IDE) for Cypress's PSoC (Programmable System-on-Chip) dynamically reconfigurable mixed-signal controllers. PSoC Designer offers embedded designers much faster time-to-market and design change flexibility. Try PSoC Designer today!

This online training module introduces the powerful PSoC Designer debugging tools that can save you hours in the troubleshooting process. This module goes over debugging features such as trace buffers, watch variables, breakpoints and dynamic event points. The last part of the module also walks you through debugging of a real project. For this project, you will need the CY3215-DK Basic Development Kit which includes an In-Circuit Emulator (ICE).

**Exam reference: The reference to the exam is only applicable to Cypress distributors and sales reps. To receive CYU credit, Cypress distributors and sales reps should access this course from the Cypress University Learning Management site.

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This is a web-based course that provides an overview of the PSoC Programmable System on Chip, the system level design of the PSoC Designer Design Tool, and hands-on example design projects. It will take you deep into the various valuators that are available in PSoC Designer system-level editor, the monitoring features available in the system-level editor, and will cover each of these features using example projects and the CY3270-FirstTouch Starter Kit.

This module is part of a series of courses designed to provide the necessary training to enable you to quickly take advantage of the PSoC 3 and PSoC 5 programmable system-on-chips and get to market faster.

This module introduces the analog peripherals of PSoC 3 and PSoC 5 devices that can be implemented using PSoC Creator.

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Supported Products: PSoC® 3, PSoC® 5
Required Software   : PSoC™ Creator

This module is part of a series of courses designed to provide the necessary training to enable you to quickly take advantage of the PSoC 3 and PSoC 5 programmable system-on-chips and get to market faster.

This module introduces the digital peripherals of PSoC 3 and PSoC 5 devices that can be implemented using PSoC Creator.

Download Projects

Supported Products: PSoC® 3, PSoC® 5
Required Software   : PSoC™ Creator

This module is part of a series of courses designed to provide the necessary training to enable you to quickly take advantage of the PSoC 3 and PSoC 5 programmable system-on-chips and get to market faster.

This module focuses on the system resources of the PSoC 3 and PSoC 5 devices and ends with an introductory analog design project.

Download Projects

Supported Products: PSoC® 3, PSoC® 5
Required Software   : PSoC™ Creator

This module is part of a series of courses designed to provide the necessary training to enable you to quickly take advantage of the PSoC 3 and PSoC 5 programmable system-on-chips and get to market faster.

This module focuses on the architecture and design flow of the PSoC 3 and PSoC 5 devices and ends with an introductory digital design project.

Download Projects

Supported Products: PSoC® 3, PSoC® 5
Required Software   : PSoC™ Creator

Cypress offers clock generators with programmable spread spectrum to optimize EMI reduction. By using a Cypress spread spectrum clock, you never need to worry about potential EMI test failures or changing your design. In this module, we will cover what is spread spectrum and how it will reduce EMI(Electromagnetic Interference).

This module focuses on the architecture and design flow of the PSoC 5 device and ends with an introductory digital design project.

This module focuses on the system resources of the PSoC 5 device and ends with an introductory analog design project.

The architecture, features & expansion logic of Cypress’s Asynchronous FIFOs are presented in this training module. A brief note on the applications of these devices is also included. The topics covered are:

• Overview - Asynchronous FIFOs
  • Definition
  • Basic Operations
• Features of Asynchronous FIFOs
  • Introduction
  • Read & Write operations
  • Status flags
  • Retransmit functionality
  • Common FIFO Configurations
    • Width Expansion Configuration
    • Depth Expansion Configuration
• Applications of Asynchronous FIFOs

This self paced training module provides a general introduction to the features & functionality of Cypress’s Synchronous FIFOs. It includes a brief discussion on Cypress’s portfolio of Synchronous FIFOs and their applications.

The topics covered in the training module are:

• FIFO Overview
  • Definition
  • Basic Operations
• Operations & Features of Synchronous FIFOs
  • Architecture
  • Write / Read operations
  • Status flags
  • Expansion Logic
  • Retransmit
  • Cypress Synchronous FIFO portfolio
    • Cypress’s CY7C42x1 family of Synchronous FIFOs
    • Cypress’s CY7C42x5 family of Synchronous FIFOs
• Applications of Synchronous FIFOs

This web based trainig module provides a basic understanding of the different types of memory products and discusses in detail Cypress's Asynchronous SRAM product, types features and their applications.

This tutorial will cover the following topics:

An Overview of dual port where we present the definition and the basic operations of a Dual port SRAM. We will then cover the common features in Synchronous Dual Port SRAMs like timing modes, depth & width configurations, bus matching, mailbox operations etc. The third section provides a brief overview of the unique fetures found in Cypress's Fullflex families of Synchronous Dual Port SRAMs. In the last section we present examples of applications where these devices can be used.

The datapath is an important element of the programmable digital architecture in PSoC 3 and PSoC 5. Digital components that make use of the datapath can offer better functional density along with capabilities that are not available in a Verilog implementation built using just macrocells. This course is the first in a series of courses on development using the datapath. The datapath development flow using the Datapath Configuration Tool is introduced. The shifting capability of the datapath is covered as the first capability of the datapath covered.

The development of APIs for components was first covered in "PSoC Creator 112: Intro to API Generation". This course extends on that training with the development of APIs for datapath based components.

An individual datapath is a one byte hardware element. These one byte datapaths can be combined to form multi-byte wide components. This course covers how to extend the development required for a single datapath to multiple chained datapaths.

The FIFO capability of the datapath is a differentiating capability of the datapath. FIFOs allows for high performance and reliable communication between a component and the CPU or DMA. This course covers the configuration and operation of a datapath that takes advantage of FIFOs. Usage of the Auxiliary Control Register and the Status Register is also explained.

This course extends the introduction course by covering the computational aspects of the datapath. This includes the arithmetic capabilities of the datapath along with the generation of comparison outputs. Usage of the Control Register from within a Verilog component is also explained.