Knowledge Base Articles - Cypress.com

Footprint / Landpattern of an SRAM?

Wed, 12 Sep 2012 03:22:01 -0600

The footprint sram parts can be found at ipc.org. Please click on the following link: http://ipc.org/default.aspx You would have to register to get to the calculator. Once you register in the dropbox you will be given an option to enter your choice of package and there you can find the landpattern.

Maximum Junction Temperature and Power Consumption Calculator

Mon, 07 May 2012 07:42:34 -0600

The power consumption and maximum junction temperature within the operating range can be calculated following the steps provided in Application note 'AN4017 – Understanding Temperature Specifications: An introduction'.

We have created a html tools for the same and are attached below. One is for Sync SRAMs and other one is for Async and NVSRAMs. You can use it to find Maximum Power Consumption and Maximum Junction Temperature for a Cypress SRAM part.

The following is the absolute maximum junction temperatures for the SRAM families:

Sync SRAM: 125°C
Async SRAM: 150°C
nvSRAM: 150°C

Why do your address pins not match Samsungs or other vendors?

Mon, 16 Apr 2012 00:15:06 -0600

The address can be laid out in any order. The address pinout in the case of any sram does not matter since internally you might be addressing different locations but externally you read and write from the same location. Please refer to the following appnote for further clarification. AN1083

Vss and Vcc clarification

Tue, 13 Mar 2012 06:15:50 -0600

Vss refers to ground. Vcc is the supply pin.

Battery back up for SRAM's

Tue, 13 Mar 2012 06:13:25 -0600

Cypress does not recommend any backup battery because, this varies from system to system. Its better to determine the system requirements and contact the battery manufacturer. But have a look at our NVSRAM series of products which retain the content when there is loss of power.

Floating data input on CMOS SRAM

Tue, 13 Mar 2012 06:11:11 -0600

It is not recommended to leave the CMOS inputs floating. None of the SRAM parts have any internal pullups or pulldowns on the data inputs to have a valid signal when an input is left floating. If the customer does not want to use the datalines for parity, they have to be pulled up or pulled down.

Do Address pins have internal Pull-up or Pull-down circuits?

Tue, 13 Mar 2012 06:09:13 -0600

There are no pullups or pulldowns on address pins. If the customer doesn't want to use half of the memory, then any one of the address pins can be tied high or low and the remaining can be used to address the part.

Do you have Land Patterns or layouts

Tue, 13 Mar 2012 06:07:41 -0600

There are no recommended land patterns for any devices, it is recommended that customers refer to the IPC database of land patterns for the same.

Does

Tue, 13 Mar 2012 06:05:40 -0600

The "T" on the end of the part number stands for the 'Tape-and-reel' packaging option.

For Eg. - 'T' in CY7C1021DV33-10ZSXIT implies Tape and Reel.

You can avail the packaging details of a part in the Ordering information section of the datasheet.

DRAM Availability

Tue, 13 Mar 2012 06:03:21 -0600

Cypress does not currently manufacture DRAM.

How to Submit Parts for FA

Tue, 13 Mar 2012 04:47:25 -0600

To request an FA, the customer should contact their local FAE or sales office. These groups are the point-of-contact for a failure analysis (FA). The customer should fill out the FA form that they receive from these groups, and follow the instructions given on the FA form. The can raise a service request on the website in the Failure Analysis catagory. They will be guided from there on.

Moisture Sensitivity Level (MSL) of Cypress Parts

Thu, 08 Sep 2011 21:22:46 -0600

If you know the Cypress part number:

1. Go to www.cypress.com. On the top right, you will see a “Keyword / Part Number” search box (adjacent to “Contact Us.”)

2. Select the “Part Number” tab above this text box.

3. Type the exact part number, for example CY8C29466-12PVXE.

4. The part number will be listed in the search results page.

5. Click on the part number link (1st column starting from the left). This will open a new web page.

Moisture Sensitivity Level (MSL) can be found by clicking the “Quality & Pb-free Data” link on the top, or by just scrolling down to the Quality & Pb-free Data” section about half way down the page.

All other Quality information for this part number (e.g., RoHS compliance, Lead/Ball Finish, Qualification Reports, IPC reports) can also be found on this web page.

In case of any questions, or if the information is not available for a particular part number, please create a support case at www.cypress.com/support

If you do not know the Cypress part number:

1. Go to www.cypress.com. Browse the different products (“Products” tab on the top navigation menu) by family.

2. Once you choose the relevant product family (e.g., “Clocks and Buffers->Clock Distribution,” “Memory->FIFOs”), scroll down the particular page to get to the “Parametric Product Selector.”

3. Use this tool to find the part number by function/feature, and click on the part number you are interested in. This will lead you directly to step # 5 above.

Interleaved part

Thu, 01 Sep 2011 09:48:49 -0600

The device is an interleaved part. Two adjacent bits of a logical word are separated by 7 other bits. This design scheme significantly reduces the susceptibility of the device to multi-bit upsets caused by neutrons in the atmosphere.

Does CY62256 have pull up resistor on the I/O ?

Sun, 26 Jun 2011 09:32:08 -0600

Yes, the CY62256 has pmos pull ups on the I/Os. Basically, this specific part is only designed to go up to 3.8V

Overshoot and Undershoot spec in datasheet

Sun, 26 Jun 2011 08:58:24 -0600

"Data bus input over/under shoot pulse voltage and width" In datasheet of devices says that the ViL (min) of the part is -2.0v for pulse durations of less than 20ns which is the undershoot. The part can usually withstand an overshoot voltage of Vcc + 0.5V ( Check actual values with datasheet). The duration of the overshoot does not matter as long as the overshoot is within the specified voltage range and hence we currently do not specify the duration. The part will function irrespective of the duration of the overshoot if it is within the specified max input voltage range.

Async SRAM's support BSDM format models (Boundary Scan Description Model)?

Sun, 26 Jun 2011 08:50:11 -0600

Cypress's micropower devices do not have boundary scan logic included, so we don't have BSDM models.

Decoupling for the CY7C1041CV33-12BAI ?

Sun, 26 Jun 2011 08:27:27 -0600

Cypress recommends using 0.1uF capacitors and please use them them as close to the power pin as possible.

Data retention mode for the CY7C1049CV33 ?

Sun, 26 Jun 2011 08:19:08 -0600

In the data-retention mode, the chip enable of the part will be deselected and the input voltage will be 2.0V where as in the case of standby mode the part will be deselected but the input voltage will be 3.3V.

cross-section drawings and thickness ?

Sun, 26 Jun 2011 08:17:27 -0600

The cross-section drawings and thickness are internal design rule specs, which are not supposed to be shipped out.

DIFFERENCE BETWEEN THE CY62128LL-70SC AND CY62128BLL-70SC ?

Mon, 20 Jun 2011 06:52:54 -0600

The only difference between the CY62128LL-70SC and the CY62128BLL-70SC is the die. The B revision is the same in the form, fit and function as the CY62128LL70SC.

SRAM Environmental Testing

Mon, 20 Jun 2011 02:19:11 -0600

The environmental and mechnanical testing data are available in the Qualification report available in the part number page.

Unused OE# and CE1 Pins

Sat, 11 Jun 2011 12:50:49 -0600

If you are not using OE# or CE1, they should be tied active: OE# to GND, CE1 to VCC.

SRAM powerup data output

Mon, 04 Apr 2011 23:13:44 -0600

On power up, if a read occurs, the memory will put out undefined data, i.e. '1' or '0' or 'X' since nothing was written into those memory locations.

tLZOE and tHZOE demystified

Mon, 04 Apr 2011 23:13:23 -0600

On the first look, it seems that there is a mistake in the datasheet. But, please note that these parameters are tested at opposite conditions, i.e. tLZOE is tested at high Vcc, low temp and fast corner whereas tHZOE istested at low Vcc, high temp and slow corner as the former is a min. spec.and the latter is a max. spec. So, at any given temperature and voltage, the design is guaranteed such that tHZOE is less than tLZOE to prevent bus contention.

UL94V-0_compliance

Mon, 04 Apr 2011 23:12:46 -0600

Yes, most of our devices are compliant. However please check with the quality reports for exact information.

Extra 4 or 2 bits if 32/16 bits are used in x36/x18 part.

Mon, 04 Apr 2011 23:12:15 -0600

Some layouts do have a problem of interfacing the SRAM to a standard DSP or a processor which uses only 16/32 bits. In these cases, the extra 4/2 bits have to be tied to a LOW or a HIGH value through individual resitors. These resistors could be 10K ohms or other high values. If the extra bits are not used for parity checking better to tie them to a HIGH or a LOW.

Ram 4 and Ram 5 on your Reliability report

Mon, 04 Apr 2011 23:09:15 -0600

Ram 4 and Ram 5 are the different technologies used to manufacture Cypress products. Ram 4 on the reliability report means that its a 0.35u technology and Ram 5 means its 0.25u Technology.

extra 2 bits for parity check?

Mon, 04 Apr 2011 23:06:27 -0600

The extra 2 bits for parity check are an industry standard. They can be used as an extra data lines also or as parity bits. The parity has to be calculated by external controller and our SRAM's do not have any circuitry to calculate parity.

Mean time between failures?

Mon, 04 Apr 2011 23:06:03 -0600

The formula for calculating the MTBF(mean time between failiures) is 1/FIT. FIT stands for failure in time. The FIT rate for a particular part can be found in the qual report, which can be obtained off the cypress website in qualification report in the part number page.

Parity during read and write

Mon, 04 Apr 2011 23:05:31 -0600

In all of cypress's srams, parity check logic is not implemented on the part. The parity check is upto the discretion of the customer. If they decide not to use the parity feature then, they can use the extra 4 I/O bits as data bits. For eg; the CY7C1347B is a 128K x 36 SRAM. So, generally what most of our customers do is, if they decide to include parity check feature, they will use the four bytes(8 bits each) for data and the extra 4 I/O lines for parity check. Even parity or Odd parity check has to be decided and a logic to generate the parity bit in the memory controller has to be implemented. When a write is intiated, the external memory controller will decide (depending on the data of the 8 bits and whether to check for even or odd parity) to write either a '1' or a '0' on the parity bit. When a read is intiated, the parity decoder logic in the external memory controller will read the 8 bits coming and see whether the parity bit should be a 1 or a zero and flag if there is any discrepancy found.

Failure In Time (FIT)

Mon, 04 Apr 2011 23:05:04 -0600

The FIT (Failure in Time) for a particular part is found in the Qualification Report of that part. To locate the Qualification Report please refer to the Knowledge Based article on "Qualification Report (QTP)".

Qualification Report (QTP)

Mon, 04 Apr 2011 23:02:52 -0600

Response: In most cases "Qualification report" will be available in the part number page. If it is not available, check for the following methods below.

Option-1:

1. Go to www.cypress.com

2. Enter the part number whose "Qualification Report" is needed in the "Keyword" search.

3. All the related document to this part will be displayed.

4. In the "Resource Type" select "Qualification Report", all related qualification report will be displayed.

Option-2:

1. Go to www.cypress.com,

2. Select "Design Support",

3. Select "Quality & Reliability"

4. Now in the "Qualification Report" Tab, there are two option.

a) Drop down menu to select the product family eg: Memory (All QTP related to Memory will be shown)

b) Search the QTP with a part number (eg: CY7B923) . All the related QTP will be shown.

Option-3:

1. Go to www.cypress.com

2. Select "Part Number" search.

3. Search for the part whose qualification report is required.

4. Click on the Base/Root Part.

5. Now the Qual Report download will be shown, sometimes it may require to login.

If none of the above procedure works, then create a support case to get the Qualification Report.

Initial data at power-up for the SRAMs

Wed, 30 Mar 2011 12:31:21 -0600

When the SRAM initially powers up, the register where the data settles is random. The data cannot be predicted.

Use of second chip enable on the SRAM parts ?

Wed, 30 Mar 2011 12:19:06 -0600

The Second chip enable on the some of our Cypress SRAM's does not provide any additional functionality. The primary purpose of having two chip enable pins is to allow memory banking. If you are using the part without any depth/width expansion then you should make sure to have both the chip enables active. If you want to use the part for depth/width expansion then you can take advantage of two chip enable pins by disabling one memory when the other is active. The part will operate only if you have /CE1=low and CE2=High, if either one is disabled the part becomes inactive.

Pb-Free option of SRAMs

Sat, 26 Mar 2011 03:11:43 -0600

There are requirements and conditions for the Pb-Free devices reflow process and are tabulated in the Cypress Pb-Free reflow profile shown below. The product must meet two stringent requirements, zero lead and high temperature (260 ?C) reflow capability. Higher temperature reflow capability is needed because Pb-Free solder pastes melt at higher temperatures. The Pb-Free devices are marked with an 'X' on the package in the standard parts number.

For leadframe-based packages, Nickel Palladium Gold (Ni-Pd-Au) and Matte Tin (Sn) are the primary options. Nickel Palladium Gold (Ni-Pd-Au) for internally manufactured product and Tin (Sn) for subcontract manufactured products.

BGA packages will use Tin-Silver-Copper (SnAgCu) instead of Tin-Lead (SnPb) balls

Cypress Semiconductor 260 Pb-Free Reflow Profile

PROFILE ELEMENTS	IR - INFRA RED REFLOW
Ramp Rate 217 ?C	3 ?C /sec max
Preheat Temperature 150 ?C (+/-25?C)	60 to 120 seconds max
Time 50 ?C to Peak Temperature	3.5 minutes, 6 seconds max
Temperature maintained above 217 ?C	60 to 150 seconds
Time within 5 ?C of actual peak temperature	10 to 20 seconds
Peak temp range	260 ?C (-5/+0) ?C
Ramp-down rate	6 ?C /second max

PSRAM devices Availability

Sat, 26 Mar 2011 01:29:47 -0600

Unfortunately, we do not support PSRAM devices anymore. We had sold off the PSRAM business unit to taiwan based Elite Semiconductor Memory Technology (ESMT). Their company website address is www.esmt.com.tw.

Comparison of Iccdr Between Cy7C109 and CY7C109BN

Sat, 26 Mar 2011 00:46:45 -0600

The CY7C109 was manufactured using our 0.35 micron technology. The CY7C109BN is manufactured using the 0.25 micronTechnology. Because of the change in technology and since the internal voltage of the 0.25 micron technology being less, the data retention current for the CY7C109BN has gone up to 150uA from 50uA for the CY7C109.

Data Retention Procedure for Async SRAM's

Sat, 26 Mar 2011 00:38:19 -0600

It is sufficient to pull up /CE1. This will ensure that the chip is deselected. You can use any one of the Chip enable pins(/CE1 or CE2) to select or deselect the chip. In this case, if you want to use /CE1 to deselect the chip, then leave the CE2 pin connected HIGH always. You don't have to control /WE and /OE when /CE is pulled up, but make sure that /WE and /CE are not toggling or the device might consume some current. Vcc should not drop to 0V to retain the data. It can only drop to the minimum possible voltage at which the SRAM can retain the data (as mentioned in the data retention mode characterstics in the datasheet). Also, /CE should be pulled up before lowering the voltage to Vcc.

High Z parameters for some SRAM's clarifications

Sat, 26 Mar 2011 00:32:10 -0600

Yes, this is correct. Note #7 on the datasheet, which states that tHZWE is less than tLZWE at any given temperature and voltage range. On some of our Fast Asynchronous datasheets, the value for tLZWE is less than that of tHZWE, but tLZWE is always specified as a min, while tHZWE is specified as a max. Over the course of normal operation, tHZWE should be less than that of tLZWE.

Definition of Data Retention Voltage

Thu, 24 Mar 2011 12:40:19 -0600

Data retention voltage could be explained as the lowest possible power supply voltage at which the data can be retained inside the SRAM. One thing to remember is that the chip is deselected at this point of time.

Comparative parameter of Write Recovery Time given in IDT Datasheet

Thu, 24 Mar 2011 12:14:20 -0600

The write recovery time parameter of IDT part should be compared with the THA (Address Hold from Write End) on the Cypress part.

Difference Between the CY7C1018BV33 and the CY7C1019BV33

Thu, 24 Mar 2011 12:12:23 -0600

Both the 1018 and 1019 are functionally compatible; the only difference is that one is a 300mil package and the other is a 400mil package, respectively.

Difference Between the CY7C1021B and the CY7C10211B

Thu, 24 Mar 2011 11:57:33 -0600

The Memory access parameters of CY7C1021BN are bit higher than that of CY7C10211BN. The Write and Read Cycles value is 12nS for CY7C1021BN, where it is 10nS for CY7C10211BN.

Width and Depth Expansion of the CY7C1021 (64K x 16) SRAM

Thu, 24 Mar 2011 11:46:17 -0600

Depth Expansion: Connect to each other 16 bit address lines and 16 bit data lines respectively of both the SRAMs and use the chip select as 17th address line to select one memory chip. Now we have total depth of Memory is 128K x 16 bits.

Width Expansion: Combine 16-bit data bus of each chip and use it as 32-bit data bus, connect to each other 16 bit address lines respectively. Now total width of memory is 64K x 32 bits.

Difference between the CY7C1021CV33 and CY7C1021DV33

Thu, 24 Mar 2011 11:40:45 -0600

'C' in CY7C1021CV33 part indicates the die revision. 'D' is a later die revision than 'C'. Both are Form, Fit and Funciton Compatible.

Please find attached the PCN which details about the difference.

For more informaiton, Please refer to this KB article -Part Number Decoder for Fast Asynchronous SRAMs

Calculate average current consumption of Async SRAM

Thu, 24 Mar 2011 11:16:43 -0600

For simplification, let's assume a 100ns cycle where 12ns is dedicated for a read or a write operation and for the remaining 88ns, the part is in standby mode. In this case, the average current consumed by the part is (.12 * Icc) + (.88 * Isb). Isb could be either Isb1 or Isb2, depending upon whether the inputs are switching or stationary.

BHE\ and BLE\ pins of a x16 part

Thu, 24 Mar 2011 11:10:50 -0600

BHE\ and BLE\ pins are intended to use for byte level access of data as explained in datasheet, but for 16 bit access both the pins can be tied to ground (logic low signal). In this case, read and write operation will be controlled respectively by OE\ and WE\.

Asynchronous Address Glitch During Write Cycle

Thu, 24 Mar 2011 11:09:34 -0600

The address can change while the write cycle is low, but it should be stable for a twc (write cycle time) to meet all other parameters. If address changes during write cycle, there is a possibility of data to be written on wrong address.

Operation of devices outside specified temperature range

Sat, 05 Mar 2011 10:47:54 -0600

The Commercial temperature rating on our datasheets guarantee an operation between 0C and 70C. The Industrial rating on our datasheets guarantee and operation between -40C and 85C. The commercial device(C) is not tested at lower temperatures and the operation at temperatures below 0C is not guaranteed. We do not recommend operation outside of the published temperature ranges, although there is a a probablity that the Cypress device could operate beyond these temperatures. We do not guarentee the performance of the device outside the range.

sram async to sync

Sat, 05 Mar 2011 10:43:57 -0600

First of all, the external device which provides all the control signals to the SRAM needs to have a clock or atleast some signals from which a clock can be extracted. Secondly, the input signals to the SRAM from the external device should be synchronized with respect to this clock. If an almost exact conversion from fast async. to Synchronous is required, then it is recommended to choose a Flowthrough Synchronous SRAM with the appropriate speed. The minimum cycle time of this Synchronous SRAM has to be lesser than the cycle time of the Asynchronous SRAM which was being used. The setup and hold times on all the signals have to be met on both the sides of the interface.

SRAM and DRAM difference

Sat, 05 Mar 2011 03:29:28 -0600

DRAM stands for Dynamic Random Access Memory. It is a type of semiconductor memory in which the memory is stored in the form of a charge. Each memory cell in a DRAM is made of a transistor and a capacitor. The data is stored in the capacitor. Capacitors loose charge due to leakage and hence DRAM's are volatile devices. To keep the data in the memory, the device must be regularly refreshed whereas SRAM is static, so it will retain a value as long as power is supplied. SRAM is typically faster than DRAM since it doesn't have refresh cycles. Since each SRAM memory cell is comprised of 6 Transistors unlike a DRAM memory cell, which is comprised of 1 Transistor and 1 Capacitor, the cost per memory cell is far greater in an SRAM compared to a DRAM. With similar reasoning, it can be asserted that DRAMs come in larger densities than SRAMs given a fixed area. Example : SRAMs are used in Caches because of higher speed and DRAMs are used for main memory in a PC because of higher densities.

No, Cypress does not manufacture DRAM's

SRAM models link

Sat, 05 Mar 2011 03:07:39 -0600

Models can be found on the part number page of the part.

However, the models can be searched on the link given below.
http://www.cypress.com/?app=search&searchType=advanced&keyword=&rtID=114&id=0&applicationID=0&l=0

SRAM tape and reel requirement

Sat, 05 Mar 2011 02:37:43 -0600

First, the part are sealed on the reel by tape and, although not hermetically sealed, it will offer additional shelf exposure time. However, this time is neither measured nor guaranteed. Second, the tape and reel materials can not withstand the standard bake temperature of 125C. However, if the parts do need to be baked then a lower temperature, but longer time, may be acceptable to reach level moisture content specification. The tape and reel bake requirement is temperature of less than 60C and a time limit of 24hrs.

Thermal resistances

Sat, 05 Mar 2011 02:30:28 -0600

Theta Ja and Theta Jc values are present in the datasheet. If the values are not present in the datasheet. Please raise a service request under "Quality Documentation"

Criteria for submitting a part for failure analysis

Sat, 05 Mar 2011 02:13:58 -0600

There are no fixed criteria to determine if the component has to be released for failure analysis. The customer should determine to the best of their ability that it is a malfunctioning Cypress part(s) that is causing their system failure.

Current (Idd) consumption at -40 and +85 degrees?

Sat, 05 Mar 2011 02:08:32 -0600

The part consumes the max current at +85degrees (High temperature)

Information on Industry standard JTAG interfaces on SRAM's.

Sat, 05 Mar 2011 02:03:07 -0600

The existing JTAG functionality on the Cypress device is the same as the JTAG functionality on all compatible memories from other vendors. Let us address this in two different steps: - Standard SRAMs: - On standard SRAM's the JTAG functionality is the same for all vendors, but the BSDL file could be different depending on the design(Silicon & Package). The difference in the BSDL file is more in terms of the pin numbering and not for anything else. QDR SRAMs:- On the QDR SRAMs, we have struggled over the last couple of months to standardize the functionality and the pin ordering of the JTAG port. Quite recently we have acheived this and the BSDL file from each of the vendor will be the same for the QDR-II. The only difference in the BSDL file is from the device ID, which is supposed to remain different for every device. But users can ignore the device ID and test the device without any problems. We have been able to achieve this on the QDR-II, becuase of the fact that we are a closed consortium of 6 companies. Standard Sync SRAMs are manufactured by multiple vendors and it is very difficult to standardize the BSDL files of varied vendors.

Different in pin out for T version and TA version?

Sat, 05 Mar 2011 01:57:00 -0600

Multiple chip enables for depth expansion: three chip enables for TA (GVTI) /A (CY) package version and two chip enables for B (GVTI) /BG (CY) and T (GVTI) /AJ (CY) package versions. JTAG boundary scan for B/BG and T/AJ package version. So we get: T-version= 2 chip enables w/JTAG {/AJ (CY) package } TA-version= 3 chip enables w/o JTAG {/A (CY) package}

Address pins assignments in SRAMs

Tue, 01 Mar 2011 11:05:16 -0600

Once a address pin is assigned with a particular address bit, You will Read and Write from the same address. So, it doesn't affect the Read and Write operation. Hence, we do not provide the exact Address(A) pin numbers . This is true for all Asynchronous SRAMs.

Hence, the user can connect the address pins on their side to any address pins on the SRAM.

On Synchronous and NoBL SRAMs, however, address A0 and A1 have to be in place for all the vendors as these bits load into a burst counter.

x24 Static RAM with low standby current not available

Tue, 01 Mar 2011 11:03:52 -0600

The x24 SRAMs were originally designed to operate with high speed DSP's. Hence most of the x24 were designed for high speed operation and power was not a concern on these. So currently we do not have low power SRAM which are 24 bit wide. The x8 and x16 SRAMs are used on several wireless devices. Hence some of these SRAM's have been designed with power in mind.

NC and DNU pin

Tue, 01 Mar 2011 10:41:09 -0600

NC stands for No Connect which means that the pin is not internally connected to the die. So it can be either left floating or tied to GND or tied to VCC. DNU stands for Do Not Use. DNU pins might be used for test mode entry and hence these pins have to be left unconnected/floating.

Order of address pins

Tue, 01 Mar 2011 00:23:00 -0600

Please note that the address pins (Ax) can be assigned in any bit order for all Asynchronous SRAMs. That means you can do the address bit assignment with any of the Address pins A[18:0] mentioned in the datasheet. Once address pin is assigned with a particular address bit, you will Read and Write from the same address. This way it does not affect the Read and Write operation. Hence, we do not provide the exact Address(A) pin numbers.

The following articles explaining this in deep and tells why some Async SRAMs do have address pins order while some don't have.

Knowledge base article - Constraints and Interchangeability of Data and Address pins in Async SRAMs:

http://www.cypress.com/?id=4&rID=40896

Pin Definitions of Async SRAM's

Sun, 27 Feb 2011 08:18:50 -0600

The functionality of the different pins of Asynchronous SRAM's are:

1. CE# (or CE1# and CE2) : Chip Enables (CE#, CE1#, CE2) are used for enabling /disabling the chip.
2. WE#: Write Enable (WE#) is used for enabling write operation in the SRAM
3. A0-An: represent the address pins
4. IO0-IOn: represent the IO (data) pins
5. OE# : Output Enable(OE#) is used for enabling or disabling the output buffer on all IO0-IO15 pins (for a x16 device) and IO0-IO7 pins (for a x8 device).
6. BHE# (for x16 device): Byte High Enable is used for enabling or disabling the IO buffers on IO8-IO15 pins.
7. BLE# (for x16 device): Byte Low Enable is used for enabling or disabling the IO buffers on IO0-IO7 pins.
8. VCC: Power pin
9. VSS: Typically, the ground pin
10. NC: These are the pins not connected to the die
11. DNU: These pins could be connected to the die, and should be left floating or tied to VSS (as specified in the datasheet)

Part Number Decoder for Fast Asynchronous SRAMs

Sat, 26 Feb 2011 23:26:58 -0600

Please find attached the Part number decoder for Cypress Fast Async SRAMs.

1. Greater than or equal to 1 Mb SRAMs

2. Less than 1 Mb SRAMs

All new products have part number decoders present in the datasheet. Check the datasheet if the information is not available in documents below.

IO power in SRAMs

Sat, 26 Feb 2011 23:21:52 -0600

IO power is the power dissipated due to switching of the IO lines of the memory.

The operating current ICC mentioned in the datasheet includes only the core power, does not include the IO power. You can compute the IO power as shown below.

Assuming capacitive load only, IO power can be estimated to be ((α)* f *N * CL* V * V)
where
α is called the activity factor ; if on an average half the IO's switch per clock cycle, then α is 0.5.
f is the switching frequency or clock frequency
N is the number of IO's
CL is the capacitive load;
V is the Voltage swing of the IO.

For example: IO power for (CYD18S36V18) = (10MHz * 36 * 20pF * 3.3^2)/2 = 39.2mW.

More information can be obtained from this Application Note: http://www.cypress.com/?rID=12896

Datasheet for CYM1620 Asynchronous Module

Sat, 26 Feb 2011 22:55:07 -0600

The datasheet for the CYM1620 (64Kx16) Ram Module is attached below.

MSL (Moisture sensitivity level) of SRAMs

Wed, 02 Feb 2011 22:46:55 -0600

MSL for all the Cypress parts is available in part quality report.

Please find the quality reports for SRAMs available on following link:

http://www.cypress.com/?rID=38078