Knowledge Base Articles - Cypress.com

CapSense® Clock Warning in CY8CKIT-023 Example Projects with PSoC Creator™ 2.1 - KBA82008

Mon, 24 Sep 2012 04:37:43 -0600

Answer: When using CY8CKIT-023 PSoC MFi Expansion Board Kit example projects with PSoC Creator 2.1, it surfaces an incorrect clock setup for CapSense during build. This incorrect clock setup was not shown by previous version of PSoC Creator. The warning that comes during build of example projects states as:

Clock Warning: A clock marked as "Sync" cannot be faster than half the frequency of the clock synchronizing it.

To remove this warning, please do the following in example project:

Go to TopDesign of the project.
Double click the CapSense component.
Under General Tabs, in the Clock Settings, change the Scan Clock from 24 MHz to 12 MHz.
Clean and build the project

This change will not impact the CapSense performance much and overall look and feel of CapSense buttons and Sliders will remain same.

The knowledge base article "New clock synchronization check exposes aliased scan rate issue in CapSense" includes more details regarding this.

SETTING THE SLIDER RESOLUTION PARAMETER FOR CYONS FAMILY - KBA#82146

Wed, 12 Sep 2012 02:43:42 -0600

Answer: There is no option to set the ‘Slider Resolution’ parameter in PSoC Designer GUI, for devices belonging to CYONS series. Hence, to set the slider resolution parameter for these devices, the ‘Generate Project’ icon must be clicked. Once the relevant APIs and .asm files are attached to the project, CSA_HL.asm file must be opened and the portion stating CSA_SLIDER_RESOLUTION_TABLE: @SliderResolutionTable must be replaced by CSA_SLIDER_RESOLUTION_TABLE: dw 0x64. Here, the value 64 indicates a slider resolution of 100 represented in HEX. You may type the resolution of your choice in HEX. Once the modification is made, the file must be saved and built using ‘Build project’ icon. You may also do the same by pressing F7. After modification, the ‘Generate Project’ icon must not be clicked as it would remove the modification made.

Configuring a CY8C201xx Device for Use Either with External Pull-ups or With a Master Operating at Different VDD – KBA80735

Tue, 03 Jul 2012 02:15:44 -0600

Answer: The CY8C201xx devices support internal pull-up resistors on I2C lines. Table 1 shows the factory default settings for internal pull-up resistors.

Table 1: Factory Default Values for Internal Pull-Up Setting

Device	Internal Pull-Up (factory default)
CY8C20111/21	Disabled
CY8C201A0	Enabled
CY8C20110/80/60/40/42	Enabled

The setting for the internal pull-up resistors must match the requirements of the overall design. When the setting is incorrect, the following problems can occur:

Pull-ups should be sized correctly to meet rise time and IOL requirements in an I2C design. Use of internal pull-ups enabled in combination with external pull-ups in a CapSense® device reduces the effective resistance. Proper bus operation is not guaranteed.
Consider the scenario in which the CapSense device operates at 3.3 V with internal pull-ups enabled while the master operates at 1.8 V and external pull-ups pull the bus to 1.8 V. Bus voltage (VIH) seen by the master is between 1.8 V and 3.3 V due to the voltage divider formed by internal and external pull-ups. This condition can damage the master device.

In the above scenarios, it is recommended to DISABLE the internal pull-up resistor. This has to be done during the device configuration, before soldering it in the end system. To enable or disable the internal pull-up resistors, configure the I2CDM bit (MSB) in the I2C_ADDR_DM (7Ch) register. For more information, see CY8C201xx : Register Reference Guide.

Wake up time of CY8C20X66 family chip from sleep

Thu, 03 Sep 2009 09:43:35 -0600

Question: What is the wake up time of CY8C20X66 family chip from sleep?
Response: Wake up time sequence from sleep of this chip is given on page 87 of attached TRM. Here “Power Good” time will be around 100uS and total wake up time from GPIO interrupt to execution of first instruction in GPIO ISR is 180uS maximum.