Refer to Getting Started with CapSense for more information on how to use springs as CapSense sensors.

If you are new to the PSoC family of devices and the PSoC Creator™ development tool, read the supplemental material available within the PSoC Creator integrated development environment (IDE). Launch PSoC Creator and navigate to the following items:

• Quick Start Guide: Select the menu item: Help > Documentation > Quick Start Guide. This guide teaches you how to create projects using PSoC Creator.
• Simple Component Example Projects: Select File > Open > Example projects. These example projects demonstrate how to configure and use Creator components.
• Starter Designs: Select File > New > Project > PSoC3 Starter Designs (or) PSoC 5LP Starter Designs. These starter designs demonstrate the unique features of the PSoC 3 and PSoC 5LP product families.

The Cypress website at www.cypress.com has additional resources for your learning needs:

Training videos: Cypress website has several “Training on-Demand” videos for PSoC 3 and PSoC 5LP. These videos are located at http://www.cypress.com/?id=2232&rtID=134. Some of the listed videos are:

• PSoC 3 and PSoC 5 101: Introduction to the Architecture and Design Flow
• PSoC 3 and PSoC 5 102: Introduction to System Resources
• PSoC 3 and PSoC 5 103: Introduction to Digital Peripherals
• PSoC 3 and PSoC 5 104: Introduction to Analog Peripherals
• Introduction to PSoC Creator

Application Notes (ANs): Application notes are available on the Cypress website to assist you with designing your PSoC application:

• A list of PSoC 3 ANs is available at http://www.cypress.com/?id=2232&rtID=76
• A list of PSoC 5LP ANs is available at http://www.cypress.com/?id=4562&rtID=76

Here are a few application notes that can help you get started with developing PSoC 3 and PSoC 5LP applications:

• AN54181 - Getting Started with PSoC® 3
• AN77759 - Getting Started with PSoC® 5LP
• AN52705 - PSoC® 3 and PSoC 5LP - Getting Started with DMA
• AN77835 - PSoC® 3 to PSoC 5LP Migration Guide
• AN57821 - PSoC® 3 and PSoC 5LP Mixed Signal Circuit Board Layout Considerations
• AN61290 - PSoC® 3 and PSoC 5LP Hardware Design Considerations

Component Datasheets: PSoC Creator utilizes "components" as interfaces to functional Hardware (HW). Each component in PSoC Creator has an associated datasheet that describes the functionality, APIs, and electrical specifications for the HW. You can access component datasheets in PSoC Creator by right-clicking a component on the schematic page or by going through the component library listing. You can also access component datasheets from the Cypress website:

• PSoC 3 Component Datasheets
• PSoC 5LP Component Datasheets

In most cases, the component datasheet provides sufficient documentation for development use. If you need additional information, refer to the technical reference manual.

Technical Reference Manuals: The TRM provides detailed descriptions of the internal architecture of PSoC 3 and PSoC 5LP devices:

• PSoC 3 Technical Reference Manuals
• PSoC 5LP Technical Reference Manuals

Datasheets: Device datasheets list the features and electrical specifications of PSoC 3 and PSoC 5LP families of devices:

• PSoC 3 Datasheets
• PSoC 5LP Datasheets

Technical Support: If you have any queries or questions, our technical support team would be happy to assist you. You can create a support request at https://secure.cypress.com/myaccount/?id=25&techSupport=1, or if you are in the United States, you can talk to our technical support team by calling our toll-free number +1-800-541-4736 and then selecting option 8 at the IVR prompt.

You can also use the following support resources if you need quick assistance:

• Self-help: http://www.cypress.com/support
• Local Sales office locations: http://www.cypress.com/?id=1062

However, for production, you will need your own VID/PID to pass USB compliance and get the hub certified. You can configure the hub to use your VID/PID either of the following ways:

1. Add an external EEPROM to your design. The external EEPROM will be programmed to provide your VID/PID, descriptors, and other hub configuration settings.


2. Purchase your parts with the internal fuse links set to your VID/PID (this is a factory function only and cannot be done after packaging).

For more information, refer to the device datasheet.

FX2LP was designed to be used in either one of the modes: Port I/O, Slave FIFO, or GPIF. For more information, refer to the application note Endpoint FIFO Architecture of EZ-USB FX1/FX2(TM) - AN4067.

It is possible to switch from one mode to another. Before switching from slave FIFO to GPIF or vice versa, you must make sure that there is no data transfer in progress as far as the physical interface is concerned or for that master on the USB end (host is not sending or receiving data from any of the endpoint).

You must make sure that the FIFO is reset and the device is in a state (no data activity in progress). When this is done, you may switch from one mode to the other. Switching from one mode of operation to another is not an intended feature, but something that you may do as long as the device is in a stable state.

For reading and writing to the external memory you can download vend_ax example to the device, and then use the A3 vendor command. Both these vendor commands use Value field to specify the memory location.

Note Install CY3684 FX2LP and CY3681 FX2 development kits for a different version of vend_ax (file path:C:\Cypress\USB\Examples).

The MiniProg3 5- and 10-pin debug connectors provide support for SWD interface modes. The pin mapping for the SWD interface mode is shown in the following figures. Note that Vtarg (pin #1) must be connected to V_DDD supply and XRES (Pin#3 for 5-pin, Pin#10 for 10-pin) must be connected to the device reset pin.

For more information, refer to the chapter “Program and Debug Interface” in the TRM.

Debug Connector (5-pin)
SWD

Thus, to get 1-MSPS sample rate, you must set the internal main oscillator (IMO) frequency at 36 MHz. Open the Clocks tab in cydwr and click Edit Clock to set the IMO at 36 MHz, as shown in the following figure.

Figure 1. IMO Frequency Setup

Note The total absolute current of all GPIOs cannot exceed 200 mA.

If you need a more accurate method of calculating the delay time, consider using hardware (PWM, Timer, SysTick) mode.

Note The WUSB-NL radio module provided with CY3668 Rev. *A does not require these modifications.

CAUTION

• ANY CHANGE TO THE MODULE HAS TO BE CARRIED OUT BY A PERSON QUALIFIED IN REPLACING CHIP COMPONENTS.
• USE ESD PROTECTION WHILE CARRYING OUT THE MODIFICATION.
• USE TEMPERATURE-CONTROLLED SOLDERING STATION (RECOMMENDED).

INSTRUCTIONS TO MODIFY WUSB-NL MODULES
Perform the following changes on both the WUSB-NL modules:

• Replace the existing capacitor at location C7 with a 33-pF, 0603 size capacitor
• Replace the existing capacitor at location C8 with a 27-pF, 0603 size capacitor

Figure 1. WUSB-NL Module and Location of C7 and C8

Cypress recommends the following parts from Murata for this purpose:

• 33-pF capacitor : GRM1885C1H330JA01D
• 27-pF capacitor : GRM1885C1H270JA01D

After you complete these changes, the WUSB-NL modules are ready to interoperate with any nonDVK hardware.

INTEROPERATING WITH NON DVK WUSB-NL HARDWARE

For a modified WUSB-NL module to interoperate with nonDVK hardware, the firmware running on both hardware must be compatible.For this reason you must port the WUSB-NL driver provided with CY3668 Rev. ** to the nonDVK hardware before initiating data communication between them. If your application requires AgileHID protocol, you must port the AgileHID protocol provided with CY3668 Rev. ** DVK to the nonDVK hardware as well. Alternatively, you can also port the firmware (WUSB-NL driver and AgileHID protocol) running on the nonDVK hardware to CY3668 Rev. ** DVK.

Answer: No. CyUSB.sys is a generic USB device driver that assumes a device has only one interface. However, composite devices are bound to windows composite driver (usbccgp.sys) by default. This exposes each interface as if it were a separate USB device. Each of these interfaces can be bound to CyUSB.sys (one instance of CyUSB.sys per interface). The composite device part of the overhead is handled by usbccgp.sys.

Answer: Error codes can be converted into strings using:

CCyUSBDevice::UsbdStatusString(ULONG stat, PCHAR s)

Where:
‘stat’ is the UsbdStatus error code obtained from NtStatus
‘s’ holds the converted string

Answer: FX2LP does not support debugging over JTAG, it only support serial port debugging. PSoC3 supports JTAG debugging and is an alternative if you only require full-speed USB.

For more details on serial port debugging with FX2LP refer to AN58009.

Answer: Yes, you use SW9 on the DVK board to select self-powered or bus-powered. J53 should be populated when using bus-powered configuration.

Answer: Yes, the FX2LP I2C controller supports clock stretching. Once the master (FX2LP) drives SCL low, external slave devices can hold SCL low to extend clock-cycle times.

For best operation, design the product so that the main antenna radiation is away from the body or at least not proximity-loaded by the human body or dielectric objects within the product.

Remember to keep the antenna away from clock lines, digital bus signals, and power supply; otherwise, harmonics of the clock frequency will jam certain receive frequencies.

•  RF path: Adhere closely to the recommended reference design circuit (Refer TRM, FIGURE-3.1)
•  Clock traces: Keep the quartz crystal traces simple and direct. The self-bias resistor should be close to the XTALi and XTALo pins. The oscillation loop, consisting of the series resistor and crystal, should be a simple, small loop. The crystal-loading capacitors should be near the crystal. The ground connection to these capacitors must be good, clean, and quiet. This prevents noise from being injected into the oscillator. It is best to have one ground plane for the entire RF section. Do not keep any unwanted trace below the crystal. The crystal and the associated components should be kept as close as possible to the IC pins (XTALOUT and XTALIN) to keep stray capacitance as minimum.
•  Power distribution and decoupling: Capacitors should be located near the VDD pins, as shown in Typical Application on page 13 of the WUSB-NL TRM.
•  Antenna placement: When using an antenna, follow the manufacturer's recommendation regarding layout.
•  Digital interface: The digital interface should be routed with a solid ground reference, to have a good return path you need a good grounding between RF and MCU that can help reduce noise 'seen' at the antenna, thus improving performance.

1. Disable the spread spectrum setting of the host
2. Update the host controller driver to the latest version
3. U3TXVDDQ and U3RXVDDQ require a 22 uF decoupling capacitor to avoid issues caused by inrush current Refer to AN70707-EZ-USB® FX3 Hardware Design Guidelines and Schematic Checklist
4. The CyU3PConnectState () API must be called in firmware with both input parameters as CyTrue

An update to CY8CKIT-033 to resolve this issue is underway. Meanwhile, multiple PSoC Creator versions can co-exist in a single PC. This implies that the same project running on Creator 2.0 can run on later versions of Creator. If you prefer to run the CY8CKIT-033 example projects with the latest version of PSoC Creator, please do the following changes to the CY8CKIT-033 example project:

1. In CY8CKIT-033 project (PSoC3_MFi_Digital_Audio_DVK), right-click the project name > Update Components > Update All to Latest > Next. A message appears asking you to add a Bootloader/Bootloadable component in TopDesign. Close the dialogue box and click Finish.
   
   Figure 1. Update all Components
     
   Note: After the update, there will be a few errors with the Bootloadable component and terminal connection. This will be solved when you complete the following steps.
2. In the Component catalog, search for the Bootloadable component. Drag the component to TopDesign of the project and double- click it. Rename the Component to ‘Bootloadable’. Also, in the Dependencies tab, browse for the bootloader .hex file (available at …\Digital_Audio_Top\Dependent Projects\Custom_I2C_Bootloader.cydsn\DP8051_Keil_903\Debug) and click OK.
   
   Figure 2. Add Bootloadable Component

   
3. In EAFramework.c, inside 'ReceiveDataFromAppleDevice' routine definition, replace 'CyBtldr_Load()' with 'Bootloadable_Load()'.
4. In TopDesign > iAP Page, reconnect the terminals of the current surge filter. 'CurrentSurgeFilterClock' net connects to 'clock', Logic 0 connects to 'reset' pin, 'Comp5VregCurrent' output connects to 'd' input and 'q' output of 'CurrentSurgeFilter' connects to 'isr_OverCurrent' interrupt.
   
   Figure 3. Reconnect Glitch Filter connections

   
5. In AudioControl.c, inside both 'ProcessAudioOut()' and 'ProcessAudioIn()' routines, the USBOutDMA and USBInDMA are dynamically configured. Replace the next TD parameter in TD configurations from 'DMA_INVALID_TD' to 'CY_DMA_DISABLE_TD'.
6. In AudioControl.c, inside ConfigureAudioPath() routine definition, add the following lines of code after 'CyPLL_OUT_SetSource(CY_PLL_SOURCE_DSI)':
   
   iAP_UartBaud_Clock_SetSourceRegister(CYCLK_SRC_SEL_IMO);
   iAP_UartBaud_Clock_SetDividerRegister(52, TRUE);
7. Do a Clean and build the project. The project is ready to work with PSoC Creator 2.2.

Response: When the Rb and Cmod is breakdown then there are 4 possibilities which can be detected with the help of supervisory code. The 4 possibilities are as follows:

1. Cmod Short: In this particular case the counts will be zero because it'll connect the input of the CapSense module directly to ground. Thus, supervisory code will be able to detect that the Cmod has been shorted.

Also, in this particular case, no matter whether the sensor was active or not, the rawcounts and baseline will snap down to 0 and the sensor will be turned OFF. The counts will be zero irrespective of the state of Rb (open/shorted/normal).

2. Cmod Open: If CMOD is open device continues to operate at higher level of noise. If your application uses thin overlay and has strong touch signal this could be painless. If touch signal is weak then you could encounter false buttons activation in this case.

3. Rb Shorted: If Rb is shorted device continues to operate at higher level of noise. If your application uses thin overlay and has strong touch signal this could be painless. If touch signal is weak you could encounter false buttons activation in this case.

Also, In this particular case the raw counts will decrease and the baseline will follow this because of its negative baseline reset.

4. Rb Open: If Rb is open counts will get saturated and the counts will be 2^Resolution -1. If resolution is set as 12 then the counts will be 4095 irrespective of Cmod open/normal. You can easily detect this as well from you supervisory code.
 

Answer: You can use supervisory code to detect if Rb or Cmod are damaged by monitoring them for shorts or opens. The four possible failure modes are:

Cmod Shorted: If this is the case, the input of the CapSense module will be connected directly to ground. Whether the sensor is active or not, the raw counts and baseline will snap down to zero and the sensor will be turned OFF. The counts will be zero irrespective of the state of Rb (open/shorted/normal).

Cmod Open: If this is the case, the device will continue to operate with a higher level of noise. If your application uses a thin overlay and has a strong touch signal this may not cause a problem. However, if the touch signal is weak in your application, you could encounter false button activations.

Rb Shorted: If this is the case, the device will continue to operate with a higher level of noise. The raw counts will decrease and the baseline will follow because of its negative baseline reset. If your application uses a thin overlay and has a strong touch signal this may not cause a problem. However, if the touch signal is weak in your application, you could encounter false button activations.

Rb Open: If this is the case, the raw counts will saturate at 2^{(Resolution -1)}. For example, if the resolution is 12, raw counts will be 4095 even if Cmod if open.

To order a CD:

PSoC Creator http://www.cypress.com/?app=cart&action=add&itemID=13084&type=2
PSoC Designer http://www.cypress.com/?app=cart&action=add&itemID=13085&type=2

To download the ISO file:

PSoC Creator: http://www.cypress.com/go/creator/download
PSoC Designer: http://www.cypress.com/go/designer/download

Once you download the ISO file you can burn a CD or mount the ISO file. For instructions see Mounting ISO Files and CD Burning

Refer to the Register Reference Guide for more information on these registers.

The difference count is calculated by subtracting the raw count without a finger on the sensor (C_S = C_P) from the raw count with a finger present on the sensor (C_S = C_P + C_F):

By substituting the equation for raw counts you can see the linear relationship between difference counts and finger capacitance:

Note: This linear relationship holds true as long as raw counts do not saturate and assumes that the sensors are fully charged and discharged to VDD and Vref respectively within 1/f_{s max}. If PRS is selected as the clock source, the average switching frequency is f_IMO/4 but the maximum switching frequency is f_IMO/2.

Answer: Cypress’s CY2305 part family has approximately 5200 transistors or 1300 gates.

Answer: Yes, the PMODE[2:0] signals can be controlled on the DVK board using SW25 or by an external processor connected to the GPIF II interface. You make this selection with J96, J97, and J98.

Answer: Each EZI2C component can support a maximum of two slave addresses and uses one Fixed Function I2C Block in PSoC 3 and PSoC 5. Because there are two hardware blocks in PSoC 3 and PSoC 5, you can place a maximum of two EZI2C components in your project. This supports up to four slave addresses. If you need additional slave addresses for your application, you can also select an I2C Slave (UDB). However, there are differences between EZI2C and I2C. The following figure shows an EZI2C component and its configuration window.

For best results, ensure that the voltage remains in one of the three operating ranges. Additionally, at 2.4 VDC the CapSense scanning functions operate at a slower frequency and response time decreases by a factor of 4.

For more details please refer to Application Note AN53490.

Answer: CapSense Express devices are designed to operate at one of three voltage ranges: 2.4 - 2.9 VDC, 3.1 - 3.6 VDC, or 4.75 - 5.25 VDC. CapSense Express devices are not designed to operate continuously over the full range of 5.25 - 2.4 VDC. This is important to know if your application is battery powered and the operating voltage may gradually decrease as the battery gradually discharges. When the operating voltage is not in the initial operating range the device will still communicate over the I2C bus but the CapSense functionality will not work. Once the device returns to the initial operating range the CapSense functionality will start again but the sensing capability may be impaired unless the system is enabled to recalibrate itself with a reset.

For best results, ensure that the voltage remains in one of the three operating ranges. Additionally, at 2.4 VDC the CapSense scanning functions operate at a slower frequency and response time decreases by a factor of 4.

If you are not adding this Additional Library then you will get the following Build error "undefined reference to `sqrt'" where sqrt is a math function.

To build DE3:

1. Open a BASH window Start → Programs → Cypress → BASH → EnvironmentOTG — Host → USB
2. Change directories to DE3
   [cy]$ cd Source/stand-alone/de3
3. Do a make clean to start from scratch
   [cy]$ make clean
4. Do a make all to rebuild all code
   [cy]$ make all

To download the code to the EZ-Host Development Board RAM:

1. Open a BASH environment and go to the de3 directory
2. Use a text editor to view de3.ld to see where the code is org’d at (. = 0x####)
   [cy]$ cy16-elf-objdump –f de3
   [cy]$ cy16-elf-readelf –h de3
   [cy]$ head -20 de3.ld
3. Run scanwrap on the binary image
   [cy]$ scanwrap de3.bin de3_scan.bin 0x04A4

To download the code to the EZ-Host Development Board EEPROM:

1. Set all of the board’s dipswitches to off
2. Power up the board by plugging in the power connector
3. Reset the board by pressing the reset button
4. Set the dipswitches for EEPROM 4/stand-alone mode
5. Open a BASH window and go to the de3 directory
6. Plug in a USB cable to SIE2 (Peripheral–2A)
7. Verify the device manager is using the correct driver
   Cypress USB EZ-OTG Device VID=04B4, PID=7200
8. Run qtui2c
   [cy]$ qtui2c de3_scan.bin f

Refer to the application note AN4065 - QDR™-II, QDR-II+, DDR-II, and DDR-II+ Design Guide for different termination schemes, designs, and signal integrity guidelines. For more information on the QDR-DDR II/II+/Xtreme SRAMs, refer to the respective datasheets in the Sync SRAM category.

Reference Schematic for QDR-DDR II/II+/Xtreme SRAMs (from internal characterization board)

Figure 1. (a) QDRII/II+/II+Xtreme-DDRII/II+/II+Xtreme (Non ODT) Reference Schematic

Figure 1. (b) QDRII/II+/II+Xtreme-DDRII/II+/II+Xtreme (ODT) Reference Schematic

Figure 2. QDRII/II+/II+Xtreme-DDRII/II+/II+Xtreme (Supply Pins) Reference Schematic

Assumptions

• The reference schematics provided in the previous section are from an internal characterization board. Cypress recommends that you perform signal integrity simulations with specific board conditions before finalizing your design.
• Figure 1 (a) and (b) are the reference schematics for all on-die termination (ODT) and Non ODT QDR-DDR II/II+/Xtreme SRAMs respectively. For example, if the part is an x18 device, then the data pin notation D_[x:0] will be interpreted as D_[17:0].
• QDRII+/II+Xtreme-DDRII+/II+Xtreme devices do not have the input clocks C and C#.
• Non ODT QDRII+/II+Xtreme-DDRII/II+/II+Xtreme devices do not contain the ODT pin.
• ODT devices have an ODT feature for Data inputs (D_[x:0]), Byte Write Selects (BWS_[x:0]), and Input Clocks (K and K#). Hence, there is no termination for the D_[x:0], BWS_[x:0] , K, and K# pins shown in Figure 1 (b). Refer to the application note AN42468 - On-Die Termination for QDR™II+/DDRII+ SRAMs that discusses the ODT scheme, implementation, advantages, and power calculation for the QDRII+ and DDRII+ family of Synchronous SRAMs on 65-nm technology devices.
• Data output (Q_[x:0]) and Echo clock (CQ/CQ#) signals drive FPGA/ASIC without termination, considering the inputs of the FPGA/ASIC that supports ODT. In the case of FPGA/ASIC without ODT, Cypress recommends that you terminate (pull-up to V_TT) Data output (Q_[x:0]) and Echo clock (CQ/CQ#) signals to reduce signal integrity issues.
• The value of the termination resistor (R) is 50Ω, because most designs have a trace characteristic impedance of 50Ω. The termination resistor value must be equal to the characteristic impedance of the trace.
• An external resistor, RQ, must be connected between the ZQ pin on the SRAM and V_SS to allow the SRAM to adjust its output driver impedance. The value of RQ must be five times the value of the intended line impedance driven by the SRAM. As a result, the value of RQ is 250Ω to match the output impedance of 50Ω in Figure 1 (a) and (b). The acceptable range of RQ that guarantees impedance matching with a tolerance of ±15% is between 175Ω and 350Ω, with V_DDQ = 1.5V. The output impedance is adjusted every 1024 cycles upon power-up to account for drifts in supply voltage and temperature.
• Keep termination resistors as close to the device as possible to reduce the stub length, and thereby, reduce reflections.

Decoupling Capacitor Recommendations for Power Supply Pins

• Decoupling capacitors on power-supply pins play a significant role in filtering noise in the power supply.
• Cypress recommends that you place the decoupling capacitors close to the memory devices for best results.
• The following decoupling capacitor recommendations are from an internal characterization board:

Figure 3. Decoupling Capacitor Recommendation for V_DD

Figure 4. Decoupling Capacitor Recommendation for V_DDQ

Note Refer to the datasheets for V_DDQ value

Figure 5. Decoupling Capacitor Recommendation for V_TT

Figure 6. Decoupling Capacitor Recommendation for V_REF

If you face any issue while creating your design or if you would like Cypress to do a schematic review, create a technical support case at www.cypress.com.

Note: The attachment is an expanded version of Appendix A in the application note AN82156 - PSoC® 3 and PSoC 5LP - Designing PSoC Creator™ Components with UDB Datapaths. Cypress encourages you to read this application note if you are new to PSoC Datapaths.

Answer: There is no specific maximum value for overlay thickness. You should select the overlay material and thickness depending on the following factors:

• The sensitivity of your CapSense system is directly proportional to the overlay material and thickness.

C_finger = (ε_o ε_r A)/D

where:

ε_o = free space permittivity
ε_r = dielectric constant of overlay
A = area of finger and sensor pad overlay
D = overlay thickness

• A thicker overlay lowers finger capacitance, which in turn lowers finger response. A thicker overlay can also increase parasitic capacitance. However, the overlay must be thick enough to prevent breakdown during an ESD event. Remember that you can increase finger response by increasing button size to compensate for thicker overlays. The following table gives the minimum overlay thickness for different materials.

For further details, refer to the Capsense Getting Started guide.

The recommended minimum SNR is 5:1. A typical SNR is between 10:1 and 20:1 when finger capacitance is 0.1pF. The actual SNR depends on your project settings, especially scan time and sensitivity. You can increase the SNR by reducing the scan speed but this results in increased power consumption.

Figure 1. Read and Write Pointers

The FIFO is empty when the read pointer catches up with the write pointer, and full when the write pointer catches up with read pointer.

One way of accomplishing this is by making each counter one bit wider than required. All counter bits except the MSB are used to address the FIFO array. In this configuration, every location in the FIFO is accessed twice before the counter rolls over. When the MSBs of the write counter equal those of the read counter, the FIFO is empty. When the MSBs are not equal and the actual count value is same, then the FIFO is full. This scheme makes it relatively simple to generate the empty and full flags. Since the FIFO logic prevents additional writes to a full FIFO and also prevents reads from an empty FIFO, the counters can never get further apart than the depth of the FIFO. This prevents reading old data or overwriting new data.

Previous versions of PSoC Designer allowed you to leave the argument list blank in function definitions. For example:

If you attempt to compile this code with the new ImageCraft compiler, you will receive an “Old Style Function Definition for 'main' ” warning. This warning can be safely ignored; however, you can eliminate this warning by adding void to the argument list.

Cypress recommends that you connect the TEST/I2C_SCL pin to the SCL of another IC on the schematic, without the pull-up resistor. HX2VL DVK designs that do not use pull-up resistors have been tested and verified.

Flow Control. Choose this function if the two UART links have different processing speeds. If the UART receiver has a processing delay between two consecutive receptions over the UART, it can signal ‘wait’ to the UART transmitter by deasserting the CTS line. When you are ready to send data, the transmitter can use the RTS pin to signal the receiver to keep its receiving line active. The DTR/DSR pin can enable and disable the Transmit/Receive function. The RTS/CTS pin can enable and disable the transfer of individual blocks of data.

I/O. You can choose this function if the UART transmitter and receiver have similar processing speeds. You can use the CTS, RTS, DTR, and DSR pins as I/Os that can be read and written to from the PC by USB requests. In this mode, CTS and DSR serve as input pins and RTS and DTR serve as output pins.

The device can resume normal operations when the USB detects activity or a reset signal. When the device is in Suspend, and Remote wakeup is enabled, then asserting the wakeup signal generates remote wakeup signaling on the upstream. The device resumes normal operations when the host acknowledges the signal.

The ReadFile API returns are based on the following conditions:

1. A short data packet is received.
2. The ReadFile API buffer is completely filled.
3. A read timeout has occurred.
4. The device port is closed.

A short data packet is as small as one byte or as much as the maximum data packet size described in the device descriptors. You can use the User Mode Driver or the application to check the number of bytes read by the ReadFile API.

Contact Cypress Sales for more information about Windows CE Driver.

• Baud rate: 230K baud. This rate does not support flow control.
• Parity bit: ‘None’.

The current implementation takes the next available COM port number and assigns it to the Cypress USBUART driver. This avoids any COM port number conflicts. However, you can change the registry setting to use a fixed COM port number. For more information, refer to Windows CE documentation.

You can follow these steps to load the driver without using the Cypress VID and PID:

1. Change Windows registry settings to reflect the new VID and PID.
2. Add and set a new global environment variable called BSP_NO_CYP_VID. Recompile the source and build the Windows CE image.

You can download and install the kit from http://www.cypress.com/?rID=14321. After the kit contents are installed, browse to the location: Install_root_directory\CY3684_EZ-USB_FX2LP_DVK\1.0\Drivers\cyusbfx1_fx2lp. All the drivers are located in this folder.

In this file, the implementation of read occurs in the ISR. The I2C_Read function sends the Read Command and changes the I2C.PktStatus to I2C_PRIME. The I2C enters the ISR every time a byte of data is successfully transferred when the DONE bit is set High.

When the following section of code is executed for the first time, the data that has been read is stored to I2CPckt.dat and the status is changed to I2C_RECEIVING:

To read more data, the following section of the code is executed the next time the ISR is serviced:

For information on how to increase the ESD protection, refer to page 10 of the document titled High Speed USB Platform Design Guidelines at the USB-IF website www.usb.org.

• PSoC Creator: http://www.cypress.com/?app=cart&action=add&itemID=13084&type=2
• PSoC Designer: http://www.cypress.com/?app=cart&action=add&itemID=13085&type=2

To download the ISO file, go to the following links:
 

•  PSoC Creator: http://www.cypress.com/go/creator/download
• PSoC Designer: http://www.cypress.com/go/designer/download

 
After you download the ISO file, burn a CD or mount the ISO file. For instructions, see Mounting ISO Files and CD Burning

To download the package, go to www.cypress.com/?rID=57990. Download the file: “FX3 SDK for Linux platforms - This is a Tar archive containing the FX3 firmware libraries and examples, the ARM GNU tool chain, Eclipse IDEs (x64 and x86 versions) and the CyUSB suite for Linux platforms.” Ignore the FX3 firmware files.

Refer to the documents cyusb_linux_user_guide.pdf and cyusb_linux_programmers_guide.pdf, which will get installed in the docs folder along with the software development kit at the location cyusb_linux_1.0.2/ docs.

The following supplies are permanently tied to 1.2V:
VDD
AVDD
VDD_SRAM
U3TXVDDQ
U3RXVDDQ

PCON (SFR 0x87) Bit 7, Serial Port 0 rate control SMOD0 (Table 14-13)

SCON0 (SFR 0x98) Serial Port 0 control (Table 14-11)

SBUF0 (SFR 0x99) Serial Port 0 transmit/receive buffer

EICON (SFR 0xD8) Bit 7, Serial Port 1 rate control SMOD1 (Table 14-12)

SCON1 (SFR 0xC0) Serial Port 1 control (Table 14-14)

SBUF1 (SFR 0xC1) Serial Port 1 transmit/receive buffer

T2CON (SFR 0xC8) Baud clock source for modes 1 and 3 (Table 14-5)

UART230 (0xE608) High-Speed Baud Rate Generator enable (Section 14.3.2)

Note: The registers PCON and EICON include functionalities that are not part of the serial interface.

The Filter 2.0 component in PSoC Creator enables the use of direct-form I biquad filters, which are second order IIRs. The following diagram shows the direct-form I biquad.

The following equation describes first order IIR lag filters:

Another way to write the difference equation for the IIR lag filter is:

To fit this lower order IIR into the biquad, we set the coefficients b1, b2, and a2 to zero, and then set coefficients b0 and a1 as described at the end of this section. Custom coefficients in the Filter component are in the order b0, b1, b2, a1, and a2. In the custom coefficients field, they must appear as:

k
0
0
-(1-k)
0

Just like the biquad sections in which they are implemented, these filters may be cascaded in the Filter component.

However, you can make the two radio modules compatible by replacing the passives C7 and C8 on the radio module provided with the Rev. ** kit. For more information on how to do this modification, see KBA83288.

Note: You can identify the CY3668 kit revision by the sticker attached behind the kit box. Similarly, you can identify the radio module provided with the CY3668 Rev *A kit by the sticker attached behind the module.

Figure 1. CY3668 Kit Revision

Figure 2. CY3668 Rev. *A Radio Module

1. Make sure that POD is connected to the ICE properly. For more details on the POD connection please refer the ‘Debugging hardware setup’ section in the Application Note AN73212: Debugging with PSoC1.
2. If using ICE-Cube to power pod: Ensure that under the Project>Settings>Debugger menu the radio button with "ICE may power pod" is checked.
3. If using external supply to power the pod, first ensure that power is applied to ICE-Cube. Next ensure if the radio button “External only” under the Project>Settings>Debugger menu is checked.
   

Other possible errors that could occur while using the ICE cube to debug are

1. Could not connect to ICE or is Incompatible with the Pod
2. ICE Disconnects During Debug Session
3. Invalid Memory Reference Occurs During Debug Session
4. The Selected ICE Port Cannot be Found
5. Program Execution Halts at Unexpected Locations
6. USB Hub Power is Exceeded
7. No Events are Ever Detected

To troubleshoot the above mentioned error, please refer the section: Troubleshooting in the Application Note AN73212: Debugging with PSoC1 . Also for more details on how to troubleshoot the error ‘Could not connect to the ICE’, please refer the KB article PSoC Designer Error Message "Could not connect to ICE”.

The first four columns of the spreadsheet provide tags for quick sorting. These tags are based on content domain, application function, type of PSoC building blocks or IP, and document complexity. The spreadsheet also lets you know if there are example projects, what version of PSoC Designer is supported, what hardware platform was used to test the project, and the supported PSoC 1 device family. You can filter and sort our application notes using any of the fields and find relevant application notes available for download.

If you are using PSoC Creator 2.1 or later, you should add a Bootloader or Bootloadable component for a Bootloader and Bootloadable project respectively. Remove these components if you are changing from Bootloader or Bootloadable.

Multi App Bootloader is just another type of Bootloader project. Refer to AN73854 - PSoC® 3 and PSoC 5 - Introduction to Bootloaders for more information.

The Pseudo Random Sequence Generator project demonstrates how to use the PRS8 User Module to generate a random bit stream with a 10 ms interval and transmit it using a TX8 serial transmitter.

Answer: To resolve the Windows Internet Explorer error for ActiveX controls:

1. Open Internet Explorer, click “Tools” and then “Internet Options”
   
   If you cannot open Internet Explorer, you can get to the Internet Options window through the Control Panel.
2. Select the “Advanced” tab in the Internet Options window and click ”Reset…”
   
3. Click “Reset” in the Reset Internet Explorer Settings window
   
4. Restart Internet Explorer
5. Close and reopen PSoC Designer