1. In the µVision2 Editor, click ‘Options for Target’ and then select the ‘Output’ Tab. Ensure that the following path is described in the ‘ Run User Program #1’:

    

   ..\..\..\Bin\hex2bix -i -f 0xC2 -o fw.iic fw.hex

2. If at power-on-reset, the EZ-USB detects an EEPROM connected to its I2C with the value 0xC2 at address zero, the EZ-USB loads the firmware in EEPROM into an on-chip RAM. It also sets the RENUM bit to ‘1’, causing standard device requests to be handled by the firmware instead of the default USB device.

Counts are calculated using Equation 1.

Where:

Sensitivity is calculated using Equation 2.

The upper limit of the capacitance measurement range is calculated using Equation 3.

For example, given the following User Module settings:

Sensitivity = 184.3 Counts/pF

Capacitance measurement range (upper limit) = 88.9 pF

Note: The “sensitivity” calculated above is the capacitive measurement module sensitivity, not the system sensitivity to button/sensor activation.

Note: It is not possible to measure capacitance values all the way down to zero because there will always be some parasitic capacitance, C_P, and pin capacitance measured by the sensor.

Where:

For example, given the following User Module settings:

Resolution = 0.00543 pF

Note: Although the calculation indicates that a change as small as 0.00543 pF can be detected, raw-count noise limits the use of such high resolution. CapSense is not recommended for measuring absolute capacitances.

Note: The “sensitivity” calculated above is the capacitive measurement module sensitivity, not the system sensitivity to button/sensor activation.

1. PSoC Designer: The PSoC Designer 5.2 IDE is a full featured development tool for designing and debugging PSoC applications. The PSoC Designer comes with a free Imagecraft C compiler.
2. PSoC Programmer: The PSoC Programmer 3.15.1 programs PSoC devices using the MiniProg1 programmer.
3. Bridge Control Panel and Multichart: These tools are used to tune your CapSense design. The Bridge Control Panel is installed along with PSoC Programmer. The Multichart tool is available for download.
4. USB-to-I2C Bridge: The USB-I2C Bridge Kit allows you to read data from the CapSense controller through the I2C interface and transmit it to your PC through USB. You can use the Bridge Control Panel to view and log the data. For more details see CapSense Data Viewing Tools -AN2397.This method is used with the following devices: CapSense and CapSense Plus: CY8C21x34, CY8C21x34B, CY8C21x45, CY8C22x45, CY8C24x94, CY8C20xx6A, CY8C20xx6H, CY8C20xx7, CY8C20XX6AS
   CapSense Express: CY8C201xxx
5. USB-to-UART Bridge: Implementing a USB-to-UART Bridge as described in USB-to-UART Bridge-AN49943 allows you to read data from the CapSense controller through an RS232 interface and transmit it to your PC through USB. For more details see CapSense Data Viewing Tools -AN2397. This method is used with the following devices: CapSense Express:CY8CMBR2044, CY8CMBR2016, CY8CMBR2010
6. Development Kits:
   • Universal Controller Kits: These kits feature predefined control circuitry and plug-in hardware to make prototyping and debugging easy. Programming and I2C-to-USB Bridge hardware are included.
     CY3280 - 20xx6
     CY3280 - 21x34
     CY3280 - 24x94
     CY3280 - 22x45
     CY3280 - 20x34
   • Universal CapSense Module Boards
     • The CY3280-BSM Simple Button Module consists of ten CapSense buttons and ten LEDs. This module connects to any CY3280 Universal CapSense Controller Board.
     • The CY3280-BMM Matrix Button Module consists of eight LEDs as well as eight CapSense sensors organized in a 4x4 matrix format to form 16 physical buttons. This module connects to any CY3280 Universal CapSense Controller Board.
     • The CY3280-SLM Linear Slider Module consists of five CapSense buttons, one linear slider (with ten sensors), and five LEDs. This module connects to any CY3280 Universal CapSense Controller Board.
     • The CY3280-SRM Radial Slider Module consists of four CapSense buttons, one radial slider (with ten sensors), and four LEDs. This module connects to any CY3280 Universal CapSense Controller Board.
     • The CY3280-BBM Universal CapSense Prototyping Module provides access to every signal routed to the 44-pin connector on the attached controller board(s). The prototyping module board is used in conjunction with a Universal CapSense Controller board to implement additional functionality that is not part of the other single-purpose Universal CapSense Module boards.
   • CapSense Express Evaluation Kits for CY8C201xx: With Cypress's PSoC Designer visual embedded system design tool and CapSense Express configuration tool, designers configure, monitor, and tune buttons or sliders, LEDs, and other general purpose I/Os over I2C in real time using a graphical user interface.
     CY3218-CAPEXP1 CapSense Express Kit
     CY3218-CAPEXP2 CapSense Express Kit
   • CapSense Express Evaluation Kit for CY8CMBR2044:
     CY3280-MBR-Capsense Express kit with Smartsense Auto-tuning

Architecture:

PSoC 3/PSoC 5/PSoC 5LP has total of 24 UDBs. Each UDB mainly consists of: 8 macrocells, PLA (which can implement 16 Product terms), 1 datapath cell, 1 Control cell and 1 Status cell.

Altera MAXV 570ZM device has a total of 570 Logic elements. Each logic element consists of: One 4-input LUT and One register (D flip-flop).

Lattice MACHXO2 256HC device has a total of 128 slices. Each slice consists of: Two 4-input LUTs and Two registers (D flip-flop).

Xilinx XC2C384 consists of 24 Function blocks. Each function block consists of 16 Macrocells and a PLA (which can implement 56 Pterms).

Conclusion:

Data from the above table shows that the PSoC 3/PSoC 5/PSoC 5LP UDB utilization is comparable to:

Mid to higher end CPLDs from Altera MAXV series

Mid to higher end CPLDs from Xilinx Cool runner series

Lower end to mid range FPGAs from Lattice’s MACHXO2 series

Cypress FX3 DVK Bridge Boards provides interface for Cypress FX3 DVK to all the Xilinx and Altera FPGA boards. You can use the Xilinx or Altera bridge board to connect FX3 DVK either by using FMC or HSMC connector.

1. To connect FX3 DVK to Xilinx (Spartan/Virtex) FPGA boards, use FMC to FX3 DVK interconnection board. You can buy this board from Agile Solutions (http://www.agile-sdr-solutions.com)


2. To connect FX3 DVK to Altera (Stratix/Arria/Cyclone) FPGA boards, use HSMC to FX3 DVK interconnection board. You can buy this board from Agile Solutions (http://www.agile-sdr-solutions.com)

There are two workarounds in PSoC Designer for this issue:

1. Change the value of the ORDER attribute for the 'Watchdog Enable' resource from '19' to '20' in the StdDevicesBH1.xml device’s description. You can find this file in the PSoC Designer installation path at
   Common\CypressSemiDeviceEditor\Devices\CY8C29000\StdDevicesBH1.xml.


2. Execute the following macro in the project application code:

M8C_EnableWatchdog

AN32200 has more information on Clocks and Global Resources configuration of PSoC® 1 devices in PSoC Designer.

For other technical issues, contact Cypress technical support at www.cypress.com/go/support.

For example, if ‘UART’ is the instance name of the UART component in your project, then write the following function in the main.c file to override Keil’s built-in putchar function:

Then, printf can be used to send data to UART in the following manner (note that the putchar() function should either be defined or declared before the first call to the printf() function for proper execution):

• USB Clock for Full-Speed operation – 48 MHz (+0.25% tolerance).
• UART with 8x oversampling, voting enabled, the tolerance for tclock: ±3.9%
• UART with 16x oversampling, voting enabled, he tolerance for tclock: ±4.6%
• The accuracy of CAN CLK_BUS must be at least 1.58% for 125 Kbps and slower bit rates

  For bit rates faster than 125 Kbps, the accuracy of CAN CLK_BUS must be 0.5% or better.

Therefore, the project that uses IMO as clock source with USB/UART/CAN does not work in PSoC Creator 2.0 or later version. You must use an external crystal-base for clocking the device when using USB, CAN, and UART communication. For USB communication, you must use a 24-Mhz external crystal.

Refer to AN54439 - PSoC® 3 and PSoC 5 External Crystal Oscillators for more details on how to configure hardware and firmware for PSoC 3 or PSoC 5 using the integrated oscillator subsystems and external resonators.

The defect will be fixed in the future versions of PSoC Designer but for the current version the following workaround can be used:

1. Download the attached “SmartSense.asm”.
2. Copy this file (and replace the old SmartSense.asm) to the following folder:
   C:\Program Files\Cypress\PSoC Designer\5.2\Common\CypressSemiDeviceEditor\Data\Stdum\SmartSense\Ver_1_30\CY8C21034

It should be noted that the configuration wizard will still show the R_b connection to P1[1]. But the hardware connection for R_b gets modified when the API SmartSense_Start() is called in “main.c” of the project. This workaround modifies ACE00CR2, ACE00CR1, ALT_CR0, CMP_GO_EN, PRT1DM0, PRT1DM1, and PRT1DM2 registers in the SmartSense_Start() API. The details of these registers can be found in the Technical Reference Manual (TRM) for CY8C21x34.

(5) Using Scripting method.See application note on Downloading FX2LP/FX1 Firmware Using CyConsole Script Capabilities 

Bulk transfer from FX3 device to USB host: 430 MBps

Bulk transfer from USB host to FX3 device: 360 MBps

1. Change CY_FX_EP_BURST_LENGTH from ‘1’ to ‘16’ in cyfxbulksrcsink.h
2. Change the Manual OUT DMA channel’s buffer size to 63 KB and reduce the buffer count to two
3. Have only one endpoint (IN or OUT) this avoids any USB host bandwidth issues.

For example, in the BL51 locate tab, you can specify your code to begin at a location greater than (0x0080 + length of your descriptor table). Here, 0x0000 - 0x0080 will contain the interrupt vector table. For example if the length of your descriptor table is 80h, you can safely start your code from 0x120h.

The PSoC 3 device supports eight hardware program address breakpoints and one data address watch point.

PSoC 5 and PSoC 5LP support six hardware program address breakpoints and four data address watch points.

However, PSoC Creator reserves one breakpoint to use it to perform operations such as step, jump, and run-to-cursor. After all the hardware breakpoints are exhausted, PSoC Creator automatically uses software breakpoints for all future breakpoints, which is implemented on the host PC side.

A breakpoint is used to cause the debugger to halt the next time its location is reached. If you set a hardware breakpoint, a red dot appears in the left margin of the source/disassembly corresponding to the line in which the breakpoint is assigned. If the number of hardware breakpoints has been exhausted, and if you attempt to add another, the debugger displays an information message to announce that the maximum number of breakpoints has been reached. You will be prompted to place a software breakpoint instead. Software breakpoint is indicated by a green dot in the left margin of the source/disassembly corresponding to the line in which the breakpoint is assigned.

A watchpoint is used to set a breakpoint on a place in data memory as opposed to the standard breakpoint, which is used for program memory. Instead of setting the breakpoint on a line of code, you set it on a variable in the code. This watchpoint is hit each time the address that the variable is located at is read, written, or accessed based on your selection for Break on.

Documentation

The following application notes guide you through the process of component development:

1. AN82250 - PSoC® 3 and PSoC 5LP Implementing Programmable Logic Designs with Verilog
2. AN82156 - PSoC® 3 and PSoC 5LP - Designing PSoC Creator™ Components With UDB Datapaths

The Component Author Guide included with PSoC Creator provides instructions and information on how to create components for PSoC Creator. To open the component guide from PSoC Creator, select Help > Documentation > Component Author Guide.
To download from the website, browse to: PSoC Creator Component Author Guide

The Component Development Kit installed with PSoC Creator includes additional documents. To open from your desktop, select
Start > All Programs > Cypress > PSoC Creator > Component Development Kit.
 

The Component Development kit contains the following:
 

• Component Author Guide: Provides instructions and information on how to create components for PSoC Creator.
• Customizer API Reference Guide: Provides API reference information for PSoC Creator Extensions code.
• Datapath Configuration Tool: Used to edit datapath instance configurations in a Verilog implementation of a PSoC component.
• Tuner API Reference Guide: Provides API reference information for PSoC Creator Tuner code.
• Warp Verilog Reference Guide: The Warp synthesis tool is a Verilog compiler used by PSoC Creator to design with PSoC devices.
   

Training
 

Cypress also has a series of instructional videos for component development.
 

Basic Component Trainings

PSoC Creator 110: Schematic Components
PSoC Creator 111: Component Parameters
PSoC Creator 112: Introduction to Component API Generation
PSoC Creator 113: PLD Based Verilog Components
 

Advanced Component Trainings

PSoC Creator 210: Intro to Datapath Components
PSoC Creator 211: Datapath Computation
PSoC Creator 212: Datapath FIFOs
PSoC Creator 213: Multi-Byte Datapath Components
PSoC Creator 214: Datapath API Generation

Note PSoC 5LP has a more accurate IMO than PSoC 5, and does not require an external crystal in as many circumstances.

Hardware Configuration: The MHz crystal and loading capacitors must be installed in the proper locations. The component designators and part numbers are shown for each kit in the tables below.

Note The latest versions of these kits ship with the MHz crystal and loading capacitors already installed.

CY8CKIT-050 MHz ECO components:

CY8CKIT-010 MHz ECO components:

Firmware Configuration: The MHz ECO may be configured using the Design Wide Resources interface in PSoC Creator. To enable the MHz ECO, make sure the “XTAL” checkbox in the upper left corner of the “Configure System Clocks” dialog is checked, as shown below. In the XTAL configuration window, configure the MHz crystal as shown below. The clock tree can also be configured to use the MHz ECO as the source for various clocks throughout the part.

More details on PSoC 3, 5, and 5LP MHz and kHz ECOs can be found in AN54439 - PSoC® 3 and PSoC 5LP External Crystal Oscillators.

A function pointer can be declared as:

(*) (type of function arguments)

For example:

void (*fptr) (int);

Here, fptr is a pointer to a function taking one argument, an integer, and that returns void. To call the function pointed to by a function pointer, you treat the function pointer as though it were the name of the function you wish to call.

#include
void my_func1(int x)
{
 //print the function

Workaround:

• PSoC Creator allows the user to force the VDAC8 component into a fixed DAC location. PSoC 3 and PSoC 5 have up to four DAC locations that are used for either the VDAC8.
• If you use PSoC Creator 2.1 or later, the graphical analog device editor can be used to force placement of any analog block. To do this follow these steps and refer to Figure 1.
  1. Select the Design Wide Resource file ProjectName.cydwr, where “ProjectName” is the name of your project.
  2. Select the Analog tab, which displays a representation of the PSoC analog structure.
  3. Right-click on the DAC block labeled DAC0 and select Relocate.
  4. Select one of the other DAC locations that appear in the drop-down menu. In this case, DAC1 is selected because it is not used.

Figure 1. Selecting DAC Block in PSoC Creator 2.1

For PSoC Creator versions prior to 2.1, use the following procedure. In this example, the instance name of the VDAC8 in question is “VDAC8_1”. Refer to Figure 2 or do the following:
 

1. Go to .cydwr file
2. Select the Directives tab.
3. In the Component (Signal) Name section, type "\:viDAC8\"
4. Set the Directive type to "Force Component Fixed"
5. Add "F(VIDAC,1)" in the Directive Value. For other DACs, replace '1' with 2/3.
6. Compile and go to cyfitter.h file and check if all DAC User Modules are using the respective hardware DACs. Search for the string “VDAC8_1_viDAC8”. Find the lines of code similar to the following:

/* VDAC8_1_viDAC8 */

#define VDAC8_1_viDAC8__CR0 CYREG_DAC1_CR0

This confirms that the viDAC8 used is now DAC1 instead of DAC0

Figure 2. PSoC Creator Directives Tab

Refer to the errata document of PSoC 3 (ES2) and PSoC 5 (ES1) for more details.

The following is a list of affected PSoC 5 parts:

• CY8C5245PVI-112
• CY8C5245PVI-113
• CY8C5246PVI-012
• CY8C5246PVI-071
• CY8C5246PVI-091
• CY8C5246PVI-092
• CY8C5247PVI-066
• CY8C5247PVI-068
• CY8C5247PVI-074
• CY8C5247PVI-082
• CY8C5248PVI-009
• CY8C5248PVI-024
• CY8C5248PVI-028
• CY8C5248PVI-101
• CY8C5385PVI-010
• CY8C5385PVI-042
• CY8C5385PVI-080
• CY8C5385PVI-109
• CY8C5386PVI-040
• CY8C5386PVI-057
• CY8C5386PVI-070
• CY8C5386PVI-098
• CY8C5387PVI-031
• CY8C5387PVI-036
• CY8C5387PVI-045
• CY8C5387PVI-072
• CY8C5388PVI-014
• CY8C5388PVI-016
• CY8C5388PVI-027
• CY8C5388PVI-055
• CY8C5485PVI-006
• CY8C5485PVI-085
• CY8C5486PVI-046
• CY8C5486PVI-094
• CY8C5487PVI-056
• CY8C5487PVI-069
• CY8C5488PVI-077
• CY8C5488PVI-103
• CY8C5585PVI-048
• CY8C5585PVI-090
• CY8C5586PVI-084
• CY8C5586PVI-107
• CY8C5587PVI-073
• CY8C5587PVI-095
• CY8C5588PVI-065
• CY8C5588PVI-067
• CY8C5588PVI-115

cyp3fit: V2.1.0.1118, Family: PSoC3, Started at: Tuesday, 20 November 2012 15:12:08

Here, 1118 is the build number used for the compiling the project.

…\Program Files\Cypress\Programmer\[3.16.1 or greater]\3rd_Party_Configuration_Files\BSDL\

The minimum release of PSoC Programmer that supports the BSDL JTAG files for PSoC 3 and PSoC 5 LP devices is PSoC Programmer 3.16.1. The files can be found in the Third Party Configuration Files folder under the BSDL subfolder.
You can download the latest release of PSoC Programmer from the following web page: www.cypress.com/go/psocprogrammer

Therefore, if the project based on PSoC 3 ES2 or PSoC 5 ES1 compiles without any warning, it is because the tool is disabled for those devices and the design is not guaranteed to work as expected if it fails due to timing issues. For more information about STA, refer to the application note: AN81623 – “PSoC® 3 and PSoC 5 Digital Design Best Practices.

When the SPIM_PutArray API is used in the SPI master component, it only calls the SPIM_WriteTxData internally multiple times. This function is blocking in nature; which means that it continuouslychecks the space in the transmit FIFO and writes to it only when there is space.

Now, when data rate of SPI is very high, there is not enough time for the CPU to keep up the speed with the SPI master’s throughput, especially when the CPU is running on lower clock rates or the code optimization level is low. In this situation, when the SPI master completes transmission of one byte of data, the next byte is yet to be written in its transmit FIFO. Therefore, there is a delay until that byte is written to the FIFO.

One method to overcome this issue is the use of DMA to transfer data from the memory array to the SPI master.

Answer: Application notes are updated when a new version of software (PSoC Creator) or silicon is released. The software version and silicon version supported for a particular AN is specified along with the zip file of the corresponding project. See the following screenshot for an example.

In this example, the first zip file (AN64275.zip) contains the project for the AN64275, which is designed using the latest version of PSoC Creator software, that is, PSoC Creator 2.1 SP1 and supports PSoC 3 and PSoC 5LP devices for production. The second zip file (AN64275_Archive.zip) contains projects for the AN64275, which is designed using previous versions of PSoC Creator software such as PSoC Creator 2.1 and PSoC Creator 2.0. This supports only PSoC 3 and PSoC 5 devices.

Question: How do I select a device and device revision from PSoC Creator™?

Answer: Go to Project > Device Selector in PSoC Creator. If you are using PSoC 3 device (such as CY8C3866AXI-040) with production revision, then use the selection shown in the following screenshot.

Similarly, select the appropriate device number to work with the PSoC 5 device family (for example, CY8C5568AXI-060) and PSoC 5LP family (for example, CY8C5868AXI-LP035).

Figure 1: Flash Memory Organization for PSoC5/ PSoC5 LP

The blocks of N rows are called arrays and the array-ID parameter in the CyWriteRowData() API refers to these blocks. The details of the API are available in the ‘System reference guide’, which can be located in PSoC Creator at the following path:

Help > Documentation > System Reference > System Reference Guide

The parameters required for the CyWriteRowData() API are as follows:

• Array-ID: The block number in which the required row is present
• RowAddress: Row number within the specific block
• RowData: The data to be written

1.  AN60317 - PSoC® 3/PSoC 5 I2C Bootloader
2.  AN73503 - USB HID Bootloader for PSoC® 3 and PSoC 5
3. AN68272 - PSoC® 3 and PSoC 5 - Customizing the Bootloader Communication Channel

The application note AN68272 enables to build a custom bootloader using other communication channels.

Select either ‘Empty PSoC 3 Design’ or ‘Empty PSoC 5 Design’, depending on the project. The ‘Device’ drop-down menu shows two devices by default. The first one is the device that was selected in the latest PSoC Creator project; it says ‘Last Used PSoC 3 Device’ (or it would say ‘Last Used PSoC 5 Device’). The second device shown, CY8C3866AXI-040, says ‘Default PSoC 3 Device’. If you want to select a device that is not one of these two, select ‘Launch Device Selector’.

You may select ‘Launch Device Selector’ even after the project is created (see screenshot below). In the menu bar of PSoC Creator, choose Project > Device Selector. Alternatively, in the PSoC Creator Workspace Explorer window, you can right-click on the project name and choose Device Selector. The following screenshot shows this option.

After you use one of these methods to open the ‘Select Device’ window (see screenshot below), look at the characteristics of the part to help you choose the appropriate part.

You can add or remove columns by selecting ‘Hide / Show Columns’ button on the top left of the window. In addition, you can filter or sort columns to find a device that best fits a particular project.

Another useful feature is the ‘Start Auto Select’ option at the bottom left corner of the window. Before using this option, make sure that the ‘Design Fits on Device’ column is visible. After you press ‘Start Auto Select’, PSoC Creator will start to generate the project on every visible device in the Select Device window. If PSoC Creator can place and route the Top Design of the project for a device, the ‘?’ sign in the ‘Design Fits on Device’ column turns to ‘√’. If an error occurs, the symbol turns to ‘×’. During this process, the ‘Notices’ and ‘Log’ tabs are updated with details of each build. Thus, the ‘Start Auto Select’ option gives you a one-click estimate of the set of devices in which a particular project can fit. Note that this option does not compile the code, and therefore it does not indicate whether the code can fit into the flash of a given device.

Note: For engineering sample (ES) devices, the device revision, such as ES1, ES2, or ES3, is marked on the package as a suffix to the part number. Production silicon will not have ES marking.

The EMIF in PSoC 3 and PSoC 5LP supports only 8-bit and 16-bit wide data bus and 8, 16, or 24 bit address bus.

Out of all possible configurations, only one is supported in one design at a time.

Note that EMIF is supported only in PSoC 3 and PSoC 5 LP. PSoC 5 does not support EMIF.

For best operation, design the product so that the main antenna radiation is away from the body or at least not proximity-loaded by the human body or dielectric objects within the product.

Remember to keep the antenna away from clock lines, digital bus signals, and power supply; otherwise, harmonics of the clock frequency will jam certain receive frequencies.

• 1 second
• 5 seconds
• 30 seconds
• 1 minute
• 5 minutes

For example, when the report interval is 30 seconds, a data packet is sent once every 30 seconds. The size of the data packet is uniform (7 bytes) for all five report interval values. The lowest report interval (1 second) gives you the fastest data rate.

The firmware changes its current report interval value to next value when the SW2 button on RF Expansion Card (FTRF) is pressed for more than 2 seconds. If current report interval value is 1 second, the firmware changes it to 5 seconds. If the current report interval value is 5 minutes it rolls back and changes the report interval to 1 second.

Follow this procedure to change the report interval value:

Figure 1 RF Expansion Card (FTRF)

• Press the SW2 button for more than 2 seconds
• Release the button when the red LED glows continuously. When SW2 is pressed for more than 2 seconds the firmware changes the report interval to next value and lights the red LED continuously.
• Look at the red LED immediately after you release the SW2 button. The red LED blinks a finite number of times to indicate the current report interval value as shown below.

To ensure that enCoRe MCU based USB devices comply with this, follow the steps below:

1. Configure the unused pins on the enCoRe MCU to High impedance analog mode.
2. Configure the sleep timer for 2 ms. Check the USB bus activity every 2 ms. If there is no activity on the bus for more than 3 ms, put the device into Sleep mode.

Cypress enCoRe MCUs pass the test for USB compliance, and the selective suspend current is less than 2.5 mA.

For selective suspend current test procedure, follow this link.

Please refer to “AN4065 - QDR™-II, QDR-II+, DDR-II, and DDR-II+ Design Guide” for different termination schemes, design, and signal integrity guidelines.

The following pages provide a snapshot of the schematics from the internal characterization board for the QDR-DDR II/II+/Xtreme SRAMs. For more information on the QDR-DDR II/II+/Xtreme SRAMs, please refer the respective datasheet in the link, http://www.cypress.com/?id=95.

Reference schematic for QDR-DDR II/II+/Xtreme SRAMs

Figure 1a. QDRII/II+/II+Xtreme-DDRII/II+/II+Xtreme (Non ODT) Reference Schematic (From internal characterization board)

Figure 1b. QDRII/II+/II+Xtreme-DDRII/II+/II+Xtreme (ODT) Reference Schematic (From internal characterization board)

Figure 2. QDRII/II+/II+Xtreme-DDRII/II+/II+Xtreme (Supply Pins) Reference Schematic (From internal characterization board)

Assumptions

• The reference schematic above is from an internal characterization board. It is recommended to perform Signal integrity simulations with the specific board conditions before finalizing the design.
• Figure 1a and Figure 1b are the reference schematics for all Non ODT and ODT QDR-DDR II/II+/Xtreme SRAMs respectively. As an example if the part is x18 device, then Data pins notation D[x:0] will be interpreted as D[17:0].
• QDRII+/II+Xtreme-DDRII+/II+Xtreme devices do not have the input clocks C and C#
• Non ODT QDRII+/II+Xtreme-DDRII/II+/II+Xtreme devices do not contain ODT pin.
• ODT devices have an On-Die Termination feature for Data inputs (D[x:0]), Byte Write Selects (BWS[x:0]), and Input Clocks (K and K#). Hence, there is no termination for D[x:0], BWS[x:0] , K and K# pins in Figure 1b. Please refer to “AN42468 - On-Die Termination for QDR™II+/DDRII+ SRAMs”, which discusses on-die termination (ODT) scheme, implementation, advantages and power calculation for the QDR™II+ and DDRII+ family of Synchronous SRAMs on the 65-nm technology devices.
• The value of termination resistor (R) is 50 Ω because most of the designs have 50 Ω characteristic impedance for the trace. The termination resistor value should be equal to the characteristic impedance of the trace.
• An external resistor, RQ, must be connected between the ZQ pin on the SRAM and VSS to allow the SRAM to adjust its output driver impedance. The value of RQ must be 5x the value of the intended line impedance driven by the SRAM, hence RQ value is 250 Ω to match output impedance of 50 Ω in Figure 1a and Figure 1b. The allowable range of RQ to guarantee impedance matching with a tolerance of ±15% is between 175 Ω and 350 Ω, with VDDQ = 1.5 V. The output impedance is adjusted every 1024 cycles upon power up to account for drifts in supply voltage and temperature.
• Keep termination resistors as close to the device as possible to reduce the stub length and thereby reduce reflections.

Decoupling Capacitor Recommendation for Power Supply Pins
 

• Decoupling capacitors on power supply pins play a significant role to filter noise in the power supply.
• It is recommended to place the de-coupling capacitors need to be placed close to the memory devices for best results.
• Following decoupling capacitors recommendation is from internal characterization board.

Decoupling Capacitors for VDD

Figure 3. Decoupling Capacitors Recommendation for VDD (From internal characterization board)

Decoupling Capacitors for VDDQ

• Please refer to the datasheets for VDDQ value.

Figure 4. Decoupling Capacitors Recommendation for VDDQ (From internal characterization board)

Decoupling Capacitors for VTT

Figure 5. Decoupling Capacitors Recommendation for VTT (From internal characterization board)

Decoupling Capacitors for VREF

Figure 6. Decoupling Capacitors Recommendation for VREF (From internal characterization board)

Please, create a technical support case if you are facing any issue, while creating your design or if you would like Cypress to do a schematic review.

• K Clock Cycle Time (tCYC)
• K Clock Rise to K# Clock Rise (tKHK#H)
• Input Setup and Hold Times Referenced to K Clock

K Clock Cycle Time (tCYC): This parameter denotes the cycle time of the input K clock. If the cycle time of this clock at any instance goes below the minimum datasheet specification due to the input clock jitter, then the device may not function properly. Use the next higher speed bin to accommodate input clock non-idealities. For example, a 400 MHz SRAM has a minimum tCYC of 2.5 ns. If the system runs at 400 MHz with input clock jitter that drives tCYC down to 2.3 ns (or 434 MHz), then use the next higher speed bin, which is the 450 MHz speed bin.

K Clock Rise to K# Clock Rise (tKHK#H): This parameter denotes the time between the rising edge of the K clock and the rising edge of the K# clock. To ensure proper device operation it is critical that the tKHK#H parameter must never exceed the minimum value as defined in the datasheet.

Input Setup and Hold Times Referenced to K Clock: Under any input jitter condition, all setup and hold parameters must be met to guarantee operation. These include, tSA, tSC, tSCDDR, tSD, tHA, tHC, tHCDDR, tHD.

To summarize, any type or amount of input clock jitter does not affect device operation as long as the above critical timing parameters are met. Also note that the tKCVar (clock phase jitter) parameter does not affect device functionality if the above conditions are met. However, this parameter does have an impact on the jitter performance of the output data and echo clocks.

Jitter Performance

The 65 nm QDRII/II+/DDRII/II+ device family has a phase-locked loop (PLL) internal to the device. The PLL actively filters the incoming jitter of K clock to a certain degree depending on the jitter frequency component.

Jitter Transfer Function Measurement

Figure 1 shows the measured jitter transfer function. The X-axis represents the frequency component offset from the K-clock frequency (Fk). The Y-axis represents the amplitude of the jitter transmitted to CQ/CQ#. The plot represents the positive side of a band pass filter and indicates that any jitter with a frequency component outside Fk ±3 MHz will be heavily filtered.

Figure 1. Measured Jitter Transfer Function for QDR/DDR PLL Based Memories

Jitter Histogram Measurement

Figure 2 shows the output from an experiment in which jitter is injected to the K clock using a white noise source. The input clock frequency is 350 MHz. The experiment shows almost 6x reduction in jitter standard deviation (σ). This experiment was done to evaluate the PLL performance in filtering input clock noise and shows the performance improvement of PLL based devices. Additional noise is generated at the output clock during read/write operations to the SRAM.

Figure 2. (a) Noise Injected into K Clock (b) Noise Measured on Echo CQ Clock

PLL Implementation

Figure 3 shows a simplified diagram that explains the PLL based implementations. In the PLL implementation, CQ is generated from a voltage controlled oscillator (VCO) that is driven by a low pass loop filter. If jitter is injected to the input K clock, then the loop filter eliminates the high frequency components. Therefore, the VCO does not respond to that jitter and the CQ clock is kept at a steady phase.

Figure 3. PLL Based Implementation

Problem statement: QDR-DDR II/II+/Xtreme verilog models give erroneous simulation results with Synopsys VCS while other simulators like Altera Modelsim, Xilinx ISE, and Mentor Graphics Questa do not produce the same errors.

Below is the simulation result for verilog model using Altera Modelsim.

............                                        (e.g. CY7C2564XV18)
.......................
# Line:            12 OUTPUT DATA OK data = 06038180e test = 06038180e
# Line:            13 OUTPUT DATA OK data = 04028100a test = 04028100a
# Line:            14 OUTPUT DATA OK data = zzzzzzzzz test = zzzzzzzzz
# Line:            15 OUTPUT DATA OK data = zzzzzzzzz test = zzzzzzzzz
# Line:            16 OUTPUT DATA OK data = 0884c2213 test = 0884c2213
# Line:            17 OUTPUT DATA OK data = 0683c1a0f test = 0683c1a0f
# Line:            18 OUTPUT DATA OK data = 0b0602c18 test = 0b0602c18
# Line:            19 OUTPUT DATA OK data = 090502414 test = 090502414
# Line:            20 OUTPUT DATA OK data = 0d874361d test = 0d874361d
# Line:            21 OUTPUT DATA OK data = 0b8642e19 test = 0b8642e19
.......................     

Below is the simulation result for the same verilog model using Synopsys VCS.

 ....... ..                                (e.g. CY7C2564XV18)
....................
Line:            12 OUTPUT DATA OK data = 06038180e test = 06038180e
Line:            13 ERROR data                     = zzzzzzzzz test = 04028100a
Line:            14 OUTPUT DATA OK data = zzzzzzzzz test = zzzzzzzzz
Line:            15 OUTPUT DATA OK data = zzzzzzzzz test = zzzzzzzzz
Line:            16 OUTPUT DATA OK data = 0884c2213 test = 0884c2213
Line:            17 ERROR data                    = zzzzzzzzz test = 0683c1a0f
Line:            18 OUTPUT DATA OK data = 0b0602c18 test = 0b0602c18
Line:            19 ERROR data                    = zzzzzzzzz test = 090502414
Line:            20 OUTPUT DATA OK data = 0d874361d test = 0d874361d
Line:            21 ERROR data                    = zzzzzzzzz test = 0b8642e19
.....................................................................
……………

Explanation for the errors:

VCS simulation result shows some erroneous output from the same verilog model. The reason for this is that, the reg Data_out is been driven by two drivers at the same time, as shown in the verilog code snippet,

`define tcqd #0.15
`define tcqdoh #0.15
reg [35:0] Data_out;

......

always @(datahold_clk)
begin
  if(chip_oe == 1) `tcqdoh Data_out = 36'bz;
end

...

always @(posedge echo_clk)
begin
   if (rpen_o_o_o_o == 0)
     Data_out = `tcqd mem2[Read_Address_o_o_o_o];
end

always @(posedge echo_clkb)
begin
   if (rpen_o_o_o == 0)
        Data_out = `tcqd mem1[Read_Address_o_o_o];
end

...

always @(datahold_clk)
begin
     if(tristate == 0) `tcqdoh Data_out = 36'bz;
end

Here all clk events happen at same time and the drivers are writing Data_out after 0.15 ns delay (tcqd and tcqdoh), causing nondeterminism in the model. The simulator takes the liberty of executing the statements in different processes in different order. This nondeterminism in event ordering is random and different HDL simulators may behave differently in terms or resolving these or behave same.

Resolution of error:

To actually resolve this, we need to make sure the driving events are not happening at the same time in non-blocking assignment statements. Change the delay "tcqdoh" to 0.14 or a value slightly less than 0.15. This will make a VCS simulator to know the defined order of event execution.

Configuration 1 – Internally regulated mode (Vddd and Vdda > 1.89 V):

This is the default mode of operation. In this mode, the internal regulators are switched ON and they provide power supply to internal blocks of PSoC. In this mode, external power must not be applied to the Vccd or Vcca pins. Both of the Vccd pins should be shorted together and connected to Vssd pin through a parallel combination of 1uF and 0.1uF capacitors. The Vcca pin should be connected to Vssa through a single 1 uF capacitor. Following diagram shows this configuration:

In this case, both Vccd pins should be connected together with shortest possible route on the PCB, preferably under the PSoC chip.

Configuration 2 – Externally regulated mode (Vddd and Vdda between 1.71 V and 1.89 V):

This configuration should be used only when external power supply is between 1.71 V to 1.89 V. In this configuration, Vccd pins should be shorted to Vddd and Vcca pin should be shorted to Vdda. After power up in this configuration, the internal regulators are on by default, and should be disabled to reduce power consumption. Refer PWRSYS_CR0 register from PSoC3 Registers TRM to understand how to disable the internal regulators. Following diagram shows this configuration:

Note that the externally regulated mode is applicable only for PSoC 3 and PSoC 5LP. PSoC 5 does not support this mode since the minimum operating voltage to PSoC 5 is 2.7 V.

The PSoC 3 or PSoC 5 VDAC, by implementation, is an IDAC driving into a load resistance to make a voltage DAC. The two ranges of VDAC are determined by the resistance into which the IDAC drives. For 1 V and 4 V range, the IDAC drives a 4K and 16K resistor respectively. Because of this I to V conversion, the VDAC cannot drive an external resistive load directly. The external load will appear in parallel to the internal resistive load and will change the range of the DAC. Hence the VDAC cannot drive external resistive loads.

•  RF path: Adhere closely to the recommended reference design circuit (Refer TRM, FIGURE-3.1)
•  Clock traces: Keep the quartz crystal traces simple and direct. The self-bias resistor should be close to the XTALi and XTALo pins. The oscillation loop, consisting of the series resistor and crystal, should be a simple, small loop. The crystal-loading capacitors should be near the crystal. The ground connection to these capacitors must be good, clean, and quiet. This prevents noise from being injected into the oscillator. It is best to have one ground plane for the entire RF section. Do not keep any unwanted trace below the crystal. The crystal and the associated components should be kept as close as possible to the IC pins (XTALOUT and XTALIN) to keep stray capacitance as minimum.
•  Power distribution and decoupling: Capacitors should be located near the VDD pins, as shown in Typical Application on page 13 of the WUSB-NL TRM.
•  Antenna placement: When using an antenna, follow the manufacturer's recommendation regarding layout.
•  Digital interface: The digital interface should be routed with a solid ground reference, to have a good return path you need a good grounding between RF and MCU that can help reduce noise 'seen' at the antenna, thus improving performance.

To activate the license, go to "Help >> Register >> Keil" menu in PSoC Creator.  This opens the below dialog box with a pre-filled Computer ID.  Press “Get LIC via Internet…” button.

This will launch your browser on the Keil Single user License registration page with the CID and Product Serial Number (PSN) pre-populated. Fill in the required information and press the “Submit” button.

Keil will send the New License Id (LIC) to your mail id [mail id which you had given in Keil website during registration]. Copy that string into the New License ID Code box and press “Add LIC”. The table at the bottom of the dialog updates to show you how long the license will be active.

If the above method did not work and if you are getting any of the following errors:

1. Error-->prj.M0132: Unable to register your LIC number. Confirm if the number you entered is correct then try again.
2. 'Your Keil License has expired'
3. "Add LIC" button is disabled.

Then please go through the following link ‘http://www.cypress.com/?id=4&rID=58944’.

Note:

1. If you already have a Keil CA51 Compiler license then you need not register a Keil compiler license for PSoC 3. For further details refer to the link ‘http://www.cypress.com/?id=4&rID=38516’
2. If you have enabled "Don't show Keil registration dialog every time PSoC Creator Starts" in Tools -> Options -> Project Management -> General, then the Keil Registration Pop-up will not come. Please disable it and try to open the Registration Dialog from Help -> Register -> Keil now.
3. This License will be valid for 1 year. After 1 year it will prompt for registration again .You have to follow the same registration process.
4. In case if you want to register for a PC without internet connection follow the steps mentioned in following link ‘http://www.cypress.com/?id=4&rID=44355’.

There are two types of solutions available for a wireless keyboard design:

1. 2-chip solutions: separate MCU and RF ICs
2. Single-chip solution: combing RF and MCU in a single chip

The following table lists Cypress’s wireless keyboard portfolio. Based on the required features of the solution, the relevant products can be chosen for the design.

There are two types of solutions available for a wireless presenter design:

1. 2-chip solutions: separate MCU and RF ICs
2. Single-chip solution: combing RF and MCU in a single chip

The following table lists Cypress’s wireless presenter portfolio. Based on the required features of the solution, the relevant products can be chosen for the design.

There are two types of solutions available for RF remote control design:

1. 2-chip solutions: separate MCU and RF ICs
2. Single-chip solution: combing RF and MCU in a single chip

The following table lists Cypress’s RF remote control portfolio. Based on the required features of the solution, the relevant products can be chosen for the design.

There are two types of solutions available for a wireless mouse design:

1. 2-chip solutions: separate MCU and RF ICs
2. Single-chip solution: combing RF and MCU in a single chip

The following table lists Cypress’s wireless mouse portfolio. Based on the required features of the solution, the relevant products can be chosen for the design.

There are two types of solutions available for a wireless dongle design:

1. 2-chip solutions: separate MCU and RF ICs
2. Single-chip solution: combing RF and MCU in a single chip

The following table lists Cypress’s wireless dongle portfolio. Based on the required features of the solution, the relevant products can be chosen for the design.

1. Button Bind
   In this type of binding, a separate bind button is provided for dongle and device. Binding takes place once the bind button is pressed on both dongle and device side. At the end of binding device stores unique ID of dongle in the flash. On subsequent power-on, device uses the stored unique ID of dongle for data transfer. Bind button can be used again to bind a different evice to the same dongle or vice versa.

   Advantage	Disadvantage
   Possibility of device wrongly binding to a different dongle is very less.	Increase in cost due to additional hardware circuitry needed for bind switch on both device and dongle. It is difficult to provide a bind switch in nano-dongle.

2. Power Bind
   In this type of binding there will not be a separate bind button in dongle or device. After power on, dongle goes to bind state if both keyboard and mouse are not bound. If one of the devices is bound then dongle will be in bind state for a period of 8 (configurable) sec and then move to Operating/Idle state. Once device is in Operating/Idle state, no device can be bound. To bind again, dongle power needs to be reset.
   Power bind con be made conditional too. In this case, it will go to binding mode on power on only if some condition (for example, a set of buttons pressed concurrently) is met.

   Advantage	Disadvantage
   No additional hardware circuitry required resulting in reduced cost. Simple to implement. If manufacturer wants to associate a dongle to a single device (like mouse) then binding is same as enhanced KISS bind.	If dongle is bound only to one device and if second device required to be bound then power to dongle needs to be reset. This would cause inconvenience to user.

3. Factory set Bind
   For factory set binding, unique ID of Dongle is read from PC using proprietary tool and stored in device flash. Device by default will be bound with specific dongle.

http://www.cypress.com/?docID=23984

For example, let us consider a QDR-II memory (for example, CY7C1315KV18 - Density 512 K x 36)

1. Activity factor ‘α’ =1 (Because the data gets transferred on both edges of the clock, 0.5 for Standard Sync and NoBL)
2. Maximum Clock Frequency ‘f’ is 333 MHz
3. Load Capacitance C_L is 5 pF (This value depends on the actual board layout and the load capacitance seen by the output pin of the memory)
4. Number of Switching I/Os N is 36 (This will be the number of I/Os driving the load)
5. V_DDQ is 1.9 V maximum
   Based on the formula, P = α f C_L V_DDQ² N
   I/O Switching Power is 216 mW
   I_DDQ is 113 mA

Customers must use this to design their power circuitry accordingly.

How to enable/disable:

To enable/disable FEC, register 32 (bytes b4 and b5) can be programmed with the following options:

How to enable:

To enable data whitening, program register bit 14 of register 41, as the direction below:

How to select whitening seed:

To select data whitening seed, program register 35 (bit b0, b1, b2, b3, b4, b5, and b6) as the direction below:

The protocol provides the following functionalities:

1. Binding device (mouse/keyboard) with bridge connected to PC
2. Packet transmit
3. Packet receive

The following functionalities of the protocol are not visible to application:

1. Configuring transmit, receive, and transaction parameters
2. Channel change algorithm to handle interference/noise
3. Reconnection between device and bridge
4. CRC generation
5. Network ID generation

Extended Response:

By design, a CY8CKIT-050 kit ships factory programmed with a project called “VoltageDisplay_SAR_ADC”. The project measures the potentiometer voltage and displays it on the LCD. Unfortunately, Cypress shipped some of the CY8CKIT-050 kits with a different project. If you received one of these kits, the kit does not have a “VoltageDisplay_SAR_ADC” project when used out of box as described in the Quick Start Guide.

Cypress guarantees that this does not represent a hardware issue with the kit.

Please reprogram the board with CY8CKIT-050_QuickStart.hex. This hex file is available on the Cypress website. The “VoltageDisplay_SAR_ADC” project is also included with the kit software. It is installed in: <install_directory>:\Cypress\PSoC 5 Development Kit\<version>\Firmware.

1. USBUART should work on all Android versions, and should enumerate as Communication Device Class (CDC) device. However, you cannot interface with a serial port unless you write your own Hardware Abstraction Layer.
2. The core USB component is the best method of communicating with an Android system - HID and vendor specific drivers are supported.

   The following resource may help you:
   http://developer.android.com/guide/topics/usb/host.html

   Note: Android has added USB Host support from Android 3.1 onwards. Developing an Android-host USB application with an earlier version of Android would be very difficult.

Blaster and primer are two software utilities that come with CY4605 and CY4606 Hub RDKs, which can be used for this in-system programming from a PC running Windows.

Blaster allows editing of the hub capability and descriptors whereas primer is a manufacturing line programming tool. Primer takes an EEPROM image (.iic file) created by Blaster and programs the Hub as soon as it is plugged in.

Note: For programming the EEPROM using the programming utilities the hub has to be connected to cyusb.sys.

An external pull-up resistor to Vt = Vddq/2 is normally recommended termination scheme for HSTL inputs for better signal integrity at high switching speeds. However, in ODT enabled devices, the termination is available internal to the die, for the input signals such as D bus, BWSb, and K/Kb clocks. So there is no need for external pull-up on these signals.

For more information, refer to the Application Note AN42468 - On-Die Termination for QDRII+/DDRII+ SRAMs.

Answer: There are no internal pull-ups on the OVR# pins of HX2LP. They are set to inputs by default (on power-up) and do not need to have an external pull-up if you are not using the respective port at all. The OVR# is an input (active low) used to detect over-current and it should be setup to default to a state of '1' (so that the port is not marked or detected as over current).

If you are not using the port, you do not need to use an external pull-up, as you don't care about the status of this unused port.

If you are using this port or there is a possibility of using this port, you will need an external pull-up to set the state to '1' (no over current detected on the port).

In any case having an external pull-up (not leaving it floating) is always a good (recommended) idea regardless of whether the port is configured to be used or not.

Please add the below code snippet in the beginning of “main.c” code in order to use LVI/HVI circuits to generate interrupt to be handled by CPU instead of issuing a device reset:

For more details on the above registers, refer to the PSoC 3 Registers TRM or PSoC 5 Registers TRM.

The following table lists down the various values which can be entered in the CYDEV_RESET_CR0 register to configure the LVI_A (LVI on Analog power supply - Vdda) and LVI_D (LVI on Digital power supply – Vddd) circuits to generate interrupt on various levels of supply voltage from 1.71 to 5.45 V in steps of 250 mV:

This is a known issue and has been resolved in the next version of PSoC 5 chip. This issue is also not there on PSoC 3 Production devices. A software workaround will be available in the next release of PSoC Creator (Expected in Q4-12).

This problem can have a negative impact on the flash's endurance and/or data retention after a bootload is executed.

There is no negative impact on:

• The flash's performance (endurance and/or retention), if the bootloader has not yet been used to do a bootload operation.
• The flash used by the bootloader code. Only flash that the bootloader erases and writes to is affected by this problem.
• The flash if the checksum verification fails during boot-up and the bootloader then enters bootloader mode. In this case, the proper value from the "Flash_Program_Temperature_Deg_C" user module parameter is used during the bootload, that must subsequently occur.

Workaround:

• Call the "BL_SetTemp()" API function in application code to set the proper temperature value to be used before making any call to the "ENTER_BOOTLOADER()" API function in the application code.
• Or, call the "BL_SetTemp()" API function in application code to set the proper temperature value to be used, before executing a bootload, while communicating with the device using the bootloader I2C address.

The problem has been fixed in the BootLdrI2C user module version 2.30 (in PSoC Designer 5.2).

For Sync SRAMs Write happens when a LOW is detected on the rising edge of the sampling clock, as against a /WE pulse in Async SRAMs. So for back-to-back Write operations, /WE can be kept LOW.

The input signal of Del-Sig ADC can be amplified by the following possible ways:

1. Using the ADC Buffer at the input of Delta Sigma Modulator (ADC Buffer gain can be configured in the Del Sig ADC component configuration window)
2. Using a PGA at the input of ADC (Drag and drop the PGA component and configure its gain in PGA component configuration window)
3. Using Modulator gain by selecting lower input range of ADC (only in Differential Mode)

In order to get better results, the following order of amplification is preferred:

Modulator Gain > ADC Buffer > PGA

Note: What is modulator gain in Del Sig ADC?

Delta sigma modulator is a Switched capacitor block with input & feedback capacitors around OpAmps. The Capacitors sizing will determine the amplification of the input signal. Based on the input voltage selection, PSoC Creator will determine the sizing automatically and use them. As there are limited set of input & feedback capacitors available only certain gain factors are available.

There was an issue with UM update in PSoC Designer 5.1 Service Pack 3. During the UM update, new UM version set default parameters first (default pins), but later the parameters are restored from the old UM version. Therefore when update was finished, pin settings for the pins, intended to be default for CSD ("Feedback Resistor Pin" and "Modulator Capacitor Pin") were corrupted.

This issue is fixed and handled in the next service packs including SP4, SP5, and SP6 of PSoC Designer 5.1.

• Wireless HID – Mice, keyboards, presenters
• Remote controllers – For consumer electronics (TVs, Set Top Boxes, and so on) and for radio controlled models or toys
• R/C Models and toys

If you have any doubts as to whether your application can be supported with PRoC-EMB please contact procui@cypress.com.

Thus in the case of PRoC-CS (40 pin) you have 7 general purpose I/Os free for capacitive buttons in your design if you want to use the radio. The 7 I/Os can be used to support a maximum of 12 buttons using a matrix layout or it can be used to support a maximum of 14 segments on a capacitive slider using a diplexer. The 68 pin PRoC-CS part has 35 GPIOs (26 for capacitive sensing) and can be used for applications where there is a need for larger number of GPIOs.

The PRoC-TT part supports 35 general purpose I/Os that can be used for capacitive sensing. If you are using the radio, a maximum of 26 XY sensors are available for touch support.

In some cases your design may require more general purpose I/Os (GPIOs) than available on the PRoC-UI parts. An example of a design like this is a keyboard with a built-in trackpad.In such cases PRoC-UI supports connection of an external MCU over SPI. In the case of the keyboard with built in trackpad, the external MCU can handle mechanical buttons while the PRoC-UI can handle the trackpad and radio functionality.

We recommend the enCoRe Low Voltage series of MCUs for use with PRoC-UI. To find out more about our enCoRe low voltage MCUs please click here

PRoC-CS is enabled by SmartSense™ technology for auto tuning, which automatically optimizes CapSense® performance in a wide range of applications. The EMC version of SmartSense boasts of best in class noise immunity.

PRoC-TT, PRoC-USB, and PRoC-EMB are not intended for CapSense and thus do not support auto-tuning for capacitive sensors.

 PRoC-CS (CYRF89435-68LTXC) and PRoC-EMB (CYRF89135-40LTXC) will be supported in later releases of PSoC Designer.

Please contact procui@cypress.com to know more about this.

PRoC-CS (CYRF89435-68LTXC) and PRoC-EMB (CYRF89135-40LTXC) will be in production in the first quarter of 2013.

Please contact your local sales or procui@cypress.com for more details.

• Touch mouse - Unlike a typical mouse, this species of mice has a touch-sensitive surface on top, so instead of clicking with fingers, users can tap and swipe and perform other gestures as they would on a touch-screen. PRoC-TT can be used as a single chip solution for such designs. PRoC-TT enables touch mice to support Windows 8 specific gestures as well as normal one and two finger gestures.
  

  

• Wireless trackpad - Wireless trackpads have a touch sensitive surface to them to recognize gestures performed by users together with a wireless 2.4 GHz link to transmit the recognized gestures to a dongle on the PC side. The dongle forwards the gestures to the windows OS. PRoC-TT can be used as a single chip solution on the trackpad side for touch sensing and wireless communication. PRoC-TT enables wireless trackpads to support Windows 8 specific gestures as well as normal one and two finger gestures.
• Keyboard with built in trackpad - Wireless keyboards design with built-in trackpads enable users to perform gestures together with typing. Such designs enable ease of use for end users. Activities such as scrolling, zooming in and out, and switching between applications become easy to perform without having to switch to a mouse while typing on the keyboard. PRoC-TT together with an external MCU offers a two chip solution for such designs. Moreover with Windows 8 Metro UI coming out, PRoC-TT which supports Windows 8 gestures opens up more possibilities for such designs.
• Remote controller with trackpad - With Smart TVs or Connected TVs providing users with a range of functionality such as web browsing, on demand streaming and so on, remote controllers for TVs and Set Top Boxes (STBs) are also evolving. Remote controllers are incorporating trackpads for cursor movement and gesture support. PRoC-TT enables a single chip solution (both touch sensing and wireless communication) for such remotes.
• Remote controlled toys - Radio Controlled (R/C) models and R/C toys are controlled using a remote controller. Remote controllers with trackpads allow users to use touch i.e. finger movements to control R/C toys. PRoC-TT can be used as a single chip solution for touch sensing and wireless communication on such remote controllers.

Please note that this list is not exhaustive. If you have any doubts as to whether your application can be supported with PRoC-TT please contact us at procui@cypress.com

• Mouse with capacitive scroll and haptics – Capacitive sensing based sliders (to replace scroll wheels) and haptic feedback enable user friendly and sleek mouse design. PRoC-CS provides a single chip solution to support capacitive sensing, haptic feedback control and wireless communication on a single chip. Keyboard with multimedia keys – Wireless keyboards which have capacitive keys for multimedia control, LEDs for battery monitoring, and so on, can be supported with PRoC-CS. Depending on functionality required, single chip (PRoC-CS) and two chip (PRoC-CS + external enCoRe V MCU) solutions are available.
• Remote controllers with capacitive touch buttons – Remote controllers for TVs, Set Top Boxes and other consumer electronics, which use capacitive buttons look sleeker and more stylish than those with mechanical buttons. PRoC-CS provides a single chip solution for such devices, integrating capacitive sensing and wireless 2.4 GHz on a single chip.Remote controlled toys – Radio Controlled (R/C) models and R/C toys are controlled using a remote controller. Remote controllers which use capacitive buttons look sleeker and more stylish than those with mechanical buttons. PRoC-CS provides a single chip solution for such devices, integrating capacitive sensing and wireless 2.4 GHz on a single chip.

Please note that this list is not exhaustive. If you have any doubts as to whether your application can be supported with PRoC-CS please contact us at procui@cypress.com

NOTE: WUSB-NL DVK is intended for use with the WUSB-NL modules supplied with the kit. In case you need to use this kit with any other WUSB-NL based device, the WUSB-NL module needs to be modified. Follow the instructions provided in this article to modify the module.

CAUTION

1. ANY CHANGE TO THE MODULE HAS TO BE CARRIED OUT BY A PERSON QUALIFIED IN REPLACING CHIP COMPONENTS
2. USE ESD PROTECTION WHILE CARRYING OUT THE MODIFICATION
3. USE TEMPERATURE CONTROLLED SOLDERING STATION (RECOMMENDED)

INSTRUCTIONS TO MODIFY WUSB-NL MODULES

Perform the following changes on both the WUSB-NL modules:

• Replace the existing capacitor at location C7 with a 33 pF, 0603 size capacitor
• Replace the existing capacitor at location C8 with a 27 pF, 0603 size capacitor

Figure 1 WUSB-NL Module and Location of C7 and C8

Cypress recommends the following parts from Murata for this purpose:

• 33 pF capacitor : GRM1885C1H330JA01D
• 27 pF capacitor : GRM1885C1H270JA01D

After the changes are completed, the WUSB-NL modules are ready to inter-operate with any non-DVK hardware.

INTEROPERATING WITH NON-DVK WUSB-NL HARDWARE

In order for a modified WUSB-NL module to inter-operate with a non-DVK hardware, the firmware running on both the hardware’s needs to be compatible. For this reason you must port the WUSB-NL driver provided with CY3668 to the non-DVK hardware before initiating data communication between them. If your application requires AgileHID protocol, you must port the AgileHID protocol provided with CY3668 DVK to the non-DVK hardware as well. Alternately, you can port the firmware (WUSB-NL driver and AgileHID protocol) running on the non-DVK hardware to CY3668 DVK as well.

Clock Warning: A clock marked as "Sync" cannot be faster than half the frequency of the clock synchronizing it.

To remove this warning, please do the following in example project:

1. Go to TopDesign of the project.
2. Double click the CapSense component.
3. Under General Tabs, in the Clock Settings, change the Scan Clock from 24 MHz to 12 MHz.
4. Clean and build the project

This change will not impact the CapSense performance much and overall look and feel of CapSense buttons and Sliders will remain same.

The knowledge base article "New clock synchronization check exposes aliased scan rate issue in CapSense" includes more details regarding this.

If you have any doubts as to whether your application can be supported with PRoC-USB please contact us at procui@cypress.com