Refer to Getting Started with CapSense for more information on how to use springs as CapSense sensors.

Response: When the Rb and Cmod is breakdown then there are 4 possibilities which can be detected with the help of supervisory code. The 4 possibilities are as follows:

1. Cmod Short: In this particular case the counts will be zero because it'll connect the input of the CapSense module directly to ground. Thus, supervisory code will be able to detect that the Cmod has been shorted.

Also, in this particular case, no matter whether the sensor was active or not, the rawcounts and baseline will snap down to 0 and the sensor will be turned OFF. The counts will be zero irrespective of the state of Rb (open/shorted/normal).

2. Cmod Open: If CMOD is open device continues to operate at higher level of noise. If your application uses thin overlay and has strong touch signal this could be painless. If touch signal is weak then you could encounter false buttons activation in this case.

3. Rb Shorted: If Rb is shorted device continues to operate at higher level of noise. If your application uses thin overlay and has strong touch signal this could be painless. If touch signal is weak you could encounter false buttons activation in this case.

Also, In this particular case the raw counts will decrease and the baseline will follow this because of its negative baseline reset.

4. Rb Open: If Rb is open counts will get saturated and the counts will be 2^Resolution -1. If resolution is set as 12 then the counts will be 4095 irrespective of Cmod open/normal. You can easily detect this as well from you supervisory code.
 

Answer: You can use supervisory code to detect if Rb or Cmod are damaged by monitoring them for shorts or opens. The four possible failure modes are:

Cmod Shorted: If this is the case, the input of the CapSense module will be connected directly to ground. Whether the sensor is active or not, the raw counts and baseline will snap down to zero and the sensor will be turned OFF. The counts will be zero irrespective of the state of Rb (open/shorted/normal).

Cmod Open: If this is the case, the device will continue to operate with a higher level of noise. If your application uses a thin overlay and has a strong touch signal this may not cause a problem. However, if the touch signal is weak in your application, you could encounter false button activations.

Rb Shorted: If this is the case, the device will continue to operate with a higher level of noise. The raw counts will decrease and the baseline will follow because of its negative baseline reset. If your application uses a thin overlay and has a strong touch signal this may not cause a problem. However, if the touch signal is weak in your application, you could encounter false button activations.

Rb Open: If this is the case, the raw counts will saturate at 2^{(Resolution -1)}. For example, if the resolution is 12, raw counts will be 4095 even if Cmod if open.

Refer to the Register Reference Guide for more information on these registers.

The difference count is calculated by subtracting the raw count without a finger on the sensor (C_S = C_P) from the raw count with a finger present on the sensor (C_S = C_P + C_F):

By substituting the equation for raw counts you can see the linear relationship between difference counts and finger capacitance:

Note: This linear relationship holds true as long as raw counts do not saturate and assumes that the sensors are fully charged and discharged to VDD and Vref respectively within 1/f_{s max}. If PRS is selected as the clock source, the average switching frequency is f_IMO/4 but the maximum switching frequency is f_IMO/2.

For best results, ensure that the voltage remains in one of the three operating ranges. Additionally, at 2.4 VDC the CapSense scanning functions operate at a slower frequency and response time decreases by a factor of 4.

For more details please refer to Application Note AN53490.

Answer: CapSense Express devices are designed to operate at one of three voltage ranges: 2.4 - 2.9 VDC, 3.1 - 3.6 VDC, or 4.75 - 5.25 VDC. CapSense Express devices are not designed to operate continuously over the full range of 5.25 - 2.4 VDC. This is important to know if your application is battery powered and the operating voltage may gradually decrease as the battery gradually discharges. When the operating voltage is not in the initial operating range the device will still communicate over the I2C bus but the CapSense functionality will not work. Once the device returns to the initial operating range the CapSense functionality will start again but the sensing capability may be impaired unless the system is enabled to recalibrate itself with a reset.

For best results, ensure that the voltage remains in one of the three operating ranges. Additionally, at 2.4 VDC the CapSense scanning functions operate at a slower frequency and response time decreases by a factor of 4.

Answer: There is no specific maximum value for overlay thickness. You should select the overlay material and thickness depending on the following factors:

• The sensitivity of your CapSense system is directly proportional to the overlay material and thickness.

C_finger = (ε_o ε_r A)/D

where:

ε_o = free space permittivity
ε_r = dielectric constant of overlay
A = area of finger and sensor pad overlay
D = overlay thickness

• A thicker overlay lowers finger capacitance, which in turn lowers finger response. A thicker overlay can also increase parasitic capacitance. However, the overlay must be thick enough to prevent breakdown during an ESD event. Remember that you can increase finger response by increasing button size to compensate for thicker overlays. The following table gives the minimum overlay thickness for different materials.

For further details, refer to the Capsense Getting Started guide.

The recommended minimum SNR is 5:1. A typical SNR is between 10:1 and 20:1 when finger capacitance is 0.1pF. The actual SNR depends on your project settings, especially scan time and sensitivity. You can increase the SNR by reducing the scan speed but this results in increased power consumption.

Counts are calculated using Equation 1.

Where:

Sensitivity is calculated using Equation 2.

The upper limit of the capacitance measurement range is calculated using Equation 3.

For example, given the following User Module settings:

Sensitivity = 184.3 Counts/pF

Capacitance measurement range (upper limit) = 88.9 pF

Note: The “sensitivity” calculated above is the capacitive measurement module sensitivity, not the system sensitivity to button/sensor activation.

Note: It is not possible to measure capacitance values all the way down to zero because there will always be some parasitic capacitance, C_P, and pin capacitance measured by the sensor.

Where:

For example, given the following User Module settings:

Resolution = 0.00543 pF

Note: Although the calculation indicates that a change as small as 0.00543 pF can be detected, raw-count noise limits the use of such high resolution. CapSense is not recommended for measuring absolute capacitances.

Note: The “sensitivity” calculated above is the capacitive measurement module sensitivity, not the system sensitivity to button/sensor activation.

1. PSoC Designer: The PSoC Designer 5.2 IDE is a full featured development tool for designing and debugging PSoC applications. The PSoC Designer comes with a free Imagecraft C compiler.
2. PSoC Programmer: The PSoC Programmer 3.15.1 programs PSoC devices using the MiniProg1 programmer.
3. Bridge Control Panel and Multichart: These tools are used to tune your CapSense design. The Bridge Control Panel is installed along with PSoC Programmer. The Multichart tool is available for download.
4. USB-to-I2C Bridge: The USB-I2C Bridge Kit allows you to read data from the CapSense controller through the I2C interface and transmit it to your PC through USB. You can use the Bridge Control Panel to view and log the data. For more details see CapSense Data Viewing Tools -AN2397.This method is used with the following devices: CapSense and CapSense Plus: CY8C21x34, CY8C21x34B, CY8C21x45, CY8C22x45, CY8C24x94, CY8C20xx6A, CY8C20xx6H, CY8C20xx7, CY8C20XX6AS
   CapSense Express: CY8C201xxx
5. USB-to-UART Bridge: Implementing a USB-to-UART Bridge as described in USB-to-UART Bridge-AN49943 allows you to read data from the CapSense controller through an RS232 interface and transmit it to your PC through USB. For more details see CapSense Data Viewing Tools -AN2397. This method is used with the following devices: CapSense Express:CY8CMBR2044, CY8CMBR2016, CY8CMBR2010
6. Development Kits:
   • Universal Controller Kits: These kits feature predefined control circuitry and plug-in hardware to make prototyping and debugging easy. Programming and I2C-to-USB Bridge hardware are included.
     CY3280 - 20xx6
     CY3280 - 21x34
     CY3280 - 24x94
     CY3280 - 22x45
     CY3280 - 20x34
   • Universal CapSense Module Boards
     • The CY3280-BSM Simple Button Module consists of ten CapSense buttons and ten LEDs. This module connects to any CY3280 Universal CapSense Controller Board.
     • The CY3280-BMM Matrix Button Module consists of eight LEDs as well as eight CapSense sensors organized in a 4x4 matrix format to form 16 physical buttons. This module connects to any CY3280 Universal CapSense Controller Board.
     • The CY3280-SLM Linear Slider Module consists of five CapSense buttons, one linear slider (with ten sensors), and five LEDs. This module connects to any CY3280 Universal CapSense Controller Board.
     • The CY3280-SRM Radial Slider Module consists of four CapSense buttons, one radial slider (with ten sensors), and four LEDs. This module connects to any CY3280 Universal CapSense Controller Board.
     • The CY3280-BBM Universal CapSense Prototyping Module provides access to every signal routed to the 44-pin connector on the attached controller board(s). The prototyping module board is used in conjunction with a Universal CapSense Controller board to implement additional functionality that is not part of the other single-purpose Universal CapSense Module boards.
   • CapSense Express Evaluation Kits for CY8C201xx: With Cypress's PSoC Designer visual embedded system design tool and CapSense Express configuration tool, designers configure, monitor, and tune buttons or sliders, LEDs, and other general purpose I/Os over I2C in real time using a graphical user interface.
     CY3218-CAPEXP1 CapSense Express Kit
     CY3218-CAPEXP2 CapSense Express Kit
   • CapSense Express Evaluation Kit for CY8CMBR2044:
     CY3280-MBR-Capsense Express kit with Smartsense Auto-tuning

The CSDADC device is sensitive to EMC signals at the operation frequency and harmonics in VC2 configuration. This configuration is only recommended when you do not plan to run EMC/EMI certification tests.

The defect will be fixed in the future versions of PSoC Designer but for the current version the following workaround can be used:

1. Download the attached “SmartSense.asm”.
2. Copy this file (and replace the old SmartSense.asm) to the following folder:
   C:\Program Files\Cypress\PSoC Designer\5.2\Common\CypressSemiDeviceEditor\Data\Stdum\SmartSense\Ver_1_30\CY8C21034

It should be noted that the configuration wizard will still show the R_b connection to P1[1]. But the hardware connection for R_b gets modified when the API SmartSense_Start() is called in “main.c” of the project. This workaround modifies ACE00CR2, ACE00CR1, ALT_CR0, CMP_GO_EN, PRT1DM0, PRT1DM1, and PRT1DM2 registers in the SmartSense_Start() API. The details of these registers can be found in the Technical Reference Manual (TRM) for CY8C21x34.

Clock Warning: A clock marked as "Sync" cannot be faster than half the frequency of the clock synchronizing it.

To remove this warning, please do the following in example project:

1. Go to TopDesign of the project.
2. Double click the CapSense component.
3. Under General Tabs, in the Clock Settings, change the Scan Clock from 24 MHz to 12 MHz.
4. Clean and build the project

This change will not impact the CapSense performance much and overall look and feel of CapSense buttons and Sliders will remain same.

The knowledge base article "New clock synchronization check exposes aliased scan rate issue in CapSense" includes more details regarding this.

Table 1: Factory Default Values for Internal Pull-Up Setting
 

• Water tolerant buttons and sliders,  
• Buttons and sliders in presence of metal objects and  
• Proximity sensors. 

1. If Cmod value is low, then high frequency noise will find a low impedance path to the ground via Cmod and will get coupled to the system very easily.
2. If the value is too high, the voltage swing about Vref will be lesser as the capacitor will discharge lesser within the given discharge time. If this happens, the signal might get lost in the comparator noise itself as the signal strength (in terms of amplitude) is low.

Due to these reasons, an optimum value of Cmod is required. We have observed during characterization that the system performs quite well with a 2.2nF capacitor.

Thus, the reset mode current would be higher than the deep sleep current (0.10 uA typical).

For CapSense applications, following are the basic two considerations while selecting an adhesive:

1. Since the dielectric constant of air is very low, an air gap between the overlay and sensor degrades the performance of the sensor. Thus, the adhesive should be used to properly stick the overlay with the PCB.

2. The adhesive must be nonconductive.

A transparent acrylic adhesive film from 3M™ called 200MP is qualified for use in CapSense applications. This special adhesive is dispensed from paper-backed tape rolls (3M™ product numbers 467MP and 468MP).

Refer "getting started with CapSense" design guide for CapSense design guidelines.

1. None of the GPIOs is sourcing any current.

2. I2C_ON bit in the SLP_CFG2  and the USB_enable bit in USB_CR0 register is disabled.

3. The buzz rate is set to to 1/32768 using the ALT_Buzz bits of the SLP_CFG2 register.

4. The current is measured by putting the ammeter between supply and Vdd of pin i.e. the current measurement should not include any current other than device current.

Attached a code example that achieves the Isb1 current on the CY3280-20xx6A development kit.

1) Set properties of P1.0:

Name: SPISSCLK (here, the UM is named as SPIS. If it's named as SPIS_1, the name should be set as SPIS_1SCLK)

Select: StdCPU

Drive: Open Drain Low

Interrupt: DisableInt

AnalogMuxBus: Normal

InitialValue: 1

2) Change back the properties of P1.3 to its default values:

Name: Port_1_3

Select: StdCPU

Drive: High Z Analog

Interrupt: DisableInt

AnalogMuxBus: Normal

InitialValue: 0

Make sure to set the bit SPICLK_ON_P10 in the register IO_CFG1 before calling SPI_Start() API:

IO_CFG1 |= 0x04; 

1. Humidity indicator card (HIC) is equal or greater than 10% when read at 23ºC +/- 5 ºC
2. After removal from bag, parts are not mounted on board within 168 hours (in equal or less 30 ºC /60%RH)
3. If they have not been stored in equal or less than 10% RH (as required on the MSL label)
    

If baking is required, devices may be baked for 24 hours at 125 ºC +5/-0 ºC.

Please note that the above baking condition is applicable for MSL-3 and MSL-5 parts only. Also, please ensure that only metal tubes or bakeable trays with rating of greater than 125 ºC must be used for baking. MSL 1 parts do not require baking.

Cypress recommends the customers to follow the Shelf Life condition of the parts as stipulated on the MSL label which can be found on the Moisture Barrier Bag (MBB) bag. A separate article on the Shelf Life of Cypress products is available at the following link: http://www.cypress.com/?id=4&rID=62201

COO on Intermediate Label:

COO on Outer Box Label:

COO on Top Mark:

Country of Origin Codes/Abbreviations:

Reflow Profiles (per Jedec J-STD-020D.1)

Table 2A
SnPb Eutectic Process - Classification Temperatures (Tc)

Table 2B
Pb-Free Process -Classification Temperatures (Tc)

Note:

1. Peak Temperature tolerance is +5/-0 °C of Classification Temp (Tc).
2. All temperatures refer to topside of the package, measured on the package body surface.
3. Package volume excludes external terminals (e.g., balls, bumps, lands, leads) and/or nonintegral heat sinks.

 For example:
To be able to get the reflow profile of a part, we need to know first the Package dimension or volume. 

MPN: CY7C65620-56LTXC
Package: QFN56, Pb-Free Part
Package Dimension: 8x8x1.0mm
Package Volume: 64mm³
Package Thickness: 1.0mm

You can get package dimension on the datasheet’s Package Diagram.

Since the part is a Pb Free Part, Table 2B should be used. Based on this table, is the package volume is <350 mm³ and the package thickness is <1.6mm, Peak Temperature = 260 °C

If the part number is SnPb Part, Table 2a is applicable.

This is because Windows Vista and Windows 7 restrict access to 'Program Files' folders for OS security settings. To successfully build the project using PSoC Designer, the example project folder  "Firmware" should be copied to a location other than 'Program Files' in the computer to successfully build the project.

PSoC Designer 5.0 SP6 can be used to configure PSoC express devices since it supports system level design (which is a requirement for configuring PSoC Express Devices).

PSoC Designer 5.0 SP6 can be downloaded from our website through this link http://www.cypress.com/?rID=34517. Note that PSoC Designer 5.0 can co-exist with PSoC Designer 5.1. (It will co-exist with future releases of PSoC Designer also, because of system level design support).

Raw_Count  = (V_dd/V_ref - 1).R_b.f_s.(2ⁿ - 1).C_s (Here,V_ref is the comparator reference as selected in the user module configuration window in PSoC Designer, R_b is the bleed resistance used on the board, f_s is the average switching frequency of sensors and depends on the CSD configuration used like PRS, prescalar etc. and "n" is the resolution as set in the user module configuration window).

If C_p is the sensor capacitance and C_f is the finger capacitance, the difference counts would be:

Diff_count = Raw_Count_Cp+Cf - Raw_Count_Cp

                   = ( V_dd/V_ref - 1).R_b.f_s.(2ⁿ - 1).Cf     

Note that the above relation holds true as long as the capacitance C_p+C_f does not lead to raw_counts being saturated and also assumes that the sensors are fully charged and discharged within the time 1/f_{s max}. Thus, the linear relationship shown above does not hold true if C_p+C_f or C_pis so high that the sensors do not charge and discharge to Vdd and Vref respectively within the time 1/f_{s max.} (If PRS is used as clock source, average switching frequency is f_IMO/4 but maximum switching frequency is f_IMO/2.).

For the sensors to fully charge and discharge to required voltages in every switching cycle, the period of the sensor modulation signal (1/F_SW) should be greater than 10 * R_SERIES * C_SENSOR. So, if the R_SERIES value gets so large that it start to filter out the sensor modulation signal enough so that the sensor is not fully charged by the modulation signal, the difference counts begin to decrease when the R_SERIES value increases. Note that this is not a desired behaviour. If your sensors are not fully charging and discharging properly it is recommended to decrease the switching frequency by using prescalar configuration and putting proper prescalar value. (1/F_SW>=  10 * R_SENSOR*C_SENSOR)

Noise in the system should be limited to below 50 counts to achieve a 5:1 SNR (5:1 SNR is the minimum requirement for any CapSense design). If a noise count is greater than 50 filtering techniques or layout changes need to be made.

Note: A properly designed system will have noise counts less than 20.
 

Response: The switching accuracy is dependent on the accuracy or tolerance of whatever clock is used as the source for the System Clock (SysClk). In typical applications, SysClk is derived from the Internal Main Oscillator (IMO) of the PSoC device. In the CSD application, all the blocks in the system have a clock source derived from SysClk. So, all clocks will have an accuracy that is the same as SysClk.

The IMO frequency tolerance over temperature and voltage can be seen in any PSoC device datasheet.

Avoiding/Solving this problem requires avoiding CY8C20X36A/46A/66A/96A chip from seeing the “AC52” key in reset condition, which in turn is possible if ISSP lines of CY8C20X36A/46A/66A/96A are not shared.

Note: Cypress do not recommend sharing ISSP bus of CY8C20X36A/46A/66A/96A parts with other PSoC devices

This is in compliance with standard EN61000-4-2:2009, device is able to withstand indirect discharge of ±4KV (contact discharge) and air discharge for ±8KV.

Any level of discharge exceeding ~±15KV will damage the CY3217-MiniProg1 unit.

CY8C20xx7 family of CapSense Controller does not support on-chip debug (OCD) feature unlike other CapSense controllers from Cypress.

CapSense system and other features supported by CY8C20xx7 family are also supported by CY8C20xx6A family of CapSense controllers, hence on-chip debug feature supported by CY8C20xx6A can be used for developments and debugging purpose.

Wake up from sleep on sleep timer interrupt >> scan the capsense sensors >> go to sleep again

To reduce the power consumption even further, instead of all the sensors, only one proximity sensor can be scanned such that the active time (time required to scan all sensors) is reduced. Note that the proximity sensor need not be an extra sensor on the layout, various buttons can be ganged together to form the proximity sensor as well.
 

Related resources:

1. Code examples

2. Power consumption calculation

3. Getting started with CapSense design guide

Related resources:

1. Getting started design guide

2. Backlight fading code examples

If a full duplex UART functionality is needed along with CapSense, the following devices could be used:

1. CY8C21x34, CY8C21x34B or CY8C24x94: Here, CSDADC can be used for CapSense functionality (PRS8 configuration using two digital blocks) along with the UART user module. Note that these devices use Rb method instead of IDAC method and hence, an external Rb would be required in both the cases.

2. CY8C22x45 or CY8C28xxx: These devices have larger number of digital blocks and hence can support UART with CapSense. Also, these suppport both Rb and IDAC methods and also support dual channel CapSense which means two buttons can be scanned simultaneously with these devices.

3. PSoC3/5: These have universal digital blocks which could be used for UART along with CapSense. These also suppport both Rb and IDAC methods and dual channel CapSense as 22x45/28xxx.

Step2: Enable I2C block interrupt (INT_MSK0 | = 0x80)

Step3: Enable I2C hardware address matching feature, this is done by replacing assembly instruction "mov reg[I2C_XCFG], 0" with "mov reg[I2C_XCFG], 0x01" in EzI2Cs_Start() API. API can be found in EzI2Cs.asm file.

Step4: Set I2C hardware address in register I2C_ADDR. Set address should be same as the "Slave_Addr" parameter of EzI2C UM

Note: Above modifications are to be made on top of a working EzI2C UM configuration/code in PD5 SP6 (or earlier). Step3 can be skipped if “EzI2Cs.asm” template file residing in the location “C:\Program Files\Cypress\Common\CypressSemiDeviceEditor\Data\CY8C20060\EzI2Cs” is replaced with the one attached with this KB article (before replacing make sure that PSoC designer version is of PD5SP6 if not follow Step3 above)

Sleep Entry/Exit:

Following procedure need to be followed every time for putting /waking-up device to/from sleep,

Step1:  Call M8C_Sleep Macro; Device entry to sleep should be directly under the control of I2C Master.  

Step2:  Master can wake-up the device from sleep by sending a read instruction targeted to the device.

Step3:  Data contained in the above wake-up I2C read instruction should be discarded by I2C master.

If the requirement demands an air gap, you may connect a spring between the capsense button and the overlay, this should enable to detect it as a button with better sensitivity.

You may also refer an application note "Using Springs as CapSense Sensors AN44999"

This application note considers the possibility of using springs as sensors. A comparison with solid conductive sensors and recommendations for the practical usage of springs are also discussed.

- BP Microsystems
http://www.bpmicro.com
Programmer Model 1400 and 1700
Running BP WIN Software Revision V4.64.0 or V4.66.1

- HiLo
http://www.hilosystems.com.tw/
Programmer Model All 100
Running S/W v1.59

- RPM Systems
www.rpmsys.com
Programmer Model: MPQ 4 Port Programmer, MPQ-E2 4 Port Programmer
Running S/W Rev 1.11.1 (Firmware 2.14)

The AN53490 describes Design to Production of Capsense express in detail.

Follow the below steps to install it :

Download Microsoft Report tool from:
http://www.microsoft.com/download/en/details.aspx?displaylang=en&id=21916#Instructions

1. Close PSoC Designer

2. Install Microsoft Report tool

3. Open PSoC Designer project

4. Observe defect is not reproduced

Scanning Time vs Scanning Speed and Resolution information is present in the CSD2X user module datasheet (001-50243 revision *E) is incorrect. Please refer to the latest CSD2X user module datasheet (001-50243 revision *F) for correct information.

The updated CSD2X user module datasheet (001-50243 revision *F) can be downloaded from http://www.cypress.com/?rID=36673 and same will be available in PSoC Designer 5.2 (next release of PSoC Designer)

1. Go to www.cypress.com.  On the top right, you will see a “Keyword / Part Number” search box (adjacent to “Contact Us.”) 

2. Select the “Part Number” tab above this text box.

3. Type the exact part number, for example CY8C29466-12PVXE.

4. The part number will be listed in the search results page.

5. Click on the part number link (1st column starting from the left). This will open a new web page.

Moisture Sensitivity Level (MSL) can be found by clicking the “Quality & Pb-free Data” link on the top, or by just scrolling down to the Quality & Pb-free Data” section about half way down the page.

All other Quality information for this part number (e.g., RoHS compliance, Lead/Ball Finish, Qualification Reports, IPC reports) can also be found on this web page. 

In case of any questions, or if the information is not available for a particular part number, please create a support case at www.cypress.com/support

If you do not know the Cypress part number: 

1. Go to www.cypress.com.  Browse the different products (“Products” tab on the top navigation menu) by family.

2. Once you choose the relevant product family (e.g., “Clocks and Buffers->Clock Distribution,” “Memory->FIFOs”), scroll down the particular page to get to the “Parametric Product Selector.”

3. Use this tool to find the part number by function/feature, and click on the part number you are interested in. This will lead you directly to step # 5 above.

If you are trying to program CY3280-20xx6 kit using MiniProg3 and external power, even though the device (Vcc) gets powered from the external supply, the Vcc_prog pin at the ISSP header of the board is not powered. Thus, MiniProg3 does not detect power and hence does not acquire the device. In order that the device is programmed, make sure to Vcc_prog pin is connected to the Vcc pin using an external wire.

Note that the MiniProg1 does not do a power detect check and hence tries to program even if the Vdd pin of the MiniProg1 is not powered externally.

If you had made any manual connections of pins to the Analog mux bus in the chip level view of the project (in SP4 or SP4.5), then these connections were not implemented in the generated code. Hence, the functionality of CSD user module was not affected.

When you upgraded to SP5.0 or higher version of PD5.0 where the bug is fixed, it actually implemented the manual connections of pins to the Analog mux bus (by setting MUX_CRx registers properly), which you had done in chip level view before. These undesired connections caused the improper functionality of CSD user module in SP5.0 (or higher).

Solution: Go to the chip level view of project & break the connections of the pins to Analog mux bus which you had done manually. If your project has CSD & any other user module which needs Analog mux bus for its operation (such as ADCINC user module), then in firmware of the project write the code in such a way that Analog mux bus is used by them in time division multiplexed form. Example: For ADCINC user module, If you want to convert the analog voltage level on port pin P0[0] to digital form, then before starting the A-D conversion, connect P0[0] pin to the Analog mux bus by setting bit-0 of MUX_CR0 register. After the conversion is completed, break this connection by clearing the bit-0 of MUX_CR0 & then assert the CSD scanning process.

Note: PSoC Designer 5.0 Service Pack 6 is the last release of PSoC Designer that supports System-Level Design (PSoC Express). PSoC Designer 5.1 and beyond will not support System Level Design. PSoC Designer 5.0 SP6 will continue to be available for System Level Design users, and it will co-exist with future PSoC Designer releases. However, we are not recommending System Level Design for production designs.

If you had made any manual connections of pins to the Analog mux bus in the chip level view of the project (in SP4 or SP4.5), then these connections were not implemented in the generated code. Hence, the functionality of CSD user module was not affected.

When you upgraded to SP5.0 or higher version of PD5.0 where the bug is fixed, it actually implemented the manual connections of pins to the Analog mux bus (by setting MUX_CRx registers properly), which you had done in chip level view before. These undesired connections caused the improper functionality of CSD user module in SP5.0 (or higher).

To fix this, go to the chip level view of project & break the connections of the pins to Analog mux bus which you had done manually. If your project has CSD & any other user module which needs Analog mux bus for its operation (such as ADCINC user module), then in firmware of the project write the code in such a way that Analog mux bus is used by them in time division multiplexed form. Example: For ADCINC user module, If you want to convert the analog voltage level on port pin P0[0] to digital form, then before starting the A-D conversion, connect P0[0] pin to the Analog mux bus by setting bit-0 of MUX_CR0 register. After the conversion is completed, break this connection by clearing the bit-0 of MUX_CR0 & then assert the CSD scanning process.

• CY8C24x23A
• CY8C22x13A
• CY8C21x23
• CY8C21x34
• CY8C20x34

The following part families can work on a minimum supply voltage of 3 V:

• CY8C24x94
• CY8C29X66
• CY8C27X43
• CY8C22x45
• CY8C28xxx

CY8C20xx6A can work on a minimum supply voltage of 1.71 V.

Note: CY8C21x34 devices need a minimum voltage of 2.5V during POR.

Important note:

Note: This is just for reference and gives the approximate parasitic capacitance. Parasitic capacitance varies with temperature, overlay, humidity and device.

A code example for proximity sensing using CY8C21x34 device along with associated documentation and video could be found here. A proximity of around 10 cm can be sensed, based upon the radius of track or wire used for it.

Method 1:

1. Add a comparator and select for reference input the ASE10 or ASE11 source. Start it with Full power.
2. Add an counter as PWM generator, select row broadcast bus source the counter block. Start it.
3. Write to AMD_CR0 by selection modulator source the boardcast bus.
4. Clear ADCx_TR register to set maximum capacitor array values.
5. Clear FVal bit in ASExxCR0 register.

Note: This analog output can only be used internally for example as a Reference to a comparator input.

For more details have a look at the example project attached here.

Method 2:

Route the PWM output to a GPIO pin, pass the PWM output through a low pass filter such that the cut off frequency is lower than the PWM frequency. The analog output level is varied by changing the duty cycle of the PWM. For 90% duty cycle of PWM, you get an analog signal of 4.5V and for 10% duty cycle of PWM, you get an analog signal of 0.5V.

Note: This method requires external components but the analog output can be used externally.

CY8C21434-24LTXI ----- (5x5 mm 1.00 MAX) SAWN QFN
CY8C21434-24LFXI ----- (5x5 mm 0.93 MAX) QFN

If you are using Capsense controllers, you can find more information on Design Considerations here: Getting Started with Capsense

There are two ways to implement CSD + ADC.

1) Use the CSDADC user module.  In this UM, Analog resources are shared among capsense and ADC.

2)  Use dynamic reconfiguration : More details and implementation can be found in application note AN49079-CapSense(TM) PLUS: Dynamically Configuring Capsense

Note:  This is applicable to CY8C21x34 and CY8C24x94 family of devices. You can place CSD and ADC together in CY8C20xx6A family of devices.

1. Place the input driver that you would like to monitor in the Design window.

2. Place an I2C Valuator in the Design Window.

3. Build the project and program the board.

4. Once the board is programmed, go to the Monitor window and connect the device and monitor the input.