Knowledge Base Articles - Cypress.com http://www.cypress.com/?app=search&searchType=advanced&keyword%3D%26rtID%3D118%26id%3D1575%26applicationID%3D0%26l%3D0 CY3217-MiniProg1 Electrostatic Discharge Resistance – KBA83013 http://www.cypress.com/?rID=58804 Answer: The ESD acceptance level of the CY3217-MiniProg1 kit is ±8 KV, air discharge. This is in compliance with standard EN61000-4-2:2009. The device is able to withstand an indirect discharge of ±4 KV (contact discharge) and an air discharge of ±8 KV.

Any level of discharge exceeding approximately ±15 KV will damage the CY3217-MiniProg1 unit.

For more information, see documentation for Development Kits/Boards: CY3217-MiniProg1.

]]>
Fri, 05 Dec 2014 00:43:17 -0600
Addressing Multiple CY8CMBR3xxx CapSense<sup>®</sup> Express™ Devices on the Same I<sup>2</sup>C Bus – KBA90792 http://www.cypress.com/?rID=91928 Answer: By default, all I2C addresses of CY8CMBR3xxx CapSense Express devices are set to 0x37. You can use one of the following methods to enable addressing multiple devices on the same I2C bus:

Method 1 (Applicable for all parts in the CY8CMBR3xxx family):

Configure CapSense Express controllers with different I2C addresses by using the production programmer before assembly.

Method 2 (Applicable only for parts that have the XRES input):

If configuring the CapSense Express Controller is performed by the Host Controller after the assembly, perform the following sequence of tasks from the Master Controller. You perform these steps on one device at a time.

  1. Put CE#1 in reset mode by pulling the XRES pin LOW for all devices with the same I2C address, except the one you are configuring. This is applicable if there are more than two CapSense Express devices with the same address on the bus.
  2. Send the configuration file generated by the EZ-Click™ Customizer tool to CE#2 over the I2C bus. The configuration file must have different addresses for CE#1 and CE#2 in EZ-Click to avoid address conflicts.
  3. Reset CE#2 for the configuration to take effect. This can be a software reset or a hardware reset.
  4. Configure CE#1.
]]>
Thu, 21 Aug 2014 02:15:56 -0600
MiniProg3 Programming in XRES Mode – KBA82808 http://www.cypress.com/?rID=98721 Answer: XRES mode requires the board to be powered prior to starting the program. When the MinProg3 is used to program a board in XRES mode, it first checks for power at the pin connected to its VTARG pin. If that pin does not have power, it does not acquire the device.

If you are trying to program the CY3280-20xx6 kit using the MiniProg3 and an external power supply, the Vcc_prog pin at the ISSP header of the board is not powered, even though the device is getting power from the external supply. Make sure that the Vcc_prog pin is connected to the VCC pin using an external wire.

The MiniProg1 does not check for power prior to programming. It will try to program the device even if the VDD pin of the MiniProg1 is not powered externally.

]]>
Tue, 12 Aug 2014 03:52:07 -0600
Variation of Parasitic Capacitance (C<sub>P</sub>) Between Segments in a Slider Design Using CY8CMBR3106S – KBA91404 http://www.cypress.com/?rID=93424 Answer: A slider has many segments, each of which is connected separately to the SLDxy pin of the CY8CMBR3106S device. Each segment is separately scanned and the centroid algorithm is applied finally on the signal values of all the segments to calculate the centroid position. The SmartSense™ algorithm implements a specific tuning method for slider to avoid nonlinearity in the centroid that could occur due to the difference of CP in the segments. However, the following layout conditions need to be met in order for the slider to work.

  1. CP of any segment should always be within the supported range of 5-45 pF. To meet this condition, ensure that the layout best practices provided in the CY8CMBR3xxx CapSense design guide are followed
  2. CP of other segments should be greater than 75% of the CP of the segment with the maximum value in that slider. For example, if the CP of the segment with the maximum value is 30 pF, the Cp of other segments should be greater than 22.5 pF.

    Implement the following layout design rules to meet this condition:

    • Design the shape of all segments to be as uniform as possible.
    • Keep the length and the width of the traces connecting the segments to the CapSense controller the same for all segments.
    • Maintain the same air gap between the sensor or traces to ground plane or hatch.
]]>
Fri, 11 Jul 2014 02:15:56 -0600
Proximity sensing using CSD http://www.cypress.com/?rID=46609 The proximity sensor should be placed as a "button" in CSD Wizard. The firmware for proximity sensor remains similar to that of a normal button. However, the range of the sensors is decided by the layout and the tuning parameters. Depending upon the noise in the RawCounts, firmware filters may have to be used. Please refer to the design guides for layout and design considerations.

A code example for proximity sensing using CY8C21x34 device along with associated documentation and video could be found here http://www.planetpsoc.com/psoc1-projects-capsense/31-proximity-sensing-csd-and-cy8c21x34.html. A proximity of around 10 cm can be sensed, based upon the radius of track or wire used for it.

]]>
Tue, 01 Jul 2014 06:52:41 -0600
The Measured Current Is Smaller Than Set in the CapSense<sup>®</sup> User Modules and IDACL_D/IDACR_D Registers – KBA92751 http://www.cypress.com/?rID=96157 Answer: The PSoC® 1 iDACs are not trimmed by default. To get correct iDAC values, the iDACs should be trimmed. Use the following command to trim the iDACs:

DAC_CR1 |= 0x10;

The command should be executed before the CapSense_Start API. The trimming operates correctly because the CapSense User Modules do not change the IDAC_TRIM bitfields of the IDAC_CR1 register.

]]>
Tue, 10 Jun 2014 00:55:42 -0600
Capacitive Proximity Sensing – KBA92366 http://www.cypress.com/?rID=95776 Answer: The attached project implements capacitive proximity sensing using the CY3280-21x34 kit. Use the following steps to test this project.

Programming the PSoC®

  1. Open PSoC Programmer™ from the path Start > All Programs > Cypress > PSoC Programmer.
  2. Load the hex file Proximity_CY3280_21x34_Kit.hex from the attached project folder “Proximity_CY3280_21x34_Kit” by clicking the File Load option and setting the Programmer settings as shown in Figure 1.

    Figure 1. PSoC Programmer Settings

    PSoC Programmer

  3. Connect the MiniProg3 to the ISSP header of the CY3280-21x34 kit as shown in Figure 2.

    Figure 2. MiniProg3 Connection

    MiniProg3 Connection

  4. Click the Program option as shown in Figure 3.

    Figure 3. Program the PSoC

Proximity Sensing and Data Viewing

Follow the steps below to set up the hardware for proximity sensing and data viewing:

  1. Connect the MiniProg3 (used as I2C to USB bridge) to the CY3280-21x34 kit and a wire loop (10 cm circumference) to P0[0] on the P2 connector of the CY3280-21x34 kit as shown in Figure 4.

    Figure 4. MiniProg3 Connection and Sensor Connection

    MiniProg3 Connection

  2. Open the Bridge Control Panel (BCP) software from Start > All Programs > Cypress > Bridge Control Panel.
  3. Open the Variable Setting window from Chart > Variable Settings in the BCP software.
  4. Enter the variable names and data type in the Variable Settings window as shown in Figure 5 and click OK.

    Figure 5. Variable Settings on the Bridge Control Panel

    Variable Settings

  5. Enter the commands shown in Figure 6 into the Editor window of the BCP.

    Figure 6. I2C Communication Commands

    I<sup>2</sup>C Communication Commands

  6. Click on the Toggle Power button (shown in Figure 7) at the bottom of the BCP window to power the board using the MiniProg3.

    Figure 7. Bridge Control Panel Settings

    Bridge Control Panel Settings

  7. Keep the cursor on the first command (w 04 0) in the Editor window and press Enter.
  8. Keep the cursor on the second command line in the Editor window and click Repeat.
  9. Click the Chart tab on the BCP and select the plot Status listed in the top right corner.
  10. Bring the hand towards the wire loop and observe in the BCP that the status variable becomes ‘1’ as shown in Figure 8.

    Figure 8. Status Variable on Bridge Control Panel

    Status Variable

  11. Deselect the Status plot and select the plot RawCount to see the profile of Raw counts shown in Figure 9.

    Figure 9. Raw Count Profile

    Raw Count Profile

Proximity Tuning Steps

The following steps can be used to tune the CapSense® system for proximity detection.

  1. Determining Proximity Distance

    For reliable proximity detection, the SNR needs to be 5:1. Follow the steps below to determine the proximity distance.

    1. Find the Noise Count.
    2. Calculate the Signal count that is required to achieve a 5:1 SNR (Signal Count = 5*Noise Count).
    3. Bring the hand towards the wire sensor until the signal count reaches the value calculated in Step-ii. The present distance between the wire sensor and the hand is called the Proximity distance.

    Note: Refer to section 4.1.1, “Signal, Noise, and SNR” in the CY8C21x34/B CapSense Design Guide for more information about SNR calculation.

  2. Determining CapSense Sigma Delta (without Prescalar) User Module Parameters for Proximity Detection

    The following steps can be used to determine the CapSense Sigma Delta (CSD) User Module (UM) parameters for proximity detection.

    1. Find the peak Difference Count from the BCP when there is no hand present.
    2. Find the Peak Difference Count from the BCP when the hand is present at the proximity distance calculated above.
    3. Set the Finger Threshold parameter to 60 percent of the Difference Count observed in Step-ii (when the hand is present).
    4. Set the Noise Threshold parameter to 40 percent of the Difference Count observed in Step-i (when no hand is present).
    5. Set Baseline Update Threshold to 100.
    6. Set Sensor Autoreset to Disabled.
    7. Set Hysteresis to 15 percent of the Difference Count observed in Step-ii (when the hand is present).
    8. Set Negative Noise Threshold equal to Noise Threshold.
    9. Set Scanning Speed to Slow.
    10. Set Resolution to 16.
    11. Set Ref Value to 1.
    12. Leave all the other parameters as their default values.

    Note: Click on the tab Table in the BCP to observe the Difference count values.

]]>
Fri, 30 May 2014 02:03:45 -0600
Resources Available for CapSense<sup>®</sup> Controllers – KBA92181 http://www.cypress.com/?rID=95458 Answer: This article provides a comprehensive list of resources that you can use to design applications using CapSense Controllers.

CapSense Controllers are categorized as follows.

Introduction:

Software and drivers: The following software is required for designing CapSense applications:

The following sections list the resources available for individual CapSense controller families:

Technical Support: If you have any queries or questions, the technical support team would be happy to assist you. You can create a support request, or if you are in the United States, you can talk to our technical support team by calling our toll-free number +1-800-541-4736 and then selecting option 2 at the IVR prompt.

You can also use the following support resources if you need quick assistance:

]]>
Fri, 23 May 2014 06:15:54 -0600
Accuracy of CapSense<sup>®</sup> Controllers - KBA82716 http://www.cypress.com/?rID=78029 Answer: CapSense controllers convert Capacitance into a digital value. Let us consider an example where we are representing a capacitance value between 0-45 pF with a 14-bit digital value. Now with 1LSB we can represent 45 pF/16384 = 2.7fF approximately 3fF. Thus, we could say that the accuracy is 3fF. But because of the inherent noise in the system we will always observe around 5-15 counts of noise (this noise is system dependent). So, in reality we can measure a minimum of only 5*3fF = 15pF.

Note that absolute capacitance measurement (raw count) is not very important in realizing a capacitive touch interface. Instead, measuring change in capacitance (signal) is critical for detecting when a finger touches a sensor. So, for the above system, it is not possible to successfully differentiate finger touch from noise if the finger produces only 15 fF signal (which means finger signal is equal to noise). Hence, it is recommended to have at-least 5:1 SNR which means finger signal should be a minimum of 75fF to enable a safe detection.

]]>
Tue, 08 Apr 2014 06:40:07 -0600
Tools for Developing Applications with CapSense Controllers - KBA83347 http://www.cypress.com/?rID=37995 Answer: The following tools and resources will help you quickly develop robust CapSense applications:


  1. PSoC Designer: The PSoC Designer 5.2 IDE is a full featured development tool for designing and debugging PSoC applications. The PSoC Designer comes with a free Imagecraft C compiler.
  2. PSoC Programmer: The PSoC Programmer 3.15.1 programs PSoC devices using the MiniProg1 programmer.
  3. Bridge Control Panel and Multichart: These tools are used to tune your CapSense design. The Bridge Control Panel is installed along with PSoC Programmer. The Multichart tool is available for download.
  4. USB-to-I2C Bridge: The USB-I2C Bridge Kit allows you to read data from the CapSense controller through the I2C interface and transmit it to your PC through USB. You can use the Bridge Control Panel to view and log the data. For more details see CapSense Data Viewing Tools -AN2397.This method is used with the following devices: CapSense and CapSense Plus: CY8C21x34, CY8C21x34B, CY8C21x45, CY8C22x45, CY8C24x94, CY8C20xx6A, CY8C20xx6H, CY8C20xx7, CY8C20XX6AS
    CapSense Express: CY8C201xxx
  5. USB-to-UART Bridge: Implementing a USB-to-UART Bridge as described in USB-to-UART Bridge-AN49943 allows you to read data from the CapSense controller through an RS232 interface and transmit it to your PC through USB. For more details see CapSense Data Viewing Tools -AN2397. This method is used with the following devices: CapSense Express:CY8CMBR2044, CY8CMBR2016, CY8CMBR2010
  6. Development Kits:
    • Universal Controller Kits: These kits feature predefined control circuitry and plug-in hardware to make prototyping and debugging easy. Programming and I2C-to-USB Bridge hardware are included.
      CY3280 - 20xx6
      CY3280 - 21x34
      CY3280 - 24x94
      CY3280 - 22x45
      CY3280 - 20x34
    • Universal CapSense Module Boards
      • The CY3280-BSM Simple Button Module consists of ten CapSense buttons and ten LEDs. This module connects to any CY3280 Universal CapSense Controller Board.
      • The CY3280-BMM Matrix Button Module consists of eight LEDs as well as eight CapSense sensors organized in a 4x4 matrix format to form 16 physical buttons. This module connects to any CY3280 Universal CapSense Controller Board.
      • The CY3280-SLM Linear Slider Module consists of five CapSense buttons, one linear slider (with ten sensors), and five LEDs. This module connects to any CY3280 Universal CapSense Controller Board.
      • The CY3280-SRM Radial Slider Module consists of four CapSense buttons, one radial slider (with ten sensors), and four LEDs. This module connects to any CY3280 Universal CapSense Controller Board.
      • The CY3280-BBM Universal CapSense Prototyping Module provides access to every signal routed to the 44-pin connector on the attached controller board(s). The prototyping module board is used in conjunction with a Universal CapSense Controller board to implement additional functionality that is not part of the other single-purpose Universal CapSense Module boards.
    • CapSense Express Evaluation Kits for CY8C201xx: With Cypress's PSoC Designer visual embedded system design tool and CapSense Express configuration tool, designers configure, monitor, and tune buttons or sliders, LEDs, and other general purpose I/Os over I2C in real time using a graphical user interface.
      CY3218-CAPEXP1 CapSense Express Kit
      CY3218-CAPEXP2 CapSense Express Kit
    • CapSense Express Evaluation Kit for CY8CMBR2044:
      CY3280-MBR-Capsense Express kit with Smartsense Auto-tuning
]]>
Fri, 21 Mar 2014 04:33:44 -0600
No Provision in PSoC<sup>®</sup> Designer™ 5.4 to Provide Number of Spaces for Indent/Tab – KBA91230 http://www.cypress.com/?rID=93026 Answer: In PSoC Designer 5.4 it is not possible to set the tab spaces. But it is possible to enable the feature to use space whenever tab is pressed under the option Tools > Options > Code Editor > Behavior.

]]>
Thu, 20 Mar 2014 05:24:05 -0600
Operating Voltage Range for CY8CMBR3xxx Family of CapSense Express Devices - KBA90791 http://www.cypress.com/?rID=91927 Answer: CY8CMBR3xxx CapSense Express devices are designed to operate at one of two voltage ranges: 1.8 V ±5% or 1.8 to 5.5 V.

CY8CMBR3xxx CapSense Express devices are not designed to operate continuously over the full range of 1.71 V to 5.5 V, but can operate continuously over the full range of 1.8 V to 5.5 V. This is important to know if your application is battery-powered and the operating voltage may gradually decrease as the battery gradually discharges.

Depending upon the operating voltage, you must enter the appropriate value for the SUPPLY_LOW_POWER bit in the I2C register map for the best CapSense performance. Note that setting an incorrect value for the SUPPLY_LOW_POWER bit in the register will not damage the part. However, the CapSense performance may be affected.

When operating in the 1.8 to 5.5 V range, the VCC pin must be connected to a 0.1μF capacitor and must not be connected to any other power source. When operating in the 1.8 V±5% range, VCC and VDD pins must be connected together.

]]>
Thu, 06 Mar 2014 02:36:55 -0600
Slider Diplexing in CY8C3106S CapSense® Express Devices - KBA90793 http://www.cypress.com/?rID=91929 Answer: No, the CY8CMBR3xxx CapSense® Express devices do not support the diplexing feature on linear sliders and radial sliders.

]]>
Mon, 24 Feb 2014 19:48:24 -0600
Resetting the Sensor Baseline With CY8CMBR3xxx CapSense® Express Devices - KBA90794 http://www.cypress.com/?rID=91933 Answer: A reset input to a CY8CMBR3xxx CapSense® controller (software reset, hardware reset, or power cycle reset) can reset the baseline. Sending a SLEEP command through the I2C interface and waking up the device can also reset the baseline without resetting the controller.

]]>
Mon, 24 Feb 2014 19:47:56 -0600
Sensor Dimensions of CY8CMBR3xxx CapSense® Express™ Devices - KBA90795 http://www.cypress.com/?rID=91935 Answer: You can use the Design Tool Box available in the EZ-Click™ Customizer tool to determine the dimensions of the sensor.

In addition to this tool, you can refer to the CapSense® Getting Started Guide and other CY8CMBR3xxx Design Guide documents that have detailed and complete design guidelines for sensors, layout, and system design.

]]>
Mon, 24 Feb 2014 19:47:30 -0600
Tuning the MBR3xxx CapSense® Controllers - KBA90796 http://www.cypress.com/?rID=91936 Answer: The CY8CMBR3xxx family of CapSense® controllers is built around the SmartSense™ auto-tuning algorithm. This algorithm reads the sensor properties and automatically adjusts the tuning parameters. You only need to configure the sensitivity register of the sensor (how sensitive the sensor should be to a human touch) through the I2C register map.

At the same time, you can disable the thresholds that were automatically set by the SmartSense auto-tuning algorithm and take control over the threshold parameters. You can disable the automatic threshold mode and manually set threshold values through the I2C register map.

]]>
Mon, 24 Feb 2014 19:46:30 -0600
Controlling the Digital Outputs of MBR3xxx CapSense® Express Devices - KBA90797 http://www.cypress.com/?rID=91937 Answer: You can control and configure the digital outputs (general purpose outputs) of CY8CMBR3xxx CapSense® controllers in several ways.

The GPOs (General Purpose Outputs) can be configured to be directly driven by the corresponding sensor status. GPOs can also be controlled through the I2C register map value, where the host controller writes the output status of GPOs to the I2C register to control the GPO outputs.

Regardless of how the GPOs are controlled (either through the I2C register map or directly by the sensor status), the PWM feature can be enabled on GPOs. In this configuration, duty cycles for active and inactive states can be configured on the GPO. The active-state duty cycle represents the duty cycle of PWM when the input of the GPO (the register map value or sensor status) is in the active (ON) state. On the other hand, the inactive duty cycle represents the duty cycle of PWM when the input of the GPO (the register map value or sensor status) is in the inactive (OFF) state.

Regardless of these configurations, the GPO can be configured in active HIGH logic and active LOW logic.

In the active HIGH logic configuration, the GPO input state (the sensor status or register map value) is driven on the GPO. When the active LOW logic mode is selected, the GPO input state is inverted and driven on the GPO. If PWM is enabled, the active LOW logic mode inverts the duty cycle on the GPO output. This mode can be used to drive LEDs; you can choose active HIGH or LOW logic depending on how the LEDs are connected (in current sink or source mode).

In addition to these configurations, GPOs can be configured in open-drain (logic HIGH = HI-Z and Logic LOW= Ground) or strong drive (logic HIGH = VDD and logic LOW = Ground) modes.

]]>
Mon, 24 Feb 2014 19:45:51 -0600
Communication Interface Supported by CY8CMBR3xxx CapSense® Express Devices - KBA90798 http://www.cypress.com/?rID=91939 Answer: CY8CMBR3xxx CapSense® controllers support only I2C interface and general-purpose outputs (GPOs). GPOs are uni-directional and output-only interfaces. GPOs can indicate the sensor status, and can be inputs to other controllers.

]]>
Mon, 24 Feb 2014 19:43:59 -0600
Addressing multiple capsense express devices on the same I2C bus http://www.cypress.com/?rID=43563 By default the I2C address of capsense express capacitive controllers are all set to 0x00h. If customer board needs to have two capsense express parts then master should follow the below steps to avoid data corruption in I2C bus,


Step#1: Master puts CE#1 in reset mode by pulling XRES pin high
Step#2: Master sends CE#2 configuration file (generated by PSoC designer) over the I2C bus. Customer should select different address for CE#1 & CE#2 in PSoC designer to avoid address conflict.
Step#3: Master resets CE#2 (software reset or hardware reset)
Step#4: Master puts CE#2 in reset mode by pulling XRES pin high, this step is optional since after Step#3 CE#2 address will get updated from 0x00h to user configured value.
Step#5: Master sends CE#1 configuration file (generated by PSoC designer) over the I2C bus.
Step#5: Master resets CE#1 (software reset or hardware reset).

Note:
i)      CE#1 - refers to 'Capsense Express' device #1
ii)     CE#2 - refers to 'Capsense Express' device #2
iii)    For the above procedure to work, make sure that atleast one of the capsense express part (out of the two) on board have XRES pin bonded out.

 

]]>
Fri, 22 Nov 2013 05:22:33 -0600
POR default Data structure table http://www.cypress.com/?rID=39646 The command code ’03’ sends new power-up defaults to the Capsense controller without changing current settings unless the 06h command is issued afterwards. This command is to be followed by 123 data bytes according to the POR Default Data Structure table.

The POR default data structure is the array of registers starting from location 0x04[OUTPUT_PORT0] to 0x81[CS_READ_BUTTON] . Note that this range has 126 bytes, but the POR default data structure is of 122 bytes, this is because of the two Read only bytes at 7A and 7B and two reserved location at 76 and 7D. Barring this, the default data structure table is the continuous array from 0x04 to 0x81. For these Register details, you can check the attached CY8C201xx register reference manual.

Further, the 123rd byte will be the CRC byte, which is the XOR of the first 122 bytes.

 

]]>
Fri, 22 Nov 2013 05:13:33 -0600
Air Gap between Capsense Button and Overlay Material http://www.cypress.com/?rID=40435 Firstly, our capsense is not recommended to have any air gap between the capsense button PCB and an Overlay material.

 
If your application demands an air gap, We suggest you to connect a spring between the capsense button and the overlay, this should enable to detect it as a button with better sensitivity.

For more information you may have a look at an application note "
Using Springs as CapSense Sensors AN44999
This application note considers the possibility of using springs as sensors. A comparison with solid conductive sensors and recommendations for the practical usage of springs are also discussed.
]]>
Fri, 22 Nov 2013 05:06:20 -0600
Knowledge Base – Cypress Semiconductor Cage Code – KBA89258 http://www.cypress.com/?rID=86132 Answer: The Commercial and Government Entity Code, or CAGE Code, is a unique identifier assigned to suppliers to various government or defense agencies, as well as to government agencies themselves and also various organizations.

CAGE codes provide a standardized method of identifying a given facility at a specific location.

Cypress Semiconductor’s Cage Code is 65786.

Cypress Minnesota - Fab4 who ship wafers has Cage Code 5AZZ0.

Ramtron International who specialized memory who and was acquired by Cypress Semiconductor has a CAGE code OJP56.

]]>
Fri, 27 Sep 2013 02:08:09 -0600
Controlling Digital Outputs of CapSense® Express (CY8C201xxx) Devices - KBA82461 http://www.cypress.com/?rID=39727 Answer: Yes, it is possible to control the status of a digital output using I2C host control. The host must write the desired output value to the corresponding bit of the OUTPUT_PORTx register, and then write a "0" to the digital output’s Op_En bit of the OP_SEL_x register. To return to normal operation with the CapSense input controlling the digital output, the host must write a "1" to the digital output’s Op_En bit of the OP_SEL_x register. 

]]>
Mon, 29 Jul 2013 06:18:08 -0600
CapSense® with a Flex PCB - KBA82731 http://www.cypress.com/?rID=35290 Answer: You need to follow two important guidelines when using a Flex PCB for your CapSense design:

  1. You may need to use a slower CapSense clock, because the resistance per square inch for Flex is higher.
  2. Do not use a hatched ground below your sensor. Flex PCB is much thinner than FR4 PCB, and a hatched ground will increase parasitic capacitance.

Refer to the design guide Getting Started with CapSense for more design guidelines.

]]>
Mon, 29 Jul 2013 06:10:33 -0600
Resetting Sensor Baseline with CapSense® Express™ - KBA82926 http://www.cypress.com/?rID=39726 Answer: Yes, you can do this by writing a "1" to bit 7 of the CS_Filtering register, which reinitializes the baseline. The bit automatically clears after the baseline is reset. You should not reset the baseline when a finger is on the button.

]]>
Thu, 18 Jul 2013 02:19:23 -0600
CapSense® Signal-to Noise Ratio - KBA82807 http://www.cypress.com/?rID=36855 Answer: The SNR for a CapSense system is defined as the ratio of the increase in the raw counts caused by a finger touch to the peak-to-peak raw counts caused by noise present in the system.

The recommended minimum SNR is 5:1. A typical SNR is between 10:1 and 20:1 when finger capacitance is 0.1pF. The actual SNR depends on your project settings, especially scan time and sensitivity. You can increase the SNR by reducing the scan speed but this results in increased power consumption.

]]>
Thu, 18 Jul 2013 02:16:10 -0600
Maximum Overlay Thickness for CapSense® - KBA82812 http://www.cypress.com/?rID=36862 Answer: There is no specific maximum value for overlay thickness. You should select the overlay material and thickness depending on the following factors:

  • The sensitivity of your CapSense system is directly proportional to the overlay material and thickness.

Cfinger = (εo εr A)/D

where:

εo = free space permittivity
εr = dielectric constant of overlay
A = area of finger and sensor pad overlay
D = overlay thickness

  • A thicker overlay lowers finger capacitance, which in turn lowers finger response. A thicker overlay can also increase parasitic capacitance. However, the overlay must be thick enough to prevent breakdown during an ESD event. Remember that you can increase finger response by increasing button size to compensate for thicker overlays. The following table gives the minimum overlay thickness for different materials.

  

For further details, refer to the Capsense Getting Started guide.

]]>
Thu, 18 Jul 2013 01:57:57 -0600
Latched Output with CapSense Express Devices - KBA82888 http://www.cypress.com/?rID=39719 Answer: Yes. Set the output latch direction using PSoC Designer 5.0 or by writing to the STATUS_HOLD_MSK register. Reading the STATUS_PORTx (02h) register reads the latched CapSense input data and clears the register as shown below.

Refer to the Register Reference Guide for more information on these registers.

]]>
Thu, 18 Jul 2013 01:25:20 -0600
Operating Voltage Range for CapSense Express Devices - KBA82463 http://www.cypress.com/?rID=39722 Answer: CapSense Express devices are designed to operate at one of three voltage ranges: 2.4—2.9 VDC, 3.1—3.6 VDC, or 4.75—5.25 VDC. CapSense Express devices are not designed to operate continuously over the full range of 5.25—2.4 VDC. This is important to know if your application is battery powered and the operating voltage may gradually decrease as the battery gradually discharges. When the operating voltage is not in the initial operating range the device will still communicate over the I2C bus but the CapSense functionality will not work. Once the device returns to the initial operating range the CapSense functionality will start again but the sensing capability may be impaired unless the system is enabled to recalibrate itself with a reset.


For best results, ensure that the voltage remains in one of the three operating ranges. Additionally, at 2.4 VDC the CapSense scanning functions operate at a slower frequency and response time decreases by a factor of 4.

]]>
Thu, 18 Jul 2013 01:11:52 -0600
Objects That Can Activate CapSense Sensors - KBA82822 http://www.cypress.com/?rID=36844 Answer: CapSense sensors detect changes in capacitance, therefore, any conductive object could potentially activate the sensors. This includes liquids, solid metal objects, and metal-coated objects.

]]>
Wed, 08 May 2013 04:36:04 -0600
Extending a CapSense Sensor Above the PCB - KBA82851 http://www.cypress.com/?rID=36845 Answer: A CapSense sensor can be extended using any conductive object that makes direct electrical contact with the PCB. However, using conductive rubber could be problematic if it can be deformed. The capacitance of a sensor is based on the shape of the sensor. If the conductive rubber is deformed, it could change the sensor capacitance and cause a false finger touch to be reported.


Refer to Getting Started with CapSense for more information on how to use springs as CapSense sensors.

]]>
Tue, 07 May 2013 01:59:07 -0600
Configuring Unused Buttons - KBA82818 http://www.cypress.com/?rID=29385 Answer: The GPIO setting for the unused button inputs need to be configured as "Strong" and driven low. These pins should not be configured as buttons in the designer project. Often, the default designer setting is "Hi Z", but this may cause a problem if the unused buttons are capacitively coupled to adjacent buttons in the Hi Z state.

]]>
Tue, 07 May 2013 01:42:03 -0600
Housing CapSense Circuits - KBA82823 http://www.cypress.com/?rID=36841 Answer: Yes, the entire area above the CapSense sensor must not contain any conductive materials or air gaps. This includes any metal, paint with metallic flakes on the overlay, and air bubbles beneath the overlay. Also, thicker overlays will reduce the sensitivity of the sensor and make it difficult to detect a finger touch. There are no restrictions on the housing to the sides and below the CapSense circuit.

]]>
Tue, 07 May 2013 01:25:24 -0600
Detecting Bleed Resistor or Modulating Capacitor Damage - KBA85698 http://www.cypress.com/?rID=39725 Question: Is there any method of detecting that the external Rb or Cmod has been damaged or not?

Response: When the Rb and Cmod is breakdown then there are 4 possibilities which can be detected with the help of supervisory code. The 4 possibilities are as follows:

1. Cmod Short: In this particular case the counts will be zero because it'll connect the input of the CapSense module directly to ground. Thus, supervisory code will be able to detect that the Cmod has been shorted.

Also, in this particular case, no matter whether the sensor was active or not, the rawcounts and baseline will snap down to 0 and the sensor will be turned OFF. The counts will be zero irrespective of the state of Rb (open/shorted/normal).

2. Cmod Open: If CMOD is open device continues to operate at higher level of noise. If your application uses thin overlay and has strong touch signal this could be painless. If touch signal is weak then you could encounter false buttons activation in this case.

3. Rb Shorted: If Rb is shorted device continues to operate at higher level of noise. If your application uses thin overlay and has strong touch signal this could be painless. If touch signal is weak you could encounter false buttons activation in this case.

Also, In this particular case the raw counts will decrease and the baseline will follow this because of its negative baseline reset.

4. Rb Open: If Rb is open counts will get saturated and the counts will be 2^Resolution -1. If resolution is set as 12 then the counts will be 4095 irrespective of Cmod open/normal. You can easily detect this as well from you supervisory code.
 

-->

Answer: You can use supervisory code to detect if Rb or Cmod are damaged by monitoring them for shorts or opens. The four possible failure modes are:

Cmod Shorted: If this is the case, the input of the CapSense module will be connected directly to ground. Whether the sensor is active or not, the raw counts and baseline will snap down to zero and the sensor will be turned OFF. The counts will be zero irrespective of the state of Rb (open/shorted/normal).

Cmod Open: If this is the case, the device will continue to operate with a higher level of noise. If your application uses a thin overlay and has a strong touch signal this may not cause a problem. However, if the touch signal is weak in your application, you could encounter false button activations.

Rb Shorted: If this is the case, the device will continue to operate with a higher level of noise. The raw counts will decrease and the baseline will follow because of its negative baseline reset. If your application uses a thin overlay and has a strong touch signal this may not cause a problem. However, if the touch signal is weak in your application, you could encounter false button activations.

Rb Open: If this is the case, the raw counts will saturate at 2(Resolution -1). For example, if the resolution is 12, raw counts will be 4095 even if Cmod if open.

]]>
Fri, 12 Apr 2013 03:54:52 -0600
Relationship between Difference Counts and Sensor Capacitance - KBA82706 http://www.cypress.com/?rID=77994 Answer: The relationship between CSD raw counts (raw counts) and sensor capacitance (CS) is:

Where:
Vref = The comparator reference (selected in the user module configuration window in PSoC Designer)
Rb = The external bleed resistor
fs = The average switching frequency of the sensors (depends on the CSD configuration settings such as PRS and prescalar)
n = The resolution (set in the user module configuration window)

The difference count is calculated by subtracting the raw count without a finger on the sensor (CS = CP) from the raw count with a finger present on the sensor (CS = CP + CF):

By substituting the equation for raw counts you can see the linear relationship between difference counts and finger capacitance:

Note: This linear relationship holds true as long as raw counts do not saturate and assumes that the sensors are fully charged and discharged to VDD and Vref respectively within 1/fs max. If PRS is selected as the clock source, the average switching frequency is fIMO/4 but the maximum switching frequency is fIMO/2.

]]>
Tue, 09 Apr 2013 06:46:19 -0600
Storing User Data in CapSense® Express™ Devices - KBA82931 http://www.cypress.com/?rID=78024 Answer: There is no memory space available for user data in CapSense Express devices.

]]>
Tue, 09 Apr 2013 00:03:52 -0600
Raw Count Drift - KBA82718 http://www.cypress.com/?rID=77991 Answer: Raw count is a function of the capacitance of the sensor, reference voltage, external bleed resistance (for CSD-Rb), internal IDAC (for CSD-IDAC), and IMO. Environmental conditions such as temperature and humidity can vary over time and affect these values. Therefore, raw counts can change over time. However, these changes are gradual, and the baseline update algorithm assures that they do not result in false touches being reported.

]]>
Mon, 08 Apr 2013 06:47:29 -0600
Software Reset in Normal Mode for CapSense® Express™ (CY8C201xxx) - KBA82924 http://www.cypress.com/?rID=39728 Answer: No, it is not possible to do a software reset while the device is in normal mode. The device should be in set up mode. To enter set up mode and do a software reset use the following command: W 00 A0 08 W 00 A0 06.

]]>
Tue, 19 Mar 2013 01:46:25 -0600
Sensitivity and Capacitance Range for the CY8C21x34 CSD - KBA82522 http://www.cypress.com/?rID=46406 Answer: Sensitivity is calculated using the digital capacitive measurement result returned by the User Module, referred to as Counts. Capacitance measurement range is calculated using sensitivity.

Counts are calculated using Equation 1.

Where:

 
N = Resolution of the User Module
RB = Bleed resistor value
CSENSOR = Capacitance of the sensor (Parasitic Capacitance, CP + Finger Capacitance, CF)
FSW-AVG = Average switching frequency of the sensor
RefVal = Reference value of the User Module

Sensitivity is calculated using Equation 2.

 
 

The upper limit of the capacitance measurement range is calculated using Equation 3.

 
 

For example, given the following User Module settings:

 
N = 14
RB = 10 kΩ
FSW-AVG = 375 kHz (Prescaler = 15)
RefVal = 0

Sensitivity = 184.3 Counts/pF

Capacitance measurement range (upper limit) = 88.9 pF

Note: The “sensitivity” calculated above is the capacitive measurement module sensitivity, not the system sensitivity to button/sensor activation.

Note: It is not possible to measure capacitance values all the way down to zero because there will always be some parasitic capacitance, CP, and pin capacitance measured by the sensor.

]]>
Thu, 31 Jan 2013 23:04:28 -0600
Calculating the Resolution for CY8C21x34 CapSense CSD - KBA82521 http://www.cypress.com/?rID=46407 Answer: Resolution is equal to the inverse of sensitivity. Sensitivity is calculated using the following formula:

Where:

 
Counts = Digital capacitance measurement result returned by the User Module
N = Resolution of the User Module
RB = Bleed resistor value
FSW-AVG = Average switching frequency of the sensor
RefVal = Reference value of the User Module

For example, given the following User Module settings:

 
N = 14
RB = 10 kΩ
FSW-AVG = 375 kHz (Prescaler = 15)
RefVal = 0

Resolution = 0.00543 pF

Note: Although the calculation indicates that a change as small as 0.00543 pF can be detected, raw-count noise limits the use of such high resolution. CapSense is not recommended for measuring absolute capacitances.

Note: The “sensitivity” calculated above is the capacitive measurement module sensitivity, not the system sensitivity to button/sensor activation.

]]>
Thu, 31 Jan 2013 22:49:37 -0600
CSDADC Datasheet Error for VC2 Configuration - KBA82886 http://www.cypress.com/?rID=55099 Answer: The CSDADC datasheet version 1.30 has an error. The operation (or switching) frequency should be IMO/(VC2xVC1) for VC2 configuration, since the source of the VC2 divider is VC1 itself. This has been fixed in PSoC Designer 5.2.

The CSDADC device is sensitive to EMC signals at the operation frequency and harmonics in VC2 configuration. This configuration is only recommended when you do not plan to run EMC/EMI certification tests.

]]>
Tue, 08 Jan 2013 03:16:06 -0600
Difference between CY8C20x34 and CY8C20x24 - KBA82927 http://www.cypress.com/?rID=43454 Answer: The only difference between these two devices is the number of sliders they can implement. The CY8C20x24 supports one slider, and the CY8C20x34 supports multiple sliders. The CY8C20x24 is intended for multimedia keyboard designs with one slider for volume control and few buttons. All other functions are the same for the CY8C20x34 and CY8C20x24 devices.

]]>
Tue, 08 Jan 2013 03:06:09 -0600
Clock Frequency of I2C Slave in CapSense Express Devices - KBA82517 http://www.cypress.com/?rID=74081 Answer: The I2C slave is configured to operate at 400 kHz. However, per the specification, the I2C bus operates at the frequency of the slowest device on the bus. Therefore, if the master is sending data at a rate of 50 kHz, the CapSense Express I2C slave will operate at 50 kHz.

]]>
Mon, 07 Jan 2013 22:36:28 -0600
Add P1[4] for R<sub>b</sub> in CY8C21234B SmartSense™ Version 1.30 - KBA83339 http://www.cypress.com/?rID=62400 Answer: This is a defect in PSoC Designer™ version 5.2 Service Pack 1(and earlier). For the SmartSense version 1.30, the CapSense® configuration wizard allows only one configuration for Rb, that is, to connect it to P1[1]. But since P1[1] is used as SCL (ISSP clock) line, it is not always possible to use it for Rb.

The defect will be fixed in the future versions of PSoC Designer but for the current version the following workaround can be used:

  1. Download the attached “SmartSense.asm”.
  2. Copy this file (and replace the old SmartSense.asm) to the following folder:
    C:\Program Files\Cypress\PSoC Designer\5.2\Common\CypressSemiDeviceEditor\Data\Stdum\SmartSense\Ver_1_30\CY8C21034

It should be noted that the configuration wizard will still show the Rb connection to P1[1]. But the hardware connection for Rb gets modified when the API SmartSense_Start() is called in “main.c” of the project. This workaround modifies ACE00CR2, ACE00CR1, ALT_CR0, CMP_GO_EN, PRT1DM0, PRT1DM1, and PRT1DM2 registers in the SmartSense_Start() API. The details of these registers can be found in the Technical Reference Manual (TRM) for CY8C21x34.

]]>
Thu, 27 Dec 2012 02:46:53 -0600
Configuring a CY8C201xx Device for Use Either with External Pull-ups or With a Master Operating at Different VDD – KBA80735 http://www.cypress.com/?rID=64957 Answer: The CY8C201xx devices support internal pull-up resistors on I2C lines. Table 1 shows the factory default settings for internal pull-up resistors.
 

Table 1: Factory Default Values for Internal Pull-Up Setting
 

Device
Internal Pull-Up (factory default)
CY8C20111/21
Disabled
CY8C201A0
Enabled
CY8C20110/80/60/40/42
Enabled


The setting for the internal pull-up resistors must match the requirements of the overall design. When the setting is incorrect, the following problems can occur:
 

  • Pull-ups should be sized correctly to meet rise time and IOL requirements in an I2C design. Use of internal pull-ups enabled in combination with external pull-ups in a CapSense® device reduces the effective resistance. Proper bus operation is not guaranteed.
  • Consider the scenario in which the CapSense device operates at 3.3 V with internal pull-ups enabled while the master operates at 1.8 V and external pull-ups pull the bus to 1.8 V. Bus voltage (VIH) seen by the master is between 1.8 V and 3.3 V due to the voltage divider formed by internal and external pull-ups. This condition can damage the master device.
     
In the above scenarios, it is recommended to DISABLE the internal pull-up resistor. This has to be done during the device configuration, before soldering it in the end system. To enable or disable the internal pull-up resistors, configure the I2CDM bit (MSB) in the I2C_ADDR_DM (7Ch) register. For more information, see CY8C201xx : Register Reference Guide.
]]>
Tue, 03 Jul 2012 02:15:44 -0600
CapSense Express Controller - CY8CMBR2016 http://www.cypress.com/?rID=57282 You can use any number of buttons from 1 to 16. Connect the unwanted sensors to ground to disable them. It is recommended to ground the last (16-n) buttons when you need only n buttons out of the available 16.

]]>
Wed, 13 Jun 2012 08:26:09 -0600
CapSense Express Controller - CY8CMBR2016 http://www.cypress.com/?rID=57283 Yes, the waveform to be sent over the scan line is defined in the device datasheet (~25us setup time) – if your design satisfies that, you can use the lines as such

]]>
Wed, 13 Jun 2012 08:24:50 -0600
CapSense Express Controller - CY8CMBR2016 http://www.cypress.com/?rID=57286 The auto reset function is used to prevent false triggers from stuck sensors – for example, if the sensor is turned ON due to the presence of some object on it or some voltage spikes in the system, auto reset will disable the sensor till the object is removed or helps recover the baseline from the spike impact. For more details on timings refer to the datasheet.

]]>
Wed, 13 Jun 2012 08:24:30 -0600
CapSense Express Controller - CY8CMBR2016 http://www.cypress.com/?rID=57285 No, anytime the overlay is changed, a hardware reset is required for the device to retune to the overlay changes.

]]>
Wed, 13 Jun 2012 08:23:34 -0600
CapSense Express Controller - CY8CMBR2016 http://www.cypress.com/?rID=57288 FMEA signal will be sent out on POR for manufacturing failure testing. Additionally, debug mode can help identify faulty sensors – refer to CY8CMBR2016 datasheet for details.]]> Wed, 13 Jun 2012 08:23:20 -0600 CY8C20xx7 device family supports water tolerance applications http://www.cypress.com/?rID=56355 Yes, the CY8C20xx7 device family supports shield electrodes on 5 ports pins. Each shield electrode can be enabled independently from other shield electrode. Maximum parasitic capacitance of shield electrode should be less than 100pF for a 3MHz sensor scan clock for the shield electrode to work perfectly. The shield electrode feature in CY8C20xx7 is ideal for implementing: 

  • Water tolerant buttons and sliders,  
  • Buttons and sliders in presence of metal objects and  
  • Proximity sensors. 
Additionally, the shield electrode implementation also supports a shield-tank capacitor, which can be used to limit the bandwidth of shield electrode to lower radiated noise from shield electrode.
]]>
Wed, 13 Jun 2012 08:22:51 -0600
CapSense Express Controller - CY8CMBR2016 http://www.cypress.com/?rID=57284 Multi touch is not supported and is automatically disabled for Truth table interface and Encoded Output interface – use Key Scan interface if multi touch is required.

]]>
Wed, 13 Jun 2012 08:22:17 -0600
Key features of CY8C20xx7 device family http://www.cypress.com/?rID=56357  

 Below are the key features of CY8C20xx7 device family
  • The CY8C20xx7 device family supports enhanced I2C slave interface that requires no clock stretching. The I2C block can also wake device up from sleep when there is an I2C address match event, which makes the device suitable for low power applications. 
  • CY8C20xx7 device family is an ultra low power device  which supports supply voltage from 1.71 to 5.5V with deep sleep current of 100nA. 
  • CY8C20xx7 family of device provides 40% improvement  in SNR performance which makes the device suitable for proximity sensing and support thicker overlays. 
  • Supports improved shield electrode enabling water tolerance, proximity sensing and button implementation in presence of metal objects applications
]]>
Wed, 13 Jun 2012 08:21:59 -0600
Smartsense tuning http://www.cypress.com/?rID=57554 Smart sense Auto Tuning calculates and sets the various parameters which are needed for proper functioning of the sensors.Out of these the following parameters are set during the bootup process i.e when the device is powered on or is reset using XRES:
-DAC compensation
-Prescalar
-Scanning speed
-Resolution

And the below parameters are set dynamically during every scan i.e to say intermittently:
-Finger threshold
-Noise threshold
-Hysterisis
-Negative noise threshold
-Baseline update threshold

]]>
Wed, 13 Jun 2012 08:21:24 -0600
Effect of Cmod value http://www.cypress.com/?rID=57885 The effect of Cmod is explained in the following two cases:

  1. If Cmod value is low, then high frequency noise will find a low impedance path to the ground via Cmod and will get coupled to the system very easily.
  2. If the value is too high, the voltage swing about Vref will be lesser as the capacitor will discharge lesser within the given discharge time. If this happens, the signal might get lost in the comparator noise itself as the signal strength (in terms of amplitude) is low.

Due to these reasons, an optimum value of Cmod is required. We have observed during characterization that the system performs quite well with a 2.2nF capacitor.

]]>
Wed, 13 Jun 2012 08:20:25 -0600
CY8C20xx7 device family support I2C transaction without clock stretching http://www.cypress.com/?rID=56356  

Yes, the CY8C20xx7 device family implements a 32 byte hardware data buffer, accessible as an I2C slave hence, transactions between the host and the buffer requires 
no clock stretching. This enhanced I2C block is available as the I2CSBUF user module in PSoC Designer SP3/4 and supports 50 KHz, 100 KHz and 400 KHz data transfer speed. Additionally, device can also wake up from sleep based on an I2C address match event. 
]]>
Wed, 13 Jun 2012 08:16:52 -0600
Reset mode current consumption http://www.cypress.com/?rID=57791 There is an internal 5.6k pull down (typical value) at the XRES pin, so if you hold that pin high, there would be around 1mA (considering 5V supply) current flowing through the XRES pin.

Thus, the reset mode current would be higher than the deep sleep current (0.10 uA typical).

]]>
Wed, 13 Jun 2012 08:12:55 -0600
Adhesive recommendations for CapSense overlays http://www.cypress.com/?rID=57788  

For CapSense applications, following are the basic two considerations while selecting an adhesive:

1. Since the dielectric constant of air is very low, an air gap between the overlay and sensor degrades the performance of the sensor. Thus, the adhesive should be used to properly stick the overlay with the PCB.

2. The adhesive must be nonconductive.

A transparent acrylic adhesive film from 3M™ called 200MP is qualified for use in CapSense applications. This special adhesive is dispensed from paper-backed tape rolls (3M™ product numbers 467MP and 468MP).

 

Refer "getting started with CapSense" design guide for CapSense design guidelines.

]]>
Wed, 13 Jun 2012 08:10:48 -0600
Using sleep mode with CY8C20xx6A http://www.cypress.com/?rID=57072 To achieve the standby current mentioned in the device datasheet ((Document Number: 001-54459 Rev. *G)), the following needs to be ensured:

1. None of the GPIOs is sourcing any current.

2. I2C_ON bit in the SLP_CFG2  and the USB_enable bit in USB_CR0 register is disabled.

3. The buzz rate is set to to 1/32768 using the ALT_Buzz bits of the SLP_CFG2 register.

4. The current is measured by putting the ammeter between supply and Vdd of pin i.e. the current measurement should not include any current other than device current.

Attached a code example that achieves the Isb1 current on the CY3280-20xx6A development kit.

 

]]>
Wed, 13 Jun 2012 08:09:30 -0600
Alternate pin for SPI slave clock pin in CY8C20xx6 http://www.cypress.com/?rID=62394 When using SPIS UM in CY8C20xx6 ,by default P1.3 is selected as the slave clock pin. There is an alternate option to use P1.0 as the slave clock by setting the Bit 2, SPICLK_ON_P10 in the register IO_CFG1. We need to change the pin configuration in the pinout window of the designer. Two things need to be done here:

1) Set properties of P1.0:

Name: SPISSCLK (here, the UM is named as SPIS. If it's named as SPIS_1, the name should be set as SPIS_1SCLK)

Select: StdCPU

Drive: Open Drain Low

Interrupt: DisableInt

AnalogMuxBus: Normal

InitialValue: 1

 

2) Change back the properties of P1.3 to its default values:

Name: Port_1_3

Select: StdCPU

Drive: High Z Analog

Interrupt: DisableInt

AnalogMuxBus: Normal

InitialValue: 0

 

Make sure to set the bit SPICLK_ON_P10 in the register IO_CFG1 before calling SPI_Start() API:

IO_CFG1 |= 0x04; 

]]>
Wed, 13 Jun 2012 08:08:27 -0600
CapSense Express Controller - CY8CMBR2016 http://www.cypress.com/?rID=57281 Yes, you can – refer to the CY8CMBR2016 Design Toolbox for recommended sizes/limits for your system

]]>
Wed, 13 Jun 2012 07:47:22 -0600
CapSense Express Controller - CY8CMBR2016 http://www.cypress.com/?rID=57280 Simple, just connect the last 4 sensors to ground, the device will disable the sensors and the output will be in 4x3 format. For more details – refer CY8CMBR2016 datasheet]]> Wed, 13 Jun 2012 07:46:03 -0600 CapSense Express Controller - CY8CMBR2016 http://www.cypress.com/?rID=57287 Higher sensitivity is needed for thicker overlay designs. Use the Design Toolbox for checking supported overlay thickness with a given sensitivity, button size, trace length and overlay type.]]> Wed, 13 Jun 2012 07:43:57 -0600 CY3280-SmartSense kit example project does not work from default location with Windows 7 and Windows Vista operating system http://www.cypress.com/?rID=47463 If the CY3280-SmartSense evaluation kit content is installed in a computer using installer, example projects are located in the default location “C:\Program Files\Cypress\CY3280-SmartSense\1.0\CY3280-SmartSense\Firmware”. If the example project is opened using PSoC Designer from the same location, it cannot be build and PSoC Designer 5.1 generates errors.

This is because Windows Vista and Windows 7 restrict access to 'Program Files' folders for OS security settings. To successfully build the project using PSoC Designer, the example project folder  "Firmware" should be copied to a location other than 'Program Files' in the computer to successfully build the project.

]]>
Tue, 13 Mar 2012 08:23:38 -0600
Configuring CapSense Express devices through PSoC Designer 5.1 http://www.cypress.com/?rID=46622 System level design is not supported in the latest versions of PSoC Designer 5.1 (PSoC Designer 5.1 onwards).

PSoC Designer 5.0 SP6 can be used to configure PSoC express devices since it supports system level design (which is a requirement for configuring PSoC Express Devices).

PSoC Designer 5.0 SP6 can be downloaded from our website through this link http://www.cypress.com/?rID=34517. Note that PSoC Designer 5.0 can co-exist with PSoC Designer 5.1. (It will co-exist with future releases of PSoC Designer also, because of system level design support).

]]>
Tue, 13 Mar 2012 08:20:43 -0600
Linear relationship between difference counts and Sensor Capacitance http://www.cypress.com/?rID=46414 The relation between CSD raw counts and sensor capacitance is as given below:

Raw_Count  = (Vdd/Vref - 1).Rb.fs.(2n - 1).C(Here,Vref is the comparator reference as selected in the user module configuration window in PSoC Designer, Rb is the bleed resistance used on the board, fs is the average switching frequency of sensors and depends on the CSD configuration used like PRS, prescalar etc. and "n" is the resolution as set in the user module configuration window).

If Cp is the sensor capacitance and Cf is the finger capacitance, the difference counts would be:

Diff_count = Raw_CountCp+Cf - Raw_CountCp

                   = ( Vdd/Vref - 1).Rb.fs.(2n - 1).Cf     

Note that the above relation holds true as long as the capacitance Cp+Cf does not lead to raw_counts being saturated and also assumes that the sensors are fully charged and discharged within the time 1/fs max. Thus, the linear relationship shown above does not hold true if Cp+Cf or Cpis so high that the sensors do not charge and discharge to Vdd and Vref respectively within the time 1/fs max. (If PRS is used as clock source, average switching frequency is fIMO/4 but maximum switching frequency is fIMO/2.).

]]>
Tue, 13 Mar 2012 08:17:08 -0600
Effect of series resistor on raw counts of the sensor http://www.cypress.com/?rID=46413 If FSW (the sensor modulation frequency or switching frequency) is selected such that CSENSOR is fully charged and discharged, then RSERIES values do not affect raw or difference counts of sensor measurements. In CapSense systems, series resistors are used to filter out EMI and reduce radiated emissions. Cypress recommends typical RSERIES values to be 560Ω.

For the sensors to fully charge and discharge to required voltages in every switching cycle, the period of the sensor modulation signal (1/FSW) should be greater than 10 * RSERIES * CSENSOR. So, if the RSERIES value gets so large that it start to filter out the sensor modulation signal enough so that the sensor is not fully charged by the modulation signal, the difference counts begin to decrease when the RSERIES value increases. Note that this is not a desired behaviour. If your sensors are not fully charging and discharging properly it is recommended to decrease the switching frequency by using prescalar configuration and putting proper prescalar value. (1/FSW>=  10 * RSENSOR*CSENSOR)

]]>
Tue, 13 Mar 2012 08:13:55 -0600
Maximum allowed noise in CapSense http://www.cypress.com/?rID=46410 Noise in the raw counts depends on many factors including board layout, external components, and external environmental noise. It is difficult to predict what would be the peak-peak noise in a system without actually monitoring it.

Noise in the system should be limited to below 50 counts to achieve a 5:1 SNR (5:1 SNR is the minimum requirement for any CapSense design). If a noise count is greater than 50 filtering techniques or layout changes need to be made.

Note: A properly designed system will have noise counts less than 20.
 

]]>
Tue, 13 Mar 2012 08:10:48 -0600
Accuracy of switching/precharge clocks used in CSD http://www.cypress.com/?rID=46409 Question: What is the accuracy of the switching/precharge clocks used in the CSD?

Response: The switching accuracy is dependent on the accuracy or tolerance of whatever clock is used as the source for the System Clock (SysClk). In typical applications, SysClk is derived from the Internal Main Oscillator (IMO) of the PSoC device. In the CSD application, all the blocks in the system have a clock source derived from SysClk. So, all clocks will have an accuracy that is the same as SysClk.

The IMO frequency tolerance over temperature and voltage can be seen in any PSoC device datasheet.

]]>
Tue, 13 Mar 2012 08:07:58 -0600
CY8C20X36A/46A/66A/96A: ISSUE WITH SHARING ISSP BUS http://www.cypress.com/?rID=45442 While in reset (XRES held high), if key “AC52” is pushed to ISSP bus CY8C20X36A/46A/66A/96A parts will enter into device test mode. In this mode internal regulator of the chip will be disabled and the core of the controller will be powered at a higher voltage than spec’d, thus damaging the device.

Avoiding/Solving this problem requires avoiding CY8C20X36A/46A/66A/96A chip from seeing the “AC52” key in reset condition, which in turn is possible if ISSP lines of CY8C20X36A/46A/66A/96A are not shared.

Note: Cypress do not recommend sharing ISSP bus of CY8C20X36A/46A/66A/96A parts with other PSoC devices

]]>
Tue, 13 Mar 2012 07:59:47 -0600
Drift in raw counts over a period of time http://www.cypress.com/?rID=39729 Raw counts is the function of capacitance of the sensor. So, as long as the capacitance remains constant over a period of time, i.e. environmental conditions like temperature, humidty etc. remain constant (so that the parasitic capacitance of sensor does not vary) over a period of time, the raw counts obtained from the sensor will not change as well.

]]>
Tue, 13 Mar 2012 07:48:33 -0600
ADC gives incorrect value when CapSense is enabled http://www.cypress.com/?rID=39720 While the CapSense is running, the precharge clocks will continuously charge and discharge the Cmod capacitor connected at Analog Mux Bus. Thus, the voltage across Cmod will create an offset for the input signal connected on analog mux bus. The signal which ADC see at its input will be the sum of input signal and the voltage across Cmod. Thus, it'll give the wrong values.

Workaround:

1. Stop the CapSense UM before measuring the analog signal using ADC.
2. Disconnect the Cmod from the bus. The below mentioned code snippet can be used for enabling and disabling the external connected capacitor.

backup_amux = AMUXCFG;
AMUXCFG &= 0xC0;   // Disable external cap

backup_clock = OSC_CR1; // Take the backup of VC1 and VC2 divider as it determines the resolution and scan speed of CSD
OSC_CR1 = 0x66; // Load the VC1 and VC2 divider with the desired column clock divider values


After completing the ADC measurement, restore AMUXCFG and OSC_CR1:

AMUXCFG = backup_amux;
OSC_CR1 = backup_clock;

]]>
Tue, 13 Mar 2012 07:42:33 -0600
Vih and Vil values when LDO enabled in CY8C20X66 http://www.cypress.com/?rID=37944 To avoid voltage compatibility issues, there  is a provision to reduce threshold voltage of input buffers. This can be done by setting bit P1_LOW_THRS (bit 3) in register IO_CFG1.
By setting this bit, Vil and Vih will be 1.366V and 1.476V respectively.
]]>
Tue, 13 Mar 2012 07:32:57 -0600
Capsense Power Consumption http://www.cypress.com/?rID=37701 For calculating the average power consumption we need to know value of some parameters like Sleep Current, Active Current, Sleep Time and Active Time. Knowing these values we can calculate the average power consumption for both CSA and CSD capacitve sensing methodoligies using the attached CapSense Power Consumption Calculator.

]]>
Tue, 13 Mar 2012 06:50:57 -0600
CY8C20xx7 family CapSense Controller does not provide on-chip debug (OCD) support http://www.cypress.com/?rID=58782  

CY8C20xx7 family of CapSense Controller does not support on-chip debug (OCD) feature unlike other CapSense controllers from Cypress.

CapSense system and other features supported by CY8C20xx7 family are also supported by CY8C20xx6A family of CapSense controllers, hence on-chip debug feature supported by CY8C20xx6A can be used for developments and debugging purpose.

]]>
Thu, 02 Feb 2012 00:27:07 -0600
Settling time http://www.cypress.com/?rID=57551  

Settling time:
Settling time is the amount of time given by the CSA user module for the voltage on Cmod to reach Vstart.  This is accomplished by connecting a current source to an equivalent resistor created by a switch capacitor network around the parasitic capacitance of the button.  There is an external capacitor used in CSA, often referred to as Cmod, which creates an RC filter with the equivalent resistor.  The proper settling time(minimum) is five time constants of this RC network.
 
 
So settling time,
                         Ts=5*Cmod/(Cp*Fcsa)
 
where Cp is the parasitic capacitance value,
      Fcsa is the clock frequency given to the csa module
 
So the settling time is inversely proportional to the parasitic capacitance.  For lower Cp the system requires higher settling times.  Conversely,for larger Cmods, the system also requires higher settling times. 
 
Settling time is also a function of the CapSense clock.   The higher the clock frequency, the smaller amount of settling time is needed.
 
In PSoC designer this can be adjusted by changing the settling time parameter of the user module.It is an 8bit value,and the possible values are 2 to 255.
The amount of delay introduced by this parameter(for the Cmod to reach Vstart)is given by,
 
                 Delay(us)=(6+21.(Settling time))/(CPU_SPEED MHz)
]]>
Mon, 16 Jan 2012 08:31:50 -0600
CapSense wake up on finger touch http://www.cypress.com/?rID=29397
PSoC CapSense uses the technique of continuous scanning (polling) the sliders and buttons for detecting finger touch. Therefore PSoC has to be awake to receive inputs from sliders or buttons and it is not possible generate an interrupt that can return PSoC from sleep mode. However the device can use the sleep timer to return from sleep mode. Following method can be used to reduce the current consumption:

Wake up from sleep on sleep timer interrupt >> scan the capsense sensors >> go to sleep again

To reduce the power consumption even further, instead of all the sensors, only one proximity sensor can be scanned such that the active time (time required to scan all sensors) is reduced. Note that the proximity sensor need not be an extra sensor on the layout, various buttons can be ganged together to form the proximity sensor as well.
 

Related resources:

1. Code examples

2. Power consumption calculation

3. Getting started with CapSense design guide

]]>
Sun, 01 Jan 2012 08:27:58 -0600
LED backlight support in capsense http://www.cypress.com/?rID=29398
CapSense works well with LED backlighting. A hole can be made in the sensor pad. LEDs are available in a surface mount package that are designed for backlighting (LED shines light on to board). LED traces should be kept to the bottom side of the board. If more than one LED is mounted behind each button, ensure that the active sensing area of the button has not been negatively impacted by multiple backlight holes punched out of the board.

 

Related resources:

1. Getting started design guide

2. Backlight fading code examples

]]>
Sun, 01 Jan 2012 08:13:53 -0600
Heat seal paper in Capsense http://www.cypress.com/?rID=29388 The heat seal paper can be used for connecting CapSense buttons since it is a conductor and should perform as well as the metal conductor. However, it may lead to more noise as it is thin and flexible.

]]>
Sun, 01 Jan 2012 08:02:10 -0600
Slow slider response http://www.cypress.com/?rID=29386 The CapSense slider requires the centroid function to be computed, and this calculation requires many operations to be processed by the CPU.  In order to get a fast response for the slider, a SysClk of 12MHz or faster needs to be used.  A 6MHz SysClk is not a good setting for a slider.

]]>
Sun, 01 Jan 2012 07:51:59 -0600
two rings surrounding thermal pad of CY8C20434-12LKXI (32 QFN) http://www.cypress.com/?rID=28179 Yes, they can all be connected. In fact, they are connected internally. The reason Amkor, our package supplier, makes them that way is for bonding and stress relief purposes.

]]>
Sun, 01 Jan 2012 07:13:44 -0600
UART Communication on CY8C20436 http://www.cypress.com/?rID=44852 The CY8C20xx6 devices do not support UART functionality. However, a bit banging based software user module i.e. TX8SW is available for transmitting the data.  Reciever module is NOT available.

If a full duplex UART functionality is needed along with CapSense, the following devices could be used:

1. CY8C21x34, CY8C21x34B or CY8C24x94: Here, CSDADC can be used for CapSense functionality (PRS8 configuration using two digital blocks) along with the UART user module. Note that these devices use Rb method instead of IDAC method and hence, an external Rb would be required in both the cases.

2. CY8C22x45 or CY8C28xxx: These devices have larger number of digital blocks and hence can support UART with CapSense. Also, these suppport both Rb and IDAC methods and also support dual channel CapSense which means two buttons can be scanned simultaneously with these devices.

3. PSoC3/5: These have universal digital blocks which could be used for UART along with CapSense. These also suppport both Rb and IDAC methods and dual channel CapSense as 22x45/28xxx.

]]>
Wed, 28 Dec 2011 04:52:22 -0600
Waking up CY8C20xx6 using the I2C hardware address http://www.cypress.com/?rID=43292 Step1: Configure I2C block to work in sleep mode (SLP_CFG2 |= 0x02)

Step2: Enable I2C block interrupt (INT_MSK0 | = 0x80)

Step3: Enable I2C hardware address matching feature, this is done by replacing assembly instruction "mov reg[I2C_XCFG], 0" with "mov reg[I2C_XCFG], 0x01" in EzI2Cs_Start() API. API can be found in EzI2Cs.asm file.

Step4: Set I2C hardware address in register I2C_ADDR. Set address should be same as the "Slave_Addr" parameter of EzI2C UM

Note: Above modifications are to be made on top of a working EzI2C UM configuration/code in PD5 SP6 (or earlier). Step3 can be skipped if “EzI2Cs.asm” template file residing in the location “C:\Program Files\Cypress\Common\CypressSemiDeviceEditor\Data\CY8C20060\EzI2Cs” is replaced with the one attached with this KB article (before replacing make sure that PSoC designer version is of PD5SP6 if not follow Step3 above)

Sleep Entry/Exit:

Following procedure need to be followed every time for putting /waking-up device to/from sleep,

Step1:  Call M8C_Sleep Macro; Device entry to sleep should be directly under the control of I2C Master.  

Step2:  Master can wake-up the device from sleep by sending a read instruction targeted to the device.

Step3:  Data contained in the above wake-up I2C read instruction should be discarded by I2C master.

]]>
Wed, 28 Dec 2011 04:40:08 -0600
Air Gap between Capsense Sensor and an Overlay http://www.cypress.com/?rID=43938 Capsense is not recommended to have any air gap between Capactitve Sensor PCB and an Overlay material.

If the requirement demands an air gap, you may connect a spring between the capsense button and the overlay, this should enable to detect it as a button with better sensitivity.

You may also refer an application note "
Using Springs as CapSense Sensors AN44999"

This application note considers the possibility of using springs as sensors. A comparison with solid conductive sensors and recommendations for the practical usage of springs are also discussed.

]]>
Wed, 07 Dec 2011 03:12:02 -0600
Programming tool for Capsense Express device - CY8C201xx http://www.cypress.com/?rID=46338 At present, the following vendors offer programming tools support programming the configuration file into a CapSense Express device, which uses an I2C interface: 

- BP Microsystems
http://www.bpmicro.com
Programmer Model 1400 and 1700
Running BP WIN Software Revision V4.64.0 or V4.66.1

- HiLo
http://www.hilosystems.com.tw/
Programmer Model All 100
Running S/W v1.59

- RPM Systems
www.rpmsys.com
Programmer Model: MPQ 4 Port Programmer, MPQ-E2 4 Port Programmer
Running S/W Rev 1.11.1 (Firmware 2.14)

The AN53490 describes Design to Production of Capsense express in detail.

]]>
Wed, 30 Nov 2011 00:19:18 -0600
Export data option doesn't work in CapSense Express Tuner http://www.cypress.com/?rID=55706 Microsoft Report tool needs to be installed for the 'Export data' option to work.

Follow the below steps to install it :

Download Microsoft Report tool from:
http://www.microsoft.com/download/en/details.aspx?displaylang=en&id=21916#Instructions

1. Close PSoC Designer

2. Install Microsoft Report tool

3. Open PSoC Designer project

4. Observe defect is not reproduced

]]>
Wed, 09 Nov 2011 23:11:34 -0600
CapSense sensor scan time mentioned in CSD2X user module datasheet does not match with measurement from hardware http://www.cypress.com/?rID=55645  

Scanning Time vs Scanning Speed and Resolution information is present in the CSD2X user module datasheet (001-50243 revision *E) is incorrect. Please refer to the latest CSD2X user module datasheet (001-50243 revision *F) for correct information.

The updated CSD2X user module datasheet (001-50243 revision *F) can be downloaded from http://www.cypress.com/?rID=36673 and same will be available in PSoC Designer 5.2 (next release of PSoC Designer)

]]>
Thu, 03 Nov 2011 07:35:15 -0600
Moisture Sensitivity Level (MSL) of Cypress Parts http://www.cypress.com/?rID=54061 If you know the Cypress part number: 

1. Go to www.cypress.com.  On the top right, you will see a “Keyword / Part Number” search box (adjacent to “Contact Us.”) 

2. Select the “Part Number” tab above this text box.

3. Type the exact part number, for example CY8C29466-12PVXE.

4. The part number will be listed in the search results page.

5. Click on the part number link (1st column starting from the left). This will open a new web page.

Moisture Sensitivity Level (MSL) can be found by clicking the “Quality & Pb-free Data” link on the top, or by just scrolling down to the Quality & Pb-free Data” section about half way down the page.

All other Quality information for this part number (e.g., RoHS compliance, Lead/Ball Finish, Qualification Reports, IPC reports) can also be found on this web page. 

In case of any questions, or if the information is not available for a particular part number, please create a support case at www.cypress.com/support

If you do not know the Cypress part number: 

1. Go to www.cypress.com.  Browse the different products (“Products” tab on the top navigation menu) by family.

2. Once you choose the relevant product family (e.g., “Clocks and Buffers->Clock Distribution,” “Memory->FIFOs”), scroll down the particular page to get to the “Parametric Product Selector.”

3. Use this tool to find the part number by function/feature, and click on the part number you are interested in. This will lead you directly to step # 5 above.

]]>
Thu, 08 Sep 2011 21:22:46 -0600
MiniProg3 can't program my device in XRES mode http://www.cypress.com/?rID=47504 XRES mode requires that the board is powered prior to starting the program. When MinProg3 is used to program a board in XRES mode, it first checks for the power at the pin connected to the Vtarg pin of theMiniProg. If that pin is not powered, it does not acquire the device.

If you are trying to program CY3280-20xx6 kit using MiniProg3 and external power, even though the device (Vcc) gets powered from the external supply, the Vcc_prog pin at the ISSP header of the board is not powered. Thus, MiniProg3 does not detect power and hence does not acquire the device. In order that the device is programmed, make sure to Vcc_prog pin is connected to the Vcc pin using an external wire.

Note that the MiniProg1 does not do a power detect check and hence tries to program even if the Vdd pin of the MiniProg1 is not powered externally.

]]>
Fri, 05 Aug 2011 01:04:57 -0600
Routing 32 KHz ILO output to pin in CY8C20xx6A http://www.cypress.com/?rID=46376 CY8C20xx6A family of devices doesn't allow routing of digital signals to output pins due to the unavailability of digital interconnects. However, you can write to registers for routing the 32kHz clock to pins. OUT_P1 register is used to route the internal 32K clock to P1[6]. OUT_P0 register can be used to route the internal 32K clock to P0[4] but this output will not be available in sleep mode. Remember that you have to change the drive mode of these pins to strong. Please refer to Technical reference manual to know more about these registers.

]]>
Sun, 26 Jun 2011 11:25:50 -0600
Upgrading CapSense projects to PSoC Designer5.0 SP5.0 or higher http://www.cypress.com/?rID=39410 There was a bug in PD5.0 SP4 & SP4.5. Upon reopening and generating/building a CY8C20x34, CY8C20x46, or CY8C20x66 project, the generated code disables any connections to the Analog Mux Bus shown in the chip level view.

If you had made any manual connections of pins to the Analog mux bus in the chip level view of the project (in SP4 or SP4.5), then these connections were not implemented in the generated code. Hence, the functionality of CSD user module was not affected.

When you upgraded to SP5.0 or higher version of PD5.0 where the bug is fixed, it actually implemented the manual connections of pins to the Analog mux bus (by setting MUX_CRx registers properly), which you had done in chip level view before. These undesired connections caused the improper functionality of CSD user module in SP5.0 (or higher).

Solution: Go to the chip level view of project & break the connections of the pins to Analog mux bus which you had done manually. If your project has CSD & any other user module which needs Analog mux bus for its operation (such as ADCINC user module), then in firmware of the project write the code in such a way that Analog mux bus is used by them in time division multiplexed form. Example: For ADCINC user module, If you want to convert the analog voltage level on port pin P0[0] to digital form, then before starting the A-D conversion, connect P0[0] pin to the Analog mux bus by setting bit-0 of MUX_CR0 register. After the conversion is completed, break this connection by clearing the bit-0 of MUX_CR0 & then assert the CSD scanning process.

]]>
Sun, 26 Jun 2011 10:29:34 -0600
Ok and Cancel Options missing from CSD wizard http://www.cypress.com/?rID=38972 This may happen under certain screen resolutions, when the resolution is less than the optimum. Changing the resolution to an optimum range specific to the size of monitor used will solve this problem. Therefore change the resolution of the screen and check if this solves the problem.  The ideal resolution is 1280 x 800 pixels.

]]>
Sun, 19 Jun 2011 14:29:35 -0600
Bringing out Shield Electrode in System Level Design for Capsense CSD http://www.cypress.com/?rID=38060 Shield electrode option is not available in System level Design of PSoC Designer. The shield electrode option can be set in the System level design, by switching to chip view from the system level view. Please follow the below steps to enable shied electrode option in system level design.

1. Build the project in system level design.
2. In the Workspace Explorer window, double click on Projectname[Chip]. This will change the view from system level to chip level.
3. In Project->Settings->Chip Editor tab, uncheck the "Lock automatically generated system resources"  box.
4. In Project explorer, expand Projectname[Chip].
5. Expand Projectname - x User Modules [System Editor Generated]
6. Click on CSD. You can view the CSD properties on the Properties - CSD windows on the left side.
7. Select the required Row Output in the "ShiedElectrodeOut" option in the CSD properties window.
8. Click on the blue square box on the end of the Row Output bus and connect the Row Output bus to a Global Output bus.
9. Click on the Global Output bus and select a pin.
10. Now the shield electrode is connected to an external pin.
11. Build the project by clicking on the "Build" button or by pressing F7 or by selecting the Build Project option from the Build menu. Do not use Generate Project menu as this will regenerate the device editor configuration and will overwrite the modifications done to bring out the shield electrode.  So, enable the shield electrode as the last step in the development process after finalizing everything else in the design.

Note: PSoC Designer 5.0 Service Pack 6 is the last release of PSoC Designer that supports System-Level Design (PSoC Express). PSoC Designer 5.1 and beyond will not support System Level Design. PSoC Designer 5.0 SP6 will continue to be available for System Level Design users, and it will co-exist with future PSoC Designer releases. However, we are not recommending System Level Design for production designs.

]]>
Sun, 19 Jun 2011 14:19:05 -0600
Upgrading CapSense projects to PSoC Designer5.0 SP5.0 or higher http://www.cypress.com/?rID=39411 There was a bug in PD5.0 SP4 & SP4.5. Upon reopening and generating/building a CY8C20x34, CY8C20x46, or CY8C20x66 project, the generated code disables any connections to the Analog Mux Bus shown in the chip level view.

If you had made any manual connections of pins to the Analog mux bus in the chip level view of the project (in SP4 or SP4.5), then these connections were not implemented in the generated code. Hence, the functionality of CSD user module was not affected.

When you upgraded to SP5.0 or higher version of PD5.0 where the bug is fixed, it actually implemented the manual connections of pins to the Analog mux bus (by setting MUX_CRx registers properly), which you had done in chip level view before. These undesired connections caused the improper functionality of CSD user module in SP5.0 (or higher).

To fix this, go to the chip level view of project & break the connections of the pins to Analog mux bus which you had done manually. If your project has CSD & any other user module which needs Analog mux bus for its operation (such as ADCINC user module), then in firmware of the project write the code in such a way that Analog mux bus is used by them in time division multiplexed form. Example: For ADCINC user module, If you want to convert the analog voltage level on port pin P0[0] to digital form, then before starting the A-D conversion, connect P0[0] pin to the Analog mux bus by setting bit-0 of MUX_CR0 register. After the conversion is completed, break this connection by clearing the bit-0 of MUX_CR0 & then assert the CSD scanning process.

]]>
Sun, 19 Jun 2011 11:32:04 -0600
Minimum Supply Voltage to PSoC 1 http://www.cypress.com/?rID=34108 The following part families can work on a minimum supply voltage of 2.4 V:

  • CY8C24x23A
  • CY8C22x13A
  • CY8C21x23
  • CY8C21x34
  • CY8C20x34

The following part families can work on a minimum supply voltage of 3 V:

  • CY8C24x94
  • CY8C29X66
  • CY8C27X43
  • CY8C22x45
  • CY8C28xxx

CY8C20xx6A can work on a minimum supply voltage of 1.71 V.

Note: CY8C21x34 devices need a minimum voltage of 2.5V during POR.

]]>
Wed, 15 Jun 2011 03:43:33 -0600
Minimum PWM frequency in System level design http://www.cypress.com/?rID=48408 PWM in System level design should use a frequency greater than 100kHz.  Any frequency below that has no effect on the output.  This is a software limitation of PSoC Express/ System Level Design.

Important note:

Beginning with PSoC Designer 5.0, service pack 6, we are de-emphasizing System-Level Design (PSoC Express). PSoC Designer 5.1 onwards, System Level Design has been completely removed. While no functionality of system level design has been removed from release in 5.0 SP6, we recommend using Chip-Level Design (PSoC Designer style). We are not recommending System Level Design for production designs (except for CapSense Express). There will be continued support for CapSense Express in a service pack of PSoC Designer 5.1. Inconvenience is regretted.
]]>
Mon, 13 Jun 2011 01:23:22 -0600
CSD Parasitic Capacitance Calculator http://www.cypress.com/?rID=42720 Please find the excel sheet attached which calculates Parasitic Capacitance of your sensor. You are required to flash your CY8C21x34 project on your device and input the Resolution, SysClk, Rb, Ref Value and the Sensor RawCounts values in the excel sheet to get the parasitic capacitance of the sensor.

Note: This is just for reference and gives the approximate parasitic capacitance. Parasitic capacitance varies with temperature, overlay, humidity and device.

]]>
Mon, 13 Jun 2011 00:51:05 -0600
I2C clock frequency of CapSense Exress device http://www.cypress.com/?rID=39723 I2C slave in CapSense Express devices is configured at 400KHz but as per the I2C spec, the I2C bus works at the speed of the slowest device on the bus. So, if the master is sending data at a rate of 50KHz or 100KHz then the CapSense express I2C will work at a rate of 50KHz or 100Khz only.

]]>
Fri, 01 Apr 2011 04:37:21 -0600
User defined area in CapSense Express device http://www.cypress.com/?rID=39718 In CapSense Express devices, there is no memory space available for user which can be used for storing the data like firmware version etc.

]]>
Fri, 01 Apr 2011 04:35:00 -0600
Can slider segments be used as capsense buttons? http://www.cypress.com/?rID=28916 Yes, you can use all segments as different switches. But while doing so, please take care that the pin assignment should be according the actual hardware which has been implemented on first touch kit. Please find one code example in which first, middle and last segment have been configured as three different switches.

]]>
Mon, 28 Mar 2011 12:19:51 -0600