White Papers - Cypress.com http://www.cypress.com/?app=search&searchType=advanced&keyword%3D%26rtID%3D115%26id%3D2%26applicationID%3D0%26l%3D0 An Introduction to CY8C22x45 http://www.cypress.com/?rID=37730

This whitepaper is a brief introduction to CY8C22x45, an enhanced product of CY8C21xxx PSoC® family.

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Mon, 22 Oct 2012 02:04:44 -0600
Noise Wars: Projected Capacitance Strikes Back http://www.cypress.com/?rID=68748 Touchscreen performance in the presence of noise is one of the major obstacles facing mobile electronics device designers today. This article will discuss the two major sources of noise, display noise and charger noise. It will discuss design techniques and available solutions that can be used to overcome these challenges.

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Wed, 05 Sep 2012 03:07:58 -0600
nvSRAM as Write Journal in RAID Storage Systems http://www.cypress.com/?rID=38194 RAID Storage Systems Overview

RAID was first described by Garth Gibson, Randy Katz, and Dave Patterson of UC Berkeley in the late 1980s as a 'Redundant Array of Inexpensive Disks'. It has now become a blanket term for data storage schemes that implement redundancy and parallelism for better fault tolerance and input/output (I/O) performance than a single disk drive or 'Just a Bunch Of Disks' (JBOD). RAID commonly represents a system consisting of many storage disks that are accessed by servers through high speed Ethernet or Fiber Channel media. Disk drive I/O speed is the primary performance bottleneck in most storage systems. Generally, RAID Systems use parallel disk access and cache memories to increase the read and write performance, while using redundant disks for failure recovery to enhance fault tolerance.

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Wed, 27 Jun 2012 04:41:31 -0600
Power Supply Noise and Clock Generator http://www.cypress.com/?rID=37763 The power supply noise affects the clock noise performance. Through this White paper you will learn the various sources that cause power supply noise. You will also learn various techniques to measure power supply noise and methods to improve system performance by cleaning up the noise at the source. ]]> Fri, 08 Jun 2012 03:28:35 -0600 Non-volatile SRAMs (nvSRAMs) in Gaming Applications http://www.cypress.com/?rID=62891 Cypress’s nonvolatile static RAM (nvSRAM) technology offers a combination of fast access speed SRAM interface and reliable non-volatility.

Gaming machines use SRAM memory solutions to record multiple gaming data and to hold the data in case of power failure or power outages. This white paper describes the ideal suitability of Cypress nvSRAM solutions in these applications.
 

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Tue, 08 May 2012 04:14:13 -0600
Implementing Accurate Peak Detection http://www.cypress.com/?rID=61521 Thu, 05 Apr 2012 14:16:13 -0600 Introduction to DMA http://www.cypress.com/?rID=61520 Thu, 05 Apr 2012 14:15:26 -0600 Reducing CPU Loading through Data Buffering of ADCs Using DMA http://www.cypress.com/?rID=61519 Thu, 05 Apr 2012 14:14:47 -0600 Calibrating the Analog Signal Chain http://www.cypress.com/?rID=61518 Thu, 05 Apr 2012 14:13:50 -0600 Getting More Resolution from 8-bit DACs http://www.cypress.com/?rID=61517 Thu, 05 Apr 2012 14:12:52 -0600 Rise Above the Noise - TrueTouch Gen 4 White Paper http://www.cypress.com/?rID=61033 Wed, 28 Mar 2012 23:54:15 -0600 Using Cypress nvSRAM as Program Memory http://www.cypress.com/?rID=60138 Introduction

Because of the increasing speed of CPUs, parallel NOR Flash devices often are too slow to “execute in place” (XIP) program code stored in them. However, SRAMs offer access times below 10 ns. As a result, you often must “shadow” code stored in Flash into the RAM; that is, code must be copied from Flash into RAM before execution, so that the CPU may access it at full speed. In compact board designs where PCB form factor is fixed, the two-chip solution becomes difficult to implement because it requires additional board area. The two-chip solution also requires a special bootup subroutine as the system has to configure the memory controllers first, followed by the rest of the bootup sequence, after program code is copied to the SRAM from the Flash memory. Cypress nvSRAM offers a simple and compact solution because it combines high-speed random access with non-volatility in a single chip.

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Tue, 06 Mar 2012 23:57:00 -0600
Crystal Parameters Recommendation for Cypress Frequency Synthesizers http://www.cypress.com/?rID=12862 Introduction

A PLL-based frequency synthesizer uses a reference input to generate output clocks. The reference can be provided by a quartz crystal or an external clock source. The accuracy and stability of the output clock is directly proportional to that of the reference. Thus, it is important to provide a stable, accurate, and appropriate reference input.

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Wed, 18 Jan 2012 06:25:16 -0600
Specific Features of CY22388,CY22389,CY22391 http://www.cypress.com/?rID=12597 Introduction

CY22388/89/91 device family is part of the Cypress programmable clock generators. It is a quad PLL clock generator with complete voltage-control crystal oscillator (VCXO) solution with +/- 120 ppm. It is best suited for consumer applications and meets most of the application requirement for digital setup box, DVD recorder, and DTV. Industries leading consumer companies, such as Sony, Funai, and Hitachi have designed using this device.

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Wed, 18 Jan 2012 06:22:14 -0600
Timing Uncertainty in High Performance Clock Distribution http://www.cypress.com/?rID=49040 Several factors contribute to the timing uncertainty when using fanout buffers to distribute a clock to synchronize various devices within a system. For non-PLL clock fanout buffers, output skew, propagation delay, and edge rates play a critical role in determining system timing margin. This White Paper briefly discusses these parameters and their effect on system performance.

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Mon, 16 Jan 2012 03:07:38 -0600
Additive Phase Jitter in High Performance Clock Distribution http://www.cypress.com/?rID=12861 One of the critical parameters in high-end clock distribution is an additive phase jitter. This document outlines what additive phase jitter is and why it is important to consider while selecting devices for the clock signal fanout in a system. A sample additive phase jitter measurement of the Cypress High-Performance Buffer product is also described

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Wed, 23 Nov 2011 03:15:27 -0600
nvSRAM in Portable Ultrasound Scanners http://www.cypress.com/?rID=54063 Medical sonography (Ultrasonography) is an ultrasound-based diagnostic medical imaging technique used to visualize muscles, tendons, and other internal organs for their size, structure, and any pathological lesions with real time images.

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Fri, 09 Sep 2011 01:22:43 -0600
Terminating RoboClock II™ Output http://www.cypress.com/?rID=12856 This document describes the methods available for terminating the output for the RoboClock II family of products. It also weighs the benefits of each method.

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Tue, 23 Aug 2011 07:06:31 -0600
Datasheet Jitter Specifications for Cypress Timing Products http://www.cypress.com/?rID=12791 This document serves to outline the most common types of jitter along with clear definitions of each type and how it is specified in Cypress clock product datasheets.

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Tue, 23 Aug 2011 07:00:38 -0600
EMI and Spread Spectrum Technology http://www.cypress.com/?rID=12782 EMI reduction can be achieved using Spread spectrum technique. Spread spectrum technology is discussed in detail and examples of SST supporting devices are included. Application diagram of hard disk drive using SST is discussed. This white paper describes about Electronic Magnetic Interference (EMI) and different EMI suppression techniques.

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Tue, 23 Aug 2011 06:48:21 -0600
RoboClock™ and RoboClock II™ Test Mode http://www.cypress.com/?rID=49041 This document discusses the test mode capabilities of the RoboClock™ and RoboClock II™ family. It begins with an introduction to these devices and then discusses how to use the test mode features. The RoboClock II test mode disables the PLL, which allows you to debug your system design. Using the test mode function can improve your design and give you additional stability.

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Tue, 23 Aug 2011 06:43:10 -0600
SRAM System Design Guidelines http://www.cypress.com/?rID=12894 The guidelines in this white paper, although not mandatory, will lead to excellent long-term system performance if properly implemented. Moreover, they are simply smart electrical engineering practices. The topics covered in this white paper are decoupling capacitors, printed circuit board (PCB) issues, and terminations.

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Wed, 10 Aug 2011 06:19:44 -0600
Cypress SONOS Technology http://www.cypress.com/?rID=2937 Tue, 12 Jul 2011 08:22:18 -0600 Cypress' CapSense Sigma-Delta Algorithm http://www.cypress.com/?rID=2934 CapSense Sigma Delta algorithm (CSD) is Cypress' latest capacitive sensing algorithm for the CY8C21x34 and CY8C24x94 PSoC(R) device family.

CSD enables the implementation of an array of capacitive sensors through switched capacitor circuitry, an analog multiplexer, digital counting, and PWM functions.

The hardware configuration works in conjunction with high level software routines from the CSD User Module found in PSoC Designer(TM) to compensate for environmental and physical sensor variations

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Tue, 10 May 2011 22:48:16 -0600
FleXO(TM): Bridging the Cost/Performance Gap in the Oscillator Market http://www.cypress.com/?rID=46308 This paper compares Cypress' FleXO oscillator with the other main types of oscillators. It discusses the advantages, disadvantages, and typical applications of each type.

FleXO offers several key benefits over other common types of timing solutions. FleXO's primarily targets telecommunications and networking applications. It provides superior flexibility, cost, and lead time compared to alternative solutions while still offering excellent frequency stability and low phase noise, giving the customer an ideal balance of performance, cost, and flexibility.

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Tue, 15 Feb 2011 09:51:06 -0600
QDR SRAM and RLDRAM: A Comparative Analysis http://www.cypress.com/?rID=14675 Today's high-speed networking applications require high-bandwidth and high-density memory solutions. For instance, typical networking line cards need memories for a variety of operations that include packet buffering, table lookup, and queue management among a host of other functions. Choosing the right memory solution is pivotal to ensuring that the memory bandwidth does not become a bottleneck on the throughput of the application. This white paper discusses memory solutions suitable for networking applications-specifically, Quad Data Rate Static RAM (QDR SRAMs) and Reduced Latency Dynamic RAM (RLDRAM)-and compares them in relation to the applications they are best suited for. To read more about this article, click the download link or go to Network Systems DesignLine.

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Tue, 02 Nov 2010 05:20:33 -0600
Anti-Tamper Memory http://www.cypress.com/?rID=43212

Cypress’s anti-tamper memory, based on nonvolatile static RAM (nvSRAM) technology, has unique features that protect SRAM and nonvolatile data from accidental or malicious intrusion. It also provides the fastest nvSRAM function.

This white paper describes the tamper protect features implemented in the Cypress anti-tamper memory such as password protection, data destruction, functional destruction, and physical destruction. It is also possible to customize a combination of these data destruct features to suit application requirements.

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Fri, 11 Jun 2010 04:44:09 -0600
HOTLink Multi-byte Framer White Paper http://www.cypress.com/?rID=14670 Cypress's entire line of HOTLink(R) backplane physical layer (PHY) devices implement a unique function called multi-byte framing.  This feature helps HOTLink PHYs protect against false framing in a non-standards-compliant system where there is a possibility that bits can be flipped during transmission. This white paper describes how byte flipping due to noise can affect byte framing in a SERDES and how multi-byte framing can help mitigate this.

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Wed, 07 Apr 2010 13:50:31 -0600
Spread Spectrum Clock Generators for solving EMI http://www.cypress.com/?rID=14672 Benefits of Lexmark Modulation Waveform

The advantages of Lexmark's modulation waveform for EMI attenuation derive from its unique, patented shape, one embodiment of which is shown in Figure 1. In addition to the shape shown in Figure 1, other waveforms are covered by Lexmark patents (such as the triangular, or linear, waveform). A less efficient ‘sharkfin', or exponential, waveform as seen in Figure 2 is sometimes used.

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Wed, 25 Mar 2009 02:19:02 -0600
Interfacing the QDR(TM) to the XILINX SPARTAN-II FPGA http://www.cypress.com/?rID=14673 http://www.xilinx.com/products/xaw/qdr/qdrcode.htm. The customer tutorial and the white paper for the memory controller is available at http://www.xilinx.com/products/xaw/qdr.  ]]> Thu, 13 Nov 2008 00:00:00 -0600 NoBL(TM), The ZBT(TM) - Compatible Family http://www.cypress.com/?rID=14674 Thu, 13 Nov 2008 00:00:00 -0600