Features

• Powerful Harvard Architecture Processor
• Flexible On-Chip Memory
• Complete Development Tools
• Precision, Programmable Clocking
• Programmable Pin Configurations
• Additional System Resources
• For more, see pdf
   

Functional Overview

The enCoRe V LV family of devices are designed to replace multiple traditional low voltage microcontroller system components with one, low cost single chip programmable component. Communication peripherals (I2C/SPI), a fast CPU, Flash program memory, SRAM data memory, and configurable I/O are included in a range of convenient pinouts.

Features

• 256-Kbit nonvolatile static random access memory (nvSRAM)
  • Internally organized as 32 K × 8
  • STORE to QuantumTrap nonvolatile elements initiated automatically on power-down (AutoStore) or by using I2C command (Software STORE) or HSB pin (Hardware STORE)
  • RECALL to SRAM initiated on power-up (Power-Up RECALL) or by I²C command (Software RECALL)
  • Automatic STORE on power-down with a small capacitor (except for CY14MX256J1)
• High reliability
  • Infinite read, write, and RECALL cycles
  • 1 million STORE cycles to QuantumTrap
  • Data retention: 20 years at 85°C
• For more, see pdf

Overview

The Cypress CY14MC256J/CY14MB256J/CY14ME256J combines a 256-Kbit nvSRAM with a nonvolatile element in each memory cell. The memory is organized as 32 K words of 8 bits each. The embedded nonvolatile elements incorporate the QuantumTrap technology, creating the world’s most reliable nonvolatile memory. The SRAM provides infinite read and write cycles, while the QuantumTrap cells provide highly reliable nonvolatile storage of data.

Features

• Radio System-on-Chip, with built-in 8-bit MCU in a single device.
• Operates in the unlicensed worldwide Industrial, Scientific, and Medical (ISM) band (2.400 GHz to 2.483 GHz).
• On Air compatible with second generation radio WirelessUSB™ LP and PRoC LP.
• Pin-to-pin compatible with PRoC LP except the Pin31 and Pin37. 

Intelligent

• M8C based 8-bit CPU, optimized for human interface devices (HID) applications
• 256 bytes of SRAM
• 8 Kbytes of flash memory with EEPROM emulation
• In-System reprogrammable through D+/D– pins
• CPU speed up to 12 MHz
• For more, see pdf

Functional Description

PRoC LPstar devices are integrated radio and microcontroller functions in the same package to provide a dual role single-chip solution.

Communication between the microcontroller and the radio is via the SPI interface between both functions.

High Integration Device Replaces Multiple Parts

• Serial Nonvolatile Memory
• Real-time Clock (RTC)
• Low Voltage Reset
• Watchdog Timer
• Early Power-Fail Warning/NMI
• Two 16-bit Event Counters
• Serial Number with Write-lock for Security
• For more, see pdf.

Description

The FM31xx is a family of integrated devices that includes the most commonly needed functions for processor-based systems. Major features include nonvolatile memory available in various sizes, real-time clock, low-VDD reset, watchdog timer, nonvolatile event counter, lockable 64-bit serial number area, and general purpose comparator that can be used for an early power-fail (NMI) interruptor other purpose. The family operates from 2.7 to 5.5V.

Features

• Supports bus operation up to 200 MHz
• Available speed grades are 200 and 167 MHz
• Registered inputs and outputs for pipelined operation
• 3.3 V core power supply
• 2.5 V/3.3 V I/O operation
• Fast clock-to-output times
  • 3.0 ns (for 200 MHz device)
• Provide high performance 3-1-1-1 access rate
• User selectable burst counter supporting Intel® Pentium® interleaved or linear burst sequences
• For more, see pdf
   

Functional Description

The CY7C1480V33 SRAM integrates 2 M × 36 SRAM cells with advanced synchronous peripheral circuitry and a two-bit counter for internal burst operation. All synchronous inputs are gated by registers controlled by a positive-edge-triggered Clock Input (CLK).

Features

• 256-Kbit nonvolatile static random access memory (nvSRAM)
  • Internally organized as 32 K × 8
  • STORE to QuantumTrap nonvolatile elements initiated automatically on power-down (AutoStore) or by using I²C command (Software STORE) or HSB pin (Hardware STORE)
  • RECALL to SRAM initiated on power-up (Power-Up RECALL) or by I²C command (Software RECALL)
  • Automatic STORE on power-down with a small capacitor
• High reliability
  • Infinite read, write, and RECALL cycles
  • 1 million STORE cycles to QuantumTrap
  • Data retention: 20 years at 85 °C
• For more, see pdf

Overview

The Cypress CY14C256I/CY14B256I/CY14E256I combines a 256-Kbit nvSRAM with a full-featured RTC in a monolithic integrated circuit with serial I2C interface. The memory is organized as 64 K words of 8 bits each. The embedded nonvolatile elements incorporate the QuantumTrap technology, creating the world’s most reliable nonvolatile memory. The SRAM provides infinite read and write cycles, while the QuantumTrap cells provide highly reliable nonvolatile storage of data. Data transfers from SRAM to the nonvolatile elements (STORE operation) takes place automatically at power-down. On power-up, data is restored to the SRAM from the nonvolatile memory (RECALL operation). The STORE and RECALL operations can also be initiated by the user through I2C commands.

Features

• 1-Mbit nonvolatile static random access memory (nvSRAM)
  • Internally organized as 128 K × 8
  • STORE to QuantumTrap nonvolatile elements initiated automatically on power-down (AutoStore) or by using I²C command (Software STORE) or HSB pin (Hardware STORE)
  • RECALL to SRAM initiated on power-up (Power-Up RECALL) or by I²C command (Software RECALL)
  • Automatic STORE on power-down with a small capacitor (except for CY14X101J1)
• High reliability
  • Infinite read, write, and RECALL cycles
  • 1 million STORE cycles to QuantumTrap
  • Data retention: 20 years at 85 °C
• For more, see pdf
   

Overview

The Cypress CY14C101J/CY14B101J/CY14E101J combines a 1-Mbit nvSRAM with a nonvolatile element in each memory cell. The memory is organized as 128 K words of 8 bits each. The embedded nonvolatile elements incorporate the QuantumTrap technology, creating the world’s most reliable nonvolatile memory. The SRAM provides infinite read and write cycles, while the QuantumTrap cells provide highly reliable nonvolatile storage of data.

Features

• 64-Kbit nonvolatile static random access memory (nvSRAM)
  • Internally organized as 8 K × 8
  • STORE to QuantumTrap nonvolatile elements initiated automatically on power-down (AutoStore) or by using I2C command (Software STORE) or HSB pin (Hardware STORE)
  • RECALL to SRAM initiated on power-up (Power-Up RECALL) or by I2C command (Software RECALL)
  • Automatic STORE on power-down with a small capacitor (except for CY14MX064J1)
• High reliability
  • Infinite read, write, and RECALL cycles
  • 1 million STORE cycles to QuantumTrap
  • Data retention: 20 years at 85° C
• For more, see pdf

Overview

The Cypress CY14MB064J/CY14ME064J combines a 64-Kbit nvSRAM with a nonvolatile element in each memory cell. The memory is organized as 8 K words of 8 bits each. The embedded nonvolatile elements incorporate the QuantumTrap technology, creating the world’s most reliable nonvolatile memory. The SRAM provides infinite read and write cycles, while the QuantumTrap cells provide highly reliable nonvolatile storage of data.

Features

• 512-Kbit nonvolatile static random access memory (nvSRAM)
  • Internally organized as 64 K × 8
  • STORE to QuantumTrap nonvolatile elements initiated automatically on power-down (AutoStore) or by using I2C command (Software STORE) or HSB pin (Hardware STORE)
  • RECALL to SRAM initiated on power-up (Power-Up RECALL) or by I²C command (Software RECALL)
  • Automatic STORE on power-down with a small capacitor (except for CY14X512J1)
• High reliability
  • Infinite read, write, and RECALL cycles
  • 1 million STORE cycles to QuantumTrap
  • Data retention: 20 years at 85 °C
• For more, see pdf
   

Overview

The Cypress CY14C512J/CY14B512J/CY14E512J combines a 512-Kbit nvSRAM with a nonvolatile element in each memory cell. The memory is organized as 64 K words of 8 bits each. The embedded nonvolatile elements incorporate the QuantumTrap technology, creating the world’s most reliable nonvolatile memory. The SRAM provides infinite read and write cycles, while the QuantumTrap cells provide highly reliable nonvolatile storage of data. Data transfers from SRAM to the nonvolatile elements (STORE operation) takes place automatically at power-down (except for CY14X512J1). On power-up, data is restored to the SRAM from the nonvolatile memory (RECALL operation). The STORE and RECALL operations can also be initiated by the user through I2C commands.

Features

• Radio System-on-Chip with built-in 8-bit MCU in a single device.
• Operates in the unlicensed worldwide Industrial, Scientific, and Medical (ISM) band (2.400 GHz to 2.483 GHz).
• On Air compatible with second generation radio WirelessUSB™ LP and PRoC LP.
• Pin-to-pin compatible with PRoC LP except the Pin31 and Pin37.

Intelligent

• M8C based 8-bit CPU, optimized for human interface devices (HID) applications
• 256 bytes of SRAM
• 8 Kbytes of flash memory with EEPROM emulation
• In-system reprogrammable through D+/D– pins
• CPU speed up to 12 MHz
• For more, see pdf

 Functional Description

PRoC LPstar devices are integrated radio and microcontroller functions in the same package to provide a dual-role single-chip solution.

Communication between the microcontroller and the radio is through the radio’s SPI interface.

Features

• 512-Kbit nonvolatile static random access memory (nvSRAM)
  • Internally organized as 64 K × 8
  • STORE to QuantumTrap nonvolatile elements initiated automatically on power-down (AutoStore) or by using I2C command (Software STORE) or HSB pin (Hardware STORE)
  • RECALL to SRAM initiated on power-up (Power-Up RECALL) or by I2C command (Software RECALL)
  • Automatic STORE on power-down with a small capacitor
• High reliability
  • Infinite read, write, and RECALL cycles
  • 1 million STORE cycles to QuantumTrap
  • Data retention: 20 years at 85 °C
• For more, see pdf
   

Overview

The Cypress CY14C512I/CY14B512I/CY14E512I combines a 512-Kbit nvSRAM with a full-featured RTC in a monolithic integrated circuit with serial I2C interface. The memory is organized as 64 K words of 8 bits each. The embedded nonvolatile elements incorporate the QuantumTrap technology, creating the world’s most reliable nonvolatile memory. The SRAM provides infinite read and write cycles, while the QuantumTrap cells provide highly reliable nonvolatile storage of data. Data transfers from SRAM to the nonvolatile elements (STORE operation) takes place automatically at power-down. On power-up, data is restored to the SRAM from the nonvolatile memory (RECALL operation). The STORE and RECALL operations can also be initiated by the user through I2C commands.

Features

• Supports up to 100-MHz bus operations with zero wait states
  • Data is transferred on every clock
• Pin compatible and functionally equivalent to ZBT™ devices
• Internally self timed output buffer control to eliminate the need to use OE
• Registered inputs for flow-through operation
• Byte write capability
• 256 K × 18 common IO architecture
• 2.5 V / 3.3 V IO power supply (VDDQ)
• Fast clock-to-output times
• For more, see pdf
   

Functional Description

The CY7C1353G is a 3.3 V, 256 K × 18 synchronous flow-through burst SRAM designed specifically to support unlimited true back-to-back read/write operations without the insertion of wait states. The CY7C1353G is equipped with the advanced No Bus Latency™ (NoBL™) logic required to enable consecutive read/write operations with data being transferred on every clock cycle. This feature dramatically improves the throughput of data through the SRAM, especially in systems that require frequent write-read transitions.

Features

• Supports bus operation up to 250 MHz
• Available speed grades are 250, 200, and 167 MHz
• Registered inputs and outputs for pipelined operation
• 3.3V core power supply
• 2.5V or 3.3V I/O power supply
• Fast clock-to-output times
  • 2.6 ns (for 250 MHz device)
• Provides high performance 3-1-1-1 access rate
• User selectable burst counter supporting Intel Pentium® interleaved or linear burst sequences
• For more, see pdf

Functional Description

The CY7C1380D/CY7C1380F/CY7C1382D SRAM integrates 524,288 × 36 and 1,048,576 × 18 SRAM cells with advanced synchronous peripheral circuitry and a two-bit counter for internal burst operation. All synchronous inputs are gated by registers controlled by a positive edge triggered clock input (CLK). The synchronous inputs include all addresses, all data inputs, address-pipelining chip enable (CE1), depth-expansion chip enables (CE2 and CE3), burst control inputs (ADSC, ADSP, and ADV), write enables (BWX, and BWE), and global write (GW). Asynchronous inputs include the output enable (OE) and the ZZ pin. 

Features

• Can support up to 133-MHz bus operations with zero wait states
  • Data is transferred on every clock
• Pin compatible and functionally equivalent to ZBT™ devices
• Internally self-timed output buffer control to eliminate the need to use OE
• Registered inputs for flow-through operation
• Byte write capability
• 128 K × 36 common I/O architecture
• 2.5 V/3.3 V I/O power supply (VDDQ)
• Fast clock-to-output times
• For more, see pdf

Functional Description

The CY7C1351G is a 3.3 V, 128 K × 36 synchronous flow-through burst SRAM designed specifically to support unlimited true back-to-back read/write operations without the insertion of wait states. The CY7C1351G is equipped with the advanced No Bus Latency™ (NoBL™) logic required to enable consecutive Read/Write operations with data being transferred on every clock cycle. This feature dramatically improves the throughput of data through the SRAM, especially in systems that require frequent write-read transitions.

Features

• Supports 133 MHz bus operations
• 512K × 36 and 1M × 18 common I/O
• 3.3V core power supply (VDD)
• 2.5V or 3.3V I/O supply (VDDQ)
• Fast clock-to-output time
  • 6.5 ns (133 MHz version)
• Provides high performance 2-1-1-1 access rate
• User selectable burst counter supporting Intel Pentium interleaved or linear burst sequences
• Separate processor and controller address strobes
• For more, see pdf
   

Functional Description

The CY7C1381D/CY7C1383D/CY7C1383F is a 3.3 V, 512 K × 36 and 1 M × 18 synchronous flow through SRAMs, designed to interface with high speed microprocessors with minimum glue logic. Maximum access delay from clock rise is 6.5 ns (133 MHz version). A 2-bit on-chip counter captures the first address in a burst and increments the address automatically for the rest of the burst access. All synchronous inputs are gated by registers controlled by a positive edge triggered clock input (CLK).

Features

• 64-Kbit nonvolatile static random access memory (nvSRAM)
  • Internally organized as 8 K × 8
  • STORE to QuantumTrap nonvolatile elements initiated automatically on power-down (AutoStore) or by using SPI instruction (Software STORE) or HSB pin (Hardware STORE)
  • RECALL to SRAM initiated on power-up (Power Up RECALL) or by SPI instruction (Software RECALL)
  • Automatic STORE on power-down with a small capacitor
• High reliability
  • Infinite read, write, and RECALL cycles
  • 1 million STORE cycles to QuantumTrap
  • Data retention: 20 years at 85 °C
• For more, see pdf
   

Overview

The Cypress CY14X064PA combines a 64 Kbit nvSRAM with a full-featured RTC in a monolithic integrated circuit with serial SPI interface. The memory is organized as 8 K words of 8 bits each. The embedded nonvolatile elements incorporate the QuantumTrap technology, creating the world’s most reliable nonvolatile memory. The SRAM provides infinite read and write cycles, while the QuantumTrap cells provide highly reliable nonvolatile storage of data. Data transfers from SRAM to the nonvolatile elements (STORE operation) takes place automatically at power-down. On power-up, data is restored to the SRAM from the nonvolatile memory (RECALL operation). You can also initiate the STORE and RECALL operations through SPI instruction.

High Integration Device Replaces Multiple Parts

• Serial Nonvolatile Memory
• Real-time Clock (RTC)
• Low Voltage Reset
• Watchdog Timer
• Early Power-Fail Warning/NMI
• Two 16-bit Event Counters
• Serial Number with Write-lock for Security
• For more, see pdf.

Description

The FM3127x is a family of integrated devices that includes the most commonly needed functions for processor-based systems. Major features include nonvolatile memory available in various sizes, real-time clock, low-VDD reset, watchdog timer, nonvolatile event counter, lockable 64-bit serial number area, and general purpose comparator that can be used for an early power-fail (NMI) interrupt or other purpose. The family operates from 4.0 to 5.5V.

Features

• Pin compatible and functionally equivalent to ZBT™ devices
• Internally self-timed output buffer control to eliminate the need to use OE
• Byte write capability
• 256 K × 18 common I/O architecture
• 3.3 V core power supply (VDD)
• 2.5 V/3.3 V I/O power supply (VDDQ)
• Fast clock-to-output times
  • 4.0 ns (for 133-MHz device)
• Clock enable (CEN) pin to suspend operation
• For more, see pdf

Functional Description

The CY7C1352G is a 3.3 V, 256 K × 18 synchronous-pipelined burst SRAM designed specifically to support unlimited true back-to-back read/write operations without the insertion of wait states. The CY7C1352G is equipped with the advanced No Bus atency™ (NoBL™) logic required to enable consecutive read/write operations with data being transferred on every clock cycle. This feature dramatically improves the throughput of the SRAM, especially in systems that require frequent write/read transitions.

Features

• 256-Kbit nonvolatile static random access memory (nvSRAM)
  • Internally organized as 32 K × 8
  • STORE to QuantumTrap nonvolatile elements initiated automatically on power-down (AutoStore) or by using SPI instruction (Software STORE) or HSB pin (Hardware STORE)
  • RECALL to SRAM initiated on power-up (Power Up RECALL) or by SPI instruction (Software RECALL)
  • Automatic STORE on power-down with a small capacitor
• High reliability
  • Infinite read, write, and RECALL cycles
  • 1 million STORE cycles to QuantumTrap
  • Data retention: 20 years at 85 °C
• For more, see pdf

Overview

The Cypress CY14X256PA combines a 256-Kbit nvSRAM with a full-featured RTC in a monolithic integrated circuit with serial SPI interface. The memory is organized as 32 K words of 8 bits each. The embedded nonvolatile elements incorporate the QuantumTrap technology, creating the world’s most reliable nonvolatile memory. The SRAM provides infinite read and write cycles, while the QuantumTrap cells provide highly reliable nonvolatile storage of data. Data transfers from SRAM to the nonvolatile elements (STORE operation) takes place automatically at power-down. On power-up, data is restored to the SRAM from the nonvolatile memory (RECALL operation). You can also initiate the STORE and RECALL operations through SPI instruction.

Features

• 64-Kbit nonvolatile static random access memory (nvSRAM)
  • Internally organized as 8 K × 8
  • STORE to QuantumTrap nonvolatile elements initiated automatically on power-down (AutoStore) or by using I2C command (Software STORE) or HSB pin (Hardware STORE)
  • RECALL to SRAM initiated on power-up (Power-Up RECALL) or by I2C command (Software RECALL)
  • Automatic STORE on power-down with a small capacitor
• High reliability
  • Infinite read, write, and RECALL cycles
  • 1 million STORE cycles to QuantumTrap
  • Data retention: 20 years at 85 °C
• For more, see pdf

Overview

The Cypress CY14C064I/CY14B064I/CY14E064I combines a 64-Kbit nvSRAM with a full-featured RTC in a monolithic integrated circuit with serial I2C interface. The memory is organized as 8 K words of 8 bits each. The embedded nonvolatile elements incorporate the QuantumTrap technology, creating the world’s most reliable nonvolatile memory. The SRAM provides infinite read and write cycles, while the QuantumTrap cells provide highly reliable nonvolatile storage of data. Data transfers from SRAM to the nonvolatile elements (STORE operation) takes place automatically at power-down. On power-up, data is restored to the SRAM from the nonvolatile memory (RECALL operation). The STORE and RECALL operations can also be initiated by the user through I2C commands.

Features

• Fully integrated 2.4-GHz radio on a chip
• 1-Mbps over-the-air data rate
• Transmit power typical: 0 dBm
• Receive sensitivity typical: –87 dBm
• 1 μA typical current consumption in sleep state
• Closed-loop frequency synthesis
• Supports frequency-hopping spread spectrum
• On-chip packet framer with 64-byte first in first out (FIFO) data buffer
• Built-in auto-retry-acknowledge protocol simplifies usage
• For more, see pdf

Product Description

WirelessUSB™-NL, optimized to operate in the 2.4-GHz ISM band, is Cypress's third generation of 2.4-GHz low-power RF technology, bringing the next level of low-power performance into a small 4-mm × 4-mm footprint. WirelessUSB-NL implements a Gaussian frequency-shift keying (GFSK) radio using a differentiated single-mixer, closed-loop modulation design that optimizes power efficiency and interference immunity.

Features

• XRES pin to support in-system serial programming (ISSP) and external reset control in CY8C24894
• Powerful Harvard-architecture processor
• Advanced peripherals (PSoC® Blocks)
• Full speed USB (12 Mbps)
• Flexible on-chip memory
• Programmable pin configurations
• Precision, programmable clocking
• Additional system resources
• For more, see pdf

PSoC Functional Overview

The PSoC family consists of many devices with on-chip controllers. These devices are designed to replace multiple traditional MCU-based system components with one low-cost single-chip programmable component. A PSoC device includes configurable blocks of analog and digital logic, and programmable interconnect. This architecture makes it possible for you to create customized peripheral configurations, to match the requirements of each individual application.

• USB 2.0-USB-IF certified (TID # 40000552)
• Single Device, Two Functions
• Flash Based Microcontroller Function
• Industry-Leading 2.4 GHz Radio Transceiver Function
• Component Reduction
• Flexible I/O
• USB Specification Compliance
• Operating Voltage from 4.0 V to 5.5 V DC
• Operating Temperature from 0 to 70°C
• Pb-free 40-pin QFN Package
• Advanced Development Tools Based on Cypress’s PSoC® Tools
• For more,see pdf

Functional Description

PRoC LP devices are integrated radio and microcontroller functions in the same package to provide a dual role single-chip solution.

Communication between the microcontroller and the radio is via the SPI interface between both functions.

Functional Overview

The CYRF69213 is a complete Radio System-on-Chip device, providing a complete RF system solution with a single device and a few discrete components. The CYRF69213 is designed to implement low cost wireless systems operating in the worldwide 2.4 GHz Industrial, Scientific, and Medical (ISM) frequency band (2.400 GHz–2.4835 GHz).

Features

• 512-Kbit nonvolatile static random access memory (nvSRAM)
  • Internally organized as 64 K × 8
  • STORE to QuantumTrap nonvolatile elements initiated automatically on power-down (AutoStore) or by using SPI instruction (Software STORE) or HSB pin (Hardware STORE)
  • RECALL to SRAM initiated on power-up (Power-Up RECALL) or by SPI instruction (Software RECALL)
  • Automatic STORE on power-down with a small capacitor
• High reliability
  • Infinite read, write, and RECALL cycles
  • 1 million STORE cycles to QuantumTrap
  • Data retention: 20 years at 85° C
• For more, see pdf
   

Overview

The Cypress CY14X512PA combines a 512-Kbit nvSRAM with a full-featured RTC in a monolithic integrated circuit with serial SPI interface. The memory is organized as 64 K words of 8 bits each. The embedded nonvolatile elements incorporate the QuantumTrap technology, creating the world’s most reliable nonvolatile memory. The SRAM provides infinite read and write cycles, while the QuantumTrap cells provide highly reliable nonvolatile storage of data.

Features

• 1-Mbit nonvolatile static random access memory (nvSRAM)
  • Internally organized as 128 K x 8
  • STORE to QuantumTrap nonvolatile elements initiated automatically on power-down (AutoStore) or by using I2C command (Software STORE) or HSB pin (Hardware STORE)
  • RECALL to SRAM initiated on power-up (Power Up RECALL) or by I2C command (Software RECALL)
  • Automatic STORE on power-down with a small capacitor
• High reliability
  • Infinite read, write, and RECALL cycles
  • 1 million STORE cycles to QuantumTrap
  • Data retention: 20 years at 85 °C
• For more, see pdf

Overview

The Cypress CY14C101I/CY14B101I/CY14E101I combines a 1-Mbit nvSRAM[1] with a full-featured RTC in a monolithic integrated circuit with serial I2C interface. The memory is organized as 128 K words of 8 bits each. The embedded nonvolatile elements incorporate the QuantumTrap technology, creating the world’s most reliable nonvolatile memory. The SRAM provides infinite read and write cycles, while the QuantumTrap cells provide highly reliable nonvolatile storage of data. Data transfers from SRAM to the nonvolatile elements (STORE operation) takes place automatically at power-down.

Features

• 1-Mbit nonvolatile static random access memory (nvSRAM)
  • Internally organized as 128 K × 8
  • STORE to QuantumTrap nonvolatile elements initiated automatically on power-down (AutoStore) or by using SPI instruction (Software STORE) or HSB pin (Hardware STORE)
  • RECALLto SRAM initiated on power-up (Power Up RECALL) or by SPI instruction (Software RECALL)
  • Automatic STORE on power-down with a small capacitor
• High reliability
  • Infinite read, write, and RECALL cycles
  • 1 million STORE cycles to QuantumTrap
  • Data retention: 20 years at 85°C
• For more, see pdf

Overview

The Cypress CY14X101PA combines a 1 Mbit nvSRAM with a full-featured RTC in a monolithic integrated circuit with serial SPI interface. The memory is organized as 128 K words of 8 bits each. The embedded nonvolatile elements incorporate the QuantumTrap technology, creating the world’s most reliable nonvolatile memory. The SRAM provides infinite read and write cycles, while the QuantumTrap cells provide highly reliable nonvolatile storage of data.

• 50 to 166 MHz Operating Frequency Range
• Wide Range of Spread Selections: 9
• Accepts Clock and Crystal Inputs
• Low Power Dissipation
  • 70 mW-Typ at 66 MHz
• Frequency Spread Disable Function
• Center Spread Modulation
• Low Cycle-to-cycle Jitter
• 8-pin SOIC Package
   

General Description

CY25561 is a spread spectrum clock generator (SSCG) IC used to reduce electromagnetic Interference (EMI) found in today's high speed digital electronic systems.

CY25561 uses a Cypress proprietary Phase Locked Loop (PLL) and Spread Spectrum Clock (SSC) technology to synthesize and frequency modulate the input frequency of the reference clock. By doing this, the measured EMI at the fundamental and harmonic frequencies of clock (SSCLK) is reduced. 

Features

• Pin-compatible and functionally equivalent to ZBT™
• Supports 200-MHz bus operations with zero wait states
  • Available speed grades are 200 and 167 MHz
• Internally self-timed output buffer control to eliminate the need to use asynchronous OE
• Fully registered (inputs and outputs) for pipelined operation
• Byte write capability
• Single 2.5 V power supply
• 2.5 V/1.8 V I/O supply (V_DDQ)
• Fast clock-to-output times
• For more, see pdf

Functional Description

The CY7C1470V25/CY7C1472V25/CY7C1474V25 are 2.5 V, 2 M × 36/4 M × 18/1 M × 72 synchronous pipelined burst SRAMs with No Bus Latency™ (NoBL™logic, respectively. They are designed to support unlimited true back-to-back read/write operations with no wait states. The CY7C1470V25/CY7C1472V25/CY7C1474V25 are equipped with the advanced (NoBL) logic required to enable consecutive read/write operations with data being transferred on every clock cycle.

Features

• Pin compatible and functionally equivalent to ZBT
• Supports 200 MHz Bus operations with zero wait states
  • Available speed grades are 200 and 167 MHz
• Internally self timed output buffer control to eliminate the need to use asynchronous OE
• Fully registered (inputs and outputs) for pipelined operation
• Byte write capability
• Single 3.3 V power supply
• 3.3 V/2.5 V I/O power supply
• Fast clock-to-output time
• For more, see pdf

Functional Description

The CY7C1470V33, CY7C1472V33, and CY7C1474V33 are 3.3 V, 2 M x 36/4 M x 18/1 M x 72 synchronous pipelined burst SRAMs with No Bus Latency™ (NoBL™) logic, respectively. They are designed to support unlimited true back-to-back read/write operations with no wait states. The CY7C1470V33, CY7C1472V33, and CY7C1474V33 are equipped with the advanced (NoBL) logic required to enable consecutive read/write operations with data being transferred on every clock cycle.

Features

• No Bus Latency™ (NoBL™) architecture eliminates dead cycles between write and read cycles
• Supports up to 133 MHz bus operations with zero wait states
• Data is transferred on every clock
• Pin compatible and functionally equivalent to ZBT™ devices
• Internally self timed output buffer control to eliminate the need to use OE
• Registered inputs for flow through operation
• Byte Write capability
• 3.3 V/2.5 V IO supply (VDDQ)
• Fast clock-to-output times
• For more, see pdf

Functional Description

The CY7C1471V33 is 3.3 V, 2 M × 36 synchronous flow through burst SRAMs designed specifically to support unlimited true back-to-back read or write operations without the insertion of wait states. The CY7C1471V33 is equipped with the advanced No Bus Latency (NoBL) logic required to enable consecutive read or write operations with data being transferred on every clock cycle. This feature dramatically improves the throughput of data through the SRAM, especially in systems that require frequent write-read transitions.

Features

• No Bus Latency™ (NoBL™) architecture eliminates dead cycles between write and read cycles
• Supports up to 133 MHz bus operations with zero wait states
• Data is transferred on every clock
• Pin compatible and functionally equivalent to ZBT™ devices
• Internally self timed output buffer control to eliminate the need to use OE
• Registered inputs for flow through operation
• Byte write capability
• 2.5 V/1.8 V IO supply (VDDQ)
• Fast clock-to-output times
• For more, see pdf

Functional Description

The CY7C1471V25 are 2.5 V, 2 M × 36 synchronous flow through burst SRAMs designed specifically to support unlimited true back-to-back read or write operations without the insertion of wait states. The CY7C1471V25 are equipped with the advanced No Bus Latency (NoBL) logic required to enable consecutive read or write operations with data transferred on every clock cycle.

• Automotive Electronics Council (AEC) Q100 qualified
• Powerful Harvard Architecture Processor
• Advanced Peripherals (PSoC® Blocks)
• Precision, Programmable Clocking
• Flexible On-Chip Memory
• Programmable Pin Configurations
• Additional System Resources
• Complete Development Tools
• For more, see pdf
   

128K bit Ferroelectric Nonvolatile RAM
 

• Organized as 16,384 x 8 bits
• High Endurance 100 Trillion (10¹⁴) Read/Writes
• 10 year Data Retention
• NoDelay™ Writes
• Advanced High-Reliability Ferroelectric Process
• For more, see pdf.

Description

The FM24V01 is a 128Kbit nonvolatile memory employing an advanced ferroelectric process. A ferroelectric random access memory or F-RAM is nonvolatile and performs reads and writes like a RAM. It provides reliable data retention for 10 years while eliminating the complexities, overhead, and system level reliability problems caused by EEPROM and other nonvolatile memories.

64K x 4 Static RAM with Separate IO

Features

• High speed
  • 15 ns
• CMOS for optimum speed/power
• Low active power
  • 860 mW
• Low standby power
  • 55 mW
• TTL-compatible inputs and outputs
• Automatic power down when deselected
• Available in Pb-free and non Pb-free 28-Pin Molded SOJ package

Functional Description

The CY7C192 is a high performance CMOS static RAM organized as 65,536 x 4 bits with separate IO. Easy memory expansion is provided by active LOW Chip Enable (CE) and tri-state drivers. It has an automatic power down feature that reduces power consumption by 75% when deselected.

Features

• One input to four output buffer/driver
• General-purpose or PCI-X clock buffer
• Buffers all frequencies from DC to 140 MHz
• Output-to-output skew less than 100 ps
• Space-saving 8-pin TSSOP package
• 3.3V operation
• 60 ps typical output-output skew
   

Functional Description

The CY2304NZ is a low-cost buffer designed to distribute high-speed clocks for PCI-X and other applications. The device operates at 3.3V and outputs can run up to 140 MHz.

• Powerful Harvard-architecture processor:
• Advanced peripherals (PSoC® Blocks)
• High speed 10-bit SAR ADC with sample and hold optimized for embedded control
• Precision, programmable clocking
• Flexible on-chip memory
• Optimized CapSense® resource
• Programmable pin configurations
• Additional system resources
• For more, see pdf
   

PSoC Functional Overview

The PSoC family consists of many On-Chip Controller devices. These devices are designed to replace multiple traditional MCU-based system components with one low cost single-chip programmable device. PSoC devices include configurable blocks of analog and digital logic, and programmable interconnects.

Features

• Powerful Harvard-architecture processor
• Advanced peripherals (PSoC® blocks)
• Precision, programmable clocking
• Flexible on-chip memory
• Programmable pin configurations
• Additional system resources
• Complete development tools
• For more, see pdf

PSoC Functional Overview

The PSoC family consists of many programmable system-on-chip controller devices. These devices are designed to replace multiple traditional microcontroller unit (MCU)-based system components with one, low-cost single-chip programmable device. PSoC devices include configurable blocks of analog and digital logic, as well as programmable interconnects. This architecture lets you to create customized peripheral configurations that match the requirements of each individual application.

Features

• 72-Mbit density (4 M × 18)
• 250 MHz clock for high bandwidth
• Two-word burst for reducing address bus frequency
• Double data rate (DDR) interfaces (data transferred at 500 MHz) at 250 MHz
• Two input clocks (K and K) for precise DDR timing
  • SRAM uses rising edges only
• Two input clocks for output data (C and C) to minimize clock skew and flight time mismatches
• Echo clocks (CQ and CQ) simplify data capture in high speed systems
• Synchronous internally self timed writes
• For more, see pdf.

Functional Description

The CY7C1523KV18 is a1.8 V Synchronous Pipelined SRAMs, equipped with DDR II SIO (Double Data Rate Separate I/O) architecture. The DDR II SIO consists of two separate ports: the read port and the write port to access the memory array. The read port has data outputs to support read operations and the write port has data inputs to support write operations. The DDR II SIO has separate data inputs and data outputs to completely eliminate the need to “turnaround” the data bus required with common I/O devices.

• 144-Mbit density (8 M × 18)
• 333 MHz clock for high bandwidth
• Two-word burst for reducing address bus frequency
• Double Data Rate (DDR) interfaces (data transferred at 666 MHz) at 333 MHz
• Two input clocks (K and K) for precise DDR timing
  • SRAM uses rising edges only
• Two input clocks for output data (C and C) to minimize clock skew and flight time mismatches
• Echo clocks (CQ and CQ) simplify data capture in high speed systems
• Synchronous internally self timed writes
• For more, see pdf.

Functional Description

The CY7C1623KV18 is 1.8 V Synchronous Pipelined SRAM, equipped with DDR-II SIO (Double Data Rate Separate I/O) architecture. The DDR-II SIO consists of two separate ports: the read port and the write port to access the memory array. The read port has data outputs to support read operations and the write port has data inputs to support write operations. The DDR-II SIO has separate data inputs and data outputs to completely eliminate the need to ‘turnaround’ the data bus required with common I/O devices. Access to each port is accomplished through a common address bus.

16K bit Ferroelectric Nonvolatile RAM
 

• Organized as 2,048 x 8 bits
• High Endurance 100 Trillion (10¹⁴) Read/Writes
• 38 Year Data Retention (@ +75ºC)
• NoDelay™ Writes
• Advanced High-Reliability Ferroelectric Process
• For more, see pdf.

Description

The FM25L16B is a 16-kilobit nonvolatile memory employing an advanced ferroelectric process. A ferroelectric random access memory or F-RAM is nonvolatile and performs reads and writes like a RAM. It provides reliable data retention for 38 years while eliminating the complexities, overhead, and system level reliability problems caused by EEPROM and other nonvolatile memories.

Features

• Very high speed: 45 ns
• Temperature ranges
  • Industrial: –40 °C to 85 °C
  • Automotive-A: –40 °C to 85 °C
• Wide voltage range: 2.20 V to 3.60 V
• Pin compatible with CY62146DV30
• Ultra low standby power
  • Typical standby current: 1 μA
  • Maximum standby current: 7 μA
• For more, see pdf
   

Functional Description

The CY62146EV30 is a high performance CMOS static RAM organized as 256K words by 16 bits. This device features an advanced circuit design designed to provide an ultra low active current. Ultra low active current is ideal for providing More Battery Life™ (MoBL®) in portable applications such as cellular telephones. The device also has an automatic power down feature that significantly reduces power consumption by 80 percent when addresses are not toggling.

Features

• USB 2.0 hub controller
• Automotive and Industrial grade option (–40 °C to 85 °C)
• Compliant with USB 2.0 specification
• USB-IF certified: TID# 30000009
• Windows Hardware Quality Lab (WHQL) Compliant
• Up to four downstream ports supported
• Supports bus powered and self powered modes
• Single transaction translator (TT)
• Bus power configurations
• For more, see pdf
   

Introduction

EZ-USB HX2LP™ is Cypress’s next generation family of high-performance, low-power USB 2.0 hub controllers. HX2LP is an ultra low power single chip USB 2.0 hub controller with integrated upstream and downstream transceivers, a USB serial interface engine (SIE), USB hub control and repeater logic, and TT logic. Cypress has also integrated many of the external passive components, such as pull-up and pull-down resistors, reducing the overall bill of materials required to implement a hub design.

Features

The Cypress MoBL-USB™ TX2UL is a low voltage high speed (HS) USB 2.0 UTMI+ Low Pin Interface (ULPI) Transceiver. The TX2UL is specifically designed for mobile handset applications by offering tiny package options and low power consumption.

• USB 2.0 Full Speed and High Speed Compliant Transceiver
• Multi Range (1.8V to 3.3V) I/O Voltages
• Fully Compliant ULPI Link Interface
• 8-bit SDR ULPI Data Path
• UTMI Level 0 Support
• Support USB Device Mode only
• Integrated Oscillator
• Integrated Phase Locked Loop (PLL) – 13, 19.2, 24, or 26 MHz Reference
• Integrated USB Pull Up and Termination Resistors
• For more, see pdf
   

Functional Overview

UTMI+ Low Pin Interface (ULPI)

This block conforms to the ULPI Specification. It supports the 8-bit wide SDR data path. The primary I/Os of this block support multi-range LVCMOS signaling from 1.8V to 3.3V (±5%). The level used is automatically selected by the voltage applied to VCCIO and is set at any voltage between 1.8V and 3.3V.

Features

• Powerful Harvard-architecture processor
• Flexible on-chip memory
• Complete development tools
• Precision, programmable clocking
• Programmable pin configurations
• Full-Speed USB (12 Mbps)
• Additional system resources
• For more, see pdf
   

Functional Overview

The enCoRe V family of devices are designed to replace multiple traditional full-speed USB microcontroller system components with one, low cost single-chip programmable component. Communication peripherals (I2C/SPI), a fast CPU, Flash program memory, SRAM data memory, and configurable I/O are included in a range of convenient pinouts.

Features

• Three Integrated Phase-locked Loops
• Ultra Wide Divide Counters (8-bit Q, 11-bit P, and 7-bit Post Divide)
• Improved Linear Crystal Load Capacitors
• Flash Programmability
• Field Programmable
• Low-jitter, High-accuracy Outputs
• Power Management Options (Shutdown, OE, Suspend)
• Configurable Crystal Drive Strength
• Frequency Select through three External LVTTL Inputs
• 3.3V Operation
• 16-pin TSSOP and SOIC Packages
• CyClocksRT™ Support

Operation

The CY22392 is an upgrade to the existing CY2292. The new device has a wider frequency range, greater flexibility, improved performance, and incorporates many features that reduce PLL sensitivity to external system issues.

The device has three PLLs which, when combined with the reference, enable up to four independent frequencies to be output on up to six pins. These three PLLs are completely programmable.

General Description

With its unique array of configurable blocks, PSoC® 5LP is a true system-level solution providing microcontroller unit (MCU), memory, analog, and digital peripheral functions in a single chip. The CY8C58LP family offers a modern method of signal acquisition, signal processing, and control with high accuracy, high bandwidth, and high flexibility. Analog capability spans the range from thermocouples (near DC voltages) to ultrasonic signals.

The CY8C58LP family can handle dozens of data acquisition channels and analog inputs on every GPIO pin. The CY8C58LP family is also a high-performance configurable digital system with some part numbers including interfaces such as USB, multimaster I2C, and controller area network (CAN). In addition to communication interfaces, the CY8C58LP family has an easy to configure logic array, flexible routing to all I/O pins, and a high-performance 32-bit ARM® Cortex™-M3 microprocessor core.

Designers can easily create system-level designs using a rich library of prebuilt components and boolean primitives using PSoC Creator™, a hierarchical schematic design entry tool. The CY8C58LP family provides unparalleled opportunities for analog and digital bill of materials integration while easily accommodating last minute design changes through simple firmware updates.

Features

• 32-bit ARM Cortex-M3 CPU core
• Low voltage, ultra low power
• Versatile I/O system
• Digital peripherals
• Analog peripherals (1.71 V ≤ VDDA ≤ 5.5 V)
• Programming, debug, and trace
• Precision, programmable clocking
• Temperature and packaging
• For more, see data sheet pdf

• Very high speed: 45 ns
• Temperature ranges
• Automotive-A: –40 °C to 85 °C
• Automotive-E: –40 °C to 125 °C
• Wide voltage range: 2.20 V to 3.60 V
• Pin compatible with CY62147DV30
• Ultra low standby power
  • Typical standby current: 1 µA
  • Maximum standby current: 7 µA (Automotive-A)
• For more, see pdf
   

The CY62147EV30 is a high performance CMOS static RAM (SRAM) organized as 256K words by 16 bits. This device features advanced circuit design to provide ultra low active current. It is ideal for providing More Battery Life™ (MoBL®) in portable applications such as cellular telephones. The device also has an automatic power down feature that significantly reduces power consumption when addresses are not toggling.

General Description

With its unique array of configurable blocks, PSoC® 5LP is a true system level solution providing MCU, memory, analog, and digital peripheral functions in a single chip. The CY8C56LP family offers a modern method of signal acquisition, signal processing, and control with high accuracy, high bandwidth, and high flexibility. Analog capability spans the range from thermocouples (near DC voltages) to ultrasonic signals.

The CY8C56LP family can handle dozens of data acquisition channels and analog inputs on every GPIO pin. The CY8C56LP family is also a high performance configurable digital system with some part numbers including interfaces such as USB and multimaster I2C, and controller area network (CAN). In addition to communication interfaces, the CY8C56LP family has an easy to configure logic array, flexible routing to all I/O pins, and a high performance 32-bit ARM® Cortex™-M3 microprocessor core.

Designers can easily create system level designs using a rich library of prebuilt components and boolean primitives using PSoC Creator™, a hierarchical schematic design entry tool. The CY8C56LP family provides unparalleled opportunities for analog and digital bill of materials integration while easily accommodating last minute design changes through simple firmware updates.

Features

• 32-bit ARM Cortex-M3 CPU core
• Low voltage, ultra low power
• Versatile I/O system
• Digital peripherals
• Analog peripherals (1.71 V ≤ VDDA ≤ 5.5 V)
• Programming, debug, and trace
• Precision, programmable clocking
• Temperature and packaging
• For more, see pdf.

Features

• Separate independent read and write data ports
  • Supports concurrent transactions
• 250 MHz clock for high bandwidth
• 4-word burst for reducing address bus frequency
• Double data rate (DDR) interfaces on both read and write ports at 250 MHz (data transferred at 500 MHz)
• Two input clocks (K and K) for precise DDR timing
  • SRAM uses rising edges only
• Echo clocks (CQ and CQ) simplify data capture in high speed systems
• Single multiplexed address input bus latches address inputs for read and write ports
• Separate port selects for depth expansion
• For more, see pdf
   

Functional Description

The CYRS1543AV18 and CYRS1545AV18 are synchronous pipelined SRAMs, equipped with 1.8 V QDR II+ architecture with RadStop™ technology. Cypress’s state-of-the-art RadStop Technology is radiation hardened through proprietary design and process hardening techniques.

Features

• Separate independent read and write data ports
  • Supports concurrent transactions
• 250-MHz clock for high bandwidth
• 2-word burst on all accesses
• Double data rate (DDR) interfaces on both read and write ports at 250 MHz (data transferred at 500 MHz)
• Two input clocks (K and K) for precise DDR timing
  • SRAM uses rising edges only
• Echo clocks (CQ and CQ) simplify data capture in high speed systems
• Single multiplexed address input bus latches address inputs for both read and write ports
• Separate port selects for depth expansion
• For more, see pdf
   

Functional Description

The CYRS1542AV18 and CYRS1544AV18 are synchronous pipelined SRAMs, equipped with 1.8-V QDR II+ architecture with RadStop™ technology. Cypress’s state-of-the-art RadStop Technology is radiation hardened through proprietary design and process hardening techniques.

General Description

With its unique array of configurable blocks, PSoC® 3 is a true system level solution providing microcontroller unit (MCU), memory, analog, and digital peripheral functions in a single chip. The CY8C36 family offers a modern method of signal acquisition, signal processing, and control with high accuracy, high bandwidth, and high flexibility. Analog capability spans the range from thermocouples (near DC voltages) to ultrasonic signals. The CY8C36 family can handle dozens of data acquisition channels and analog inputs on every general-purpose input/output (GPIO) pin. The CY8C36 family is also a high-performance configurable digital system with some part numbers including interfaces such as USB, multi-master inter-integrated circuit (I2C), and controller area network (CAN).

Features

• Single cycle 8051 CPU core
• Low voltage, ultra low-power
• Versatile I/O system
• Digital peripherals
• Analog peripherals (1.71 V ≤ V_DDA ≤ 5.5 V)
• Programming, debug, and trace
• Precision, programmable clocking
• For more, see pdf

Features

• Separate independent read and write data ports
  • Supports concurrent transactions
• 333 MHz clock for high bandwidth
• Two-word burst on all accesses
• Double data rate (DDR) Interfaces on both read and write ports (data transferred at 666 MHz) at 333 MHz
• Two input clocks (K and K) for precise DDR timing
  • SRAM uses rising edges only
• Two input clocks for output data (C and C) to minimize clock skew and flight time mismatches
• Echo clocks (CQ and CQ) simplify data capture in high speed systems
• For more, see pdf

Functional Description

The CY7C1425KV18, CY7C1412KV18, and CY7C1414KV18 are 1.8 V synchronous pipelined SRAMs, equipped with QDR II architecture. QDR II architecture consists of two separate ports: the read port and the write port to access the memory array. The read port has dedicated data outputs to support read operations and the write port has dedicated data inputs to support write operations. QDR II architecture has separate data inputs and  data outputs to completely eliminate the need to “turnaround” the data bus that exists with common I/O devices.
 

General Description

With its unique array of configurable blocks, PSoC® 3 is a true system level solution providing microcontroller unit (MCU), memory, analog, and digital peripheral functions in a single chip. The CY8C34 family offers a modern method of signal acquisition, signal processing, and control with high accuracy, high bandwidth, and high flexibility. Analog capability spans the range from thermocouples (near DC voltages) to ultrasonic signals. The CY8C34 family can handle dozens of data acquisition channels and analog inputs on every general-purpose input/output (GPIO) pin. The CY8C34 family is also a high-performance configurable digital system with some part numbers including interfaces such as USB, multimaster inter-integrated circuit (I2C), and controller area network (CAN). In addition to communication interfaces, the CY8C34 family has an easy to configure logic array, flexible routing to all I/O pins, and a high-performance single cycle 8051 microprocessor core. You can easily create system-level designs using a rich library of prebuilt components and boolean primitives using PSoC Creator™, a hierarchical schematic design entry tool. The CY8C34 family provides unparalleled opportunities for analog and digital bill of materials integration while easily accommodating last minute design changes through simple firmware updates.

Features

• Single cycle 8051 CPU core
• Low voltage, ultra low-power
• Versatile I/O system
• Digital peripherals
• Analog peripherals ( 1.71 V ≤ V_DDA ≤ 5.5 V)
• Programming, debug, and trace
• Precision, programmable clocking
• For more, see pdf

Features

• Memory organization
  • Industry's largest first in first out (FIFO) memory densities: 18 Mbit, 36 Mbit, and 72 Mbit
  • Selectable memory organization: x9, x12, x16, x18, x20, x24, x32, x36
• Up to 133-MHz clock operation
• Unidirectional operation
• Independent read and write ports
  • Supports simultaneous read and write operations
  • Reads and writes operate on independent clocks, upto a maximum ratio of two, enabling data buffering across clock domains.
  • Supports multiple I/O voltage standard: low voltage complementary metal oxide semiconductor (LVCMOS) 3.3 V and 1.8 V voltage standards.
• For more, see pdf.
   

Functional Description

The Cypress programmable FIFO family offers the industry’s highest-density programmable FIFO memory device. It has independent read and write ports, which can be clocked up to 133 MHz. User can configure input and output bus sizes. The maximum bus size of 36 bits enables a maximum data throughput of 4.8 Gbps.

General Description

With its unique array of configurable blocks, PSoC® 3 is a true system level solution providing microcontroller unit (MCU), memory, analog, and digital peripheral functions in a single chip. The CY8C32 family offers a modern method of signal acquisition, signal processing, and control with high accuracy, high bandwidth, and high flexibility. Analog capability spans the range from thermocouples (near DC voltages) to ultrasonic signals. The CY8C32 family can handle dozens of data acquisition channels and analog inputs on every general-purpose input/output (GPIO) pin.

Features

• Single cycle 8051 CPU core
• Low voltage, ultra low-power
• Versatile I/O system
• Digital peripherals
• Analog peripherals (1.71 V ≤ V_DDA ≤ 5.5 V)
• Programming, debug, and trace
• Precision, programmable clocking
• For more, see pdf

256K bit Ferroelectric Nonvolatile RAM

• Organized as 32,768 x 8 bits
• High Endurance 100 Trillion (10¹⁴) Read/Writes
• 38 year Data Retention (@ +75ºC)
• NoDelay™ Writes
• Advanced High-Reliability Ferroelectric Process
• For more, see pdf

Description

The FM24W256 is a 256-kilobit nonvolatile memory employing an advanced ferroelectric process. A ferroelectric random access memory or F-RAM is nonvolatile and performs reads and writes like a RAM. It provides reliable data retention for 38 years while eliminating the complexities, overhead, and system level reliability problems caused by EEPROM and other nonvolatile memories.

2Mbit Ferroelectric Nonvolatile RAM

• Organized as 128Kx16
• Configurable as 256Kx8 Using /UB, /LB
• 10¹⁴ Read/Write Cycles
• NoDelay™ Writes
• Page Mode Operation to 33MHz
• Advanced High-Reliability Ferroelectric Process
• For more, see pdf

Description

The FM28V202 is a 128Kx16 nonvolatile memory that reads and writes like a standard SRAM. A ferroelectric random access memory or F-RAM is nonvolatile, which means that data is retained after power is removed. It provides data retention for over 10 years while eliminating the reliability concerns, functional disadvantages, and system design complexities of battery-backed SRAM (BBSRAM). Fast write timing and high write endurance make the F-RAM superior to other types of memory.

1Mbit Ferroelectric Nonvolatile RAM

• Organized as 64Kx16
• Configurable as 128Kx8 Using /UB, /LB
• 10¹⁴ Read/Write Cycles
• NoDelay™ Writes
• Page Mode Operation to 33MHz
• Advanced High-Reliability Ferroelectric Process

Description

The FM28V102 is a 64Kx16 nonvolatile memory that reads and writes like a standard SRAM. A ferroelectric random access memory or F-RAM is nonvolatile, which means that data is retained after power is removed. It provides data retention for over 10 years while eliminating the reliability concerns, functional disadvantages, and system design complexities of battery-backed SRAM (BBSRAM). Fast write timing and high write endurance make the F-RAM superior to other types of memory.

Features

• Very high speed: 45 ns
• Wide voltage range: 4.5 V to 5.5 V
• Ultra low standby power
  • Typical standby current: 1 μA
  • Maximum standby current: 7 μA
• Ultra low active power
  • Typical active current: 2 mA at f = 1 MHz
• Easy memory expansion with CE and OE features
• Automatic power down when deselected
• Complementary metal oxide semiconductor (CMOS) for optimum speed and power
• Available in Pb-free 44-pin thin small outline package (TSOP) II package

Functional Description

The CY62146E is a high performance CMOS static RAM organized as 256K words by 16 bits. This device features advanced circuit design to provide ultra low active current. It is ideal for providing More Battery Life™ (MoBL®) in portable applications such as cellular telephones. The device also has an automatic power down feature that reduces power consumption when addresses are not toggling. Placing the device into standby mode reduces power consumption by more than 99% when deselected (CE HIGH).

Features

• True dual-ported memory cells which allow simultaneous access of the same memory location
• 16 K × 8 organization (CY7C006A)
• 0.35-micron CMOS for optimum speed/power
• High-speed access: 20 ns
• Low operating power
  • Active: ICC = 180 mA (typical)
  • Standby: ISB3 = 0.05 mA (typical)
• Fully asynchronous operation
• Automatic power-down
• For more, see pdf.

Functional Description

The CY7C006A is low-power CMOS 16 K × 8 dual-port static RAMs. Various arbitration schemes are included on the devices to handle situations when multiple processors access the same  piece of data. Two ports are provided, permitting independent,asynchronous access for reads and writes to any location in memory. The devices can be utilized as standalone 8-bit dual-port static RAMs or multiple devices can be combined in order to function as a 16-bit or wider master/slave dual-port static RAM.

Features

• 256 K × 18 common I/O
• 3.3 V core power supply (VDD)
• 2.5 V or 3.3 V I/O power supply (VDDQ)
• Fast clock-to-output times
• 6.5 ns (133 MHz version)
• Provide high performance 2-1-1-1 access rate
• User selectable burst counter supporting Intel Pentium interleaved or linear burst sequences
• For more, see pdf

Functional Description

The CY7C1325H is a 256 K × 18 synchronous cache RAM designed to interface with high speed microprocessors with minimum glue logic. Maximum access delay from clock rise is 6.5 ns (133 MHz version). A 2 bit on-chip counter captures the first address in a burst and increments the address automatically for the rest of the burst access. All synchronous inputs are gated by registers controlled by a positive-edge-triggered Clock Input (CLK).

Features

• Separate independent read and write data ports
  • Supports concurrent transactions
• 450-MHz clock for high bandwidth
• Four-word burst for reducing address bus frequency
• Double data rate (DDR) interfaces on both read and write ports (data transferred at 900 MHz) at 450 MHz
• Available in 2.0-clock cycle latency
• Two input clocks (K and K) for precise DDR timing
  • SRAM uses rising edges only
• Echo clocks (CQ and CQ) simplify data capture in high-speed systems
• Data valid pin (QVLD) to indicate valid data on the output
• For more, see pdf.
   

Functional Description

The CY7C1643KV18, and CY7C1645KV18 are 1.8-V synchronous pipelined SRAMs, equipped with QDR II+ architecture. Similar to QDR II architecture, QDR II+ architecture consists of two separate ports: the read port and the write port to access the memory array. The read port has dedicated data outputs to support read operations and the write port has dedicated data inputs to support write operations. QDR II+ architecture has separate data inputs and data outputs to completely eliminate the need to “turnaround” the data bus that exists with common I/O devices. Each port is accessed through a common address bus. Addresses for read and write addresses are latched on alternate rising edges of the input (K) clock.

Features

• No Bus Latency™ (NoBL™) architecture eliminates dead cycles between write and read cycles
• Supports up to 133-MHz bus operations with zero wait states
• Pin-compatible and functionally equivalent to ZBT™ devices
• Internally self-timed output buffer control to eliminate the need to use OE
• Registered inputs for flow through operation
• Byte write capability
• 3.3 V/2.5 V I/O power supply (VDDQ)
• Fast clock-to-output times
• For more, see pdf
   

Functional Description

The CY7C1371DV33 is a 3.3 V, 512 K × 36 synchronous flow through burst SRAM designed specifically to support unlimited true back-to-back read/write operations with no wait state insertion. The CY7C1371DV33 is equipped with the advanced No Bus Latency (NoBL) logic required to enable consecutive read/write operations with data being transferred on every clock cycle. This feature dramatically improves the throughput of data through the SRAM, especially in systems that require frequent write-read transitions.

72-Mbit QDR®II SRAM Four-Word Burst Architecture (2.5 Cycle Read Latency) with ODT

Features

• Separate independent read and write data ports
  • Supports concurrent transactions
• 550 MHz clock for high bandwidth
• 4-word burst for reducing address bus frequency
• Double Data Rate (DDR) interfaces on both read and write ports (data transferred at 1100 MHz) at 550 MHz
• Available in 2.5 clock cycle latency
• Two input clocks (K and K) for precise DDR timing
  • SRAM uses rising edges only
• Echo clocks (CQ and CQ) simplify data capture in high-speed systems
• For more, see pdf
   

Functional Description

The CY7C25632KV18 and CY7C25652KV18 are 1.8 V Synchronous Pipelined SRAMs, equipped with QDR II+ architecture. Similar to QDR II architecture, QDR II+ architecture consists of two separate ports: the read port and the write port to access the memory array. The read port has dedicated data outputs to support read operations and the write port has dedicated data inputs to support write operations.

 

4K bit Ferroelectric Nonvolatile RAM
 

• Organized as 512 x 8 bits
• High Endurance 10¹⁴ Read/Writes
• 38 Year Data Retention
• NoDelay™ Writes
• Advanced High-Reliability Ferroelectric Process
• For more, see pdf.

Description

The FM24CL04B is a 4-kilobit nonvolatile memory employing an advanced ferroelectric process. A ferroelectric random access memory or FRAM is nonvolatile and performs reads and writes like a RAM. It provides reliable data retention for 38 years while eliminating the complexities, overhead, and system level reliability problems caused by EEPROM and other nonvolatile memories.

16K bit Ferroelectric Nonvolatile RAM

• Organized as 2,048 x 8 bits
• High Endurance 10¹⁴ Read/Writes
• 38 year Data Retention
• NoDelay™ Writes
• Advanced High-Reliability Ferroelectric Process
• For more, see pdf

Description

The FM24CL16B is a 16-kilobit nonvolatile memory employing an advanced ferroelectric process. A ferroelectric random access memory or FRAM is nonvolatile and performs reads and writes like a RAM. It provides reliable data retention for 38 years while eliminating the complexities, overhead, and system level reliability problems caused by EEPROM and other nonvolatile memories.

16K bit Ferroelectric Nonvolatile RAM

• Organized as 2,048 x 8 bits
• High Endurance (10¹²) Read/Write Cycles
• 38 year Data Retention
• NoDelay™ Writes
• Advanced High-Reliability Ferroelectric Process
• For more, see pdf

Description

The FM24C16B is a 16-kilobit nonvolatile memory employing an advanced ferroelectric process. A ferroelectric random access memory or FRAM is nonvolatile and performs reads and writes like a RAM. It provides reliable data retention for 38 years while eliminating the complexities, overhead, and system level reliability problems caused by EEPROM and other nonvolatile memories.

64K bit Ferroelectric Nonvolatile RAM

• Organized as 8,192 x 8 bits
• High Endurance 10¹⁴ Read/Writes
• 38 year Data Retention
• NoDelay™ Writes
• Advanced High-Reliability Ferroelectric Process
• For more, see pdf

Description

The FM24CL64B is a 64-kilobit nonvolatile memory employing an advanced ferroelectric process. A ferroelectric random access memory or F-RAM is nonvolatile and performs reads and writes like a RAM. It provides reliable data retention for 38 years while eliminating the complexities, overhead, and system level reliability problems caused by EEPROM and other nonvolatile memories.

PRoC™ LP Features

• Single Device, Two Functions
• Flash Based Microcontroller Function
• Industry leading 2.4 GHz Radio Transceiver Function
• Component Reduction
• Flexible I/O
• Operating Voltage from 1.8 V to 3.6 V DC
• Operating Temperature from 0 to 70 °C
• Pb-free 40-pin QFN Package
• Advanced Development Tools based on Cypress’s PSoC® Tools
• For more,see pdf

Functional Overview

The CYRF69103 is a complete Radio System-on-Chip device, providing a complete RF system solution with a single device and a few discrete components. The CYRF69103 is designed to implement low cost wireless systems operating in the worldwide 2.4 GHz Industrial, Scientific, and Medical (ISM) frequency band (2.400 GHz to 2.4835 GHz).

Features

• Universal Serial Bus (USB) Integration
  • USB 3.0 and USB 2.0 peripherals compliant with USB 3.0 specification 1.0
  • High-speed On-The-Go (HS-OTG) host and peripheral compliant with OTG Supplement Version 2.0
  • Support for battery charging Spec 1.1 and accessory charger adaptor (ACA) detection
• General Programmable Interface (GPIF™ II)
  • Programmable 100-MHz GPIF II enables connectivity to a wide range of external devices
  • 8- and 16- bit data bus
• Mass Storage Support
  • SD 3.0 (SDXC) UHS-1
  • eMMC 4.41
  • System I/O expansion with 2 secure digital I/O (SDIO) ports
• Fully accessible ARM9 with up to 512KB embedded SRAM
• For more, see pdf.

Functional Overview

EZ-USB® FX3S™ is the latest offering in the industry leading FX3™ USB 3.0 peripheral controller family that enables developers to add USB 3.0 device functionality to any system. In addition to USB 3.0 functionality and a powerful ARM core, FX3S’s integrated storage controllers enable you to add support for SD/eMMC memories and SDIO devices to your products without adding any extra controller chip. Based on the proven FX3 Platform, FX3S leverages FX3’s familiar ecosystem and package to reduce your time-to-market and design complexity. FX3S has the fully configurable General Programmable Interface (GPIF™ II), which can interface with virtually any processor, ASIC, Image Sensor or FPGA. The FX3S’s programming flexibility makes it an ideal solution to any USB 3.0 product that wants to differentiate itself while keeping cost and time-to-market down.

• Supports 133 MHz bus operations
• 1 M × 36/512 K × 72 common I/O
• 2.5 V core power supply
• 2.5 V and 1.8 V I/O power supply
• Fast clock-to-output times
• Provide high performance 2-1-1-1 access rate
• User selectable burst counter supporting Intel® Pentium® interleaved or linear burst sequences
• Separate processor and controller address strobes
• Synchronous self timed write
• For more, see pdf
   

Functional Description

The CY7C1441AV25/CY7C1447AV25 are 2.5 V, 1 M × 36/512 K × 72 Synchronous Flow-Through SRAMs, designed to interface with high speed microprocessors with minimum glue logic. Maximum access delay from clock rise is 6.5 ns (133 MHz version). A 2-bit on-chip counter captures the first address in a burst and increments the address automatically for the rest of the burst access. All synchronous inputs are gated by registers controlled by a positive edge-triggered Clock Input (CLK).

Features

• Pin-compatible and functionally equivalent to ZBT™
• Supports 250 MHz bus operations with zero wait states
  • Available speed grades are 250, 200, and 167 MHz
• Internally self-timed output buffer control to eliminate the need to use asynchronous OE
• Fully registered (inputs and outputs) for pipelined operation
• Byte Write capability
• Single 2.5V power supply
• 2.5V I/O supply (VDDQ)
• Fast clock-to-output times
• For more, see pdf

Functional Description

The CY7C1470BV25 and CY7C1472BV25 are 2.5 V, 2 M × 36/4 M × 18 synchronous pipelined burst SRAMs with No Bus Latency™ (NoBL™) logic, respectively. They are designed to support unlimited true back-to-back read or write operations with no wait states. The CY7C1470BV25 and CY7C1472BV25 are equipped with the advanced (NoBL) logic required to enable consecutive read or write operations with data being transferred on every clock cycle. This feature dramatically improves the throughput of data in systems that require frequent read or write transitions. The CY7C1470BV25 and CY7C1472BV25 are pin-compatible and functionally equivalent to ZBT devices.
 

64K bit Ferroelectric Nonvolatile RAM
 

• Organized as 8,192 x 8 bits
• High Endurance 1 Trillion (10¹²) Read/Writes
• 38 Year Data Retention
• NoDelay™ Writes
• Advanced high-reliability ferroelectric process
• For more, see pdf.

Description

The FM25640B is a 64-kilobit nonvolatile memory employing an advanced ferroelectric process. A ferroelectric random access memory or F-RAM is nonvolatile but operates in other respects as a RAM. It provides reliable data retention for 38 years while eliminating the complexities, overhead, and system level reliability problems caused by EEPROM and other nonvolatile memories.

4K bit Ferroelectric Nonvolatile RAM
 

• Organized as 512 x 8 bits
• High Endurance 1 Trillion (10¹²) Read/Writes
• 38 year Data Retention
• NoDelay™ Writes
• Advanced High-Reliability Ferroelectric Process
• For more, see pdf

Description

The FM25040B is a 4-kilobit nonvolatile memory employing an advanced ferroelectric process. A ferroelectric random access memory or F-RAM is nonvolatile but operates in other respects as a RAM. It provides reliable data retention for 38 years while eliminating the complexities, overhead, and system level reliability problems caused by EEPROM and other nonvolatile memories.

Features

• Universal Serial Bus (USB) Integration
• Universal Asynchronous Receiver Transmitter (UART)
• Full device operation from a single voltage supply of 3.3 V or 5 V
• Low power consumption in suspend mode
• Integrated 24 MHz oscillator
• Integrated 3.3 V regulator
• Integrated flash to store device configuration
• Software support for ease of development
• For more, see pdf

Functional Overview

Cypress’s USB-to-UART bridge controller enables seamless PC connectivity for peripherals with UART interface. It integrates a USB 2.0 Full-Speed device controller, UART, voltage regulator, oscillator and flash memory for storing configuration parameters, offering a cost-effective solution. The controller supports bus-powered and self-powered modes, and enables efficient system power management with suspend and remote wake-up signals. It is available in 28-pin SSOP package.

4K bit Ferroelectric Nonvolatile RAM
 

• Organized as 512 x 8 bits
• High Endurance 100 Trillion (10¹⁴) Read/Writes
• 38 Year Data Retention (@ +75ºC)
• NoDelay™ Writes
• Advanced High-Reliability Ferroelectric Process
• For more, see pdf.

Description

The FM25L04B is a 4-kilobit nonvolatile memory employing an advanced ferroelectric process. A ferroelectric random access memory or F-RAM is nonvolatile and performs reads and writes like a RAM. It provides reliable data retention for 38 years while eliminating the complexities, overhead, and system level reliability problems caused by EEPROM and other nonvolatile memories.

64K bit Ferroelectric Nonvolatile RAM
 

• Organized as 8,192 x 8 bits
• High Endurance 100 Trillion (10¹⁴) Read/Writes
• 38 Year Data Retention (@ +75ºC)
• NoDelay™ Writes
• Advanced High-Reliability Ferroelectric Process
• For more, see pdf

Description

The FM25CL64B is a 64-kilobit nonvolatile memory employing an advanced ferroelectric process. A ferroelectric random access memory or F-RAM is nonvolatile and performs reads and writes like a RAM. It provides reliable data retention for 38 years while eliminating the complexities, overhead, and system level reliability problems caused by EEPROM and other nonvolatile memories.

• Organized as 512 x 8 bits
• High Endurance 10¹² Read/Writes
• 38 Year Data Retention
• NoDelay™ Writes
• Advanced High-Reliability Ferroelectric Process
• For more, see pdf

Description

The FM24C04B is a 4-kilobit nonvolatile memory employing an advanced ferroelectric process. A ferroelectric random access memory or FRAM is nonvolatile and performs reads and writes like a RAM. It provides reliable data retention for 38 years while eliminating the complexities, overhead, and system level reliability problems caused by EEPROM and other nonvolatile memories.

16K bit Ferroelectric Nonvolatile RAM
 

• Organized as 2,048 x 8 bits
• High Endurance 1 Trillion (10¹²) Read/Writes
• 38 year Data Retention
• NoDelay™ Writes
• Advanced High-Reliability Ferroelectric Process
• For more, see pdf

Description

The FM25C160B is a 16-kilobit nonvolatile memory employing an advanced ferroelectric process. A ferroelectric random access memory or F-RAM is nonvolatile but operates in other respects as a RAM. It provides reliable data retention for 38 years while eliminating the complexities, overhead, and system level reliability problems caused by EEPROM and other nonvolatile memories.

Features  

• True dual-ported memory cells that enable simultaneous access of the same memory location
• Synchronous pipelined operation
• Pipelined output mode allows fast operation
• 0.18 micron CMOS for optimum speed and power
• High speed clock to data access
• 3.3V low power
  • Active as low as 225 mA (typ.)
  • Standby as low as 55 mA (typ.)
• For more, see pdf

Functional Description

The FLEx36™ family includes 2-Mbit pipelined, synchronous, true dual-port static RAMs that are high speed, low power 3.3V CMOS. Two ports are provided, permitting independent, simultaneous access to any location in memory. A particular port can write to a certain location while another port is reading that location. The result of writing to the same location by more than one port at the same time is undefined. Registers on control, address, and data lines allow for minimal setup and hold time.      More...

1M bit Ferroelectric Nonvolatile RAM

• Organized as 131,072 x 8 bits
• High Endurance 100 Trillion (10¹⁴) Read/Writes
• 10 year Data Retention
• NoDelay™ Writes
• Advanced High-Reliability Ferroelectric Proces
• For more, see pdf

Description

The FM24V10 is a 1-megabit nonvolatile memory employing an advanced ferroelectric process. A ferroelectric random access memory or F-RAM is nonvolatile and performs reads and writes like a RAM. It provides reliable data retention for 10 years while eliminating the complexities, overhead, and system level reliability problems caused by  EEPROM and other nonvolatile memories.

High Integration Device Replaces Multiple Parts

• Serial Nonvolatile Memory
• Real-time Clock (RTC) with Alarm
• Low VDD Detection Drives Reset
• Watchdog Window Timer
• Early Power-Fail Warning/NMI
• 16-bit Nonvolatile Event Counter
• Serial Number with Write-lock for Security
• For more, see pdf.

Description

The FM33256B device integrates F-RAM memory with the most commonly needed functions for processor-based systems. Major features include nonvolatile memory, real-time clock, low-VDD reset, watchdog timer, nonvolatile event counter, lockable 64-bit serial number area, and general purpose comparator that can be used for a power-fail (NMI) interrupt or other purpose. The device operate from 2.7 to 3.6V.

1Mbit Ferroelectric Nonvolatile RAM

• Organized as 128Kx8
• High Endurance 100 Trillion (10¹⁴) Read/Writes
• NoDelay™ Writes
• Page Mode Operation to 33MHz
• Advanced High-Reliability Ferroelectric Process
• For more, see pdf.

General Description

The FM28V100 is a 128K x 8 nonvolatile memory that reads and writes like a standard SRAM. A ferroelectric random access memory or F-RAM is nonvolatile, which means that data is retained after power is removed. It provides data retention for over 10 years while eliminating the reliability concerns, functional disadvantages, and system design complexities of battery-backed SRAM (BBSRAM). Fast write timing and very high write endurance make F-RAM superior to other types of memory.

2Mbit Ferroelectric Nonvolatile RAM

• Organized as 128Kx16
• Configurable as 256Kx8 Using /UB, /LB
• 10¹⁴ Read/Write Cycles
• NoDelay™ Writes
• Page Mode Operation to 33MHz
• Advanced High-Reliability Ferroelectric Process

Description

The FM21LD16 is a 128Kx16 nonvolatile memory that reads and writes like a standard SRAM. A ferroelectric random access memory or F-RAM is nonvolatile, which means that data is retained after power is removed. It provides data retention for over 10 years while eliminating the reliability concerns, functional disadvantages, and system design complexities of battery-backed SRAM (BBSRAM). Fast write timing and high write endurance make the F-RAM superior to other types of memory. In-system operation of the FM21LD16 is very similar to other RAM devices and can be used as a drop-in replacement for standard SRAM. Read and write cycles may be triggered by /CE or simply by changing the address. The F-RAM memory is nonvolatile due to its unique ferroelectric memory process. These features make the FM21LD16 ideal for nonvolatile memory applications requiring frequent or rapid writes in the form of an SRAM.

256K bit Ferroelectric Nonvolatile RAM
 

• Organized as 32,768 x 8 bits
• High Endurance 100 Trillion (10¹⁴) Read/Writes
• 38 Year Data Retention (@ +75ºC)
• NoDelay™ Writes
• Advanced High-Reliability Ferroelectric Process
• For more, see pdf.

Description

The FM25W256 is a 256-kilobit nonvolatile memory employing an advanced ferroelectric process. A ferroelectric random access memory or F-RAM is nonvolatile and performs reads and writes like a RAM. It provides reliable data retention for 38 years while eliminating the complexities, overhead, and system level reliability problems caused by EEPROM and other nonvolatile memories.

128K bit Ferroelectric Nonvolatile RAM
 

• Organized as 16,384 x 8 bits
• High Endurance 100 Trillion (10¹⁴) Read/Writes
• 10 Year Data Retention
• NoDelay™ Writes
• Advanced High-Reliability Ferroelectric Process
• For more, see pdf.

Description

The FM25V01 is a 128-kilobit nonvolatile memory employing an advanced ferroelectric process. A ferroelectric random access memory or F-RAM is nonvolatile and performs reads and writes like a RAM. It provides reliable data retention for 10 years while eliminating the complexities, overhead, and system level reliability problems caused by Serial Flash and other nonvolatile memories.

256K bit Ferroelectric Nonvolatile RAM

• Organized as 32,768 x 8 bits
• High Endurance 100 Trillion (10¹⁴) Read/Writes
• 10 Year Data Retention
• NoDelay™ Writes
• Advanced High-Reliability Ferroelectric Process
• For more, see pdf.

Description

The FM25V02 is a 256-kilobit nonvolatile memory employing an advanced ferroelectric process. A ferroelectric random access memory or F-RAM is nonvolatile and performs reads and writes like a RAM. It provides reliable data retention for 10 years while eliminating the complexities, overhead, and system level reliability problems caused by Serial Flash and other nonvolatile memories.

4Mbit Ferroelectric Nonvolatile RAM

• Organized as 256Kx16
• Configurable as 512Kx8 Using /UB, /LB
• 10¹⁴ Read/Write Cycles
• NoDelay™ Writes
• Page Mode Operation to 40MHz
• Advanced High-Reliability Ferroelectric Process
• For more, see pdf
   

Description

The FM22LD16 is a 256Kx16 nonvolatile memory that reads and writes like a standard SRAM. A ferroelectric random access memory or F-RAM is nonvolatile, which means that data is retained after power is removed. It provides data retention for over 10 years while eliminating the reliability concerns, functional disadvantages, and system design complexities of battery-backed SRAM (BBSRAM). Fast write timing and high write endurance make the F-RAM superior to other types of memory.

4Mbit Ferroelectric Nonvolatile RAM

• Organized as 256Kx16
• Configurable as 512Kx8 Using /UB, /LB
• 10¹⁴ Read/Write Cycles
• NoDelay™ Writes
• Page Mode Operation to 40MHz
• Advanced High-Reliability Ferroelectric Process
• For more, see pdf

Description

The FM22L16 is a 256Kx16 nonvolatile memory that reads and writes like a standard SRAM. A ferroelectric random access memory or F-RAM is nonvolatile, which means that data is retained after power is removed. It provides data retention for over 10 years while eliminating the reliability concerns, functional disadvantages, and system design complexities of battery-backed SRAM (BBSRAM). Fast write timing and high write endurance make the F-RAM superior to other types of memory.

512K bit Ferroelectric Nonvolatile RAM
 

• Organized as 65,536 x 8 bits
• High Endurance 100 Trillion (10¹⁴) Read/Writes
• 10 Year Data Retention
• NoDelay™ Writes
• Advanced High-Reliability Ferroelectric Process
• For more, see pdf.

Description

The FM25V05 is a 512-kilobit nonvolatile memory employing an advanced ferroelectric process. A ferroelectric random access memory or F-RAM is nonvolatile and performs reads and writes like a RAM. It provides reliable data retention for 10 years while eliminating the complexities, overhead, and system level reliability problems caused by Serial Flash and other nonvolatile memories.

1M bit Ferroelectric Nonvolatile RAM
 

• Organized as 131,072 x 8 bits
• High Endurance 100 Trillion (10¹⁴) Read/Writes
• 10 Year Data Retention
• NoDelay™ Writes
• Advanced High-Reliability Ferroelectric Process
• For more, see pdf.

Description

The FM25V10 is a 1-megabit nonvolatile memory employing an advanced ferroelectric process. A ferroelectric random access memory or F-RAM is nonvolatile and performs reads and writes like a RAM. It provides reliable data retention for 10 years while eliminating the complexities, overhead, and system level reliability problems caused by Serial Flash and other nonvolatile memories.

2M bit Ferroelectric Nonvolatile RAM
 

• Organized as 256K x 8 bits
• High Endurance 100 Trillion (10¹⁴) Read/Writes
• 10 Year Data Retention
• NoDelay™ Writes
• Advanced High-Reliability Ferroelectric Process
• For more, see pdf.

Description

The FM25V20 is a 2-megabit nonvolatile memory employing an advanced ferroelectric process. A ferroelectric random access memory or F-RAM is nonvolatile and performs reads and writes like a RAM. It provides reliable data retention for 10 years while eliminating the complexities, overhead, and system level reliability problems caused by Serial  Flash and other nonvolatile memories.

64K bit Ferroelectric Nonvolatile RAM

• Organized as 8,192 x 8 bits
• High Endurance 1 Trillion (10¹²) Read/Writes
• 38 Year Data Retention
• NoDelay™ Writes
• Advanced High-Reliability Ferroelectric Process
• For more, see pdf

Description

The FM24C64B is a 64-kilobit nonvolatile memory employing an advanced ferroelectric process. A ferroelectric random access memory or FRAM is nonvolatile and performs reads and writes like a RAM. It provides reliable data retention for 38 years while eliminating the complexities, overhead, and system level reliability problems caused by EEPROM and other nonvolatile memories.

256K bit Ferroelectric Nonvolatile RAM

• Organized as 32,768 x 8 bits
• High Endurance 100 Trillion (10¹⁴) Read/Writes
• 10 year Data Retention
• NoDelay™ Writes
• Advanced High-Reliability Ferroelectric Process
• For more, see pdf

Description

The FM24V02 is a 256Kbit nonvolatile memory employing an advanced ferroelectric process. A ferroelectric random access memory or F-RAM is nonvolatile and performs reads and writes like a RAM. It provides reliable data retention for 10 years while eliminating the complexities, overhead, and system level reliability problems caused by EEPROM and other nonvolatile memories.

512K bit Ferroelectric Nonvolatile RAM

• Organized as 65,536 x 8 bits
• High Endurance 100 Trillion (10¹⁴) Read/Writes
• 10 year Data Retention
• NoDelay™ Writes
• Advanced High-Reliability Ferroelectric Process
• For more, see pdf

Description

The FM24V05 is a 512Kbit nonvolatile memory employing an advanced ferroelectric process. A ferroelectric random access memory or F-RAM is nonvolatile and performs reads and writes like a RAM. It provides reliable data retention for 10 years while eliminating the complexities, overhead, and system level reliability problems caused by EEPROM and other nonvolatile memories.

• High performance, low-power USB 2.0 Hub, optimized for low cost designs with minimum Bill-of-material
• USB 2.0 hub controller
• Very low power consumption
• Highly integrated solution for reduced BOM cost
• Downstream port management
• Maximum configurability
• Available in space saving 48-pin (7 × 7 mm) TQFP and 28-pin (5 × 5 mm) QFN packages
• Supports 0 °C to 70 °C temperature range
   

Functional Overview

The Cypress CY7C6563X USB 2.0 Hubs are low power hub solutions for USB which provide maximum transfer efficiency. The CY7C6563X USB 2.0 Hubs integrate 1.5 kohm upstream pull-up resistors for full speed operation and all downstream 15 kohm pull-down resistors and series termination resistors on all upstream and downstream D+ and D- pins. This results in optimization of system costs by providing built-in support for the USB 2.0 specification.

• High-performance, low-power USB 2.0 hub, optimized for low-cost designs with minimum bill-of-material (BOM).
• USB 2.0 hub controller
• Very low-power consumption
• Highly integrated solution for reduced BOM cost
• Downstream port management
• Maximum configurability
• Available in space saving 48-pin (7 × 7 mm) TQFP and 28-pin (5 × 5 mm) QFN packages
• Supports 0 °C to +70 °C temperature range
• For more, see pdf
   

Functional Overview

The Cypress CY7C65642 USB 2.0 Hubs are low-power hub solutions for USB which provide maximum transfer efficiency with no TT multiplexing between downstream ports. The CY7C65642 USB 2.0 Hubs integrate 1.5 kΩ upstream pull-up resistors for full speed operation and all downstream 15 kΩ pull-down resistors and series termination resistors on all upstream and downstream D+ and D– pins. This results in optimization of system costs by providing built-in support for the USB 2.0 specification.

Features

• Universal serial bus (USB) integration
  • USB 3.0 and USB 2.0 peripherals compliant with USB 3.0 specification 1.0
  • 5-Gbps USB 3.0 PHY compliant with PIPE 3.0
  • High-speed On-The-Go (HS-OTG) host and peripheral compliant with OTG Supplement Version 2.0
  • Thirty-two physical endpoints
  • Support for battery charging Spec 1.1 and accessory charger adaptor (ACA) detection
• General Programmable Interface (GPIF™ II)
  • Programmable 100-MHz GPIF II enables connectivity to a wide range of external devices
  • 8-, 16-, and 32-bit data bus
  • As many as16 configurable control signals
• For more, see pdf

Functional Overview

Cypress’s EZ-USB FX3 is the next-generation USB 3.0 peripheral controller, providing integrated and flexible features. FX3 has a fully configurable, parallel, general programmable interface called GPIF II, which can connect to any processor, ASIC, or FPGA. GPIF II is an enhanced version of the GPIF in FX2LP, Cypress’s flagship USB 2.0 product. It provides easy and glueless connectivity to popular interfaces, such as asynchronous SRAM, asynchronous and synchronous address data multiplexed interfaces, and parallel ATA.