Features

• Temperature ranges
  • Industrial: –40°C to 85°C
  • Automotive-A: –40°C to 85°C
  • Automotive-E: –40°C to 125°C
• Pin and function compatible with CY7C1011BV33
• High speed
  • tAA = 10 ns (Industrial and Automotive-A)
  • tAA = 12 ns (Automotive-E)
• Low active power
  • 360 mW (max) (Industrial and Automotive-A)
• For more, see pdf

Functional Description

The CY7C1011CV33 is a high performance complementary metal oxide semiconductor (CMOS) static RAM organized as 131,072 words by 16 bits. This device has an automatic power down feature that significantly reduces power consumption when deselected.

Features

• 10 MHz to 100–133 MHz operating range
• Zero input and output propagation delay
• Multiple low skew outputs
• One input drives five outputs (CY2305C)
• One input drives nine outputs, grouped as 4 4 1 (CY2309C)
• 50 ps typical cycle-to-cycle jitter (15 pF, 66 MHz)
• Test mode to bypass phase locked loop (PLL) (CY2309C) only
• Available in space saving 16-pin 150 Mil small outline integrated circuit (SOIC) or 4.4 mm thin shrunk small outline package (TSSOP) packages (CY2309C), and 8-pin, 150 Mil SOIC package (CY2305C)
• 3.3 V operation
• Commercial, industrial and automotive-A flows available

Functional Description

The CY2305C and CY2309C are die replacement parts for CY2305 and CY2309.

The CY2309C is a low-cost 3.3 V zero delay buffer designed to distribute high speed clocks and is available in a 16-pin SOIC or TSSOP package. The CY2305C is an 8-pin version of the CY2309C. It accepts one reference input and drives out five low skew clocks. The -1H versions of each device operate up to 100–133 MHz frequencies and have higher drive than the -1 devices. All parts have on-chip phase locked loops (PLLs) which lock to an input clock on the REF pin. The PLL feedback is on-chip and is obtained from the CLKOUT pad.

Features

• Automotive Electronics Council (AEC) Q100 qualified
• Powerful Harvard Architecture Processor
• Advanced Peripherals (PSoC® Blocks)
• CY8C22345H devices integrate Immersion® TouchSense® haptics technology for ERM drive control
• Precision, Programmable Clocking
• Flexible On-Chip Memory
• Optimized CapSense® resource
• Versatile analog mux
• For more, see pdf

PSoC Functional Overview

The PSoC programmable system-on-chip series of products consists of many devices. These devices are designed to replace multiple traditional MCU-based system components with one low cost single-chip programmable device. PSoC devices include configurable blocks of analog and digital logic, as well as programmable interconnects. This architecture enables the user to create customized peripheral configurations that match the requirements of each individual application.

• Powerful Harvard-architecture processor
• Advanced peripherals (PSoC® blocks)
• Flexible on-chip memory
• Complete development tools
• Precision, programmable clocking
• Programmable pin configurations
• Versatile analog mux
• Additional system resources
• For more, see pdf

The PSoC family consists of many devices with on-chip controllers. These devices are designed to replace multiple traditional MCU-based system components with one low-cost single-chip programmable component. A PSoC device includes configurable blocks of analog and digital logic, and programmable interconnect. This architecture makes it possible for you to create customized peripheral configurations, to match the requirements of each individual application. Additionally, a fast central processing unit (CPU), flash program memory, SRAM data memory, and configurable I/O are included in a range of convenient pinouts.

Features

• Powerful Harvard-architecture processor
• Advanced peripherals (PSoC® blocks)
• Precision, programmable clocking
• Flexible on-chip memory
• Programmable pin configurations
• New CY8C24x23A PSoC device
• Additional system resources
• Complete development tools
• For more, see pdf

PSoC Functional Overview

The PSoC family consists of many programmable system-on-chips with on-chip controller devices. These devices are designed to replace multiple traditional MCU-based system components with a low-cost single-chip programmable device. PSoC devices include configurable blocks of analog and digital logic, and programmable interconnects. This architecture makes it possible for you to create customized peripheral configurations that match the requirements of each individual application.

Features

• Automotive Electronics Council (AEC) Q100 qualified
• Powerful Harvard-architecture processor
• Advanced peripherals
• Flexible on-chip memory
• Complete development tools
• Precision, programmable clocking
• Programmable pin configurations
• Versatile analog mux
• Additional system resources
• For more, see pdf
   

PSoC Functional Overview

The PSoC family consists of many devices with on-chip controllers. These devices are designed to replace multiple traditional microcontroller unit (MCU)-based system components with one, low-cost single-chip programmable component. A PSoC device includes configurable blocks of analog and digital logic, and programmable interconnect. This architecture makes it possible for you to create customized peripheral configurations, to match the requirements of each individual application.

Features

• Temperature Ranges
  • Commercial: 0°C to 70°C
  • Industrial: –40°C to 85°C
  • Automotive-A: –40°C to 85°C
• High speed
  • t_AA = 15 ns
• Low active power
  • 1540 mW (max.)
• Low CMOS standby power (L version)
• For more, see pdf
   

Functional Description

The CY7C1041BN is a high-performance CMOS static RAM organized as 262,144 words by 16 bits.

Writing to the device is accomplished by taking Chip Enable (CE) and Write Enable (WE) inputs LOW. If Byte Low Enable (BLE) is LOW, then data from I/O pins (I/O₀ through I/O₇), is written into the location specified on the address pins (A₀ through A₁₇).

• Very high speed: 45 ns
• Temperature ranges
• Automotive-A: –40 °C to 85 °C
• Automotive-E: –40 °C to 125 °C
• Wide voltage range: 2.20 V to 3.60 V
• Pin compatible with CY62147DV30
• Ultra low standby power
  • Typical standby current: 1 µA
  • Maximum standby current: 7 µA (Automotive-A)
• For more, see pdf
   

The CY62147EV30 is a high performance CMOS static RAM (SRAM) organized as 256K words by 16 bits. This device features advanced circuit design to provide ultra low active current. It is ideal for providing More Battery Life™ (MoBL®) in portable applications such as cellular telephones. The device also has an automatic power down feature that significantly reduces power consumption when addresses are not toggling.

Features

• Automotive Electronics Council (AEC) Q100 qualified
• Powerful Harvard-architecture processor
• Advanced peripherals (PSoC® blocks)
• Flexible on-chip memory
• Complete development tools
• Precision, programmable clocking
• Programmable pin configurations
• Versatile analog mux
• Additional system resources
• For more, see pdf

PSoC Functional Overview

The PSoC family consists of many devices with on-chip controllers. These devices are designed to replace multiple traditional microcontroller unit (MCU)-based system components with one, low-cost single-chip programmable component. A PSoC device includes configurable blocks of analog and digital logic, and programmable interconnect. This architecture makes it possible for you to create customized peripheral configurations, to match the requirements of each individual application.

Features

• Temperature ranges
  • Automotive -A: –40 °C to 85 °C
  • Automotive-E: –40 °C to 125 °C
• High speed
  • tAA = 10 ns
• Low active power
  • 360 mW (max)
• 2.0 V data retention
• Automatic power down when deselected
• TTL-compatible inputs and outputs
• Easy memory expansion with CE and OE features

Functional Description

The CY7C1049CV33 Automotive is a high performance CMOS Static RAM organized as 524,288 words by eight bits. Easy memory expansion is provided by an active LOW Chip Enable (CE), an active LOW Output Enable (OE), and three-state drivers. Writing to the device is accomplished by taking Chip Enable (CE) and Write Enable (WE) inputs LOW. Data on the eight I/O pins (I/O0 through I/O7) is then written into the location specified on the address pins (A0 through A18).

Features

• Automotive Electronics Council (AEC) Q100 qualified
• Powerful Harvard-architecture processor
• Advanced peripherals (PSoC® blocks)
• Precision, programmable clocking
• Flexible on-chip memory
• Programmable pin configurations
• Additional system resources
• Complete development tools
• For more, see pdf
   

PSoC Functional Overview
The PSoC programmable system-on-chip family consists of many devices with On-Chip Controllers. These devices are designed to replace multiple traditional microcontroller unit (MCU)-based system components with one, low cost single-chip programmable device.
 

Features

• Very high-speed: 45 ns
• Temperature ranges:
  • Automotive-A: –40 °C to +85 °C
  • Automotive-E: –40 °C to +125 °C
• Wide voltage range: 2.2 V to 3.6 V
• Pin compatible with CY62128DV30
• Ultra low standby power
  • Typical standby current: 1µA
  • Maximum standby current: 4µA
• For more, see pdf

Functional Description

The CY62128EV30 is a high performance CMOS static RAM module organized as 128K words by 8 bits. This device features advanced circuit design to provide ultra low active current. This is ideal for providing More Battery Life™ (MoBL®) in portable applications such as cellular telephones.
 

• Temperature ranges
  • Automotive-A: –40 °C to 85 °C
  • Automotive-E: –40 °C to 125 °C
• Pin and function compatible with CY7C1041BNV33
• High speed
  • tAA = 10 ns (Automotive-A)
  • tAA = 12 ns (Automotive-E)
• Low active power
  • 432 mW (max)
• Automatic power down when deselected
• TTL-compatible inputs and outputs
• Easy memory expansion with CE and OE features
• Available in Pb-free and non Pb-free 44-pin 400 Mil SOJ, 44-pin TSOP II and 48-ball FBGA packages
   

Functional Description

The CY7C1041CV33 Automotive is a high performance CMOS static RAM organized as 262,144 words by 16 bits.

To write to the device, take Chip Enable (CE) and Write Enable (WE) inputs LOW. If Byte Low Enable (BLE) is LOW, then data from I/O pins (I/O0 through I/O7), is written into the location specified on the address pins (A0 through A17). If Byte High Enable (BHE) is LOW, then data from I/O pins (I/O8 through I/O15) is written into the location specified on the address pins (A0 through A17).