Features

• True Dual-Ported memory cells which allow simultaneous access of the same memory location
• 32K x 16 organization (CY7C027V/027VN/027AV)
• 64K x 16 organization (CY7C028V)
• 32K x 18 organization (CY7C037V/037AV)
• 64K x 18 organization (CY7C038V)
• 0.35 micron CMOS for optimum speed and power
• High speed access: 15, 20, and 25 ns
• Low operating power
• Active: I_CC = 115 mA (typical)
• For more, see pdf
   

Functional Description

The CY7C027V/027AV/028V and CY7037AV/038V are low power CMOS 32K, 64K x 16/18 dual-port static RAMs. Various arbitration schemes are included on the devices to handle situations when multiple processors access the same piece of data. Two ports are provided, permitting independent, asynchronous access for reads and writes to any location in memory. 

General Description

With its unique array of configurable blocks, PSoC® 5LP is a true system-level solution providing microcontroller unit (MCU), memory, analog, and digital peripheral functions in a single chip. The CY8C52LP family offers a modern method of signal acquisition, signal processing, and control with high accuracy, high bandwidth, and high flexibility. Analog capability spans the range from thermocouples (near DC voltages) to ultrasonic signals.

The CY8C52LP family can handle dozens of data acquisition channels and analog inputs on every GPIO pin. The CY8C52LP family is also a high-performance configurable digital system with some part numbers including interfaces such as USB and multimaster I2C. In addition to communication interfaces, the CY8C52LP family has an easy to configure logic array, flexible routing to all I/O pins, and a high-performance 32-bit ARM®Cortex™-M3 microprocessor core.

Designers can easily create system level designs using a rich library of prebuilt components and boolean primitives using PSoC Creator™, a hierarchical schematic design entry tool. The CY8C52LP family provides unparalleled opportunities for digital bill of materials integration while easily accommodating last minute design changes through simple firmware updates.

Features

• 32-bit ARM Cortex-M3 CPU core
• Low voltage, ultra low power
• Versatile I/O system
• Digital peripherals
• Analog peripherals (1.71 V ≤ VDDA ≤ 5.50 V)
• Programming, debug, and trace
• Precision, programmable clocking
• Temperature and packaging
• For more, see data sheet pdf

General Description

With its unique array of configurable blocks, PSoC® 5LP is a true system-level solution providing microcontroller unit (MCU), memory, analog, and digital peripheral functions in a single chip. The CY8C58LP family offers a modern method of signal acquisition, signal processing, and control with high accuracy, high bandwidth, and high flexibility. Analog capability spans the range from thermocouples (near DC voltages) to ultrasonic signals.

The CY8C58LP family can handle dozens of data acquisition channels and analog inputs on every GPIO pin. The CY8C58LP family is also a high-performance configurable digital system with some part numbers including interfaces such as USB, multimaster I2C, and controller area network (CAN). In addition to communication interfaces, the CY8C58LP family has an easy to configure logic array, flexible routing to all I/O pins, and a high-performance 32-bit ARM® Cortex™-M3 microprocessor core.

Designers can easily create system-level designs using a rich library of prebuilt components and boolean primitives using PSoC Creator™, a hierarchical schematic design entry tool. The CY8C58LP family provides unparalleled opportunities for analog and digital bill of materials integration while easily accommodating last minute design changes through simple firmware updates.

Features

• 32-bit ARM Cortex-M3 CPU core
• Low voltage, ultra low power
• Versatile I/O system
• Digital peripherals
• Analog peripherals (1.71 V ≤ VDDA ≤ 5.5 V)
• Programming, debug, and trace
• Precision, programmable clocking
• Temperature and packaging
• For more, see data sheet pdf

General Description

With its unique array of configurable blocks, PSoC® 5LP is a true system level solution providing microcontroller unit (MCU), memory, analog, and digital peripheral functions in a single chip. The CY8C54LP family offers a modern method of signal acquisition, signal processing, and control with high accuracy, high bandwidth, and high flexibility. Analog capability spans the range from thermocouples (near DC voltages) to ultrasonic signals.

The CY8C54LP family can handle dozens of data acquisition channels and analog inputs on every GPIO pin. The CY8C54LP family is also a high-performance configurable digital system with some part numbers including interfaces such as USB and multi-master I2C. In addition to communication interfaces, the CY8C54LP family has an easy to configure logic array, flexible routing to all I/O pins, and a high-performance 32-bit ARM® Cortex™-M3 microprocessor core.

Designers can easily create system-level designs using a rich library of prebuilt components and boolean primitives using PSoC® Creator™, a hierarchical schematic design entry tool. The CY8C54LP family provides unparalleled opportunities for digital and analog bill of materials integration while easily accommodating last minute design changes through simple firmware updates.

Features

• 32-bit ARM Cortex-M3 CPU core
• Low voltage, ultra low power
• Versatile I/O system
• Digital peripherals
• Analog peripherals (1.71 V ≤ VDDA ≤ 5.5 V)
• Programming, debug, and trace
• Precision, programmable clocking
• Temperature and packaging
• For more, see data sheet pdf

General Description

With its unique array of configurable blocks, PSoC® 5LP is a true system level solution providing MCU, memory, analog, and digital peripheral functions in a single chip. The CY8C56LP family offers a modern method of signal acquisition, signal processing, and control with high accuracy, high bandwidth, and high flexibility. Analog capability spans the range from thermocouples (near DC voltages) to ultrasonic signals.

The CY8C56LP family can handle dozens of data acquisition channels and analog inputs on every GPIO pin. The CY8C56LP family is also a high performance configurable digital system with some part numbers including interfaces such as USB and multimaster I2C, and controller area network (CAN). In addition to communication interfaces, the CY8C56LP family has an easy to configure logic array, flexible routing to all I/O pins, and a high performance 32-bit ARM® Cortex™-M3 microprocessor core.

Designers can easily create system level designs using a rich library of prebuilt components and boolean primitives using PSoC Creator™, a hierarchical schematic design entry tool. The CY8C56LP family provides unparalleled opportunities for analog and digital bill of materials integration while easily accommodating last minute design changes through simple firmware updates.

Features

• 32-bit ARM Cortex-M3 CPU core
• Low voltage, ultra low power
• Versatile I/O system
• Digital peripherals
• Analog peripherals (1.71 V ≤ VDDA ≤ 5.5 V)
• Programming, debug, and trace
• Precision, programmable clocking
• Temperature and packaging
• For more, see pdf.

• QuietZone™ Controller
• Low power CapSense® block with SmartSense™ auto-tuning
• Driven shield available on five GPIO pins
• Powerful Harvard-architecture processor
• Flexible on-chip memory
• Four clock sources
• Programmable pin configurations
• Versatile analog mux
• Additional system resources
• Complete development tools
• Sensor and Package options
• For more, see pdf

PSoC® Functional Overview

The PSoC family consists of many devices with on-chip controllers. These devices are designed to replace multiple traditional MCU-based system components with one low-cost single-chip programmable component. A PSoC device includes configurable blocks of analog and digital logic, and programmable interconnect. This architecture makes it possible for you to create customized peripheral configurations, to match the requirements of each individual application. Additionally, a fast central processing unit (CPU), flash program memory, SRAM data memory, and configurable I/O are included in a range of convenient pinouts.

Features

• Device Operating Voltage Options:
  • MoBL Clock M200 Family: 1.8V
• Selectable clock output voltages for both MoBL Clock M200 and M500:
  • 1.5V, 1.8V, 2.5V, 3.0V, or 3.3V
• Fully integrated ultra low power phase-locked loops (PLLs)
• Input reference clock frequency range: 1–48 MHz
• Output clock frequency range: 3–50 MHz
• Three I2C™ programmable output clocks
• Programmable output drive strengths
• For more, see pdf
   

General Description

2 Configurable PLLs

The MoBL® Clock M200/M500 Family of products are two-PLL Clock Generator ICs designed for cell phone, portable, or consumer electronics applications. It can be used to generate two independent output frequencies ranging from 3 to 50MHz from a single input reference clock.

Features

• Low jitter crystal oscillator (XO)
• Less than 1 ps typical root mean square (RMS) phase jitter
• Differential low-voltage positive emitter coupled logic (LVPECL) output
• Output frequency from 50 MHz to 690 MHz
• Frequency margining through I²C bus
• Factory-configured or field-programmable
• Integrated phase-locked loop (PLL)
• Pb-free package: 5.0 × 3.2 mm leadless chip carrier (LCC)
• Supply voltage: 3.3 V or 2.5 V
• Commercial and industrial temperature ranges
   

Functional Description

The CY2XF24 is a high-performance and high-frequency XO. It uses a Cypress-proprietary low-noise PLL to synthesize the frequency from an integrated crystal. The output frequency can be changed using the I2C bus serial interface, allowing easy frequency margin testing in applications.

Features

• Low Jitter Crystal Oscillator (XO)
• Less than 1 ps Typical RMS Phase Jitter
• Differential LVDS Output
• Output Frequency from 50 MHz to 690 MHz
• Two Frequency Margining Control Pins (FS0, FS1)
• Factory Configured or Field Programmable
• Integrated Phase-Locked Loop (PLL)
• Supply Voltage: 3.3V or 2.5V
• Pb-Free Package: 5.0 x 3.2 mm LCC
• Commercial and Industrial Temperature Ranges
   

Functional Description

The CY2XF33 is a high performance and high frequency Crystal Oscillator (XO). It uses a Cypress proprietary low noise PLL to synthesize the frequency from an integrated crystal. The output frequency can be changed through two select pins, allowing easy frequency margin testing in applications.

Features

• True dual port memory enables simultaneous access to the shared array from each port
• Synchronous pipelined operation with single data rate (SDR) operation on each port
  • SDR interface at 200 MHz
  • Up to 28.8 Gb/s bandwidth (200 MHz × 72-bit × 2 ports)
• Selectable pipelined or flow-through mode
• 1.5 V or 1.8 V core power supply
• Commercial and Industrial temperature
• IEEE 1149.1 JTAG boundary scan
• Available in 484-ball PBGA (× 72) and 256-ball FBGA (× 36 and × 18) packages
• For more, see pdf

Functional Description

The FullFlex™ dual port SRAM families consist of 2-Mbit, 4-Mbit, 9-Mbit, 18-Mbit, and 36-Mbit synchronous, true dual port static RAMs that are high speed, low power 1.8 V or 1.5 V CMOS. Two ports are provided, enabling simultaneous access to the array. Simultaneous access to a location triggers deterministic access control. For FullFlex72 these ports operate independently with 72-bit bus widths and each port is independently configured for two pipelined stages. Each port is also configured to operate in pipelined or flow through mode.

Features

• Powerful Harvard-architecture processor
• Advanced peripherals (PSoC® blocks)
• Flexible on-chip memory
• Complete development tools
• Precision, programmable clocking
• Programmable pin configurations
• Additional system resources
   

PSoC Functional Overview

The PSoC family consists of many programmable system-on-chip controller devices. These devices are designed to replace multiple traditional MCU-based system components with a low cost single-chip programmable component. A PSoC device includes configurable blocks of analog and digital logic, and programmable interconnect. This architecture allows you to create customized peripheral configurations, to match the requirements of each individual application. Additionally, a fast CPU, Flash program memory, SRAM data memory, and configurable I/O are included in a range of convenient pinouts.

• 18 Mbit density (1 M x 18, 512 K x 36)
• 450-MHz clock for high bandwidth
• Two-word burst for reducing address bus frequency
• Double data rate (DDR) interfaces (data transferred at 900 MHz) at 450 MHz
• Available in 2.0 clock cycle latency
• For more, see pdf
   

Functional Description

The CY7C1148KV18, and CY7C1150KV18 are 1.8 V Synchronous Pipelined SRAMs equipped with DDR II+ architecture. The DDR II+ consists of an SRAM core with advanced synchronous peripheral circuitry. Addresses for read and write are latched on alternate rising edges of the input (K) clock.

• Separate independent read and write data ports
  • Supports concurrent transactions
• 550-MHz clock for high bandwidth
• Four-word burst for reducing address bus frequency
• Double data rate (DDR) interfaces on both read and write ports (data transferred at 1100 MHz) at 550 MHz
• Available in 2.5 clock cycle latency
• For more, see pdf
   

Functional Description

The CY7C1163KV18, and CY7C1165KV18 are 1.8 V Synchronous Pipelined SRAMs, equipped with QDR II+ architecture. Similar to QDR II architecture, QDR II+ architecture consists of two separate ports: the read port and the write port to access the memory array. The read port has dedicated data outputs to support read operations and the write port has dedicated data inputs to support write operations. QDR II+ architecture has separate data inputs and data outputs to completely eliminate the need to ‘turnaround’ the data bus that exists with common I/O devices. Each port is accessed through a common address bus. Addresses for read and write addresses are latched on alternate rising edges of the input (K) clock.

• 18-Mbit density (1 M × 18, 512 K × 36)
• 550-MHz clock for high bandwidth
• Two-word burst for reducing address bus frequency
• Double data rate (DDR) interfaces (data transferred at 1100 MHz) at 550 MHz
• Available in 2.5 clock cycle latency
• Two input clocks (K and K) for precise DDR timing
• Echo clocks (CQ and CQ) simplify data capture in high-speed systems
• For more, see pdf

Functional Description

The CY7C1168KV18, and CY7C1170KV18 are 1.8 V synchronous pipelined SRAMs equipped with DDR II+ architecture. The DDR II+ consists of an SRAM core with advanced synchronous peripheral circuitry. Addresses for read and write are latched on alternate rising edges of the input (K) clock.

• 18 Mbit density (2 M x 8, 1 M x 18)
• 333-MHz clock for high bandwidth
• Two-word burst for reducing address bus frequency
• Double data rate (DDR) interfaces (data transferred at 666 MHz) at 333 MHz
• For more, see pdf
   

Functional Description

The CY7C1392KV18 and CY7C1393KV18 are 1.8 V Synchronous Pipelined SRAMs, equipped with DDR II SIO (double data rate separate I/O) architecture. The DDR II SIO consists of two separate ports: the read port and the write port to access the memory array. The read port has data outputs to support read operations and the write port has data inputs to support write operations. The DDR II SIO has separate data inputs and data outputs to completely eliminate the need to ‘turnaround’ the data bus required with common I/O devices. Access to each port is accomplished through a common address bus. Addresses for read and write are latched on alternate rising edges of the input (K) clock.

• 18 Mbit density (1 M x 18, 512 K x 36)
• 333-MHz clock for high bandwidth
• Four-word burst for reducing address bus frequency
• Double data rate (DDR) interfaces (data transferred at 666 MHz) at 333 MHz
• Two input clocks (K and K) for precise DDR timing
• Two input clocks for output data (C and C) to minimize clock skew and flight time mismatches
• For more, see pdf
   

Functional Description

CY7C1319KV18 and CY7C1321KV18 are 1.8 V Synchronous Pipelined SRAMs equipped with DDR II architecture. The DDR II consists of an SRAM core with advanced synchronous peripheral circuitry and a two-bit burst counter. Addresses for read and write are latched on alternate rising edges of the input (K) clock.

• Separate independent read and write data ports
  • Supports concurrent transactions
• 450-MHz clock for high bandwidth
• Four-word burst for reducing address bus frequency
• Double data rate (DDR) Interfaces on both read and write ports (data transferred at 900 MHz) at 450 MHz
• Available in 2.0 clock cycle latency
• For more, see pdf
   

Functional Description

The CY7C1143KV18, and CY7C1145KV18 are 1.8 V Synchronous Pipelined SRAMs, equipped with QDR II+ architecture. Similar to QDR II architecture, QDR II+ architecture consists of two separate ports: the read port and the write port to access the memory array. The read port has dedicated data outputs to support read operations and the write port has dedicated data inputs to support write operations. QDR II+ architecture has separate data inputs and data outputs to completely eliminate the need to “turnaround” the data bus that exists with common I/O devices. Each port is accessed through a common address bus. Addresses for read and write addresses are latched on alternate rising edges of the input (K) clock.
 

• 18 Mbit density (1 M x 18, 512 K x 36)
• 550-MHz clock for high bandwidth
• Two-word burst for reducing address bus frequency
• Double data rate (DDR) interfaces (data transferred at 1100 MHz) at 550 MHz
• Available in 2.5 clock cycle latency
• Two input clocks (K and K) for precise DDR timing
  • SRAM uses rising edges only
• Echo clocks (CQ and CQ) simplify data capture in high-speed systems
• Data valid pin (QVLD) to indicate valid data on the output
• For more, see pdf

Functional Description

The CY7C2168KV18, and CY7C2170KV18 are 1.8 V Synchronous Pipelined SRAMs equipped with DDR II+ architecture. The DDR II+ consists of an SRAM core with advanced synchronous peripheral circuitry. Addresses for read and write are latched on alternate rising edges of the input (K) clock.

• One differential (LVPECL, LVDS, HCSL, or CML) input pair distributed to two LVPECL output pairs
• Translates any single-ended input signal to 3.3 V LVPECL levels with resistor bias on INx# input
• 20-ps maximum output-to-output skew
• 480-ps maximum propagation delay
• 0.15-ps maximum additive RMS phase jitter at 156.25 MHz (12-kHz to 20-MHz offset)
• Up to 1.5-GHz operation
• 8-pin SOIC or 8-pin TSSOP package
• 2.5-V or 3.3-V operating voltage
• Commercial and industrial operating temperature range
   

Functional Description

The CY2DP1502 is an ultra-low noise, low-skew, low-propagation delay 1:2 LVPECL fanout buffer targeted to meet the requirements of high-speed clock distribution applications. The device has a fully differential internal architecture that is optimized to achieve low additive jitter and low skew at operating frequencies of up to 1.5 GHz.    

• Separate independent read and write data ports
  • Supports concurrent transactions
• 450 MHz clock for high bandwidth
• Four-word burst for reducing address bus frequency
• Double Data Rate (DDR) interfaces on both read and write ports (data transferred at 900 MHz) at 450 MHz
• Available in 2.0 clock cycle latency
• Two input clocks (K and K) for precise DDR timing
  • SRAM uses rising edges only
• Echo clocks (CQ and CQ) simplify data capture in high speed systems
• For more, see pdf
   

Features

• Very high speed: 45 ns
• Wide voltage range: 2.2V to 3.6V and 4.5V to 5.5V
• Ultra low standby power
  • Typical standby current: 1 μA
  • Maximum standby current: 7 μA
• Ultra low active power
  • Typical active current: 2 mA at f = 1 MHz
• Easy memory expansion with CE and OE features
• Automatic power-down when deselected
• Complementary metal oxide semiconductor (CMOS) for optimum speed and power
• Available in Pb-free 44-pin thin small outline package (TSOP) II package
   

Functional Description

The CY62136ESL is a high performance CMOS static RAM organized as 128K words by 16 bits. This device features advanced circuit design to provide ultra low active current. This is ideal for providing More Battery Life™ (MoBL®) in portable applications such as cellular telephones. The device also has an automatic power down feature that reduces power consumption when addresses are not toggling.

Features

• True Dual-Ported memory cells which enable simultaneous access of the same memory location
• Flow-through and Pipelined devices
• 32 K × 9 organizations (CY7C09179V)
• 64 K × 8 organizations (CY7C09089V)
• 128 K × 8/9 organizations (CY7C09099V/199V)
• 3 Modes
• Flow-Through
• Pipelined
• Burst
• For more, see pdf
   

Functional Description

The CY7C09089V/99V and CY7C09179V/99V are high speed synchronous CMOS 64 K/128 K × 8 and 32 K/128 K × 9 dual-port static RAMs. Two ports are provided, permitting independent, simultaneous access for reads and writes to any location in memory. Registers on control, address, and data lines enable minimal setup and hold times.

Features

• True dual-ported memory cells that allow simultaneous access of the same memory location
• Synchronous pipelined operation
• Family of 4 Mbit, 9 Mbit, and 18 Mbit devices
• Pipelined output mode allows fast operation
• 0.18-micron complmentary metal oxide semiconductor (CMOS) for optimum speed and power
• High-speed clock to data access
• 3.3 V low power
  • Active as low as 225 mA (typ)
  • Standby as low as 55 mA (typ)
• For more, see pdf

Functional Description

The FLEx72 family includes 4 Mbit, 9 Mbit and 18 Mbit pipelined, synchronous, true dual-port static RAMs that are high-speed, low-power 3.3 V CMOS. Two ports are provided, permitting independent, simultaneous access to any location in memory. The result of writing to the same location by more than one port at the same time is undefined. Registers on control, address, and data lines allow for minimal set-up and hold time.

Features

• True dual-ported memory cells that allow simultaneous access of the same memory location
• Six flow through/pipelined devices:
  • 16 K × 16 / 18 organization (CY7C09269V/369V)
  • 32 K × 16 organization (CY7C09279V)
  • 64 K × 16 / 18 organization (CY7C09289V/389V)
• Three modes:
  • Flow through
  • Pipelined
  • Burst
• For more, see pdf
   

Functional Description

The CY7C09269V/79V/89V and CY7C09369V/89V are high speed 3.3 V synchronous CMOS 16 K, 32 K, and 64 K × 16 and 16 K and 64 K × 18 dual-port static RAMs. Two ports are provided, permitting independent, simultaneous access for reads and writes to any location in memory.

Features

• True dual-ported memory cells which allow simultaneous access of the same memory location
• Two Flow-Through/Pipelined devices
  • 16K x 36 organization (CY7C09569V)
  • 32K x 36 organization (CY7C09579V)
• 0.25-micron CMOS for optimum speed/power
• Three modes
  • Flow-Through
  • Pipelined
  • Burst
• For more, see pdf

Functional Description

The CY7C09569V and CY7C09579V are high-speed 3.3V synchronous CMOS 16K and 32K x 36 dual-port static RAMs. Two ports are provided, permitting independent, simultaneous access for reads and writes to any location in memory. Registers on control, address, and data lines allow for minimal set-up and hold times. In pipelined output mode, data is registered for decreased cycle time.

Features

• True dual-ported memory cells that allow simultaneous reads of the same memory location
• 4K ×16 organization (CY7C024E)
• 4K × 18 organization (CY7C0241E)
• 8K × 16 organization (CY7C025E)
• 8K × 18 organization (CY7C0251E)
• 0.35-μ complementary metal oxide semiconductor (CMOS) for optimum speed and power
• High-speed access: 15 ns
• Low operating power: ICC = 180 mA (typ), ISB3 = 0.05 mA (typ)
• Fully asynchronous operation
• For more, see pdf
   

Functional Description

The CY7C024E/CY7C0241E and CY7C025E/CY7C0251E are low-power CMOS 4K × 16/18 and 8K × 16/18 dual-port static RAMs. Various arbitration schemes are included on the CY7C024E/CY7C0241E and CY7C025E/CY7C0251E to handle situations when multiple processors access the same piece of data. Two ports are provided, permitting independent,  asynchronous access for reads and writes to any location in memory.

Features

• Low-voltage operation VDD = 3.3V
• 1:8 fanout
• Operation to 350 MHz
• Single input configurable for LVDS, LVPECL, or LVTTL
• 8 pair of LVPECL outputs
• Drives a 50 ohm load
• Low input capacitance
• Low output skew
• Low propagation delay (tpd = 4 ns, typical)
• Commercial and Industrial temperature ranges
• 38-Pin TSSOP Package
• For more, see pdf
   

Description

The Cypress CY2DP818 fanout buffer features a single LVDS or a single ended LVTTL compatible input and eight LVPECL output pairs.

Designed for data-communications clock management applications, the large fanout from a single input reduces loading on the input clock.

The CY2DP818 is ideal for both level translations from single ended to LVPECL and/or for the distribution of LVPECL based clock signals.

The Cypress CY2DP818 has configurable input functions. The input is user configurable via the InConfig pin for single ended or differential input.

Features

• 3.3 V operation for low-power consumption and easy integration into low-voltage systems
• High-speed, low-power, first-in first-out (FIFO) memories
• 16 K × 9 (CY7C4261V)
• 32 K × 9 (CY7C4271V)
• 64 K × 9 (CY7C4281V)
• 128 K × 9 (CY7C4291V)
• 0.35-micron CMOS for optimum speed or power
• High-speed 100-MHz operation (10-ns read/write cycle times)
• Low power
• For more, see pdf
   

Functional Description

The CY7C4261/71/81/91V are high-speed, low-power FIFO memories with clocked read and write interfaces. All are nine bits wide. The CY7C4261/71/81/91V are pin-compatible to the CY7C42x1V Synchronous FIFO family. Programmable features include Almost Full/Almost Empty flags. These FIFOs provide solutions for a wide variety of data buffering needs, including high-speed data acquisition, multiprocessor interfaces, and communications buffering.

Features

• High-speed, low-power, first-in, first-out (FIFO) memories
  • 256 x 9 (CY7C4201V)
  • 512 x 9 (CY7C4211V)
• High-speed 66-MHz operation (15-ns read/write cycle time)
• Low power (I_CC = 20 mA)
• 3.3V operation for low power consumption and easy integration into low-voltage systems
• 5V-tolerant inputs V_{IH max} = 5 V
• Fully asynchronous and simultaneous read and write operation
• Empty, full, and programmable almost empty and almost full status flags
• For more, see pdf
   

Functional Description

The CY7C42X1V are high-speed, low-power, FIFO memories with clocked read and write interfaces. All are nine bits wide. Programmable features include Almost Full/Almost Empty flags. These FIFOs provide solutions for a wide variety of data buffering needs, including high-speed data acquisition, multiprocessor interfaces, and communications buffering.

Features

• High speed, low power, first-in first-out (FIFO) memories
• 256 x 18 (CY7C4205)
• 512 x 18 (CY7C4215)
• 1K x 18 (CY7C4225)
• 4K x 18 (CY7C4245)
• High speed 100 MHz operation (10 ns read/write cycle time)
• Low power (ICC = 45 mA)
• Fully asynchronous and simultaneous read and write operation
• For more, see pdf
   

Functional Description

The CY7C42X5 are high speed, low power, first-in first-out (FIFO) memories with clocked read and write interfaces. All are 18 bits wide and are pin/functionally compatible to IDT722X5. The CY7C42X5 can be cascaded to increase FIFO depth. Programmable features include Almost Full/Almost Empty flags.      More...

Features

• Temperature ranges
  • Industrial: –40°C to 85°C
  • Automotive-A: –40°C to 85°C
  • Automotive-E: –40°C to 125°C
• Pin and function compatible with CY7C1011BV33
• High speed
  • tAA = 10 ns (Industrial and Automotive-A)
  • tAA = 12 ns (Automotive-E)
• Low active power
  • 360 mW (max) (Industrial and Automotive-A)
• For more, see pdf

Functional Description

The CY7C1011CV33 is a high performance complementary metal oxide semiconductor (CMOS) static RAM organized as 131,072 words by 16 bits. This device has an automatic power down feature that significantly reduces power consumption when deselected.

Features

• Temperature Ranges
  • Industrial: –40°C to 85°C
  • Automotive: –40°C to 125°C
• Very high speed: 45 ns
• Wide voltage range: 2.2V to 3.6V
• Pin compatible with CY62127BV
• Ultra-low active power
  • Typical active current: 0.85 mA @ f = 1 MHz
  • Typical active current: 5 mA @ f = fMAX
• For more, see pdf

Functional Description

The CY62127DV30 is a high-performance CMOS static RAM organized as 64K words by 16 bits. This device features advanced circuit design to provide ultra-low active current. This is ideal for providing More Battery Life™ (MoBL^®) in portable applications such as cellular telephones. The device also has an automatic power-down feature that significantly reduces power consumption by 90% when addresses are not toggling.

Features

• High speed: 45 ns
• Wide voltage range: 4.5 V – 5.5 V
• Pin compatible with CY62138V
• Ultra low standby power
  • Typical standby current: 1 μA
  • Maximum standby current: 5 μA
• Ultra low active power
  • Typical active current: 1.6 mA @ f = 1 MHz
• Easy memory expansion with CE1, CE2, and OE features
• Automatic power down when deselected
• complementary metal oxide semiconductor (CMOS) for optimum speed and power
• Available in Pb-free 32-pin SOIC and 32-pin thin small outline package (TSOP) II packages

Functional Description

The CY62138F is a high performance CMOS static RAM organized as 256K words by 8 bits. This device features advanced circuit design to provide ultra low active current. This is ideal for providing More Battery Life™ (MoBL®) in portable applications such as cellular telephones. The device also has an automatic power down feature that significantly reduces power consumption when addresses are not toggling.

Features

• Low jitter crystal oscillator (XO)
• Less than 1 ps typical root mean square (RMS) phase jitter
• Low-voltage differential signaling (LVDS) output
• Output frequency from 50 MHz to 690 MHz
• Factory-configured or field-programmable
• Integrated phase-locked loop (PLL)
• Output enable (OE) or power-down (PD#) function
• Supply voltage: 3.3 V or 2.5 V
• Pb-free package: 5.0 x 3.2 mm leadless chip carrier (LCC)
• Commercial and industrial temperature ranges
   

Functional Description

The CY2X013 is a high-performance and high-frequency XO. The device uses a Cypress proprietary low-noise PLL to synthesize the frequency from an integrated crystal.

The CY2X013 is available as a factory-configured device or as a field-programmable device. Factory-configured devices are configured for general use or they can be customer-specific.

Features

• Separate independent read and write data ports
  • Supports concurrent transactions
• 333 MHz clock for high bandwidth
• 4-word burst for reducing address bus frequency
• Double data rate (DDR) interfaces on both read and write ports
  (data transferred at 666 MHz) at 333 MHz
• Two input clocks (K and K) for precise DDR timing
  • SRAM uses rising edges only
• Two input clocks for output data (C and C) to minimize clock skew and flight time mismatches
• Echo clocks (CQ and CQ) simplify data capture in high speed systems
• For more, see pdf

Functional Description

The CY7C1526KV18, CY7C1513KV18, and CY7C1515KV18 are 1.8-V synchronous pipelined SRAMs, equipped with QDR II architecture. QDR II architecture consists of two separate ports: the read port and the write port to access the memory array. The read port has dedicated data outputs to support read operations and the write port has dedicated data inputs to support write operations.

Features

• Very high speed: 45 ns
• Temperature ranges
  • Industrial: –40 °C to 85 °C
• Wide voltage range: 2.20 V–3.60 V
• Pin compatible with CY62137CV/CV25/CV30/CV33, CY62137V, and CY62137EV30
• Ultra low standby power
  • Typical standby current: 1 μA
• For more, see pdf
   

Functional Description

The CY62137FV30 is a high performance CMOS static RAM organized as 128K words by 16 bits. This device features advanced circuit design to provide ultra low active current. This is ideal for providing More Battery Life™ (MoBL®) in portable applications such as cellular telephones. The device also has an automatic power down feature that significantly reduces power consumption when addresses are not toggling.

Features

• Separate Independent Read and Write Data Ports
  • Supports concurrent transactions
• 350 MHz Clock for High Bandwidth
• 2-word Burst on all Accesses
• Double Data Rate (DDR) Interfaces on both Read and Write Ports (data transferred at 700 MHz) at 350 MHz
• Two Input Clocks (K and K) for precise DDR Timing
  • SRAM uses rising edges only
• Two Input Clocks for Output Data (C and C) to minimize Clock Skew and Flight Time mismatches
• Echo Clocks (CQ and CQ) simplify Data Capture in High Speed Systems
•  Single multiplexed address input bus latches address inputs for both read and write ports
• bFor more, see pdf
 

Functional Description

The CY7C1525KV18, CY7C1512KV18, and CY7C1514KV18 are 1.8 V synchronous pipelined SRAMs, equipped with QDR II architecture. QDR II architecture consists of two separate ports: the read port and the write port to access the memory array. The read port has dedicated data outputs to support read operations and the write port has dedicated data inputs to support write operations. QDR II architecture has separate data inputs and data outputs to completely eliminate the need to “turnaround” the data bus that exists with common I/O devices.

Features
 

• Pin-and function-compatible with CY7C1011CV33
• High speed
  • tAA = 10 ns
• Low active power
  • ICC = 90 mA @ 10 ns (Industrial)
• Low CMOS standby power
  • ISB2 = 10 mA 
• Data Retention at 2.0 V
• Automatic power-down when deselected
• Independent control of upper and lower bits
• Easy memory expansion with CE and OE features
• Available in Pb-free 44-pin TSOP II, and 48-ball VFBGA
   

Functional Description

The CY7C1011DV33 is a high-performance CMOS Static RAM organized as 128 K words by 16 bits.

Features

• Pin-and function-compatible with CY7C1020CV33
• High speed
  • tAA = 10 ns
• Low active power
  • ICC = 60 mA @ 10 ns
• Low CMOS standby power
  • ISB2 = 3 mA
• 2.0V Data retention
• Automatic power-down when deselected
• For more, see pdf
   

Functional Description

The CY7C1020DV33 is a high-performance CMOS static RAM organized as 32,768 words by 16 bits. This device has an automatic power-down feature that significantly reduces power consumption when deselected.

Features

• Low jitter crystal oscillator (XO)
• Less than 1 ps typical root mean square (RMS) phase jitter
• Differential low-voltage positive emitter coupled logic (LVPECL) output
• Output frequency from 50 MHz to 690 MHz
• Factory-configured or field-programmable
• Integrated phase-locked loop (PLL)
• Output enable or power-down function
• Supply voltage: 3.3 V or 2.5 V
• Pb-free package: 5.0 x 3.2 mm leadless chip carrier (LCC)
• Commercial and industrial temperature ranges

Functional Description

The CY2X014 is a high-performance and high-frequency XO. The device uses a Cypress proprietary low-noise PLL to synthesize the frequency from an embedded crystal.

The CY2X014 is available as a factory-configured device or as a field-programmable device. Factory-configured devices are configured for general use or they can be customer specific.

• Very High-speed: 45 ns
• Temperature ranges
  • Industrial: –40 °C to 85 °C
  • Automotive-A: –40 °C to 85 °C
• Wide voltage range: 2.20 V to 3.60 V
• Pin compatible with CY62138CV25/30/33
• Ultra low standby power
  • Typical standby current: 1 μA
  • Maximum standby current: 5 μA
• For more, see pdf

Functional Description

The CY62138FV30 is a high performance CMOS static RAM organized as 256K words by 8 bits. This device features advanced circuit design to provide ultra low active current. This is ideal for providing More Battery Life™ (MoBL®) in portable applications such as cellular telephones. The device also has an automatic power down feature that significantly reduces power consumption. Place the device into standby mode reducing power consumption when deselected (CE1 HIGH or CE2 LOW).

Features

• 72-Mbit Density (4M x 18, 2M x 36)
• 333 MHz Clock for High Bandwidth
• 2-word Burst for reducing Address Bus Frequency
• Double Data Rate (DDR) Interfaces (data transferred at 666 MHz) at 333 MHz
• Two Input Clocks (K and K) for precise DDR Timing
  • SRAM uses rising edges only
• Two Input Clocks for Output Data (C and C) to minimize Clock Skew and Flight Time mismatches
• Echo Clocks (CQ and CQ) simplify Data Capture in High Speed Systems
• Synchronous Internally Self-timed Writes
• DDR II operates with 1.5 Cycle Read Latency when DOFF is asserted HIGH
• For more, see pdf.
   

Functional Description

The CY7C1518KV18, and CY7C1520KV18 are 1.8 V synchronous pipelined SRAM equipped with DDR II architecture. The DDR II consists of an SRAM core with advanced synchronous peripheral circuitry and a 1-bit burst counter. Addresses for read and write are latched on alternate rising edges of the input (K) clock.

Features

• Fast access time: 15 ns
• Wide voltage range: 5.0 V ± 10% (4.5 V to 5.5 V)
• CMOS for optimum speed and power
• TTL compatible inputs and outputs
• Available in 24-pin DIP and 24-pin SOJ

General Description

The CY7C197BN is a high performance CMOS Asynchronous SRAM organized as 256 K × 1 bits that supports an asynchronous memory interface. The device features an automatic power down feature that significantly reduces power consumption when deselected.

Features

• Low power CapSense® block with SmartSense Auto-tuning
• Powerful Harvard-architecture processor
• Operating Range: 1.71 V to 5.5 V
• Operating Temperature range: -40 °C to +85 °C
• Flexible on-chip memory
• Four Clock Sources
• Programmable pin configurations
• Versatile Analog functions
• Full-Speed USB
• For more, see pdf

PSoC^® Functional Overview

The PSoC family consists of on-chip controller devices, which are designed to replace multiple traditional microcontroller unit (MCU)-based components with one, low cost single-chip programmable component. A PSoC device includes configurable analog and digital blocks, and programmable interconnect. This architecture allows the user to create customized peripheral configurations, to match the requirements of each individual application.  

Features

• Advanced CapSense block with SmartSense Auto-Tuning
• Driven shield
• Powerful Harvard-architecture processor
• Advanced peripherals (PSoC® blocks)
• Flexible on-chip memory
• Complete development tools
• Precision, programmable clocking
• Programmable pin configurations
• Versatile analog mux
• For more, see pdf.
   

PSoC Functional Overview

The PSoC family consists of many devices with on-chip controllers. These devices are designed to replace multiple traditional MCU-based system components with one low-cost single-chip programmable component. A PSoC device includes configurable blocks of analog and digital logic, and programmable interconnect.

Features

• 10 MHz to 100/133 MHz operating range, compatible with CPU and PCI bus frequencies
• Zero input-output propagation delay
• 60-ps typical cycle-to-cycle jitter (high drive)
• Multiple low skew outputs
  • 85 ps typical output-to-output skew
  • One input drives five outputs (CY2305)
  • One input drives nine outputs, grouped as 4 4 1 (CY2309)
• Compatible with Pentium-based systems
• Test Mode to bypass phase-locked loop (PLL) (CY2309)
• Packages:
  • 8-pin, 150-mil SOIC package (CY2305)
  • 16-pin 150-mil SOIC or 4.4-mm TSSOP (CY2309)
• 3.3-V operation
• Commercial and industrial temperature ranges
   

Functional Description

The CY2309 is a low-cost 3.3-V zero delay buffer designed to distribute high speed clocks and is available in a 16-pin SOIC or TSSOP package. The CY2305 is an 8-pin version of the CY2309. It accepts one reference input, and drives out five low skew clocks. The -1H versions of each device operate at up to 100-/133 MHz frequencies, and have higher drive than the -1 devices. All parts have on-chip PLLs which lock to an input clock on the REF pin. The PLL feedback is on-chip and is obtained from the CLKOUT pad.

Features

• 2.5V or 3.3V operation
• 200-MHz clock support
• LVPECL or LVCMOS/LVTTL clock input
• LVCMOS-/LVTTL-compatible inputs
• 12 clock outputs: drive up to 24 clock lines
• Synchronous Output Enable
• Output three-state control
• 150 ps typical output-to-output skew
• Pin compatible with MPC948, MPC948L, MPC9448
• Available in Commercial and Industrial temp. range
• 32-pin TQFP package
   

Description

The CY29948 is a low-voltage 200-MHz clock distribution buffer with the capability to select either a differential LVPECL or a LVCMOS/LVTTL compatible input clock. The two clock sources can be used to provide for a test clock as well as the primary system clock. All other control inputs are LVCMOS/LVTTL compatible.

Features

• 12–100 MHz (CY7B9930V), or 24–200 MHz (CY7B9940V) input/output operation
• Matched pair output skew < 200 ps
• Zero input-to-output delay
• 10 LVTTL 50% duty-cycle outputs capable of driving 50ω terminated lines
• Commercial temperature range with eight outputs at 200 MHz
• Industrial temperature range with eight outputs at 200 MHz
• 3.3V LVTTL/LV differential (LVPECL), fault-tolerant and hot insertable reference inputs
• Multiply ratios of (1–6, 8, 10, 12)
• Operation up to 12x input frequency
• For more, see pdf

Functional Description

The CY7B9930V and CY7B9940V High-Speed Multifrequency PLL Clock Buffers offer user-selectable control over system clock functions. This multiple output clock driver provides the system integrator with functions necessary to optimize the timing of high performance computer or communication systems.

Features

• Pin-compatible and functionally equivalent to ZBT
• Supports 250 MHz bus operations with zero wait states
  • Available speed grades are 250, 200, and 166 MHz
• Internally self-timed output buffer control to eliminate the need to use asynchronous OE
• Fully registered (inputs and outputs) for pipelined operation
• Byte write capability
• Single 3.3 V power supply (VDD)
• 3.3 V or 2.5 V I/O power supply (VDDQ)
• Fast clock-to-output times
• For more, see pdf

Functional Description

The CY7C1354C and CY7C1356C are 3.3 V, 256 K x 36 and 512K x 18 synchronous pipelined burst SRAMs with No Bus Latency™ (NoBL™) logic, respectively. They are designed to support unlimited true back-to-back read/write operations with no wait states. The CY7C1354C and CY7C1356C are equipped with the advanced (NoBL) logic required to enable consecutive read/write operations with data being transferred on every clock cycle.

72-Mbit QDR® II SRAM Four-Word Burst Architecture (2.5 Cycle Read Latency)

• Separate Independent Read and Write Data Ports
  • Supports concurrent transactions
• 550 MHz Clock for High Bandwidth
• Four-word Burst for Reducing Address Bus Frequency
• Double Data Rate (DDR) Interfaces oboth Read and Write Ports (data transferred at 1000 MHz) at 500 MHz
• Available in 2.5 Clock Cycle Latency
• Two Input Clocks (K and K) for precise DDR Timing
  • SRAM uses rising edges only
• Echo Clocks (CQ and CQ) simplify Data Capture in High Speed Systems
• For more, see pdf

Functional Description

The CY7C15632KV18 is a 1.8V Synchronous Pipelined SRAM, equipped with QDR II architecture. Similar to QDR II architecture, QDR II architecture consists of two separate ports: the read port and the write port to access the memory array. The read port has dedicated data outputs to support read operations and the write port has dedicated data inputs to support write operations.

• Supports bus operation up to 250 MHz
• Available speed grade is 250 MHz
• Registered inputs and outputs for pipelined operation
• Optimal for performance (double cycle deselect)
• Depth expansion without wait state
• 3.3 V core power supply (VDD)
• 2.5 V and 3.3 V I/O operation
• Fast clock to output times
• For more, see pdf.
   

Functional Description

The CY7C1484BV33 SRAM integrates 2 M × 36 SRAM cells with advanced synchronous peripheral circuitry and a 2-bit counter for internal burst operation. All synchronous inputs are gated by registers controlled by a positive edge triggered Clock Input (CLK). The synchronous inputs include all addresses, all data  inputs, address pipelining Chip Enable (CE1), depth expansion Chip Enables (CE2 and CE3), Burst Control inputs (ADSC, ADSP, and ADV), Write Enables (BWX, and BWE), and Global Write (GW). Asynchronous inputs include the Output Enable  (OE) and the ZZ pin.

Features

• Supports 133 MHz bus operations
• 2 M × 36 common I/O
• 3.3 V core power supply (VDD)
• 2.5 V or 3.3 V I/O supply (VDDQ)
• Fast clock to output time
  • 6.5 ns (133 MHz version)
• Provide high performance 2-1-1-1 access rate
• User selectable burst counter supporting Intel® Pentium® interleaved or linear burst sequences
• Separate processor and controller address strobes
• Synchronous self timed write
• Asynchronous output enable
• CY7C1481BV33 available in JEDEC standard Pb-free 100-pin TQFP, Pb-free and non Pb-free 165-ball FBGA package.
• IEEE 1149.1 JTAG compatible boundary scan
• ZZ sleep mode option
• For more, See pdf
   

Functional Description

The CY7C1481BV33 is a 3.3 V, 2 M × 36 synchronous flow through SRAM designed to interface with high speed microprocessors with minimum glue logic. Maximum access delay from clock rise is 6.5 ns (133 MHz version). A 2-bit on-chip counter captures the first address in a burst and increments the address automatically for the rest of the burst access. All synchronous inputs are gated by registers controlled by a positive edge triggered Clock Input (CLK).

72-Mbit QDR® II SRAM 4-Word Burst Architecture (2.5 Cycle Read Latency)

Features

• Separate independent read and write data ports
  • Supports concurrent transactions
• 550-MHz clock for high bandwidth
• Four-word burst for reducing address bus frequency
• Double data rate (DDR) Interfaces on both read and write ports
  (data transferred at 1100 MHz) at 550 MHz
• Available in 2.5-clock cycle latency
• Two input clocks (K and K) for precise DDR timing
  • SRAM uses rising edges only
• Echo clocks (CQ and CQ) simplify data capture in high speed systems
• For more, see pdf
   

Functional Description

The CY7C1565KV18 is1.8-V synchronous pipelined SRAM, equipped with QDR II+ architecture. Similar to QDR II architecture, QDR II+ architecture consists of two separate ports: the read port and the write port to access the memory array. The read port has dedicated data outputs to support read operations and the write port has dedicated data inputs to support write operations. QDR II+ architecture has separate data inputs and data outputs to completely eliminate the need to “turnaround” the data bus that exists with common I/O devices.

Features

• Supports bus operation up to 250 MHz
• Available speed grades are 250 MHz
• Registered inputs and outputs for pipelined operation
• Optimal for performance (double cycle deselect)
• Depth expansion without wait state
• 2.5 V core power supply (VDD)
• 2.5 V I/O supply (VDDQ)
• Fast clock to output times
  • 3.0 ns (for 250 MHz device)
• Provide high performance 3-1-1-1 access rate
• For more, see pdf

Functional Description

The CY7C1484BV25 SRAM integrates 2 M × 36 SRAM cells with advanced synchronous peripheral circuitry and a 2-bit counter for internal burst operation. All synchronous inputs are gated by registers controlled by a positive edge triggered Clock Input (CLK).

Features

• Separate independent read and write data ports
  • Supports concurrent transactions
• 333 MHz clock for high bandwidth
• 2-word burst on all accesses
• Double data rate (DDR) Interfaces on both read and write ports (data transferred at 666 MHz) at 333 MHz
• Two input clocks (K and K) for precise DDR timing
  • SRAM uses rising edges only
• Two input clocks for output data (C and C) to minimize clock skew and flight time mismatches
• Echo clocks (CQ and CQ) simplify data capture in high speed systems
• For more, see pdf

Functional Description

The CY7C1425KV18, CY7C1412KV18, and CY7C1414KV18 are 1.8 V synchronous pipelined SRAMs, equipped with QDR II architecture. QDR II architecture consists of two separate ports: the read port and the write port to access the memory array. The read port has dedicated data outputs to support read operations and the write port has dedicated data inputs to support write operations. QDR II architecture has separate data inputs and  data outputs to completely eliminate the need to “turnaround” the data bus that exists with common I/O devices.
 

Features

• Separate independent read and write data ports
  • Supports concurrent transactions
• 333 MHz clock for high bandwidth
• Four-word burst for reducing address bus frequency
• Double data rate (DDR) Interfaces on both read and write ports (data transferred at 666 MHz) at 333 MHz
• Two input clocks (K and K) for precise DDR timing
  • SRAM uses rising edges only
• Two input clocks for output data (C and C) to minimize clock skew and flight time mismatches
• Echo clocks (CQ and CQ) simplify data capture in high speed systems
• For more, see pdf.

Functional Description

The CY7C1411KV18, CY7C1426KV18, CY7C1413KV18, and CY7C1415KV18 are 1.8 V synchronous pipelined SRAMs, equipped with QDR II architecture. QDR II architecture consists of two separate ports: the read port and the write port to access the memory array. The read port has dedicated data outputs to support read operations and the write port has dedicated data inputs to support write operations.

• Separate independent read and write data ports
  • Supports concurrent transactions
• 333-MHz clock for high bandwidth
• Four-word burst for reducing address bus frequency
• Double data rate (DDR) interfaces on both read and write ports (data transferred at 666 MHz) at 333 MHz
• Two input clocks (K and K) for precise DDR timing
  • SRAM uses rising edges only
• Two Input Clocks for Output Data (C and C) to minimize Clock skew and flight time mismatches
• Echo clocks (CQ and CQ) simplify data capture in high speed systems
• For more, see pdf

Functional Description

The CY7C1311KV18, CY7C1911KV18, CY7C1313KV18, and CY7C1315KV18 are 1.8 V Synchronous Pipelined SRAMs, equipped with QDR II architecture. QDR II architecture consists of two separate ports: the read port and the write port to access the memory array. The read port has dedicated data outputs to support read operations and the write port has dedicated data inputs to support write operations. QDR II architecture has separate data inputs and data outputs to completely eliminate the need to ‘turnaround’ the data bus that exists with common I/O devices. Each port can be accessed through a common address bus. Addresses for read and write addresses are latched on alternate rising edges of the input (K) clock.

Features

• Capacitive Slider and Button Input
• Target Applications
• Low Operating Current
• Industry's Best Configurability
• Advanced Features
• Wide Range of Operating Voltages
• I2C Communication
• Industrial Temperature Range: –40°C to 85°C.
• Available in 16-pin QFN and 16-pin SOIC Package
• For more, see pdf
   

Overview

These CapSense Express™ controllers support 4 to 10 capacitive sensing CapSense buttons. The device functionality is configured through an I2C port and can be stored in onboard nonvolatile memory for automatic loading at power on. The CapSense Express controller enables the control of 10 I/Os configurable as one capacitive sensing slider (10 segments)[1] or one slider (5 segments) with the rest of the pins as buttons or GPIOs (for driving LEDs or interrupt signals based on various button conditions).

Features

• 10/8/6/4 capacitive button input
• Target applications
• Low operating current
• Industry's best configurability
• Advanced features
• Wide range of operating voltages
• I2C communication
• Industrial temperature range: –40 °C to 85 °C.
• Available in 16-pin QFN, 8-pin, and 16-pin SOIC packages
• For more, see pdf

Overview

These CapSense Express™ controllers support four to ten capacitive sensing (CapSense) buttons. The device functionality is configured through an I2C port and can be stored in onboard nonvolatile memory for automatic loading at power-on. The CY8C20110 is optimized for dimming LEDs in 15 selectable duty cycles for back light applications. The device can be configured to have up to 10 GPIOs connected to the PWM output. The PWM duty cycle is programmable for variable LED intensities.

Features

• Separate independent read and write data ports
  • Supports concurrent transactions
• 250 MHz clock for high bandwidth
• 4-word burst for reducing address bus frequency
• Double data rate (DDR) interfaces on both read and write ports at 250 MHz (data transferred at 500 MHz)
• Two input clocks (K and K) for precise DDR timing
  • SRAM uses rising edges only
• Echo clocks (CQ and CQ) simplify data capture in high speed systems
• Single multiplexed address input bus latches address inputs for read and write ports
• Separate port selects for depth expansion
• For more, see pdf
   

Functional Description

The CYRS1543AV18 and CYRS1545AV18 are synchronous pipelined SRAMs, equipped with 1.8 V QDR II+ architecture with RadStop™ technology. Cypress’s state-of-the-art RadStop Technology is radiation hardened through proprietary design and process hardening techniques.

Features

• Separate independent read and write data ports
  • Supports concurrent transactions
• 250-MHz clock for high bandwidth
• 2-word burst on all accesses
• Double data rate (DDR) interfaces on both read and write ports at 250 MHz (data transferred at 500 MHz)
• Two input clocks (K and K) for precise DDR timing
  • SRAM uses rising edges only
• Echo clocks (CQ and CQ) simplify data capture in high speed systems
• Single multiplexed address input bus latches address inputs for both read and write ports
• Separate port selects for depth expansion
• For more, see pdf
   

Functional Description

The CYRS1542AV18 and CYRS1544AV18 are synchronous pipelined SRAMs, equipped with 1.8-V QDR II+ architecture with RadStop™ technology. Cypress’s state-of-the-art RadStop Technology is radiation hardened through proprietary design and process hardening techniques.

Features

• XRES pin to support in-system serial programming (ISSP) and external reset control in CY8C24894
• Powerful Harvard-architecture processor
• Advanced peripherals (PSoC® Blocks)
• Full speed USB (12 Mbps)
• Flexible on-chip memory
• Programmable pin configurations
• Precision, programmable clocking
• Additional system resources
• For more, see pdf

PSoC Functional Overview

The PSoC family consists of many devices with on-chip controllers. These devices are designed to replace multiple traditional MCU-based system components with one low-cost single-chip programmable component. A PSoC device includes configurable blocks of analog and digital logic, and programmable interconnect. This architecture makes it possible for you to create customized peripheral configurations, to match the requirements of each individual application.

Features

• True dual-ported memory cells which allow simultaneous access of the same memory location
• 32 K × 16 organization (CY7C027)
• 64 K × 16 organization (CY7C028)
• 0.35 micron CMOS for optimum speed and power
• High speed access: 15 and 20 ns
• Low operating power
• Active: ICC = 180 mA (typical)
• Standby: ISB3 = 0.05 mA (typical)
• Fully asynchronous operation
• For more, see pdf

Functional Description

The CY7C027 and CY7C028 are low power CMOS 32 K, 64 K × 16 dual-port static RAMs. Various arbitration schemes are included on the devices to handle situations when multiple processors access the same piece of data. Two ports are provided, permitting independent, asynchronous access for reads and writes to any location in memory.

Features

• 1-Mbit nonvolatile static random access memory (nvSRAM)
  • Internally organized as 128 K × 8
  • STORE to QuantumTrap nonvolatile elements initiated automatically on power-down (AutoStore) or by using I2C command (Software STORE) or HSB pin (Hardware STORE)
  • RECALL to SRAM initiated on power-up (Power-Up RECALL) or by I2C command (Software RECALL)
  • Automatic STORE on power-down with a small capacitor (except for CY14X101J1)
• High reliability
  • Infinite read, write, and RECALL cycles
  • 1 million STORE cycles to QuantumTrap
  • Data retention: 20 years at 85 °C
• For more, see pdf
   

Overview

The Cypress CY14C101J/CY14B101J/CY14E101J combines a 1-Mbit nvSRAM with a nonvolatile element in each memory cell. The memory is organized as 128 K words of 8 bits each. The embedded nonvolatile elements incorporate the QuantumTrap technology, creating the world’s most reliable nonvolatile memory. The SRAM provides infinite read and write cycles, while the QuantumTrap cells provide highly reliable nonvolatile storage of data.

Features

• 1-Mbit nonvolatile static random access memory (nvSRAM) internally organized as 128 K × 8
  • STORE to QuantumTrap nonvolatile elements initiated automatically on power-down (AutoStore) or by using SPI instruction (Software STORE) or HSB pin (Hardware STORE)
  • RECALL to SRAM initiated on power-up (Power-Up RECALL) or by SPI instruction (Software RECALL)
  • Support automatic STORE on power-down with a small capacitor (except for CY14X101Q1A)
• High reliability
  • Infinite read, write, and RECALL cycles
  • 1million STORE cycles to QuantumTrap
  • Data retention: 20 years at 85°C
• For more, see pdf
   

Functional Overview

The Cypress CY14X101Q combines a 1-Mbit nvSRAM with a nonvolatile element in each memory cell with serial SPI interface. The memory is organized as 128 K words of 8 bits each. The embedded nonvolatile elements incorporate the QuantumTrap  technology, creating the world’s most reliable nonvolatile memory. The SRAM provides infinite read and write cycles, while the QuantumTrap cells provide highly reliable nonvolatile storage of data.

Features

• 512-Kbit nonvolatile static random access memory (nvSRAM) internally organized as 64 K × 8
  • STORE to QuantumTrap nonvolatile elements initiated automatically on power-down (AutoStore) or by using SPI instruction (Software STORE) or HSB pin (Hardware STORE)
  • RECALL to SRAM initiated on power-up (Power-Up RECALL) or by SPI instruction (Software RECALL)
  • Support automatic STORE on power-down with a small capacitor (except for CY14X512Q1A)
• High reliability
  • Infinite read, write, and RECALL cycles
  • 1 million STORE cycles to QuantumTrap
  • Data retention: 20 years at 85 °C
• For more, see pdf

Functional Overview

The Cypress CY14X512Q combines a 512-Kbit nvSRAM with a nonvolatile element in each memory cell with serial SPI interface. The memory is organized as 64 K words of 8 bits each. The embedded nonvolatile elements incorporate the QuantumTrap technology, creating the world’s most reliable nonvolatile memory. The SRAM provides infinite read and write cycles, while the QuantumTrap cells provide highly reliable nonvolatile storage of data. Data transfers from SRAM to the nonvolatile elements (STORE operation) takes place automatically at power-down (except for CY14X512Q1A). On power-up, data is restored to the SRAM from the nonvolatile memory (RECALL operation). You can also initiate the STORE and RECALL operations through SPI instruction.

Features

• 256-Kbit nonvolatile static random access memory (nvSRAM) internally organized as 32 K × 8
  • STORE to QuantumTrap nonvolatile elements initiated automatically on power-down (AutoStore) or by using SPI instruction (Software STORE) or HSB pin (Hardware STORE)
  • RECALL to SRAM initiated on power-up (Power-Up RECALL) or by SPI instruction (Software RECALL)
  • Support automatic STORE on power-down with a small capacitor (except for CY14X256Q1A)
• High reliability
  • Infinite read, write, and RECALL cycles
  • 1million STORE cycles to QuantumTrap
  • Data retention: 20 years at 85° C
• 40 MHz, and 104 MHz High speed serial peripheral interface (SPI)
• For more, see pdf

Functional Overview

The Cypress CY14X256Q combines a 256-Kbit nvSRAM with a nonvolatile element in each memory cell with serial SPI interface. The memory is organized as 32 K words of 8 bits each. The embedded nonvolatile elements incorporate the QuantumTrap technology, creating the world’s most reliable nonvolatile memory. The SRAM provides infinite read and write cycles, while the QuantumTrap cells provide highly reliable nonvolatile storage of data.

Features

• 10 MHz to 100–133 MHz operating range
• Zero input and output propagation delay
• Multiple low skew outputs
• One input drives five outputs (CY2305C)
• One input drives nine outputs, grouped as 4 4 1 (CY2309C)
• 50 ps typical cycle-to-cycle jitter (15 pF, 66 MHz)
• Test mode to bypass phase locked loop (PLL) (CY2309C) only
• Available in space saving 16-pin 150 Mil small outline integrated circuit (SOIC) or 4.4 mm thin shrunk small outline package (TSSOP) packages (CY2309C), and 8-pin, 150 Mil SOIC package (CY2305C)
• 3.3 V operation
• Commercial, industrial and automotive-A flows available

Functional Description

The CY2305C and CY2309C are die replacement parts for CY2305 and CY2309.

The CY2309C is a low-cost 3.3 V zero delay buffer designed to distribute high speed clocks and is available in a 16-pin SOIC or TSSOP package. The CY2305C is an 8-pin version of the CY2309C. It accepts one reference input and drives out five low skew clocks. The -1H versions of each device operate up to 100–133 MHz frequencies and have higher drive than the -1 devices. All parts have on-chip phase locked loops (PLLs) which lock to an input clock on the REF pin. The PLL feedback is on-chip and is obtained from the CLKOUT pad.

Features

• Temperature ranges
  • Military/Space: -55 °C to 125 °C
• High speed
  • tAA = 12 ns
• Low active power
  • ICC = 95 mA at 12 ns (PMAX = 315 mW)
• Low CMOS standby power
  • ISB2 = 15 mA
• 2.0 V data retention
• Automatic power-down when deselected
• Transistor-transistor logic (TTL) compatible inputs and outputs
• Easy memory expansion with CE and OE features
• Available in Pb-free 36-pin ceramic flat package
   

Functional Description

The CYRS1049DV33 is a high-performance complementary metal oxide semiconductor (CMOS) static RAM organized as 512 K words by 8 bits with RadStop™ technology. Cypress’s state-of-the-art RadStop technology is radiation hardened through proprietary design and process hardening techniques. The 4-Mbit fast asynchronous SRAM with RadStop technology is also QML V certified with Defense Logistics Agency Land and Maritime (DLAM).

Features

• USB 2.0 hub controller
• Compliant with the USB 2.0 specification
• USB-IF certified: TID# 30000009
• Windows Hardware Quality Lab (WHQL) compliant
• Up to four downstream ports supported
• Supports bus powered and self powered modes
• Single Transaction Translator (TT)
• Bus power configurations
• For more, see pdf

Introduction

EZ-USB HX2LP Lite™ is Cypress’s next generation family of high performance, low power USB 2.0 hub controllers. HX2LP Lite is an ultra low power single chip USB 2.0 hub controller with integrated upstream and downstream transceivers, a USB Serial Interface Engine (SIE), USB Hub Control and Repeater logic, and Transaction Translator (TT) logic. Cypress has also integrated many external passive components such as pull up and pull down resistors, reducing the overall bill of materials required to implement a hub design.

• Single Device, Two functions
• Wide operating range: 1.9 V to 3.6 V
• Powerful Harvard-architecture processor
• Temperature range: 0 °C to +70 °C
• Flexible on-chip memory
• Precision, programmable clocking
• Programmable pin configurations
• Versatile analog system
• Additional system resources
• Complete development tools
• Package option
• For more, see pdf.

PSoC® Functional Overview

The PSoC family consists of on-chip controller devices, which are designed to replace multiple traditional microcontroller unit (MCU)-based components with one, low cost single-chip programmable component. A PSoC device includes configurable analog and digital blocks, and programmable interconnect. This architecture allows the user to create customized peripheral configurations, to match the requirements of each individual application. Additionally, a fast CPU, flash program memory, SRAM data memory, and configurable I/O are included in a range of convenient pinouts.

Features

• Multimedia device support
• Supports Microsoft® Media Transfer Protocol (MTP) with optimized data throughput
• Simultaneous Link to Independent Multimedia (SLIM®) architecture, enabling simultaneous and independent data paths between the processor and USB, and between the USB and mass storage
• High-speed USB at 480 Mbps
• GPIF (General Programmable Interface)
• For more, see pdf
   

Functional Overview

Turbo-MTP Support

Turbo-MTP is an implementation of Microsoft’s MTP enabled by West Bridge. In the current generation of MTP-enabled mobile phones, all protocol packets needs to be handled by the main processor. West Bridge Turbo-MTP switches these packet types and sends only control packets to the processor, while data payloads are written directly to mass storage, thereby bringing the high performance of West Bridge to MTP.   

• SLIM™ architecture, enabling simultaneous and independent data paths between processor and USB, and between USB and mass storage
• High speed USB at 480 Mbps
• Mass storage device support
• Memory mapped interface to main processor
• DMA slave support
• Supports Microsoft® media transfer protocol (MTP) with optimized data throughput
• Ultra low power, 1.8 V core operation
• Low power modes
• For more, see pdf

Functional Overview

SLIM™ Architecture

The Simultaneous Link to Independent Multimedia (SLIM) architecture allows three different interfaces (the P-port, the S-port, and the U-port) to connect to one another independently.

Features

• Small Footprint, 8-Pin QFN 1.7 mm x 1.7 mm x 0.6 mm Package
• Low Power and Low Jitter Operation
• Multiple Operating Voltages:
  • CY22M1S: 2.5 V, 3.0 V, or 3.3 V
  • CY22M1L: 1.8 V
• Programmable Single Output Clock Generator Frequency Range:
  • 1 to 80 MHz
• Crystal or External Reference Clock Input Frequency Range:
  • Fundamental Tuned Crystal: 8 to 48 MHz
• For more, see pdf
   

Functional Description

The MoBL® UniClock CY22M1 is a programmable, high accuracy, PLL-based clock generator device designed for low power, space constrained applications. The low jitter and accurate outputs makes this device suitable for handsets, portable media players, personal navigation devices, digital cameras, digital camcorders, and other portable applications.

Features

• Low jitter crystal oscillator (XO)
• Less than 1 ps typical root mean square (RMS) phase jitter
• Low-voltage differential signaling (LVDS) output
• Output frequency from 50 MHz to 690 MHz
• Frequency margining through I2C bus
• Factory-configured or field-programmable
• Integrated phase-locked loop (PLL)
• Pb-free package: 5.0 × 3.2 mm leadless chip carrier (LCC)
• Supply voltage: 3.3 V or 2.5 V
• Commercial and industrial temperature ranges
   

Functional Description

The CY2XF23 is a high-performance and high-frequency XO. It uses a Cypress proprietary low-noise PLL to synthesize the frequency from an integrated crystal. The output frequency can be changed using the I2C bus serial interface, allowing easy frequency margin testing in applications.

• Small Footprint, 8-Pin QFN 1.7 x 1.7 x 0.6 mm3 Package
• Low Power and Low Jitter Operation
• Multiple Operating Voltages:
  • CY22U1S: 2.5V, 3.0V, or 3.3V
  • CY22U1L: 1.8V
• Programmable Single Output Clock Generator Frequency Range:
  • 1 to 200 MHz
• Crystal or External Reference Clock Input Frequency Range
• For more, see pdf

Functional Description
 

Features

• True dual-ported memory cells that allow simultaneous access of the same memory location
• 16K x 36 organization (CY7C056V)
• 32K x 36 organization (CY7C057V)
• 0.25-micron CMOS for optimum speed/power
• High-speed access: 12/15 ns
• Low operating power
  • Active: I_CC = 250 mA (typical)
  • Standby: I_SB3 = 10 µA (typical)
• Fully asynchronous operation
• For more, see pdf

Functional Description

The CY7C056V and CY7C057V are low-power CMOS 16K and 32K x 36 dual-port static RAMs. Various arbitration schemes are included on the devices to handle situations when multiple processors access the same piece of data. Two ports are provided, permitting independent, asynchronous access for reads and writes to any location in memory.

Features

• True dual-ported memory cells that allow simultaneous access of the same memory location
• Synchronous pipelined operation
• Organization of 2-Mbit, 4-Mbit, and 9-Mbit devices
• Pipelined output mode allows fast operation
• 0.18-micron Complimentary metal oxide semiconductor (CMOS) for optimum speed and power
• High-speed clock to data access
• 3.3V low power
  • Active as low as 225 mA (typ)
  • Standby as low as 55 mA (typ)
• For more, see pdf
   

Functional Description

The FLEx36™ family includes 2M, 4M, and 9M pipelined, synchronous, true dual-port static RAMs that are high-speed, low-power 3.3V CMOS. Two ports are provided, permitting independent, simultaneous access to any location in memory. The result of writing to the same location by more than one port at the same time is undefined. Registers on control, address, and data lines allow for minimal setup and hold time.

Features

• Very high speed: 55 ns
  • Wide voltage range: 2.20 V to 3.60 V
• Temperature range:
  • Automotive-E: –40 °C to +125 °C
• Pin compatible with CY62148DV30
• Ultra low standby power
  • Typical standby current: 3 μA
  • Maximum standby current: 20 μA
• Ultra low active power
  • Typical active current: 2 mA at f = 1 MHz
• For more, see pdf

Functional Description

The CY62148EV30LL Automotive is a high performance CMOS static RAM organized as 512 K words by 8 bits. This device features advanced circuit design to provide ultra low active current. This is ideal for providing More Battery Life™ (MoBL®) in portable applications such as cellular telephones. The device also has an automatic power down feature that significantly reduces power consumption.

• 72 Mbit Density (4M x 18, 2M x 36)
• 450 MHz Clock for High Bandwidth
• 2-word Burst for reducing Address Bus Frequency
• Double Data Rate (DDR) Interfaces (data transferred at 900 MHz) at 450 MHz
• Available in 2.0 Clock Cycle Latency
• Two Input Clocks (K and K) for precise DDR Timing
  • SRAM uses rising edges only
• Echo Clocks (CQ and CQ) simplify Data Capture in High Speed Systems
• Data Valid Pin (QVLD) to indicate Valid Data on the Output
• For more, see pdf
   

The CY7C1548KV18, and CY7C1550KV18 are 1.8 V Synchronous Pipelined SRAMs equipped with DDR II+ architecture. The DDR II+ consists of an SRAM core with advanced synchronous peripheral circuitry. Addresses for read and write are latched on alternate rising edges of the input (K) clock. Write data is registered on the rising edges of both K and K. Read data is driven on the rising edges of K and K. Each address location is associated with two 18-bit words CY7C1548KV18), or 36-bit words (CY7C1550KV18) that burst sequentially into or out of the device.

Three PLL General Purpose EPROM Programmable Clock Generator

Features

• Three integrated phase locked loops (PLLs)
• Erasable programmable read only memory (EPROM) programmability
• Factory programmable (CY2292) or field programmable (CY2292F) device options
• Low-skew, low-jitter, high accuracy outputs
• Power management options (shutdown, OE, suspend)
• Frequency select option
• Smooth slewing on CPUCLK
• Configurable 3.3 V or 5 V operation
• 16-pin small-outline integrated circuit (SOIC) package (CY2292F also in TSSOP)

Operation

The CY2292 is a third-generation family of clock generators. The CY2292 is upwardly compatible with the industry standard ICD2023 and ICD2028 and continues their tradition by providing a high level of customizable features to meet the diverse clock generation needs of modern motherboards and other synchronous systems.

Features

• Three integrated phase-locked loops
• EPROM programmability
• Factory-programmable (CY2291) or field-programmable (CY2291F) device options
• Low-skew, low-jitter, high-accuracy outputs
• Power-management options (Shutdown, OE, Suspend)
• Frequency select option
• Smooth slewing on CPUCLK
• Configurable 3.3 V or 5 V operation
• 20-pin SOIC Package

Functional Description

The CY2291 is a third-generation family of clock generators. The CY2291 is upwardly compatible with the industry standard ICD2023 and ICD2028 and continues their tradition by providing a high level of customizable features to meet the diverse clock synchoronous systems.

All parts provide a highly configurable set of close for PC motherboard applications. Each of four configurable clock outputs (CLKA-CLKD) can be assigned 1 of 30 frequencies in any combination. Multiple outputs configured for the same or related[3] frequencies have low (<500 ps) skew, in effect providing on-chip buffering for heavily loaded signals.

4Mbit Ferroelectric Nonvolatile RAM
 

• Organized as 256Kx16
• Configurable as 512Kx8 Using /UB, /LB
• 10¹⁴ Read/Write Cycles
• NoDelay™ Writes
• Page Mode Operation to 40MHz
• Advanced High-Reliability Ferroelectric Process
• For more, see pdf

Description

The FM22L16 is a 256Kx16 nonvolatile memory that reads and writes like a standard SRAM. A ferroelectric random access memory or F-RAM is nonvolatile, which means that data is retained after power is removed. It provides data retention for over 10 years while eliminating the reliability concerns, functional disadvantages, and system design complexities of battery-backed SRAM (BBSRAM). Fast write timing and high write endurance make the F-RAM superior to other types of memory.

2Mbit Ferroelectric Nonvolatile RAM

• Organized as 128Kx16
• Configurable as 256Kx8 Using /UB, /LB
• 10¹⁴ Read/Write Cycles
• NoDelay™ Writes
• Page Mode Operation to 33MHz
• Advanced High-Reliability Ferroelectric Process

Description

The FM21LD16 is a 128Kx16 nonvolatile memory that reads and writes like a standard SRAM. A ferroelectric random access memory or F-RAM is nonvolatile, which means that data is retained after power is removed. It provides data retention for over 10 years while eliminating the reliability concerns, functional disadvantages, and system design complexities of battery-backed SRAM (BBSRAM). Fast write timing and high write endurance make the F-RAM superior to other types of memory. In-system operation of the FM21LD16 is very similar to other RAM devices and can be used as a drop-in replacement for standard SRAM. Read and write cycles may be triggered by /CE or simply by changing the address. The F-RAM memory is nonvolatile due to its unique ferroelectric memory process. These features make the FM21LD16 ideal for nonvolatile memory applications requiring frequent or rapid writes in the form of an SRAM.

Features

• Memory organization
  • Industry's largest first in first out (FIFO) memory densities: 18 Mbit, 36 Mbit, and 72 Mbit
  • Selectable memory organization: x9, x12, x16, x18, x20, x24, x32, x36
• Up to 133-MHz clock operation
• Unidirectional operation
• Independent read and write ports
  • Supports simultaneous read and write operations
  • Reads and writes operate on independent clocks, upto a maximum ratio of two, enabling data buffering across clock domains.
  • Supports multiple I/O voltage standard: low voltage complementary metal oxide semiconductor (LVCMOS) 3.3 V and 1.8 V voltage standards.
• For more, see pdf.
   

Functional Description

The Cypress programmable FIFO family offers the industry’s highest-density programmable FIFO memory device. It has independent read and write ports, which can be clocked up to 133 MHz. User can configure input and output bus sizes. The maximum bus size of 36 bits enables a maximum data throughput of 4.8 Gbps.

High Integration Device Replaces Multiple Parts

• Serial Nonvolatile Memory
• Real-time Clock (RTC) with Alarm
• Low VDD Detection Drives Reset
• Watchdog Window Timer
• Early Power-Fail Warning/NMI
• 16-bit Nonvolatile Event Counter
• Serial Number with Write-lock for Security
• For more, see pdf.

Description

The FM33256B device integrates F-RAM memory with the most commonly needed functions for processor-based systems. Major features include nonvolatile memory, real-time clock, low-VDD reset, watchdog timer, nonvolatile event counter, lockable 64-bit serial number area, and general purpose comparator that can be used for a power-fail (NMI) interrupt or other purpose. The device operate from 2.7 to 3.6V.

1Mbit Ferroelectric Nonvolatile RAM

• Organized as 128Kx8
• High Endurance 100 Trillion (10¹⁴) Read/Writes
• NoDelay™ Writes
• Page Mode Operation to 33MHz
• Advanced High-Reliability Ferroelectric Process
• For more, see pdf.

General Description

The FM28V100 is a 128K x 8 nonvolatile memory that reads and writes like a standard SRAM. A ferroelectric random access memory or F-RAM is nonvolatile, which means that data is retained after power is removed. It provides data retention for over 10 years while eliminating the reliability concerns, functional disadvantages, and system design complexities of battery-backed SRAM (BBSRAM). Fast write timing and very high write endurance make F-RAM superior to other types of memory.

256K bit Ferroelectric Nonvolatile RAM
 

• Organized as 32,768 x 8 bits
• High Endurance 100 Trillion (10¹⁴) Read/Writes
• 38 Year Data Retention (@ +75ºC)
• NoDelay™ Writes
• Advanced High-Reliability Ferroelectric Process
• For more, see pdf.

Description

The FM25W256 is a 256-kilobit nonvolatile memory employing an advanced ferroelectric process. A ferroelectric random access memory or F-RAM is nonvolatile and performs reads and writes like a RAM. It provides reliable data retention for 38 years while eliminating the complexities, overhead, and system level reliability problems caused by EEPROM and other nonvolatile memories.

2M bit Ferroelectric Nonvolatile RAM
 

• Organized as 256K x 8 bits
• High Endurance 100 Trillion (10¹⁴) Read/Writes
• 10 Year Data Retention
• NoDelay™ Writes
• Advanced High-Reliability Ferroelectric Process
• For more, see pdf.

Description

The FM25V20 is a 2-megabit nonvolatile memory employing an advanced ferroelectric process. A ferroelectric random access memory or F-RAM is nonvolatile and performs reads and writes like a RAM. It provides reliable data retention for 10 years while eliminating the complexities, overhead, and system level reliability problems caused by Serial  Flash and other nonvolatile memories.

1M bit Ferroelectric Nonvolatile RAM
 

• Organized as 131,072 x 8 bits
• High Endurance 100 Trillion (10¹⁴) Read/Writes
• 10 Year Data Retention
• NoDelay™ Writes
• Advanced High-Reliability Ferroelectric Process
• For more, see pdf.

Description

The FM25V10 is a 1-megabit nonvolatile memory employing an advanced ferroelectric process. A ferroelectric random access memory or F-RAM is nonvolatile and performs reads and writes like a RAM. It provides reliable data retention for 10 years while eliminating the complexities, overhead, and system level reliability problems caused by Serial Flash and other nonvolatile memories.

512K bit Ferroelectric Nonvolatile RAM
 

• Organized as 65,536 x 8 bits
• High Endurance 100 Trillion (10¹⁴) Read/Writes
• 10 Year Data Retention
• NoDelay™ Writes
• Advanced High-Reliability Ferroelectric Process
• For more, see pdf.

Description

The FM25V05 is a 512-kilobit nonvolatile memory employing an advanced ferroelectric process. A ferroelectric random access memory or F-RAM is nonvolatile and performs reads and writes like a RAM. It provides reliable data retention for 10 years while eliminating the complexities, overhead, and system level reliability problems caused by Serial Flash and other nonvolatile memories.

256K bit Ferroelectric Nonvolatile RAM

• Organized as 32,768 x 8 bits
• High Endurance 100 Trillion (10¹⁴) Read/Writes
• 10 Year Data Retention
• NoDelay™ Writes
• Advanced High-Reliability Ferroelectric Process
• For more, see pdf.

Description

The FM25V02 is a 256-kilobit nonvolatile memory employing an advanced ferroelectric process. A ferroelectric random access memory or F-RAM is nonvolatile and performs reads and writes like a RAM. It provides reliable data retention for 10 years while eliminating the complexities, overhead, and system level reliability problems caused by Serial Flash and other nonvolatile memories.

128K bit Ferroelectric Nonvolatile RAM
 

• Organized as 16,384 x 8 bits
• High Endurance 100 Trillion (10¹⁴) Read/Writes
• 10 Year Data Retention
• NoDelay™ Writes
• Advanced High-Reliability Ferroelectric Process
• For more, see pdf.

Description

The FM25V01 is a 128-kilobit nonvolatile memory employing an advanced ferroelectric process. A ferroelectric random access memory or F-RAM is nonvolatile and performs reads and writes like a RAM. It provides reliable data retention for 10 years while eliminating the complexities, overhead, and system level reliability problems caused by Serial Flash and other nonvolatile memories.

4K bit Ferroelectric Nonvolatile RAM
 

• Organized as 512 x 8 bits
• High Endurance 100 Trillion (10¹⁴) Read/Writes
• 38 Year Data Retention (@ +75ºC)
• NoDelay™ Writes
• Advanced High-Reliability Ferroelectric Process
• For more, see pdf.

Description

The FM25L04B is a 4-kilobit nonvolatile memory employing an advanced ferroelectric process. A ferroelectric random access memory or F-RAM is nonvolatile and performs reads and writes like a RAM. It provides reliable data retention for 38 years while eliminating the complexities, overhead, and system level reliability problems caused by EEPROM and other nonvolatile memories.

16K bit Ferroelectric Nonvolatile RAM
 

• Organized as 2,048 x 8 bits
• High Endurance 100 Trillion (10¹⁴) Read/Writes
• 38 Year Data Retention (@ +75ºC)
• NoDelay™ Writes
• Advanced High-Reliability Ferroelectric Process
• For more, see pdf.

Description

The FM25L16B is a 16-kilobit nonvolatile memory employing an advanced ferroelectric process. A ferroelectric random access memory or F-RAM is nonvolatile and performs reads and writes like a RAM. It provides reliable data retention for 38 years while eliminating the complexities, overhead, and system level reliability problems caused by EEPROM and other nonvolatile memories.

64K bit Ferroelectric Nonvolatile RAM
 

• Organized as 8,192 x 8 bits
• High Endurance 100 Trillion (10¹⁴) Read/Writes
• 38 Year Data Retention (@ +75ºC)
• NoDelay™ Writes
• Advanced High-Reliability Ferroelectric Process
• For more, see pdf

Description

The FM25CL64B is a 64-kilobit nonvolatile memory employing an advanced ferroelectric process. A ferroelectric random access memory or F-RAM is nonvolatile and performs reads and writes like a RAM. It provides reliable data retention for 38 years while eliminating the complexities, overhead, and system level reliability problems caused by EEPROM and other nonvolatile memories.

16K bit Ferroelectric Nonvolatile RAM
 

• Organized as 2,048 x 8 bits
• High Endurance 1 Trillion (10¹²) Read/Writes
• 38 year Data Retention
• NoDelay™ Writes
• Advanced High-Reliability Ferroelectric Process
• For more, see pdf

Description

The FM25C160B is a 16-kilobit nonvolatile memory employing an advanced ferroelectric process. A ferroelectric random access memory or F-RAM is nonvolatile but operates in other respects as a RAM. It provides reliable data retention for 38 years while eliminating the complexities, overhead, and system level reliability problems caused by EEPROM and other nonvolatile memories.

64K bit Ferroelectric Nonvolatile RAM
 

• Organized as 8,192 x 8 bits
• High Endurance 1 Trillion (10¹²) Read/Writes
• 38 Year Data Retention
• NoDelay™ Writes
• Advanced high-reliability ferroelectric process
• For more, see pdf.

Description

The FM25640B is a 64-kilobit nonvolatile memory employing an advanced ferroelectric process. A ferroelectric random access memory or F-RAM is nonvolatile but operates in other respects as a RAM. It provides reliable data retention for 38 years while eliminating the complexities, overhead, and system level reliability problems caused by EEPROM and other nonvolatile memories.

4K bit Ferroelectric Nonvolatile RAM
 

• Organized as 512 x 8 bits
• High Endurance 1 Trillion (10¹²) Read/Writes
• 38 year Data Retention
• NoDelay™ Writes
• Advanced High-Reliability Ferroelectric Process
• For more, see pdf

Description

The FM25040B is a 4-kilobit nonvolatile memory employing an advanced ferroelectric process. A ferroelectric random access memory or F-RAM is nonvolatile but operates in other respects as a RAM. It provides reliable data retention for 38 years while eliminating the complexities, overhead, and system level reliability problems caused by EEPROM and other nonvolatile memories.

1M bit Ferroelectric Nonvolatile RAM
 

• Organized as 131,072 x 8 bits
• High Endurance 100 Trillion (10¹⁴) Read/Writes
• 10 year Data Retention
• NoDelay™ Writes
• Advanced High-Reliability Ferroelectric Proces
• For more, see pdf

Description

The FM24V10 is a 1-megabit nonvolatile memory employing an advanced ferroelectric process. A ferroelectric random access memory or F-RAM is nonvolatile and performs reads and writes like a RAM. It provides reliable data retention for 10 years while eliminating the complexities, overhead, and system level reliability problems caused by  EEPROM and other nonvolatile memories.