• 18 Mbit density (1 M x 18, 512 K x 36)
• 450-MHz clock for high bandwidth
• Two-word burst for reducing address bus frequency
• Double data rate (DDR) interfaces (data transferred at 900 MHz) at 450 MHz
• Available in 2.0 clock cycle latency
• For more, see pdf
   

Functional Description

The CY7C1148KV18, and CY7C1150KV18 are 1.8 V Synchronous Pipelined SRAMs equipped with DDR II+ architecture. The DDR II+ consists of an SRAM core with advanced synchronous peripheral circuitry. Addresses for read and write are latched on alternate rising edges of the input (K) clock.

• Separate independent read and write data ports
  • Supports concurrent transactions
• 550-MHz clock for high bandwidth
• Four-word burst for reducing address bus frequency
• Double data rate (DDR) interfaces on both read and write ports (data transferred at 1100 MHz) at 550 MHz
• Available in 2.5 clock cycle latency
• For more, see pdf
   

Functional Description

The CY7C1163KV18, and CY7C1165KV18 are 1.8 V Synchronous Pipelined SRAMs, equipped with QDR II+ architecture. Similar to QDR II architecture, QDR II+ architecture consists of two separate ports: the read port and the write port to access the memory array. The read port has dedicated data outputs to support read operations and the write port has dedicated data inputs to support write operations. QDR II+ architecture has separate data inputs and data outputs to completely eliminate the need to ‘turnaround’ the data bus that exists with common I/O devices. Each port is accessed through a common address bus. Addresses for read and write addresses are latched on alternate rising edges of the input (K) clock.

• 18-Mbit density (1 M × 18, 512 K × 36)
• 550-MHz clock for high bandwidth
• Two-word burst for reducing address bus frequency
• Double data rate (DDR) interfaces (data transferred at 1100 MHz) at 550 MHz
• Available in 2.5 clock cycle latency
• Two input clocks (K and K) for precise DDR timing
• Echo clocks (CQ and CQ) simplify data capture in high-speed systems
• For more, see pdf

Functional Description

The CY7C1168KV18, and CY7C1170KV18 are 1.8 V synchronous pipelined SRAMs equipped with DDR II+ architecture. The DDR II+ consists of an SRAM core with advanced synchronous peripheral circuitry. Addresses for read and write are latched on alternate rising edges of the input (K) clock.

• 18 Mbit density (2 M x 8, 1 M x 18)
• 333-MHz clock for high bandwidth
• Two-word burst for reducing address bus frequency
• Double data rate (DDR) interfaces (data transferred at 666 MHz) at 333 MHz
• For more, see pdf
   

Functional Description

The CY7C1392KV18 and CY7C1393KV18 are 1.8 V Synchronous Pipelined SRAMs, equipped with DDR II SIO (double data rate separate I/O) architecture. The DDR II SIO consists of two separate ports: the read port and the write port to access the memory array. The read port has data outputs to support read operations and the write port has data inputs to support write operations. The DDR II SIO has separate data inputs and data outputs to completely eliminate the need to ‘turnaround’ the data bus required with common I/O devices. Access to each port is accomplished through a common address bus. Addresses for read and write are latched on alternate rising edges of the input (K) clock.

• 18 Mbit density (1 M x 18, 512 K x 36)
• 333-MHz clock for high bandwidth
• Four-word burst for reducing address bus frequency
• Double data rate (DDR) interfaces (data transferred at 666 MHz) at 333 MHz
• Two input clocks (K and K) for precise DDR timing
• Two input clocks for output data (C and C) to minimize clock skew and flight time mismatches
• For more, see pdf
   

Functional Description

CY7C1319KV18 and CY7C1321KV18 are 1.8 V Synchronous Pipelined SRAMs equipped with DDR II architecture. The DDR II consists of an SRAM core with advanced synchronous peripheral circuitry and a two-bit burst counter. Addresses for read and write are latched on alternate rising edges of the input (K) clock.

• Separate independent read and write data ports
  • Supports concurrent transactions
• 450-MHz clock for high bandwidth
• Four-word burst for reducing address bus frequency
• Double data rate (DDR) Interfaces on both read and write ports (data transferred at 900 MHz) at 450 MHz
• Available in 2.0 clock cycle latency
• For more, see pdf
   

Functional Description

The CY7C1143KV18, and CY7C1145KV18 are 1.8 V Synchronous Pipelined SRAMs, equipped with QDR II+ architecture. Similar to QDR II architecture, QDR II+ architecture consists of two separate ports: the read port and the write port to access the memory array. The read port has dedicated data outputs to support read operations and the write port has dedicated data inputs to support write operations. QDR II+ architecture has separate data inputs and data outputs to completely eliminate the need to “turnaround” the data bus that exists with common I/O devices. Each port is accessed through a common address bus. Addresses for read and write addresses are latched on alternate rising edges of the input (K) clock.
 

• 18 Mbit density (1 M x 18, 512 K x 36)
• 550-MHz clock for high bandwidth
• Two-word burst for reducing address bus frequency
• Double data rate (DDR) interfaces (data transferred at 1100 MHz) at 550 MHz
• Available in 2.5 clock cycle latency
• Two input clocks (K and K) for precise DDR timing
  • SRAM uses rising edges only
• Echo clocks (CQ and CQ) simplify data capture in high-speed systems
• Data valid pin (QVLD) to indicate valid data on the output
• For more, see pdf

Functional Description

The CY7C2168KV18, and CY7C2170KV18 are 1.8 V Synchronous Pipelined SRAMs equipped with DDR II+ architecture. The DDR II+ consists of an SRAM core with advanced synchronous peripheral circuitry. Addresses for read and write are latched on alternate rising edges of the input (K) clock.

• Separate independent read and write data ports
  • Supports concurrent transactions
• 450 MHz clock for high bandwidth
• Four-word burst for reducing address bus frequency
• Double Data Rate (DDR) interfaces on both read and write ports (data transferred at 900 MHz) at 450 MHz
• Available in 2.0 clock cycle latency
• Two input clocks (K and K) for precise DDR timing
  • SRAM uses rising edges only
• Echo clocks (CQ and CQ) simplify data capture in high speed systems
• For more, see pdf
   

Features

• Separate independent read and write data ports
  • Supports concurrent transactions
• 333 MHz clock for high bandwidth
• 4-word burst for reducing address bus frequency
• Double data rate (DDR) interfaces on both read and write ports
  (data transferred at 666 MHz) at 333 MHz
• Two input clocks (K and K) for precise DDR timing
  • SRAM uses rising edges only
• Two input clocks for output data (C and C) to minimize clock skew and flight time mismatches
• Echo clocks (CQ and CQ) simplify data capture in high speed systems
• For more, see pdf

Functional Description

The CY7C1526KV18, CY7C1513KV18, and CY7C1515KV18 are 1.8-V synchronous pipelined SRAMs, equipped with QDR II architecture. QDR II architecture consists of two separate ports: the read port and the write port to access the memory array. The read port has dedicated data outputs to support read operations and the write port has dedicated data inputs to support write operations.

Features

• Separate Independent Read and Write Data Ports
  • Supports concurrent transactions
• 350 MHz Clock for High Bandwidth
• 2-word Burst on all Accesses
• Double Data Rate (DDR) Interfaces on both Read and Write Ports (data transferred at 700 MHz) at 350 MHz
• Two Input Clocks (K and K) for precise DDR Timing
  • SRAM uses rising edges only
• Two Input Clocks for Output Data (C and C) to minimize Clock Skew and Flight Time mismatches
• Echo Clocks (CQ and CQ) simplify Data Capture in High Speed Systems
•  Single multiplexed address input bus latches address inputs for both read and write ports
• bFor more, see pdf
 

Functional Description

The CY7C1525KV18, CY7C1512KV18, and CY7C1514KV18 are 1.8 V synchronous pipelined SRAMs, equipped with QDR II architecture. QDR II architecture consists of two separate ports: the read port and the write port to access the memory array. The read port has dedicated data outputs to support read operations and the write port has dedicated data inputs to support write operations. QDR II architecture has separate data inputs and data outputs to completely eliminate the need to “turnaround” the data bus that exists with common I/O devices.

Features

• 72-Mbit Density (4M x 18, 2M x 36)
• 333 MHz Clock for High Bandwidth
• 2-word Burst for reducing Address Bus Frequency
• Double Data Rate (DDR) Interfaces (data transferred at 666 MHz) at 333 MHz
• Two Input Clocks (K and K) for precise DDR Timing
  • SRAM uses rising edges only
• Two Input Clocks for Output Data (C and C) to minimize Clock Skew and Flight Time mismatches
• Echo Clocks (CQ and CQ) simplify Data Capture in High Speed Systems
• Synchronous Internally Self-timed Writes
• DDR II operates with 1.5 Cycle Read Latency when DOFF is asserted HIGH
• For more, see pdf.
   

Functional Description

The CY7C1518KV18, and CY7C1520KV18 are 1.8 V synchronous pipelined SRAM equipped with DDR II architecture. The DDR II consists of an SRAM core with advanced synchronous peripheral circuitry and a 1-bit burst counter. Addresses for read and write are latched on alternate rising edges of the input (K) clock.

Features

• Pin-compatible and functionally equivalent to ZBT
• Supports 250 MHz bus operations with zero wait states
  • Available speed grades are 250, 200, and 166 MHz
• Internally self-timed output buffer control to eliminate the need to use asynchronous OE
• Fully registered (inputs and outputs) for pipelined operation
• Byte write capability
• Single 3.3 V power supply (VDD)
• 3.3 V or 2.5 V I/O power supply (VDDQ)
• Fast clock-to-output times
• For more, see pdf

Functional Description

The CY7C1354C and CY7C1356C are 3.3 V, 256 K x 36 and 512K x 18 synchronous pipelined burst SRAMs with No Bus Latency™ (NoBL™) logic, respectively. They are designed to support unlimited true back-to-back read/write operations with no wait states. The CY7C1354C and CY7C1356C are equipped with the advanced (NoBL) logic required to enable consecutive read/write operations with data being transferred on every clock cycle.

72-Mbit QDR® II SRAM Four-Word Burst Architecture (2.5 Cycle Read Latency)

• Separate Independent Read and Write Data Ports
  • Supports concurrent transactions
• 550 MHz Clock for High Bandwidth
• Four-word Burst for Reducing Address Bus Frequency
• Double Data Rate (DDR) Interfaces oboth Read and Write Ports (data transferred at 1000 MHz) at 500 MHz
• Available in 2.5 Clock Cycle Latency
• Two Input Clocks (K and K) for precise DDR Timing
  • SRAM uses rising edges only
• Echo Clocks (CQ and CQ) simplify Data Capture in High Speed Systems
• For more, see pdf

Functional Description

The CY7C15632KV18 is a 1.8V Synchronous Pipelined SRAM, equipped with QDR II architecture. Similar to QDR II architecture, QDR II architecture consists of two separate ports: the read port and the write port to access the memory array. The read port has dedicated data outputs to support read operations and the write port has dedicated data inputs to support write operations.

• Supports bus operation up to 250 MHz
• Available speed grade is 250 MHz
• Registered inputs and outputs for pipelined operation
• Optimal for performance (double cycle deselect)
• Depth expansion without wait state
• 3.3 V core power supply (VDD)
• 2.5 V and 3.3 V I/O operation
• Fast clock to output times
• For more, see pdf.
   

Functional Description

The CY7C1484BV33 SRAM integrates 2 M × 36 SRAM cells with advanced synchronous peripheral circuitry and a 2-bit counter for internal burst operation. All synchronous inputs are gated by registers controlled by a positive edge triggered Clock Input (CLK). The synchronous inputs include all addresses, all data  inputs, address pipelining Chip Enable (CE1), depth expansion Chip Enables (CE2 and CE3), Burst Control inputs (ADSC, ADSP, and ADV), Write Enables (BWX, and BWE), and Global Write (GW). Asynchronous inputs include the Output Enable  (OE) and the ZZ pin.

Features

• Supports 133 MHz bus operations
• 2 M × 36 common I/O
• 3.3 V core power supply (VDD)
• 2.5 V or 3.3 V I/O supply (VDDQ)
• Fast clock to output time
  • 6.5 ns (133 MHz version)
• Provide high performance 2-1-1-1 access rate
• User selectable burst counter supporting Intel® Pentium® interleaved or linear burst sequences
• Separate processor and controller address strobes
• Synchronous self timed write
• Asynchronous output enable
• CY7C1481BV33 available in JEDEC standard Pb-free 100-pin TQFP, Pb-free and non Pb-free 165-ball FBGA package.
• IEEE 1149.1 JTAG compatible boundary scan
• ZZ sleep mode option
• For more, See pdf
   

Functional Description

The CY7C1481BV33 is a 3.3 V, 2 M × 36 synchronous flow through SRAM designed to interface with high speed microprocessors with minimum glue logic. Maximum access delay from clock rise is 6.5 ns (133 MHz version). A 2-bit on-chip counter captures the first address in a burst and increments the address automatically for the rest of the burst access. All synchronous inputs are gated by registers controlled by a positive edge triggered Clock Input (CLK).

72-Mbit QDR® II SRAM 4-Word Burst Architecture (2.5 Cycle Read Latency)

Features

• Separate independent read and write data ports
  • Supports concurrent transactions
• 550-MHz clock for high bandwidth
• Four-word burst for reducing address bus frequency
• Double data rate (DDR) Interfaces on both read and write ports
  (data transferred at 1100 MHz) at 550 MHz
• Available in 2.5-clock cycle latency
• Two input clocks (K and K) for precise DDR timing
  • SRAM uses rising edges only
• Echo clocks (CQ and CQ) simplify data capture in high speed systems
• For more, see pdf
   

Functional Description

The CY7C1565KV18 is1.8-V synchronous pipelined SRAM, equipped with QDR II+ architecture. Similar to QDR II architecture, QDR II+ architecture consists of two separate ports: the read port and the write port to access the memory array. The read port has dedicated data outputs to support read operations and the write port has dedicated data inputs to support write operations. QDR II+ architecture has separate data inputs and data outputs to completely eliminate the need to “turnaround” the data bus that exists with common I/O devices.

Features

• Supports bus operation up to 250 MHz
• Available speed grades are 250 MHz
• Registered inputs and outputs for pipelined operation
• Optimal for performance (double cycle deselect)
• Depth expansion without wait state
• 2.5 V core power supply (VDD)
• 2.5 V I/O supply (VDDQ)
• Fast clock to output times
  • 3.0 ns (for 250 MHz device)
• Provide high performance 3-1-1-1 access rate
• For more, see pdf

Functional Description

The CY7C1484BV25 SRAM integrates 2 M × 36 SRAM cells with advanced synchronous peripheral circuitry and a 2-bit counter for internal burst operation. All synchronous inputs are gated by registers controlled by a positive edge triggered Clock Input (CLK).

Features

• Separate independent read and write data ports
  • Supports concurrent transactions
• 333 MHz clock for high bandwidth
• 2-word burst on all accesses
• Double data rate (DDR) Interfaces on both read and write ports (data transferred at 666 MHz) at 333 MHz
• Two input clocks (K and K) for precise DDR timing
  • SRAM uses rising edges only
• Two input clocks for output data (C and C) to minimize clock skew and flight time mismatches
• Echo clocks (CQ and CQ) simplify data capture in high speed systems
• For more, see pdf

Functional Description

The CY7C1425KV18, CY7C1412KV18, and CY7C1414KV18 are 1.8 V synchronous pipelined SRAMs, equipped with QDR II architecture. QDR II architecture consists of two separate ports: the read port and the write port to access the memory array. The read port has dedicated data outputs to support read operations and the write port has dedicated data inputs to support write operations. QDR II architecture has separate data inputs and  data outputs to completely eliminate the need to “turnaround” the data bus that exists with common I/O devices.
 

Features

• Separate independent read and write data ports
  • Supports concurrent transactions
• 333 MHz clock for high bandwidth
• Four-word burst for reducing address bus frequency
• Double data rate (DDR) Interfaces on both read and write ports (data transferred at 666 MHz) at 333 MHz
• Two input clocks (K and K) for precise DDR timing
  • SRAM uses rising edges only
• Two input clocks for output data (C and C) to minimize clock skew and flight time mismatches
• Echo clocks (CQ and CQ) simplify data capture in high speed systems
• For more, see pdf.

Functional Description

The CY7C1411KV18, CY7C1426KV18, CY7C1413KV18, and CY7C1415KV18 are 1.8 V synchronous pipelined SRAMs, equipped with QDR II architecture. QDR II architecture consists of two separate ports: the read port and the write port to access the memory array. The read port has dedicated data outputs to support read operations and the write port has dedicated data inputs to support write operations.

• Separate independent read and write data ports
  • Supports concurrent transactions
• 333-MHz clock for high bandwidth
• Four-word burst for reducing address bus frequency
• Double data rate (DDR) interfaces on both read and write ports (data transferred at 666 MHz) at 333 MHz
• Two input clocks (K and K) for precise DDR timing
  • SRAM uses rising edges only
• Two Input Clocks for Output Data (C and C) to minimize Clock skew and flight time mismatches
• Echo clocks (CQ and CQ) simplify data capture in high speed systems
• For more, see pdf

Functional Description

The CY7C1311KV18, CY7C1911KV18, CY7C1313KV18, and CY7C1315KV18 are 1.8 V Synchronous Pipelined SRAMs, equipped with QDR II architecture. QDR II architecture consists of two separate ports: the read port and the write port to access the memory array. The read port has dedicated data outputs to support read operations and the write port has dedicated data inputs to support write operations. QDR II architecture has separate data inputs and data outputs to completely eliminate the need to ‘turnaround’ the data bus that exists with common I/O devices. Each port can be accessed through a common address bus. Addresses for read and write addresses are latched on alternate rising edges of the input (K) clock.

Features

• Separate independent read and write data ports
  • Supports concurrent transactions
• 250 MHz clock for high bandwidth
• 4-word burst for reducing address bus frequency
• Double data rate (DDR) interfaces on both read and write ports at 250 MHz (data transferred at 500 MHz)
• Two input clocks (K and K) for precise DDR timing
  • SRAM uses rising edges only
• Echo clocks (CQ and CQ) simplify data capture in high speed systems
• Single multiplexed address input bus latches address inputs for read and write ports
• Separate port selects for depth expansion
• For more, see pdf
   

Functional Description

The CYRS1543AV18 and CYRS1545AV18 are synchronous pipelined SRAMs, equipped with 1.8 V QDR II+ architecture with RadStop™ technology. Cypress’s state-of-the-art RadStop Technology is radiation hardened through proprietary design and process hardening techniques.

Features

• Separate independent read and write data ports
  • Supports concurrent transactions
• 250-MHz clock for high bandwidth
• 2-word burst on all accesses
• Double data rate (DDR) interfaces on both read and write ports at 250 MHz (data transferred at 500 MHz)
• Two input clocks (K and K) for precise DDR timing
  • SRAM uses rising edges only
• Echo clocks (CQ and CQ) simplify data capture in high speed systems
• Single multiplexed address input bus latches address inputs for both read and write ports
• Separate port selects for depth expansion
• For more, see pdf
   

Functional Description

The CYRS1542AV18 and CYRS1544AV18 are synchronous pipelined SRAMs, equipped with 1.8-V QDR II+ architecture with RadStop™ technology. Cypress’s state-of-the-art RadStop Technology is radiation hardened through proprietary design and process hardening techniques.

• 72 Mbit Density (4M x 18, 2M x 36)
• 450 MHz Clock for High Bandwidth
• 2-word Burst for reducing Address Bus Frequency
• Double Data Rate (DDR) Interfaces (data transferred at 900 MHz) at 450 MHz
• Available in 2.0 Clock Cycle Latency
• Two Input Clocks (K and K) for precise DDR Timing
  • SRAM uses rising edges only
• Echo Clocks (CQ and CQ) simplify Data Capture in High Speed Systems
• Data Valid Pin (QVLD) to indicate Valid Data on the Output
• For more, see pdf
   

The CY7C1548KV18, and CY7C1550KV18 are 1.8 V Synchronous Pipelined SRAMs equipped with DDR II+ architecture. The DDR II+ consists of an SRAM core with advanced synchronous peripheral circuitry. Addresses for read and write are latched on alternate rising edges of the input (K) clock. Write data is registered on the rising edges of both K and K. Read data is driven on the rising edges of K and K. Each address location is associated with two 18-bit words CY7C1548KV18), or 36-bit words (CY7C1550KV18) that burst sequentially into or out of the device.

RH QDR®II+ Memory Controller contains the logic necessary to read from and write to RH QDRII+ SRAM memory. Its primary function involves synchronizing the Single Data Rate SDR (System Logic) and the Double Data Rate DDR (RH QDRII+ memory) data domains.

Features

• Registered inputs and outputs for pipelined operation
• 256 K × 32 common I/O architecture
• 3.3 V core power supply (VDD)
• 2.5 V/3.3 V I/O power supply (VDDQ)
• Fast clock-to-output times
• Provide high-performance 3-1-1-1 access rate
• For more, see pdf.
   

Functional Description

The CY7C1364C SRAM integrates 256 K × 32 SRAM cells with advanced synchronous peripheral circuitry and a two-bit counter for internal burst operation. All synchronous inputs are gated by registers controlled by a positive-edge-triggered Clock Input (CLK).
 

• Separate independent read and write data ports
• 333-MHz clock for high bandwidth
• Two-word burst for reducing address bus frequency
• Double data rate (DDR) interfaces on both read and write ports (data transferred at 666 MHz) at 333 MHz
• Available in 2.0-clock cycle latency
• Two input clocks (K and K) for precise DDR timing
• Echo clocks (CQ and CQ) simplify data capture in high-speed systems
• Data valid pin (QVLD) to indicate valid data on the output
• On-die termination (ODT) feature
• For more, see pdf
   

Functional Description

The CY7C2644KV18 is 1.8-V synchronous pipelined SRAM, equipped with QDR® II+ architecture. Similar to QDR II architecture, QDR II+ architecture consists of two separate ports: the read port and the write port to access the memory array. The read port has dedicated data outputs to support read operations and the write port has dedicated data inputs to support write operations. QDR II+ architecture has separate data  inputs and data outputs to completely eliminate the need to “turn around” the data bus that exists with common I/O devices. Access to each port is through a common address bus. Addresses for read and write addresses are latched on alternate rising edges of the input (K) clock.
 

• 144-Mbit density (8 M × 18, 8 M × 36)
• 333 MHz clock for high bandwidth
• 2-word burst for reducing address bus frequency
• Double data rate (DDR) interfaces (data transferred at 666 MHz) at 333 MHz
• Two input clocks (K and K) for precise DDR timing
• Two input clocks for output data (C and C) to minimize clock skew and flight time mismatches
• Echo clocks (CQ and CQ) simplify data capture in high-speed systems
• Synchronous internally self-timed writes
• DDR II operates with 1.5-cycle read latency when DOFF is asserted high
• For more, see pdf
   

Functional Description

The CY7C1618KV18, and CY7C1620KV18 are 1.8-V synchronous pipelined SRAM equipped with DDR II architecture. The DDR II consists of an SRAM core with advanced synchronous peripheral circuitry and a 1-bit burst counter. Addresses for read and write are latched on alternate rising edges of the input (K) clock.

• 144-Mbit density (14 M × 36)
• 550-MHz clock for high bandwidth
• Two-word burst for reducing address bus frequency
• Double data rate (DDR) interfaces (data transferred at 1100 MHz) at 550 MHz
• Available in 2.5 clock cycle latency
• Two input clocks (K and K) for precise DDR timing
• Echo clocks (CQ and CQ) simplify data capture in high-speed systems
• Data valid pin (QVLD) to indicate valid data on the output
• On-die termination (ODT) feature
• For more, see pdf

Functional Description

The CY7C2670KV18 is 1.8-V synchronous pipelined SRAM equipped with DDR II+ architecture. The DDR II+ consists of an SRAM core with advanced synchronous peripheral circuitry. Addresses for read and write are latched on alternate rising edges of the input (K) clock. Write data is registered on the rising edges of both K and K. Read data is driven on the rising edges of K and K. Each address location is associated with two 36-bit words (CY7C2670KV18) that burst sequentially into or out of the device.

Please refer to “AN4065 - QDR™-II, QDR-II+, DDR-II, and DDR-II+ Design Guide” for different termination schemes, design, and signal integrity guidelines.

The following pages provide a snapshot of the schematics from the internal characterization board for the QDR-DDR II/II+/Xtreme SRAMs. For more information on the QDR-DDR II/II+/Xtreme SRAMs, please refer the respective datasheet in the link, http://www.cypress.com/?id=95.

Reference schematic for QDR-DDR II/II+/Xtreme SRAMs

Figure 1a. QDRII/II+/II+Xtreme-DDRII/II+/II+Xtreme (Non ODT) Reference Schematic (From internal characterization board)

Figure 1b. QDRII/II+/II+Xtreme-DDRII/II+/II+Xtreme (ODT) Reference Schematic (From internal characterization board)

Figure 2. QDRII/II+/II+Xtreme-DDRII/II+/II+Xtreme (Supply Pins) Reference Schematic (From internal characterization board)

Assumptions

• The reference schematic above is from an internal characterization board. It is recommended to perform Signal integrity simulations with the specific board conditions before finalizing the design.
• Figure 1a and Figure 1b are the reference schematics for all Non ODT and ODT QDR-DDR II/II+/Xtreme SRAMs respectively. As an example if the part is x18 device, then Data pins notation D[x:0] will be interpreted as D[17:0].
• QDRII+/II+Xtreme-DDRII+/II+Xtreme devices do not have the input clocks C and C#
• Non ODT QDRII+/II+Xtreme-DDRII/II+/II+Xtreme devices do not contain ODT pin.
• ODT devices have an On-Die Termination feature for Data inputs (D[x:0]), Byte Write Selects (BWS[x:0]), and Input Clocks (K and K#). Hence, there is no termination for D[x:0], BWS[x:0] , K and K# pins in Figure 1b. Please refer to “AN42468 - On-Die Termination for QDR™II+/DDRII+ SRAMs”, which discusses on-die termination (ODT) scheme, implementation, advantages and power calculation for the QDR™II+ and DDRII+ family of Synchronous SRAMs on the 65-nm technology devices.
• The value of termination resistor (R) is 50 Ω because most of the designs have 50 Ω characteristic impedance for the trace. The termination resistor value should be equal to the characteristic impedance of the trace.
• An external resistor, RQ, must be connected between the ZQ pin on the SRAM and VSS to allow the SRAM to adjust its output driver impedance. The value of RQ must be 5x the value of the intended line impedance driven by the SRAM, hence RQ value is 250 Ω to match output impedance of 50 Ω in Figure 1a and Figure 1b. The allowable range of RQ to guarantee impedance matching with a tolerance of ±15% is between 175 Ω and 350 Ω, with VDDQ = 1.5 V. The output impedance is adjusted every 1024 cycles upon power up to account for drifts in supply voltage and temperature.
• Keep termination resistors as close to the device as possible to reduce the stub length and thereby reduce reflections.

Decoupling Capacitor Recommendation for Power Supply Pins
 

• Decoupling capacitors on power supply pins play a significant role to filter noise in the power supply.
• It is recommended to place the de-coupling capacitors need to be placed close to the memory devices for best results.
• Following decoupling capacitors recommendation is from internal characterization board.

Decoupling Capacitors for VDD

Figure 3. Decoupling Capacitors Recommendation for VDD (From internal characterization board)

Decoupling Capacitors for VDDQ

• Please refer to the datasheets for VDDQ value.

Figure 4. Decoupling Capacitors Recommendation for VDDQ (From internal characterization board)

Decoupling Capacitors for VTT

Figure 5. Decoupling Capacitors Recommendation for VTT (From internal characterization board)

Decoupling Capacitors for VREF

Figure 6. Decoupling Capacitors Recommendation for VREF (From internal characterization board)

Please, create a technical support case if you are facing any issue, while creating your design or if you would like Cypress to do a schematic review.

• K Clock Cycle Time (tCYC)
• K Clock Rise to K# Clock Rise (tKHK#H)
• Input Setup and Hold Times Referenced to K Clock

K Clock Cycle Time (tCYC): This parameter denotes the cycle time of the input K clock. If the cycle time of this clock at any instance goes below the minimum datasheet specification due to the input clock jitter, then the device may not function properly. Use the next higher speed bin to accommodate input clock non-idealities. For example, a 400 MHz SRAM has a minimum tCYC of 2.5 ns. If the system runs at 400 MHz with input clock jitter that drives tCYC down to 2.3 ns (or 434 MHz), then use the next higher speed bin, which is the 450 MHz speed bin.

K Clock Rise to K# Clock Rise (tKHK#H): This parameter denotes the time between the rising edge of the K clock and the rising edge of the K# clock. To ensure proper device operation it is critical that the tKHK#H parameter must never exceed the minimum value as defined in the datasheet.

Input Setup and Hold Times Referenced to K Clock: Under any input jitter condition, all setup and hold parameters must be met to guarantee operation. These include, tSA, tSC, tSCDDR, tSD, tHA, tHC, tHCDDR, tHD.

To summarize, any type or amount of input clock jitter does not affect device operation as long as the above critical timing parameters are met. Also note that the tKCVar (clock phase jitter) parameter does not affect device functionality if the above conditions are met. However, this parameter does have an impact on the jitter performance of the output data and echo clocks.

Jitter Performance

The 65 nm QDRII/II+/DDRII/II+ device family has a phase-locked loop (PLL) internal to the device. The PLL actively filters the incoming jitter of K clock to a certain degree depending on the jitter frequency component.

Jitter Transfer Function Measurement

Figure 1 shows the measured jitter transfer function. The X-axis represents the frequency component offset from the K-clock frequency (Fk). The Y-axis represents the amplitude of the jitter transmitted to CQ/CQ#. The plot represents the positive side of a band pass filter and indicates that any jitter with a frequency component outside Fk ±3 MHz will be heavily filtered.

Figure 1. Measured Jitter Transfer Function for QDR/DDR PLL Based Memories

Jitter Histogram Measurement

Figure 2 shows the output from an experiment in which jitter is injected to the K clock using a white noise source. The input clock frequency is 350 MHz. The experiment shows almost 6x reduction in jitter standard deviation (σ). This experiment was done to evaluate the PLL performance in filtering input clock noise and shows the performance improvement of PLL based devices. Additional noise is generated at the output clock during read/write operations to the SRAM.

Figure 2. (a) Noise Injected into K Clock (b) Noise Measured on Echo CQ Clock

PLL Implementation

Figure 3 shows a simplified diagram that explains the PLL based implementations. In the PLL implementation, CQ is generated from a voltage controlled oscillator (VCO) that is driven by a low pass loop filter. If jitter is injected to the input K clock, then the loop filter eliminates the high frequency components. Therefore, the VCO does not respond to that jitter and the CQ clock is kept at a steady phase.

Figure 3. PLL Based Implementation

Problem statement: QDR-DDR II/II+/Xtreme verilog models give erroneous simulation results with Synopsys VCS while other simulators like Altera Modelsim, Xilinx ISE, and Mentor Graphics Questa do not produce the same errors.

Below is the simulation result for verilog model using Altera Modelsim.

............                                        (e.g. CY7C2564XV18)
.......................
# Line:            12 OUTPUT DATA OK data = 06038180e test = 06038180e
# Line:            13 OUTPUT DATA OK data = 04028100a test = 04028100a
# Line:            14 OUTPUT DATA OK data = zzzzzzzzz test = zzzzzzzzz
# Line:            15 OUTPUT DATA OK data = zzzzzzzzz test = zzzzzzzzz
# Line:            16 OUTPUT DATA OK data = 0884c2213 test = 0884c2213
# Line:            17 OUTPUT DATA OK data = 0683c1a0f test = 0683c1a0f
# Line:            18 OUTPUT DATA OK data = 0b0602c18 test = 0b0602c18
# Line:            19 OUTPUT DATA OK data = 090502414 test = 090502414
# Line:            20 OUTPUT DATA OK data = 0d874361d test = 0d874361d
# Line:            21 OUTPUT DATA OK data = 0b8642e19 test = 0b8642e19
.......................     

Below is the simulation result for the same verilog model using Synopsys VCS.

 ....... ..                                (e.g. CY7C2564XV18)
....................
Line:            12 OUTPUT DATA OK data = 06038180e test = 06038180e
Line:            13 ERROR data                     = zzzzzzzzz test = 04028100a
Line:            14 OUTPUT DATA OK data = zzzzzzzzz test = zzzzzzzzz
Line:            15 OUTPUT DATA OK data = zzzzzzzzz test = zzzzzzzzz
Line:            16 OUTPUT DATA OK data = 0884c2213 test = 0884c2213
Line:            17 ERROR data                    = zzzzzzzzz test = 0683c1a0f
Line:            18 OUTPUT DATA OK data = 0b0602c18 test = 0b0602c18
Line:            19 ERROR data                    = zzzzzzzzz test = 090502414
Line:            20 OUTPUT DATA OK data = 0d874361d test = 0d874361d
Line:            21 ERROR data                    = zzzzzzzzz test = 0b8642e19
.....................................................................
……………

Explanation for the errors:

VCS simulation result shows some erroneous output from the same verilog model. The reason for this is that, the reg Data_out is been driven by two drivers at the same time, as shown in the verilog code snippet,

`define tcqd #0.15
`define tcqdoh #0.15
reg [35:0] Data_out;

......

always @(datahold_clk)
begin
  if(chip_oe == 1) `tcqdoh Data_out = 36'bz;
end

...

always @(posedge echo_clk)
begin
   if (rpen_o_o_o_o == 0)
     Data_out = `tcqd mem2[Read_Address_o_o_o_o];
end

always @(posedge echo_clkb)
begin
   if (rpen_o_o_o == 0)
        Data_out = `tcqd mem1[Read_Address_o_o_o];
end

...

always @(datahold_clk)
begin
     if(tristate == 0) `tcqdoh Data_out = 36'bz;
end

Here all clk events happen at same time and the drivers are writing Data_out after 0.15 ns delay (tcqd and tcqdoh), causing nondeterminism in the model. The simulator takes the liberty of executing the statements in different processes in different order. This nondeterminism in event ordering is random and different HDL simulators may behave differently in terms or resolving these or behave same.

Resolution of error:

To actually resolve this, we need to make sure the driving events are not happening at the same time in non-blocking assignment statements. Change the delay "tcqdoh" to 0.14 or a value slightly less than 0.15. This will make a VCS simulator to know the defined order of event execution.

Features

• Supports bus operation up to 250 MHz
• Available speed grades are 250 MHz and 167 MHz
• Registered inputs and outputs for pipelined operation
• Optimal for performance (double-cycle deselect)
• Depth expansion without wait state
• 3.3 V core power supply
• 2.5 V/3.3 V I/O power supply
• For more, see pdf.

Functional Description

The CY7C1444AV33 SRAM integrates 1 M × 36 SRAM cells with advanced synchronous peripheral circuitry and a two-bit counter for internal burst operation. All synchronous inputs are gated by registers controlled by a positive-edge-triggered clock input (CLK).

• Separate independent read and write data ports
• 550-MHz clock for high bandwidth
• Four-word burst for reducing address bus frequency
• Double data rate (DDR) interfaces on both read and write ports (data transferred at 1100 MHz) at 550 MHz
• Available in 2.5-clock cycle latency
• Two input clocks (K and K) for precise DDR timing
• Echo clocks (CQ and CQ) simplify data capture in high-speed systems
• Data valid pin (QVLD) to indicate valid data on the output
• On-die termination (ODT) feature
• For more, see pdf
   

Functional Description

The CY7C2663KV18, and CY7C2665KV18 are 1.8 V synchronous pipelined SRAMs, equipped with QDR II+ architecture. Similar to QDR II architecture, QDR II+ architecture consists of two separate ports: the read port and the write port to  access the memory array. The read port has dedicated data outputs to support read operations and the write port has dedicated data inputs to support write operations. 

• Separate independent read and write data ports
• 333 MHz clock for high bandwidth
• Four-word burst for reducing address bus frequency
• Double Data Rate (DDR) interfaces on both read and write ports (data transferred at 666 MHz) at 333 MHz
• Two input clocks (K and K) for precise DDR timing
• Two input clocks for output data (C and C) to minimize clock skew and flight time mismatches
• Echo clocks (CQ and CQ) simplify data capture in high speed systems
• Single multiplexed address input bus latches address inputs for read and write ports
• Separate port selects for depth expansion 
• For more, see pdf
   

 Functional Description

The CY7C1613KV18, and CY7C1615KV18 are 1.8-V synchronous pipelined SRAMs, equipped with QDR® II architecture. QDR II architecture consists of two separate ports: the read port and the write port to access the memory array. The read port has dedicated data outputs to support read operations and the write port has dedicated data inputs to support write operations. QDR II architecture has separate data inputs and data outputs to completely eliminate the need to “turn around” the data bus that exists with common I/O devices.

• 72-Mbit density (4 M × 18, 2 M × 36)
• 633 MHz clock for high bandwidth
• Two-word burst for reducing address bus frequency
• Double data rate (DDR) interfaces (data transferred at 1266 MHz) at 633 MHz
• Available in 2.5 clock cycle latency
• Two input clocks (K and K) for precise DDR timing
• Echo Clocks (CQ and CQ) simplify data capture in high speed systems
• Data valid pin (QVLD) to indicate valid data on the output
• On-die termination (ODT) feature
• For more, see pdf

Functional Description

The CY7C2568XV18, and CY7C2570XV18 are 1.8 V Synchronous Pipelined SRAMs equipped with DDR II+ architecture. The DDR II+ consists of an SRAM core with advanced synchronous peripheral circuitry. Addresses for read and write are latched on alternate rising edges of the input (K) clock. Write data is registered on the rising edges of both K and K. Read data is driven on the rising edges of K and K. Each address location is associated with two 18-bit words (CY7C2568XV18), or 36-bit words (CY7C2570XV18) that burst sequentially into or out of the device.

• Separate Independent Read and Write Data Ports
  • Supports concurrent transactions
• 633 MHz Clock for High Bandwidth
• Four-word Burst for Reducing Address Bus Frequency
• Double Data Rate (DDR) Interfaces on both Read and Write Ports (data transferred at 1266 MHz) at 633 MHz
• Available in 2.5 Clock Cycle Latency
• Two Input Clocks (K and K) for precise DDR Timing
  • SRAM uses rising edges only
• Echo Clocks (CQ and CQ) simplify Data Capture in High Speed Systems
• For more, see pdf
   

Functional Description

The CY7C1563XV18, and CY7C1565XV18 are 1.8 V Synchronous Pipelined SRAMs, equipped with QDR II+ architecture. Similar to QDR II architecture, QDR II+ architecture consists of two separate ports: the read port and the write port to access the memory array. The read port has dedicated data outputs to support read operations and the write port has dedicated data inputs to support write operations. QDR II+ architecture has separate data inputs and data outputs to completely eliminate the need to “turnaround” the data bus that exists with common I/O devices.

• Separate independent read and write data ports
• 450 MHz clock for high bandwidth
• Two-word burst for reducing address bus frequency
• Double Data Rate (DDR) interfaces on both read and write ports (data transferred at 900 MHz) at 450 MHz
• Available in 2.5 clock cycle latency
• Two input clocks (K and K) for precise DDR timing
• Echo clocks (CQ and CQ) simplify data capture in high-speed systems
• Data valid pin (QVLD) to indicate valid data on the output
• On-Die Termination (ODT) feature
• For more, see pdf

Functional Description

The CY7C2562XV18, and CY7C2564XV18 are 1.8 V Synchronous Pipelined SRAMs, equipped with QDR™-II+ architecture. Similar to QDR II architecture, QDR II+ architecture consists of two separate ports: the read port and the write port to access the memory array. The read port has dedicated data outputs to support read operations and the write port has dedicated data inputs to support write operations. QDR II+ architecture has separate data inputs and data outputs to completely eliminate the need to “turnaround” the data bus that exists with common devices.

Features

• Separate independent read and write data ports
  • Supports concurrent transactions
• 550-MHz clock for high bandwidth
• Four-word burst for reducing address bus frequency
• Double data rate (DDR) interfaces on both read and write ports (data transferred at 1100 MHz) at 550 MHz
• Available in 2.5-clock cycle latency
• Two input clocks (K and K) for precise DDR timing
  • SRAM uses rising edges only
• Echo clocks (CQ and CQ) simplify data capture in high-speed systems
• Data valid pin (QVLD) to indicate valid data on the output Single multiplexed address input bus latches address inputs for read and write ports
• For more, see pdf.

Functional Description

The CY7C1663KV18, and CY7C1665KV18 are 1.8-V synchronous pipelined SRAMs, equipped with QDR II+ architecture. Similar to QDR II architecture, QDR II+ architecture consists of two separate ports: the read port and the write port to access the memory array. The read port has dedicated data outputs to support read operations and the write port has dedicated data inputs to support write operations. QDR II+ architecture has separate data inputs and data outputs to completely eliminate the need to “turnaround” the data bus that exists with common I/O devices. Each port is accessed through a common address bus. Addresses for read and write addresses are latched on alternate rising edges of the input (K) clock.

• 256 K × 32 common I/O
• 3.3 V core power supply (VDD)
• 2.5 V/3.3 V I/O power supply (VDDQ)
• Fast clock-to-output times
  • 6.5 ns (133-MHz version)
• Provide high-performance 2-1-1-1 access rate
• User-selectable burst counter supporting Intel® Pentium® interleaved or linear burst sequences
• Separate processor and controller address strobes
• Synchronous self-timed write
• Asynchronous output enable
• Supports 3.3 V I/O level
• Available in 165-Ball FBGA package
• “ZZ” Sleep Mode option
• IEEE 1149.1 JTAG-compatible boundary scan

Functional Description

The CY7C1365C is a 256 K × 32 synchronous cache RAM designed to interface with high-speed microprocessors with minimum glue logic. Maximum access delay from clock rise is 6.5 ns (133-MHz version). A 2-bit on-chip counter captures the first address in a burst and increments the address automatically for the rest of the burst access. All synchronous inputs are gated by registers controlled by a positive-edge-triggered Clock Input (CLK).

Features

• Separate independent read and write data ports
  • Supports concurrent transactions
• 550 MHz clock for high bandwidth
• 4-word burst for reducing address bus frequency
• Double data rate (DDR) interfaces on both read and write ports (data transferred at 1100 MHz) at 550 MHz
• Available in 2.5 clock cycle latency
• Two input clocks (K and K) for precise DDR timing
  • SRAM uses rising edges only
• For more, see pdf

Functional Description

The CY7C2263KV18, and CY7C2265KV18 are 1.8 V synchronous pipelined SRAMs, equipped with QDR II+ architecture. Similar to QDR II architecture, QDR II+ architecture consists of two separate ports: the read port and the write port to access the memory array. The read port has dedicated data outputs to support read operations and the write port has dedicated data inputs to support write operations. QDR II+ architecture has separate data inputs and data outputs to completely eliminate the need to “turn-around” the data bus that xists with common I/O devices. Each port is accessed through a common address bus. Addresses for read and write addresses are latched on alternate rising edges of the input (K) clock. 

Features

• Separate independent read and write data ports
  • Supports concurrent transactions
• 450-MHz clock for high bandwidth
• Four-word burst for reducing address bus frequency
• Double data rate (DDR) interfaces on both read and write ports (data transferred at 900 MHz) at 450 MHz
• Available in 2.0-clock cycle latency
• Two input clocks (K and K) for precise DDR timing
  • SRAM uses rising edges only
• Echo clocks (CQ and CQ) simplify data capture in high-speed systems
• Data valid pin (QVLD) to indicate valid data on the output
• For more, see pdf.
   

Functional Description

The CY7C1643KV18, and CY7C1645KV18 are 1.8-V synchronous pipelined SRAMs, equipped with QDR II+ architecture. Similar to QDR II architecture, QDR II+ architecture consists of two separate ports: the read port and the write port to access the memory array. The read port has dedicated data outputs to support read operations and the write port has dedicated data inputs to support write operations. QDR II+ architecture has separate data inputs and data outputs to completely eliminate the need to “turnaround” the data bus that exists with common I/O devices. Each port is accessed through a common address bus. Addresses for read and write addresses are latched on alternate rising edges of the input (K) clock.

• Separate independent read and write data ports
  • Supports concurrent transactions
• 550-MHz clock for high bandwidth
• Four-word burst for reducing address bus frequency
• Double data rate (DDR) interfaces on both read and write ports (data transferred at 1100 MHz) at 550 MHz
• Available in 2.5 clock cycle latency
• Two input clocks (K and K) for precise DDR timing
  • SRAM uses rising edges only
• Echo clocks (CQ and CQ) simplify data capture in high-speed systems
• For more, see pdf
   

Functional Description

The CY7C2163KV18, and CY7C2165KV18 are 1.8 V synchronous pipelined SRAMs, equipped with QDR II+ architecture. Similar to QDR II architecture, QDR II+ architecture consists of two separate ports: the read port and the write port to access the memory array. The read port has dedicated data outputs to support read operations and the write port has dedicated data inputs to support write operations. QDR II+ architecture has separate data inputs and data outputs to completely eliminate the need to ‘turnaround’ the data bus that exists with common I/O devices. Each port is accessed through a common address bus. Addresses for read and write addresses are latched on alternate rising edges of the input (K) clock.

• Pin-compatible and functionally equivalent to ZBT™
• Supports 250-MHz bus operations with zero wait states
• Internally self-timed output buffer control to eliminate the need to use asynchronous OE
• Fully registered (inputs and outputs) for pipelined operation
• Byte Write capability
• 2.5 V core power supply
• 2.5 V/1.8 V I/O power supply
• Fast clock-to-output times
• Clock enable (CEN) pin to suspend operation
• Synchronous self-timed writes
• For more, see pdf.

Functional Description

The CY7C1462BV25 are 2.5 V, 2 M × 18 synchronous pipelined burst SRAMs with No Bus Latency™ (NoBL™) logic, respectively. They are designed to support unlimited true back-to-back read/write operations with no wait states. The CY7C1462BV25 are equipped with the advanced NoBL logic required to enable consecutive read/write operations with data being transferred on every clock cycle.
 

• 36 Mbit density (2 M × 18, 1 M × 36)
• 450 MHz clock for high bandwidth
• 2-word burst for reducing address bus frequency
• Double data rate (DDR) interfaces (data transferred at 900 MHz) at 450 MHz
• Available in 2.0 clock cycle latency
• Two input clocks (K and K) for precise DDR timing
  • SRAM uses rising edges only
• Echo clocks (CQ and CQ) simplify data capture in high speed systems
• Data valid pin (QVLD) to indicate valid data on the output
• For more, see pdf

Functional Description

The CY7C1248KV18, and CY7C1250KV18 are 1.8 V synchronous pipelined SRAMs equipped with DDR II+ architecture. The DDR II+ consists of an SRAM core with advanced synchronous peripheral circuitry. Addresses for read and write are latched on alternate rising edges of the input (K) clock. Write data is registered on the rising edges of both K and K. Read data is driven on the rising edges of K and K. Each address location is associated with two 18-bit words (CY7C1248KV18), or 36-bit words (CY7C1250KV18) that burst sequentially into or out of the device.
 

• Separate independent read and write data ports
  • Supports concurrent transactions
• 550 MHz clock for high bandwidth
• 4-word burst for reducing address bus frequency
• Double data rate (DDR) Interfaces on both read and write ports (data transferred at 1100 MHz) at 550 MHz
• Available in 2.5 clock cycle latency
• Two input clocks (K and K) for precise DDR timing
  • SRAM uses rising edges only
• Echo clocks (CQ and CQ) simplify data capture in high speed systems
• For more, see pdf

Functional Description

The CY7C1263KV18, and CY7C1265KV18 are 1.8 V synchronous pipelined SRAMs, equipped with QDR II+ architecture. Similar to QDR II architecture, QDR II+ architecture consists of two separate ports: the read port and the write port to access the memory array. The read port has dedicated data outputs to support read operations and the write port has dedicated data inputs to support write operations. QDR II+  architecture has separate data inputs and data outputs to completely eliminate the need to “turnaround” the data bus that exists with common I/O devices.

• Registered inputs and outputs for pipelined operation
• 256 K × 32 common I/O architecture
• 3.3 V core power supply (VDD)
• 2.5 V/3.3 V I/O power supply (VDDQ)
• Fast clock-to-output times
  • 3.5 ns (for 166-MHz device)
• Provide high-performance 3-1-1-1 access rate
• User-selectable burst counter supporting Intel® Pentium® interleaved or linear burst sequences
• Separate processor and controller address strobes
• Synchronous self-timed writes
• Asynchronous output enable
• Available in JEDEC-standard lead-free 100-pin TQFP package
• TQFP Available with 3-Chip Enable
• “ZZ” Sleep Mode Option

Functional Description

The CY7C1364CV33 SRAM integrates 256 K × 32 SRAM cells with advanced synchronous peripheral circuitry and a two-bit counter for internal burst operation. All synchronous inputs are gated by registers controlled by a positive-edge-triggered Clock Input (CLK). The synchronous inputs include all addresses, all data inputs, address-pipelining Chip Enable (CE1), depth-expansion Chip Enables (CE2 and CE3), Burst Control inputs (ADSC, ADSP, and ADV), Write Enables (BW[A:D], and BWE), and Global Write (GW). Asynchronous inputs include the Output Enable (OE) and the ZZ pin.

• Separate independent read and write data ports
• 333-MHz clock for high bandwidth
• 2-word burst on all accesses
• Double data rate (DDR) interfaces on both read and write ports (data transferred at 666 MHz) at 333 MHz
• Two input clocks (K and K) for precise DDR timing
• Two input clocks for output data (C and C) to minimize clock skew and flight time mismatches
• Echo clocks (CQ and CQ) simplify data capture in high-speed systems
• Single multiplexed address input bus latches address inputs for both read and write ports
• Separate port selects for depth expansion
• For more, see pdf

 
Functional Description

The CY7C1625KV18, CY7C1612KV18, and CY7C1614KV18 are 1.8-V synchronous pipelined SRAMs, equipped with QDR II architecture. QDR II architecture consists of two separate ports: the read port and the write port to access the memory array. The read port has dedicated data outputs to support read operations and the write port has dedicated data inputs to support write operations. QDR II architecture has separate data inputs and data outputs to completely eliminate the need to ‘turn around’ the data bus that exists with common I/O devices. Access to each port is through a common address bus. Addresses for read and write addresses are latched on alternate rising edges of the input (K) clock.

• Separate independent read and write data ports
• 450 MHz clock for high bandwidth
• 2-word burst for reducing address bus frequency
• Double Data Rate (DDR) interfaces on both read and write ports (data transferred at 900 MHz) at 450 MHz
• Available in 2.5 clock cycle latency
• Two input clocks (K and K) for precise DDR timing
• Echo clocks (CQ and CQ) simplify data capture in high-speed systems
• Data valid pin (QVLD) to indicate valid data on the output
• On-Die Termination (ODT) feature
• For more, see pdf

Functional Description

The CY7C2262XV18, and CY7C2264XV18 are 1.8 V Synchronous Pipelined SRAMs, equipped with QDR™-II+ architecture. Similar to QDR II architecture, QDR II+ architecture consists of two separate ports: the read port and the write port to access the memory array. The read port has dedicated data outputs to support read operations and the write port has dedicated data inputs to support write operations. QDR II+ architecture has separate data inputs and data outputs to completely eliminate the need to “turnaround” the data bus that exists with common devices.

• Separate independent read and write data ports
• 633 MHz clock for high bandwidth
• 4-word burst for reducing address bus frequency
• Double Data Rate (DDR) interfaces on both read and write ports (data transferred at 1266 MHz) at 633 MHz
• Available in 2.5 clock cycle latency
• Two input clocks (K and K) for precise DDR timing
• Echo clocks (CQ and CQ) simplify data capture in high-speed systems
• Data valid pin (QVLD) to indicate valid data on the output
• On-Die Termination (ODT) feature
• Single multiplexed address input bus latches address inputs for read and write ports
• Separate port selects for depth expansion
• Synchronous internally self-timed writes
• For more, see pdf

Functional Description

The CY7C2263XV18, and CY7C2265XV18 are 1.8 V Synchronous Pipelined SRAMs, equipped with QDR II+ architecture. Similar to QDR II architecture, QDR II+ architecture consists of two separate ports: the read port and the write port to access the memory array. The read port has dedicated data outputs to support read operations and the write port has dedicated data inputs to support write operations. QDR II+ architecture has separate data inputs and data outputs to completely eliminate the need to “turn-around” the data bus that exists with common I/O devices.

• 36-Mbit density (2 M × 18, 1 M × 36)
• 633 MHz clock for high bandwidth
• 2-word burst for reducing address bus frequency
• Double data rate (DDR) interfaces (data transferred at 1266 MHz) at 633 MHz
• Available in 2.5 clock cycle latency
• Two input clocks (K and K) for precise DDR timing
• Echo Clocks (CQ and CQ) simplify data capture in high speed systems
• Data valid pin (QVLD) to indicate valid data on the output
• On-die termination (ODT) feature
• Synchronous internally self-timed writes
• For more, see pdf

Functional Description

The CY7C2268XV18, and CY7C2270XV18 are 1.8 V Synchronous Pipelined SRAMs equipped with DDR II+ architecture. The DDR II+ consists of an SRAM core with advanced synchronous peripheral circuitry. Addresses for read and write are latched on alternate rising edges of the input (K) clock. Write data is registered on the rising edges of both K and K. Read data is driven on the rising edges of K and K. Each address location is associated with two 18-bit words (CY7C2268XV18), or 36-bit words (CY7C2270XV18) that burst sequentially into or out of the device.

• Separate independent read and write data ports
• 450 MHz clock for high bandwidth
• Two-word burst for reducing address bus frequency
• Double Data Rate (DDR) interfaces on both read and write ports (data transferred at 900 MHz) at 450 MHz
• Available in 2.5 clock cycle latency
• Two input clocks (K and K) for precise DDR timing
• Echo clocks (CQ and CQ) simplify data capture in high speed systems
• Data valid pin (QVLD) to indicate valid data on the output
• Single multiplexed address input bus latches address inputs for both read and write ports 
• For more, see pdf

Functional Description

The CY7C1562XV18, and CY7C1564XV18 are 1.8 V Synchronous Pipelined SRAMs, equipped with QDR® II+ architecture. Similar to QDR II architecture, QDR II+ architecture consists of two separate ports: the read port and the write port to access the memory array. The read port has dedicated data outputs to support read operations and the write port has dedicated data inputs to support write operations. QDR II+ architecture has separate data inputs and data outputs to completely eliminate the need to “turnaround” the data bus that exists with common I/Os devices.

• 72-Mbit density (4 M × 18, 2 M × 36)
• 633 MHz clock for high bandwidth
• Two-word burst for reducing address bus frequency
• Double data rate (DDR) interfaces (data transferred at 1266 MHz) at 633 MHz
• Available in 2.5 clock cycle latency
• Two input clocks (K and K) for precise DDR timing
• Echo clocks (CQ and CQ) simplify data capture in high speed systems
• Data valid pin (QVLD) to indicate valid data on the output
• Synchronous internally self-timed writes
• For more, See pdf.
   

Functional Description

The CY7C1568XV18, and CY7C1570XV18 are 1.8 V synchronous pipelined SRAMs equipped with DDR II+ architecture. The DDR II+ consists of an SRAM core with advanced synchronous peripheral circuitry. Addresses for read and write are latched on alternate rising edges of the input (K) clock. Write data is registered on the rising edges of both K and K. Read data is driven on the rising edges of K and K. Each address location is associated with two 18-bit words (CY7C1568XV18), or 36-bit words (CY7C1570XV18) that burst sequentially into or out of the device.

• Separate independent read and write data ports
• 633 MHz clock for high bandwidth
• Four-word burst for reducing address bus frequency
• Double data rate (DDR) interfaces on both read and write ports (data transferred at 1266 MHz) at 633 MHz
• Available in 2.5 clock cycle latency
• Two input clocks (K and K) for precise DDR timing
• Echo clocks (CQ and CQ) simplify data capture in high-speed systems
• Data valid pin (QVLD) to indicate valid data on the output
• On-die termination (ODT) feature
• For more, see pdf
   

Functional Description

The CY7C2563XV18 and CY7C2565XV18 are 1.8 V Synchronous Pipelined SRAMs, equipped with QDR II+ architecture. Similar to QDR II architecture, QDR II+ architecture consists of two separate ports: the read port and the write port to access the memory array. The read port has dedicated data outputs to support read operations and the write port has dedicated data inputs to support write operations. QDR II+ architecture has separate data inputs and data outputs to completely eliminate the need to “turn-around” the data bus that exists with common I/O devices.

Features

• 36-Mbit density (2 M × 18, 1 M × 36)
• 333 MHz clock for high bandwidth
• Two-word burst for reducing address bus frequency
• Double data rate (DDR) interfaces (data transferred at 666 MHz) at 333 MHz
• Two input clocks (K and K) for precise DDR timing
  • SRAM uses rising edges only
• Two input clocks for output data (C and C) to minimize clock skew and flight time mismatches
• Echo clocks (CQ and CQ) simplify data capture in high speed systems
• Synchronous internally self-timed writes
• For more, see pdf

Functional Description

The CY7C1418KV18, and CY7C1420KV18 are 1.8 V synchronous pipelined SRAM equipped with DDR II architecture. The DDR II consists of an SRAM core with advanced  synchronous peripheral circuitry and a 1-bit burst counter. Addresses for read and write are latched on alternate rising  edges of the input (K) clock.

Features

• 36 Mbit density (2 M × 18, 1 M × 36)
• 550 MHz clock for high bandwidth
• Two-word burst for reducing address bus frequency
• Double data rate (DDR) interfaces (data transferred at 1100 MHz) at 550 MHz
• Available in 2.5 clock cycle latency
• Two input clocks (K and K) for precise DDR timing
  • SRAM uses rising edges only
• Echo clocks (CQ and CQ) simplify data capture in high speed systems
• For more, see pdf

Functional Description

The CY7C2268KV18, and CY7C2270KV18 are 1.8 V synchronous pipelined SRAMs equipped with DDR II+ architecture. The DDR II+ consists of an SRAM core with advanced synchronous peripheral circuitry. Addresses for read and write are latched on alternate rising edges of the input (K) clock. Write data is registered on the rising edges of both K and K. Read data is driven on the rising edges of K and K. Each address location is associated with two 18-bit words (CY7C2268KV18), or 36-bit words (CY7C2270KV18) that burst sequentially into or out of the device.

• Separate independent read and write data ports
  • Supports concurrent transactions
• 450 MHz clock for high bandwidth
• Four-word burst for reducing address bus frequency
• Double data rate (DDR) interfaces on both read and write ports (data transferred at 900 MHz) at 450 MHz
• Available in 2.0 clock cycle latency
• Two input clocks (K and K) for precise DDR timing
  • SRAM uses rising edges only
• Echo clocks (CQ and CQ) simplify data capture in high speed systems
• For more, see pdf.

Functional Description

The CY7C1243KV18, and CY7C1245KV18 are 1.8 V synchronous pipelined SRAMs, equipped with QDR II+ architecture. Similar to QDR II architecture, QDR II+ architecture consists of two separate ports: the read port and the write port to access the memory array. The read port has dedicated data outputs to support read operations and the write port has dedicated data inputs to support write operations. QDR II+ architecture has separate data inputs and data outputs to completely eliminate the need to “turnaround” the data bus that exists with common I/O devices.

• 36 Mbit density (2 M x 18, 1 M x 36)
• 333 MHz clock for high bandwidth
• Two-word burst for reducing address bus frequency
• Double data rate (DDR) interfaces (data transferred at 666 MHz) at 333 MHz
• Two input clocks (K and K) for precise DDR timing
  • SRAM uses rising edges only
• Two input clocks for output data (C and C) to minimize clock skew and flight time mismatches
• Echo clocks (CQ and CQ) simplify data capture in high speed systems
• Synchronous internally self timed writes
• For more, see pdf 

Functional Description

The CY7C1423KV18, and CY7C1424KV18 are 1.8 V synchronous pipelined SRAMs, equipped with DDR II SIO (double data rate separate I/O) architecture. The DDR II SIO consists of two separate ports: the read port and the write port to access the memory array. The read port has data outputs to support read operations and the write port has data inputs to support write operations. The DDR II SIO has separate data inputs and data outputs to completely eliminate the need to turnaround” the data bus required with common I/O devices.

Features

• 36 Mbit density (2 M × 18, 1 M × 36)
• 550 MHz clock for high bandwidth
• 2-word burst for reducing address bus frequency
• Double data rate (DDR) interfaces (data transferred at 1100 MHz) at 550 MHz
• Available in 2.5 clock cycle latency
• Two input clocks (K and K) for precise DDR timing
  • SRAM uses rising edges only
• Echo clocks (CQ and CQ) simplify data capture in high speed systems
• For more, see pdf

Functional Description

The CY7C1268KV18, and CY7C1270KV18 are 1.8 V synchronous pipelined SRAMs equipped with DDR II+ architecture. The DDR II+ consists of an SRAM core with advanced synchronous peripheral circuitry. Addresses for read and write are latched on alternate rising edges of the input (K) clock. Write data is registered on the rising edges of both K and K. Read data is driven on the rising edges of K and K. Each address location is associated with two 18-bit words (CY7C1268KV18), or 36-bit words (CY7C1270KV18) that burst sequentially into or out of the device.. 

• 36-Mbit density (2 M × 18, 1 M × 36)
• 633 MHz clock for high bandwidth
• Two-word burst for reducing address bus frequency
• Double data rate (DDR) interfaces (data transferred at 1266 MHz) at 633 MHz
• Available in 2.5 clock cycle latency
• Two input clocks (K and K) for precise DDR timing
• Echo clocks (CQ and CQ) simplify data capture in high speed systems
• Data valid pin (QVLD) to indicate valid data on the output
• Synchronous internally self-timed writes
• DDR II+ Xtreme operates with 2.5 cycle read latency when DOFF is asserted HIGH
• Operates similar to DDR I device with 1 cycle read latency when DOFF is asserted LOW
• For more, see pdf

Functional Description

The CY7C1268XV18, and CY7C1270XV18 are 1.8 V synchronous pipelined SRAMs equipped with DDR II+ architecture. The DDR II+ consists of an SRAM core with advanced synchronous peripheral circuitry. Addresses for read and write are latched on alternate rising edges of the input (K) clock. Write data is registered on the rising edges of both K and K. Read data is driven on the rising edges of K and K. Each address location is associated with two 18-bit words (CY7C1268XV18), or 36-bit words (CY7C1270XV18) that burst sequentially into or out of the device.

• Separate independent read and write data ports
• 450 MHz clock for high bandwidth
• Two-word burst for reducing address bus frequency
• Double Data Rate (DDR) interfaces on both read and write ports (data transferred at 900 MHz) at 450 MHz
• Available in 2.5 clock cycle latency
• Two input clocks (K and K) for precise DDR timing
• Echo clocks (CQ and CQ) simplify data capture in high speed systems
• Data valid pin (QVLD) to indicate valid data on the output
• Single multiplexed address input bus latches address inputs for both read and write ports
• Separate port selects for depth expansion
• Synchronous internally self-timed writes
• For more, see pdf
   

Functional Description

The CY7C1262XV18, and CY7C1264XV18 are 1.8 V Synchronous Pipelined SRAMs, equipped with QDR® II+ architecture. Similar to QDR II architecture, QDR II+ architecture consists of two separate ports: the read port and the write port to access the memory array. The read port has dedicated data outputs to support read operations and the write port has dedicated data inputs to support write operations. QDR II+ architecture has separate data inputs and data outputs to  completely eliminate the need to “turnaround” the data bus that exists with common I/O devices.

• Separate Independent Read and Write Data Ports
• 633 MHz Clock for High Bandwidth
• Four-word Burst for Reducing Address Bus Frequency
• Double Data Rate (DDR) Interfaces on both Read and Write Ports (data transferred at 1266 MHz) at 633 MHz
• Available in 2.5 Clock Cycle Latency
• Two Input Clocks (K and K) for precise DDR Timing
• Echo Clocks (CQ and CQ) simplify Data Capture in High Speed Systems
• Data Valid Pin (QVLD) to indicate Valid Data on the Output
• Single Multiplexed Address Input Bus latches Address Inputs for Read and Write Ports
• Separate Port selects for Depth Expansion
• Synchronous Internally Self-timed Writes
• For more, see pdf
   

Functional Description

The CY7C1263XV18, and CY7C1265XV18 are 1.8 V Synchronous Pipelined SRAMs, equipped with QDR II+ architecture. Similar to QDR II architecture, QDR II+ architecture consists of two separate ports: the read port and the write port to access the memory array. The read port has dedicated data outputs to support read operations and the write port has dedicated data inputs to support write operations. QDR II+ architecture has separate data inputs and data outputs to completely eliminate the need to “turnaround” the data bus that exists with common I/O devices.

http://www.cypress.com/?docID=23984

For example, let us consider a QDR-II memory (for example, CY7C1315KV18 - Density 512 K x 36)

1. Activity factor ‘α’ =1 (Because the data gets transferred on both edges of the clock, 0.5 for Standard Sync and NoBL)
2. Maximum Clock Frequency ‘f’ is 333 MHz
3. Load Capacitance C_L is 5 pF (This value depends on the actual board layout and the load capacitance seen by the output pin of the memory)
4. Number of Switching I/Os N is 36 (This will be the number of I/Os driving the load)
5. V_DDQ is 1.9 V maximum
   Based on the formula, P = α f C_L V_DDQ² N
   I/O Switching Power is 216 mW
   I_DDQ is 113 mA

Customers must use this to design their power circuitry accordingly.

Features

• Can support up to 133-MHz bus operations with zero wait states
  • Data is transferred on every clock
• Pin compatible and functionally equivalent to ZBT™ devices
• Internally self-timed output buffer control to eliminate the need to use OE
• Registered inputs for flow-through operation
• Byte write capability
• 128 K × 36 common I/O architecture
• 2.5 V/3.3 V I/O power supply (VDDQ)
• Fast clock-to-output times
• For more, see pdf

Functional Description

The CY7C1351G is a 3.3 V, 128 K × 36 synchronous flow-through burst SRAM designed specifically to support unlimited true back-to-back read/write operations without the insertion of wait states. The CY7C1351G is equipped with the advanced No Bus Latency™ (NoBL™) logic required to enable consecutive Read/Write operations with data being transferred on every clock cycle. This feature dramatically improves the throughput of data through the SRAM, especially in systems that require frequent write-read transitions.

Features

• Pin compatible and functionally equivalent to ZBT
• Supports 250 MHz bus operations with zero wait states
  • Available speed grades are 250, 200 and 167 MHz
• Internally self timed output buffer control to eliminate the need to use asynchronous OE
• Fully registered (inputs and outputs) for pipelined operation
• Byte write capability
• 3.3 V power supply
• 3.3 V/2.5 V I/O power supply
• Fast clock-to-output times
• For more, see pdf
   

Functional Description

The CY7C1460AV33/CY7C1462AV33 are 3.3 V, 1 M × 36/2 M × 18 synchronous pipelined burst SRAMs with No Bus Latency™ (NoBL™) logic, respectively. They are designed to support unlimited true back-to-back read/write operations with no wait states. The CY7C1460AV33/CY7C1462AV33 are equipped with the advanced (NoBL) logic required to enable consecutive read/write operations with data being transferred on every clock cycle.

Features

• No Bus Latency™ (NoBL™) architecture eliminates dead cycles between write and read cycles
• Supports up to 133-MHz bus operations with zero wait states
  • Data is transferred on every clock
• Pin-compatible and functionally equivalent to ZBT™ devices
• Internally self-timed output buffer control to eliminate the need to use OE
• Registered inputs for flow through operation
• Byte write capability
• 3.3 V/2.5 V IO power supply (VDDQ)
• Fast clock-to-output times
• For more, see pdf
   

Functional Description

The CY7C1371D/CY7C1373D is a 3.3 V, 512 K × 36/1 M × 18 synchronous flow through burst SRAM designed specifically to support unlimited true back-to-back read/write operations with no wait state insertion. The CY7C1371D/CY7C1373D is equipped with the advanced No Bus Latency (NoBL) logic required to enable consecutive read/write operations with data being transferred on every clock cycle. This feature dramatically improves the throughput of data through the SRAM, especially in systems that require frequent write-read transitions.

Features

• Registered inputs and outputs for pipelined operation
• 128 K × 32 common I/O architecture
• 3.3 V core power supply (VDD)
• 2.5 V/3.3 V I/O power supply (VDDQ)
• Fast clock-to-output times
  • 4.0 ns (for 133-MHz device)
• Provide high-performance 3-1-1-1 access rate
• User-selectable burst counter supporting Intel® Pentium® interleaved or linear burst sequences
• Separate processor and controller address strobes
• For more, see pdf
   

Functional Description

The CY7C1339G SRAM integrates 128 K × 32 SRAM cells with advanced synchronous peripheral circuitry and a two-bit counter for internal burst operation. All synchronous inputs are gated by registers controlled by a positive-edge-triggered clock input (CLK). The synchronous inputs include all addresses, all data inputs, address-pipelining chip enable (CE1), depth-expansion chip enables (CE2 and CE3), burst control inputs (ADSC, ADSP, and ADV), write enables (BW[A:D], and BWE), and global write (GW). Asynchronous inputs include the output enable (OE) and the ZZ pin.

Features

• No Bus Latency™ (NoBL™) architecture eliminates dead cycles between write and read cycles
• Supports up to 133 MHz bus operations with zero wait states
• Data is transferred on every clock
• Pin compatible and functionally equivalent to ZBT™ devices
• Internally self timed output buffer control to eliminate the need to use OE
• Registered inputs for flow through operation
• Byte Write capability
• 3.3 V/2.5 V IO supply (VDDQ)
• Fast clock-to-output times
• For more, see pdf

Functional Description

The CY7C1471V33 is 3.3 V, 2 M × 36 synchronous flow through burst SRAMs designed specifically to support unlimited true back-to-back read or write operations without the insertion of wait states. The CY7C1471V33 is equipped with the advanced No Bus Latency (NoBL) logic required to enable consecutive read or write operations with data being transferred on every clock cycle. This feature dramatically improves the throughput of data through the SRAM, especially in systems that require frequent write-read transitions.

Features

• 256 K × 18 common I/O
• 3.3 V core power supply (VDD)
• 2.5 V or 3.3 V I/O power supply (VDDQ)
• Fast clock-to-output times
• 6.5 ns (133 MHz version)
• Provide high performance 2-1-1-1 access rate
• User selectable burst counter supporting Intel Pentium interleaved or linear burst sequences
• Separate processor and controller address strobes
• Synchronous self timed write
• Asynchronous output enable
• Available in Pb-free 100-pin TQFP package
• “ZZ” sleep mode option
   

Functional Description

The CY7C1325G is a 256 K × 18 synchronous cache RAM designed to interface with high speed microprocessors with minimum glue logic. Maximum access delay from clock rise is 6.5 ns (133 MHz version). A 2 bit on-chip counter captures the first address in a burst and increments the address automatically for the rest of the burst access. All synchronous inputs are gated by registers controlled by a positive-edge-triggered Clock Input (CLK).

An external pull-up resistor to Vt = Vddq/2 is normally recommended termination scheme for HSTL inputs for better signal integrity at high switching speeds. However, in ODT enabled devices, the termination is available internal to the die, for the input signals such as D bus, BWSb, and K/Kb clocks. So there is no need for external pull-up on these signals.

For more information, refer to the Application Note AN42468 - On-Die Termination for QDRII+/DDRII+ SRAMs.

Features

• Pin-compatible with and functionally equivalent to ZBT™
• Supports 250-MHz bus operations with zero wait states
• Available speed grades are 250, 200, and 166 MHz
• Internally self-timed output buffer control to eliminate the need to use asynchronous OE
• Fully registered (inputs and outputs) for pipelined operation
• Byte write capability
• Single 2.5 V power supply (VDD)
• Fast clock-to-output times
  • 2.8 ns (for 250-MHz device)
• For more, see pdf

Functional Description

The CY7C1354CV25 and CY7C1356CV25 are 2.5 V, 256 K × 36 and 512 K × 18 synchronous pipelined burst SRAMs with No Bus Latency™ (NoBL™) logic, respectively. They are designed to support unlimited true back-to-back read/write operations with no wait states. The CY7C1354CV25 and CY7C1356CV25 are equipped with the advanced (NoBL) logic required to enable consecutive read/write operations with data being transferred on every clock cycle.

Features

• Supports bus operatioup to 200 MHz
• Available speed grades:  200 and 166 MHz
• Registered inputs and outputs for pipelined operation
• 3.3 V core power supply (VDD)
• 2.5 V/3.3 V I/O operatio(VDDQ)
• Fast clock-to-output times
  • 3.0 ns (for 200 MHz device)
• Provide high performance 3-1-1-1 access rate
• User selectable burst counter supporting Intel® Pentium® interleaved or linear burst sequences
• For more, see pdf

Functional Description

The CY7C1360C/CY7C1362C SRAM integrates 256 K × 36 and 512 K × 18 SRAM cells with advanced synchronous peripheral circuitry and a two-bit counter for internal burst operation. All  synchronous inputs are gated by registers controlled by a positive-edge-triggered clock input (CLK). The synchronous inputs include all addresses, all data inputs, address-pipelining chip enable (CE1), depth-expansion chip enables (CE2 and CE3[1]), burst control inputs (ADSC, ADSP, and ADV), write enables (BWX, and BWE), and global write (GW). Asynchronous inputs include the output enable (OE) and the ZZ pin.

Features

• Pin compatible and functionally equivalent to ZBT
• Supports 200 MHz Bus operations with zero wait states
  • Available speed grades are 200 and 167 MHz
• Internally self timed output buffer control to eliminate the need to use asynchronous OE
• Fully registered (inputs and outputs) for pipelined operation
• Byte write capability
• Single 3.3 V power supply
• 3.3 V/2.5 V I/O power supply
• Fast clock-to-output time
• For more, see pdf

Functional Description

The CY7C1470V33, CY7C1472V33, and CY7C1474V33 are 3.3 V, 2 M x 36/4 M x 18/1 M x 72 synchronous pipelined burst SRAMs with No Bus Latency™ (NoBL™) logic, respectively. They are designed to support unlimited true back-to-back read/write operations with no wait states. The CY7C1470V33, CY7C1472V33, and CY7C1474V33 are equipped with the advanced (NoBL) logic required to enable consecutive read/write operations with data being transferred on every clock cycle.

Features

• Supports bus operation up to 166 MHz
• Available speed grade is 166 MHz
• Registered inputs and outputs for pipelined operation
  • Optimal for performance (double-cycle deselect)
    • Depth expansion without wait state
  • 3.3 V – 5% and 10% core power supply (VDD)
• 2.5 V/3.3 V I/O power supply (VDDQ)
• Fast clock-to-output times
  • 3.5 ns (for 166 MHz device)
• For more, see pdf
   

Functional Description

The CY7C1366C/CY7C1367C SRAM integrates 256 K × 36 and 512 K × 18 SRAM cells with advanced synchronous peripheral circuitry and a two-bit counter for internal burst operation. All synchronous inputs are gated by registers controlled by a positive-edge-triggered clock input (CLK). The synchronous inputs include all addresses, all data inputs, address-pipelining chip enable (CE1), depth-expansion chip enables (CE2 and CE3 [1]), burst control inputs (ADSC, ADSP, and ADV), write enables (BWX, and BWE), and global write (GW). Asynchronous inputs include the output enable (OE) and the ZZ pin.

Features

• Registered inputs and outputs for pipelined operation
• Optimal for performance (double-cycle deselect)
  • Depth expansion without wait state
• 256 K × 18 common I/O architecture
• 3.3 V core power supply (VDD)
• 3.3 V/2.5 V I/O power supply (VDDQ)
• Fast clock-to-output times
  • 4.0 ns (for 133-MHz device)
• Provide high-performance 3-1-1-1 access rate
• For more, see pdf
   

Functional Description

The CY7C1328G SRAM integrates 256 K × 18 SRAM cells with advanced synchronous peripheral circuitry and a two-bit counter for internal burst operation. All synchronous inputs are gated by registers controlled by a positive-edge-triggered clock input (CLK). The synchronous inputs include all addresses, all data inputs, address-pipelining chip enable (CE1), depth-expansion chip enables (CE2 and CE3), burst control inputs (ADSC, ADSP, and ADV), write enables (BW[A:B], and BWE), and global write (GW). Asynchronous inputs include the output enable (OE) and the ZZ pin.

Features

• Supports up to 100-MHz bus operations with zero wait states
  • Data is transferred on every clock
• Pin compatible and functionally equivalent to ZBT™ devices
• Internally self timed output buffer control to eliminate the need to use OE
• Registered inputs for flow-through operation
• Byte write capability
• 256 K × 18 common IO architecture
• 2.5 V / 3.3 V IO power supply (VDDQ)
• Fast clock-to-output times
• For more, see pdf
   

Functional Description

The CY7C1353G is a 3.3 V, 256 K × 18 synchronous flow-through burst SRAM designed specifically to support unlimited true back-to-back read/write operations without the insertion of wait states. The CY7C1353G is equipped with the advanced No Bus Latency™ (NoBL™) logic required to enable consecutive read/write operations with data being transferred on every clock cycle. This feature dramatically improves the throughput of data through the SRAM, especially in systems that require frequent write-read transitions.

Features

• Supports 100, 133 MHz bus operations
• Supports 100 MHz bus operations (Automotive)
• 256 K × 36/512 K × 18 common I/O
• 3.3 V – 5% and +10% core power supply (VDD)
• 2.5 V or 3.3 V I/O power supply (VDDQ)
• Fast clock-to-output times
  • 6.5 ns (133-MHz version)
• Provide high performance 2-1-1-1 access rate
• User-selectable burst counter supporting Intel® Pentium® interleaved or linear burst sequences
• For more, see pdf
   

Functional Description

The CY7C1361C/CY7C1363C is a 3.3 V, 256 K × 36/512 K × 18 synchronous flow-through SRAMs, respectively designed to interface with high speed microprocessors with minimum glue logic. Maximum access delay from clock rise is 6.5 ns (133 MHz version). A 2-bit on-chip counter captures the first address in a burst and increments the address automatically for the rest of the burst access. All synchronous inputs are gated by registers controlled by a positive-edge-triggered clock input (CLK).

Features

• Pin compatible and functionally equivalent to ZBT™ devices
• Internally self-timed output buffer control to eliminate the need to use OE
• Byte write capability
• 128 K × 36 common I/O architecture
• 3.3 V power supply (VDD)
• 2.5 V / 3.3 V I/O power supply (VDDQ)
• Fast clock-to-output times
  • 2.6 ns (for 250-MHz device)
• Clock enable (CEN) pin to suspend operation
• For more, see pdf
   

Functional Description

The CY7C1350G is a 3.3 V, 128 K × 36 synchronous-pipelined burst SRAM designed specifically to support unlimited true back-to-back read/write operations without the insertion of wait states. The CY7C1350G is equipped with the advanced No Bus Latency™ (NoBL™) logic required to enable consecutive read/write operations with data being transferred on every clock cycle. This feature dramatically improves the throughput of the SRAM, especially in systems that require frequent write/read transitions.

For Sync SRAMs Write happens when a LOW is detected on the rising edge of the sampling clock, as against a /WE pulse in Async SRAMs. So for back-to-back Write operations, /WE can be kept LOW.

Features

• 128 K × 32 common I/O
• 3.3 V core power supply (VDD)
• 2.5 V or 3.3 V I/O supply (VDDQ)
• Fast clock-to-output times
  • 8.0 ns (100-MHz version)
• Provide high-performance 2-1-1-1 access rate
• User-selectable burst counter supporting Intel® Pentium® interleaved or linear burst sequences
• Separate processor and controller address strobes
• Synchronous self-timed write
• Asynchronous output enable
• Offered in Pb-free 100-pin TQFP package
• “ZZ” sleep mode option
   

Functional Description

The CY7C1338G is a 128 K × 32 synchronous cache RAM designed to interface with high-speed microprocessors with minimum glue logic. Maximum access delay from clock rise is 8.0 ns (100-MHz version). A 2-bit on-chip counter captures the first address in a burst and increments the address automatically for the rest of the burst access. All synchronous inputs are gated by registers controlled by a positive-edge-triggered clock input (CLK).

Features

• Pin compatible and functionally equivalent to ZBT™ devices
• Internally self-timed output buffer control to eliminate the need to use OE
• Byte write capability
• 256 K × 18 common I/O architecture
• 3.3 V core power supply (VDD)
• 2.5 V/3.3 V I/O power supply (VDDQ)
• Fast clock-to-output times
  • 4.0 ns (for 133-MHz device)
• Clock enable (CEN) pin to suspend operation
• For more, see pdf

Functional Description

The CY7C1352G is a 3.3 V, 256 K × 18 synchronous-pipelined burst SRAM designed specifically to support unlimited true back-to-back read/write operations without the insertion of wait states. The CY7C1352G is equipped with the advanced No Bus atency™ (NoBL™) logic required to enable consecutive read/write operations with data being transferred on every clock cycle. This feature dramatically improves the throughput of the SRAM, especially in systems that require frequent write/read transitions.

Features

• No Bus Latency™ (NoBL™) architecture eliminates dead cycles between write and read cycles
• Can support up to 133-MHz bus operations with zero wait states
  • Data is transferred on every clock
• Pin compatible and functionally equivalent to ZBT™ devices
• Internally self-timed output buffer control to eliminate the need to use OE
• Registered inputs for flow-through operation
• Byte write capability
• 3.3 V / 2.5 V I/O power supply (VDDQ)
• Fast clock-to-output times
• For more, see pdf
   

Functional Description

The CY7C1355C/CY7C1357C is a 3.3 V, 256 K × 36 / 512 K × 18 synchronous flow-through burst SRAM designed specifically to support unlimited true back-to-back read/write operations without the insertion of wait states. The CY7C1355C/CY7C1357C is equipped with the advanced No Bus Latency (NoBL) logic required to enable consecutive read/write operations with data being transferred on every clock cycle. This feature dramatically improves the throughput of data through the SRAM, especially in systems that require frequent write-read transitions.

Features

• Pin-compatible and functionally equivalent to ZBT™
• Supports 200-MHz bus operations with zero wait states
  • Available speed grades are 200 and 167 MHz
• Internally self-timed output buffer control to eliminate the need to use asynchronous OE
• Fully registered (inputs and outputs) for pipelined operation
• Byte write capability
• Single 2.5 V power supply
• 2.5 V/1.8 V I/O supply (VDDQ)
• Fast clock-to-output times
• For more, see pdf

Functional Description

The CY7C1470V25/CY7C1472V25/CY7C1474V25 are 2.5 V, 2 M × 36/4 M × 18/1 M × 72 synchronous pipelined burst SRAMs with No Bus Latency™ (NoBL™logic, respectively. They are designed to support unlimited true back-to-back read/write operations with no wait states. The CY7C1470V25/CY7C1472V25/CY7C1474V25 are equipped with the advanced (NoBL) logic required to enable consecutive read/write operations with data being transferred on every clock cycle.

72-Mbit QDR®II SRAM Four-Word Burst Architecture (2.5 Cycle Read Latency) with ODT

Features

• Separate independent read and write data ports
  • Supports concurrent transactions
• 550 MHz clock for high bandwidth
• 4-word burst for reducing address bus frequency
• Double Data Rate (DDR) interfaces on both read and write ports (data transferred at 1100 MHz) at 550 MHz
• Available in 2.5 clock cycle latency
• Two input clocks (K and K) for precise DDR timing
  • SRAM uses rising edges only
• Echo clocks (CQ and CQ) simplify data capture in high-speed systems
• For more, see pdf
   

Functional Description

The CY7C25632KV18 and CY7C25652KV18 are 1.8 V Synchronous Pipelined SRAMs, equipped with QDR II+ architecture. Similar to QDR II architecture, QDR II+ architecture consists of two separate ports: the read port and the write port to access the memory array. The read port has dedicated data outputs to support read operations and the write port has dedicated data inputs to support write operations.

 

Features

• 128 K × 36 common I/O
• 3.3 V core power supply (VDD)
• 2.5 V or 3.3 V I/O supply (VDDQ)
• Fast clock-to-output times
  • 8.0 ns (100 MHz version)
• Provide high performance 2-1-1-1 access rate
• User selectable burst counter supporting Intel Pentium interleaved or linear burst sequences
• Separate processor and controller address strobes
• Synchronous self timed write
• Asynchronous output enable
• Available in Pb-free 100-pin TQFP package
• ZZ sleep mode option
   

Functional Description

The CY7C1345G is a 128 K × 36 synchronous cache RAM designed to interface with high speed microprocessors with minimum glue logic. The maximum access delay from clock rise is 8.0 ns (100 MHz version). A 2-bit on-chip counter captures the first address in a burst and increments the address automatically for the rest of the burst access. All synchronous inputs are gated by registers controlled by a positive edge triggered Clock Input (CLK).