64K x 4 Static RAM with Separate IO

Features

• High speed
  • 15 ns
• CMOS for optimum speed/power
• Low active power
  • 860 mW
• Low standby power
  • 55 mW
• TTL-compatible inputs and outputs
• Automatic power down when deselected
• Available in Pb-free and non Pb-free 28-Pin Molded SOJ package

Functional Description

The CY7C192 is a high performance CMOS static RAM organized as 65,536 x 4 bits with separate IO. Easy memory expansion is provided by active LOW Chip Enable (CE) and tri-state drivers. It has an automatic power down feature that reduces power consumption by 75% when deselected.

Features

• Temperature ranges
  • Military/Space: -55 °C to 125 °C
• High speed
  • tAA = 12 ns
• Low active power
  • ICC = 95 mA at 12 ns (PMAX = 315 mW)
• Low CMOS standby power
  • ISB2 = 15 mA
• 2.0 V data retention
• Automatic power-down when deselected
• Transistor-transistor logic (TTL) compatible inputs and outputs
• Easy memory expansion with CE and OE features
• Available in Pb-free 36-pin ceramic flat package
   

Functional Description

The CYRS1049DV33 is a high-performance complementary metal oxide semiconductor (CMOS) static RAM organized as 512 K words by 8 bits with RadStop™ technology. Cypress’s state-of-the-art RadStop technology is radiation hardened through proprietary design and process hardening techniques. The 4-Mbit fast asynchronous SRAM with RadStop technology is also QML V certified with Defense Logistics Agency Land and Maritime (DLAM).

Features

• Temperature ranges
  • Industrial: –40°C to 85°C
  • Automotive-A: –40°C to 85°C
  • Automotive-E: –40°C to 125°C
• Pin and function compatible with CY7C1011BV33
• High speed
  • tAA = 10 ns (Industrial and Automotive-A)
  • tAA = 12 ns (Automotive-E)
• Low active power
  • 360 mW (max) (Industrial and Automotive-A)
• For more, see pdf

Functional Description

The CY7C1011CV33 is a high performance complementary metal oxide semiconductor (CMOS) static RAM organized as 131,072 words by 16 bits. This device has an automatic power down feature that significantly reduces power consumption when deselected.

Features
 

• Pin-and function-compatible with CY7C1011CV33
• High speed
  • tAA = 10 ns
• Low active power
  • ICC = 90 mA @ 10 ns (Industrial)
• Low CMOS standby power
  • ISB2 = 10 mA 
• Data Retention at 2.0 V
• Automatic power-down when deselected
• Independent control of upper and lower bits
• Easy memory expansion with CE and OE features
• Available in Pb-free 44-pin TSOP II, and 48-ball VFBGA
   

Functional Description

The CY7C1011DV33 is a high-performance CMOS Static RAM organized as 128 K words by 16 bits.

Features

• Pin-and function-compatible with CY7C1020CV33
• High speed
  • tAA = 10 ns
• Low active power
  • ICC = 60 mA @ 10 ns
• Low CMOS standby power
  • ISB2 = 3 mA
• 2.0V Data retention
• Automatic power-down when deselected
• For more, see pdf
   

Functional Description

The CY7C1020DV33 is a high-performance CMOS static RAM organized as 32,768 words by 16 bits. This device has an automatic power-down feature that significantly reduces power consumption when deselected.

Features

• Fast access time: 15 ns
• Wide voltage range: 5.0 V ± 10% (4.5 V to 5.5 V)
• CMOS for optimum speed and power
• TTL compatible inputs and outputs
• Available in 24-pin DIP and 24-pin SOJ

General Description

The CY7C197BN is a high performance CMOS Asynchronous SRAM organized as 256 K × 1 bits that supports an asynchronous memory interface. The device features an automatic power down feature that significantly reduces power consumption when deselected.

Cypress's 90nm technology Asynchronous SRAMs have best-in-class specifications in speed and power making them an ideal choice as memories in a wide variety of applications today.

The application note below discusses how they are suited for present generation processors and controllers while Cypress' older generation SRAMs (250nm and 350nm) are a good fit for interfacing with legacy processors and controllers. The 90nm technology 5V devices are pin compatible with their older technology counterparts. The reason for Cypress continuing to support end users with older generations SRAMs is because of their increased V_OH levels that ensure compliance with CMOS V_IH levels of legacy processors and microcontrollers. While both generations of SRAM's have the same industry standard V_OH spec, the difference in actual V_OH levels enable Cypress to support processors of older and present generations, reiterating Cypress' commitment as the #1 supplier in the industry.

Please see the illustrations and the application note below for details.

Processor receiving data from SRAM on a read operation:

• High speed
  • t_AA = 12 ns
• Low active power
  • I_CC = 300 mA
• Low complementary metal oxide semiconductor (CMOS) standby power
  • I_SB2 = 100 mA
• Operating voltages of 3.3 ± 0.3 V
• 2.0-V data retention
• Automatic power-down when deselected
• Transistor-transistor logic (TTL)-compatible inputs and outputs
• Easy memory expansion with CE1 and CE2 features
• Available in Pb-free 48-ball fine ball grid array (FBGA) package

Functional Description

The CY7C1089DV33 is a high-performance CMOS static RAM organized as 8,388,608 words by 8 bits.

• High speed
  • t_AA = 12 ns
• Low active power
  • I_CC = 300 mA at 12ns
• Low complementary metal oxide semiconductor (CMOS) standby power
  • I_SB2 = 100 mA
• Operating voltages of 3.3 ± 0.3 V
• 2.0-V data retention
• Automatic power-down when deselected
• Transistor-transistor logic (TTL)-compatible inputs and outputs
• Easy memory expansion with CE1 and CE2 features
• Available in Pb-free 48-ball fine ball grid array (FBGA) package

Functional Description

The CY7C1081DV33 is a high-performance CMOS static RAM organized as 4,194,304 words by 16 bits.

Features

• Pin- and function-compatible with CY7C1020V33
• Temperature Ranges
  • Commercial: 0°C to 70°C
  • Industrial: –40°C to 85°C
  • Automotive: –40°C to 125°C
• High speed
  • t_AA = 10 ns
• CMOS for optimum speed/power
• Low active power
  • 325 mW (max.)
• Automatic power-down when deselected
• Independent control of upper and lower bits
• Available in Pb-free and non Pb-free 44-pin TSOP II package
   

Functional Description

The CY7C1020CV33 is a high-performance CMOS static RAM organized as 32,768 words by 16 bits. This device has an automatic power-down feature that significantly reduces power consumption when deselected.

Writing to the device is accomplished by taking Chip Enable (CE) and Write Enable (WE) inputs LOW. If Byte Low Enable (BLE) is LOW, then data from I/O pins (I/O₁ through I/O₈), is written into the location specified on the address pins (A₀ through A₁₄). If Byte High Enable (BHE) is LOW, then data from I/O pins (I/O₉ through I/O₁₆) is written into the location specified on the address pins (A₀ through A₁₄).

Features

• Temperature Ranges
  • Industrial: –40°C to 85°C
  • Automotive-A: –40°C to 85°C
• Piand Functiocompatible with CY7C1019BV33
• High Speed
  • tAA = 10 ns
• CMOS for optimum Speed and Power
• Data Retentioat 2.0V
• Center Power/Ground Pinout
• Automatic Power Dowwhedeselected
• Easy Memory Expansiowith CE and OE Options
• Available iPb-free and noPb-free 48-Ball VFBGA, 32-PiTSOII and 400-mil SOJ Package
   

Functional Description

The CY7C1019CV33 is a high performance CMOS static RAM organized as 131,072 words by 8 bits. Easy memory expansiois provided by aactive LOW ChiEnable (CE), aactive LOW Output Enable (OE), and tristate drivers. This device has aautomatic power dowfeature that significantly reduces power consumptiowhedeselected.

Features

• High speed
  • tAA = 10 ns
• Low active power
  • 990 mW (max)
• Operating voltages of 3.3 ± 0.3V
• 2.0V data retention
• Automatic power down when deselected
• TTL compatible inputs and outputs
• Easy memory expansion with CE1 and CE2 features
• Available in Pb-free and non Pb-free 54-pin TSOP II package and non Pb-free 60-ball fine pitch ball grid array (FBGA) package

Functional Description

The CY7C1061AV33 is a high performance CMOS Static RAM organized as 1,048,576 words by 16 bits.

To write to the device, enable the chip (CE1 LOW and CE2 HIGH) while forcing the Write Enable (WE) input LOW. If Byte Low Enable (BLE) is LOW, then data from IO pins (IO0 through IO7), is written into the location specified on the address pins (A0 through A19).

Features

• High speed
  • t_AA = 10 ns
• Low active power
  • 990 mW (max.)
• Operating voltages of 3.3 ± 0.3V
• 2.0V data retention
• Automatic power down when deselected
• TTL-compatible inputs and outputs
• Easy memory expansion with CE1 and CE2 features
• Available in Pb-free 54-pin thin small outline package (TSOP) II package

Functional Description

The CY7C1069AV33 is a high performance complementary metal oxide semiconductor (CMOS) static RAM organized as 2,097,152 words by 8 bits. Writing to the device is accomplished by enabling the chip (by taking CE1 LOW and CE2 HIGH) and Write Enable (WE) inputs LOW.

Features

• Pin- and function-compatible with CY7C1019CV33
• High speed
  • t_AA = 10 ns
• Low Active Power
  • I_CC = 60 mA @ 10 ns
• Low CMOS Standby Power
  • I_SB2 = 3 mA
• 2.0V Data retention
• Automatic power-down when deselected
• For more, see pdf
   

Functional Description

The CY7C1019DV33 is a high-performance CMOS static RAM organized as 131,072 words by 8 bits. Easy memory expansion is provided by an active LOW Chip Enable (CE), an active LOW Output Enable (OE), and three-state drivers. This device has an automatic power-down feature that significantly reduces power consumption when deselected.      More...

Features

• Pin and function compatible with CY7C1049CV33
• High speed
  • tAA = 10 ns
• Low active power
  • ICC = 90 mA @ 10 ns (Industrial)
• Low CMOS standby power
  • ISB2 = 10 mA
• 2.0V data retention
• Automatic power down when deselected
• TTL compatible inputs and outputs
• Easy memory expansion with CE and OE features
• Available in Pb-free 36-pin (400 Mil) Molded SOJ and 44-pin TSOP II packages
   

Functional Description

The CY7C1049DV33 is a high performance CMOS Static RAM organized as 512K words by 8-bits. Easy memory expansion is provided by an Active LOW Chip Enable (CE), an Active LOW Output Enable (OE), and tri-state drivers. You can write to the device by taking Chip Enable (CE) and Write Enable (WE) inputs LOW. Data on the eight IO pins (IO0 through IO7) is then written into the location specified on the address pins (A0 through A18).

Features

• Pin- and function-compatible with CY7C1049B
• High speed
  • tAA = 10 ns
• Low active power
  • ICC = 90 mA @ 10 ns
• Low CMOS Standby power
  • ISB2 = 10 mA
• 2.0V Data Retention
• Automatic power-down when deselected
• TTL-compatible inputs and outputs
• Easy memory expansion with CE and OE features
• Available in lead-free 36-Lead (400-Mil) Molded SOJ package
   

Functional Description

The CY7C1049D is a high-performance CMOS static RAM organized as 512K words by 8 bits. Easy memory expansion is provided by an active LOW Chip Enable (CE), an active LOW Output Enable (OE), and tri-state drivers. Writing to the device is  accomplished by taking Chip Enable (CE) and Write Enable (WE) inputs LOW. Data on the eight I/O pins (I/O0 through I/O7) is then written into the location specified on the address pins (A0 through A18).

Features

• Temperature ranges
  • Industrial: –40 °C to 85 °C
  • Automotive-A  : –40 °C to 85 °C
  • Automotive-E  : –40 °C to 125 °C
• Pin and function compatible with CY7C1041CV33
• High speed
  • tAA = 10 ns
• Low active power
  • ICC = 90 mA at 10 ns (industrial)
• For more, see pdf
   

Functional Description

The CY7C1041DV33 is a high performance CMOS Static RAM organized as 256 K words by 16-bits. To write to the device, take chip enable (CE) and write enable (WE) inputs LOW. If byte low enable (BLE) is LOW, then data from I/O pins (I/O0 to I/O7) is written into the location specified on the address pins (A0 to A17). If byte high enable (BHE) is LOW, then data from I/O pins (I/O8 to I/O15) is written into the location specified on the address pins (A0 to A17).

Features

• Pin-and function-compatible with CY7C1041B
• High speed
  • tAA = 10 ns
• Low active power
  • ICC = 90 mA at 10 ns (Industrial)
• Low CMOS standby power
  • ISB2 = 10 mA
• 2.0 V Data Retention
• Automatic power-down when deselected
• TTL-compatible inputs and outputs
• Easy memory expansion with CE and OE features
• Available in lead-free 44-Lead (400-Mil) Molded SOJ and 44-Pin TSOP II packages

Functional Description

The CY7C1041D is a high-performance CMOS static RAM organized as 256K words by 16 bits. Writing to the device is accomplished by taking Chip Enable (CE) and Write Enable (WE) inputs LOW. If Byte Low Enable (BLE) is LOW, then data from I/O pins (I/O0 through I/O7), is written into the location specified on the address pins (A0 through A17).

Features

• High speed
  • tAA = 10 ns
• Low active power
  • ICC = 110 mA at 10 ns
• Low CMOS standby power
  • ISB2 = 20 mA
• 2.0V data retention
• Automatic power down when deselected
• TTL-compatible inputs and outputs
• For more, see pdf

Functional Description

The CY7C1059DV33 is a high performance CMOS Static RAM organized as 1M words by 8 bits. Easy memory expansion is provided by an active LOW Chip Enable (CE), an active LOW Output Enable (OE), and tri-state drivers. To write to the device, take Chip Enable (CE) and Write Enable (WE) inputs LOW. Data on the eight IO pins (IO0 through IO7) is then written into the location specified on the address pins (A0 through A19).

Features

• Temperature ranges
  • –40 °C to 85 °C
• High speed
  • t_AA = 10 ns
• Low active power
  • I_CC = 110 mA at 10 ns
• Low CMOS standby power
  • I_SB2 = 20 mA
• 2.0V data retention
• Automatic power down when deselected
• TTL-compatible inputs and outputs
• Easy memory expansion with CE and OE features
• Available in Pb-free 48-ball fine ball grid array (FBGA) and 44-pin thin small outline package (TSOP) II packages

Functional Description

The CY7C1051DV33 is a high performance CMOS Static RAM organized as 512K words by 16 bits.

To write to the device, take Chip Enable (CE) and Write Enable (WE) inputs LOW. If Byte LOW Enable (BLE) is LOW, then data from IO pins (IO0–IO7), is written into the location specified on the address pins (A0–A18). If Byte HIGH Enable (BHE) is LOW, then data from IO pins (IO8–IO15) is written into the location specified on the address pins (A0–A18).

Features

• Temperature ranges
  • Commercial: 0°C to 70°C
• High speed
  • tAA = 8 ns
• Low active power
  • 360 mW (max)
• 2.0 V data retention
• Automatic power down when deselected
• Transistor-transistor logic (TTL) compatible inputs and outputs
• Easy memory expansion with CE and OE features

Functional Description

The CY7C1049CV33 is a high performance Complementary metal oxide semiconductor (CMOS) Static RAM organized as 524,288 words by eight bits. Easy memory expansion is provided by an active LOW Chip Enable (CE), an active LOW Output Enable (OE), and three-state drivers. Writing to the device is accomplished by taking Chip Enable (CE) and Write Enable (WE) inputs LOW. Data on the eight I/O pins (I/O₀ through I/O₇) is then written into the location specified on the address pins (A₀ through A₁₈).

Features

• Pin and function compatible with CY7C1010CV33
• High speed
  • tAA = 10 ns
• Low active power
  • ICC = 90 mA at 10 ns
• Low CMOS standby power
  • ISB2 = 10 mA
• 2.0V data retention
• Automatic power down when deselected
• TTL-compatible inputs and outputs
• Easy memory expansion with CE and OE features
• Available in Pb-Free 36-pin SOJ and 44-pin TSOP II package

Functional Description

The CY7C1010DV33 is a high performance CMOS Static RAM organized as 256K words by 8 bits. Easy memory expansion is provided by an active LOW Chip Enable (CE), an active LOW Output Enable (OE), and three-state drivers. Writing to the device is accomplished by taking Chip Enable (CE) and Write Enable (WE) inputs LOW. Data on the eight I/O pins (I/O0 through I/O7) is then written into the location specified on the address pins (A0 through A17).

Features

• High speed
  • 25 ns
• CMOS for optimum speed/power
• Low active power
  • 880 mW
• Low standby power
  • 220 mW
• TTL-compatible inputs and outputs
• Automatic power-down when deselected
   

Functional Description

The CY7C197N is a high-performance CMOS static RAM organized as 256K words by 1 bit. Easy memory expansion is provided by an active LOW Chip Enable (CE) and three-state drivers. The CY7C197N has an automatic power-down feature, reducing the power consumption by 75% when deselected.

Features

• Fast access time: 15 ns
• Wide voltage range: 5.0V ± 10% (4.5V to 5.5V)
• CMOS for optimum speed/power
• TTL-compatible inputs and outputs
• CY7C194BN is available in 24 DIP, 24 SOJ packages

General Description

The CY7C194BN is a high-performance CMOS Asynchronous SRAM organized as 64K × 4 bits that supports an asynchronous memory interface. The device features an automatic power-down feature that significantly reduces power consumption when deselected.

Features

• Pin- and function-compatible with CY7C1046CV33
• High speed
  • t_AA = 10 ns
• Low active power
  • I_CC = 90 mA @ 10 ns
• Low CMOS standby power
  • I_SB2 = 10 mA
• 2.0 V data retention
• Automatic power-down when deselected
• TTL-compatible inputs and outputs
• Easy memory expansion with CE and OE features
• Available in lead-free 400-mil-wide 32-pin SOJ package

Functional Description

The CY7C1046DV33 is a high-performance CMOS static RAM organized as 1M words by 4 bits. Easy memory expansion is provided by an active LOW Chip Enable (CE), an active LOW Output Enable (OE), and tri-state drivers. Writing to the device is accomplished by taking Chip Enable (CE) and Write Enable (WE) inputs LOW. Data on the four I/O pins (I/O0 through I/O3) is then written into the location specified on the address pins (A0 through A19).

Features

• 3.3V operation (3.0V–3.6V)
• High speed
  • t_AA = 10, 12, 15 ns
• CMOS for optimum speed/power
• Low Active Power (L version)
  • 576 mW (max.)
• Low CMOS Standby Power (L version)
  • 1.80 mW (max.)
• Automatic power-down when deselected
• Independent control of upper and lower bits
• Available in 44-pin TSOP II and 400-mil SOJ
• Available in a 48-Ball Mini BGA package
   

Functional Description

The CY7C1021BNV is a high-performance CMOS static RAM organized as 65,536 words by 16 bits. This device has an automatic power-down feature that significantly reduces power consumption when deselected.

Features

• High speed
  • tAA = 12 ns
• Low active power
  • 612 mW (max.)
• Low CMOS standby power
  • 1.8 mW (max.)
• 2.0V Data Retention (660 µW at 2.0V retention)
• Automatic power-down when deselected
• TTL-compatible inputs and outputs
• Easy memory expansion with CE and OE features
   

Functional Description

The CY7C1041BNV33 is a high-performance CMOS Static RAM organized as 262,144 words by 16 bits.

Writing to the device is accomplished by taking Chip Enable (CE) and Write Enable (WE) inputs LOW. If Byte Low Enable (BLE) is LOW, then data from I/O pins (I/O0 through I/O7), is written into the location specified on the address pins (A0 through A17). If Byte High Enable (BHE) is LOW, then data from I/O pins (I/O8 through I/O15) is written into the location specified on the address pins (A0 through A17).

Features

• Temperature Ranges
  • Industrial: –40°C to 85°C
  • Automotive-A: –40°C to 85°C
• Single 3.3V power supply
• Ideal for low-voltage cache memory applications
• High speed: 12 ns
• Low active power
  • 180 mW (max.)
• Low-power alpha immune 6T cell
• Available in Pb-free and non Pb-free Plastic SOJ and TSOP I packages
   

Functional Description

The CY7C1399BN is a high-performance 3.3V CMOS Static RAM organized as 32,768 words by 8 bits. Easy memory expansion is provided by an active LOW Chip Enable (CE) and active LOW Output Enable (OE) and tristate drivers. The device has an automatic power-down feature, reducing the power consumption by more than 95% when deselected.

An active LOW Write Enable signal (WE) controls the writing/reading operation of the memory. When CE and WE inputs are both LOW, data on the eight data input/output pins (I/O0 through I/O7) is written into the memory location addressed by the address present on the address pins (A0 through A14).

Features

• High speed
  • 15 ns
• Fast t_DOE
• CMOS for optimum speed/power
• Low active power
  • 550 mW (max, 15 ns “L” version)
• Low standby power
• 0.275 mW (max, “L” version)
• 2V data retention (“L” version only)
• Easy memory expansion with CE and OE features
• TTL-compatible inputs and outputs
• Automatic power-down when deselected
   

Functional Description

The CY7C199N is a high-performance CMOS static RAM organized as 32,768 words by 8 bits. Easy memory expansion is provided by an active LOW Chip Enable (CE) and active LOW Output Enable (OE) and three-state drivers.

Features

• Pin- and function-compatible with CY7C1046B
• High speed
  • t_AA = 10 ns
• CMOS for optimum speed/power
• Low active power
  • I_CC = 90 mA @ 10 ns
• Low CMOS Standby Power
  • I_SB2 = 10 mA
• Data Retention at 2.0 V
• Automatic power-down when deselected
• TTL-compatible inputs and outputs
• Easy memory expansion with CE and OE features
• Available in lead-free 400-mil-wide 32-pin SOJ package

Functional Description

The CY7C1046D is a high-performance CMOS static RAM organized as 1M words by 4 bits. Easy memory expansion is provided by an active LOW Chip Enable (CE), an active LOW Output Enable (OE), and tri-state drivers. Writing to the device is accomplished by taking Chip Enable (CE) and Write Enable (WE) inputs LOW. Data on the four I/O pins (I/O0 through I/O3) is then written into the location specified on the address pins (A0 through A19).

Features

• High speed
  • t_AA = 8 ns
• Low active power
  • I_CC = 225 mA at 8 ns
• Low CMOS standby power
  • I_SB2 = 25 mA
• Operating voltages of 3.3 ± 0.3V
• 2.0V data retention
• Automatic power down when deselected
• TTL compatible inputs and outputs
• Available in Pb-free standard 119-Ball PBGA

Functional Description

The CY7C1012DV33 is a high performance CMOS static RAM organized as 512K words by 24 bits. Each data byte is separately controlled by the individual chip selects (CE₁, CE₂, and CE₃). CE₁ controls the data on the IO₀ - IO₇, while CE₂ controls the data on IO₈ - IO₁₅, and CE₃ controls the data on the data pins IO₁₆ - IO₂₃. This device has an automatic power down feature that significantly reduces power consumption when deselected.     

Features

• Fast access time: 15 ns and 20 ns
• Wide voltage range: 5.0V ± 10% (4.5V to 5.5V)
• complementary metal oxide semiconductor (CMOS) for optimum speed and power
• Transistor transistor logic (TTL) compatible inputs and outputs
• 2.0 V data retention
• Low CMOS standby power
• Automated power down when deselected
• Available in Pb-free 28-pin Thin Small Outline Package (TSOP)I, 28-pin Molded Small Outline J-Lead (SOJ) and 28-pin DIP packages

General Description

The CY7C199CN is a high performance CMOS Asynchronous SRAM organized as 32K by 8 bits that supports an asynchronous memory interface. The device features an automatic power down feature that reduces power consumption when deselected.

Features

• Pin- and function-compatible with CY7C1019B
• High speed
  • tAA = 10 ns
• Low active power
  • ICC = 80 mA @ 10 ns
• Low CMOS standby power
  • ISB2 = 3 mA
• 2.0 V Data retention
• Automatic power-down when deselected
• For more, see pdf

Functional Description

The CY7C1019D is a high-performance CMOS static RAM organized as 131,072 words by 8 bits. Easy memory expansion is provided by an active LOW Chip Enable (CE), an active LOW Output Enable (OE), and tri-state drivers. This device has an automatic power-down feature that significantly reduces power consumption when deselected.

Features

• Pin- and function-compatible with CY7C1018CV33
• High speed
  • tAA = 10 ns
• Low Active Power
  • ICC = 60 mA @ 10 ns
• Low CMOS Standby Power
  • ISB2 = 3 mA
• 2.0V Data retention
• Automatic power-down when deselected
• CMOS for optimum speed/power
• Center power/ground pinout
• Easy memory expansion with CE and OE options
• Available in Pb-free 32-pin 300-Mil wide Molded SOJ

Functional Description

The CY7C1018DV33 is a high-performance CMOS static RAM organized as 131,072 words by 8 bits. Easy memory expansion is provided by an active LOW Chip Enable (CE), an active LOW Output Enable (OE), and tri-state drivers. This device has an automatic power-down feature that significantly reduces power consumption when deselected.

Features

• Temperature Ranges
  • Industrial: –40°C to 85°C
  • Automotive-A: –40°C to 85°C
• Pin-and function-compatible with CY7C1021CV33
• High speed
  • t_AA = 10 ns
• Low active power
  • I_CC = 60 mA @ 10 ns
• For more, see pdf

Functional Description

The CY7C1021DV33 is a high-performance CMOS static RAM organized as 65,536 words by 16 bits. This device has an automatic power-down feature that significantly reduces power consumption when deselected.

Features

• Pin- and function-compatible with CY7C106B/CY7C1006B
• High speed
  • t_AA = 10 ns
• Low active power
  • I_CC = 80 mA @ 10 ns
• Low CMOS standby power
  • I_SB2 = 3.0 mA
• 2.0V Data Retention
• Automatic power-down when deselected
• For more, see pdf

Functional Description

The CY7C106D and CY7C1006D are high-performance CMOS static RAMs organized as 262,144 words by 4 bits. Easy memory expansion is provided by an active LOW Chip Enable (CE), an active LOW Output Enable (OE), and tri-state drivers. These devices have an automatic power-down feature that reduces power consumption by more than 65% when the devices are deselected.

• High speed
• Low active power
• Low CMOS standby power
• 2.0 V data retention (400 µW at 2.0 V retention)
• Automatic power-down when deselected
• TTL-compatible inputs and outputs
• Easy memory expansion with CE and OE features

Functional Description

The CY7C1049BN is a high-performance CMOS static RAM organized as 524,288 words by 8 bits. Easy memory expansion is provided by an active LOW Chip Enable (CE), an active LOW Output Enable (OE), and three-state drivers. Writing to the device is accomplished by taking Chip Enable (CE) and Write Enable (WE) inputs LOW. Data on the eight I/O pins (I/O0 through I/O7) is then written into the location specified on the address pins (A0 through A18).

Features

• High speed
  • 15 ns
• Fast tDOE
• Low active power
  • 715 mW
• Low standby power
  • 85 mW
• CMOS for optimum speed/power
• Easy memory expansion with CE1, CE2 and OE features
• TTL-compatible inputs and outputs
• Automatic power down when deselected
• Available in non Pb-free 28-pin (300-Mil) Molded SOJ, 28-pin (300-Mil) Molded SOIC and Pb-free 28-pin (300-Mil) Molded DIP

Functional Description

The CY7C185 is a high-performance CMOS static RAM organized as 8192 words by 8 bits. Easy memory expansion is provided by an active LOW chip enable (CE1), an active HIGH chip enable (CE2), and active LOW output enable (OE) and tri-state drivers. This device has an automatic power down feature (CE1 or CE2), reducing the power consumption by 70% when deselected. The CY7C185 is in a standard 300-mil-wide DIP, SOJ, or SOIC package.      More...

Features

• High speed
  • tAA = 10 ns
• Low active power
  • ICC = 175 mA at f = 100MHz
• Low CMOS standby power
  • ISB2 = 25 mA
• Operating voltages of 3.3 ± 0.3V
• 2.0V data retention
• Automatic power down when deselected
• Fore more, see pdf
   

Functional Description

The CY7C1024DV33 is a high performance CMOS static RAM organized as 128K words by 24 bits. This device has an automatic power down feature that significantly reduces power consumption when deselected.      More...

Features

• Temperature ranges
  • Commercial: 0 °C to 70 °C
  • Industrial: –40 °C to 85 °C
  • Automotive-A: –40 °C to 85 °C
  • Automotive-E: –40 °C to 125 °C
• High speed
  • tAA = 10 ns (Commercial)
  • tAA = 15 ns (Automotive)
• Complementary metal oxide semiconductor (CMOS) for optimum speed/power
• For more, see pdf
   

Functional Description

The CY7C1021BN/CY7C10211BN[1] is a high performance CMOS static RAM organized as 65,536 words by 16 bits. This device has an automatic power down feature that significantly reduces power consumption when deselected.

Features

• Temperature ranges
  • Industrial: –40°C to 85°C
  • Automotive-E: –40°C to 125°C
• Pin and function compatible with CY7C199C
• High speed
  • tAA = 10 ns (Industrial)
• Low active power
  • ICC = 80 mA at 10 ns
• Low CMOS standby power
• For more, see pdf

Functional Description

The CY7C199D is a high performance CMOS static RAM organized as 32,768 words by 8 bits. Easy memory expansion is provided by an active LOW Chip Enable (CE), an active LOW Output Enable (OE) and tri-state drivers. This device has an automatic power down feature, reducing the power consumption when deselected.

Features

• High Speed
  • tAA = 12 ns
• Low Active Power
  • ICC = 250 mA at 12 ns
• Low CMOS Standby Power
  • ISB2 = 50 mA
• Operating Voltages of 3.3 ± 0.3 V
• 2.0 V Data Retention
• Automatic Power Down when Deselected
• TTL Compatible Inputs and Outputs
• Available in Pb-free 48-ball FBGA Package
   

Functional Description

The CY7C1079DV33 is a high performance CMOS Static RAM organized as 4,194,304 words by 8 bits.

To write to the device, take Chip Enable (CE [1]) and Write Enable (WE) input LOW. Data on the eight I/O pins (I/O0 through I/O7) is then written into the location specified on the address pins (A0 through A21). 

Features

• Pin- and function-compatible with CY7C109B/CY7C1009B
• High speed
  • tAA = 10 ns
• Low active power
  • ICC = 80 mA @ 10 ns
• Low CMOS standby power
  • ISB2 = 3 mA
• 2.0V Data Retention
• Automatic power-down when deselected
• For more, see pdf

Functional Description

The CY7C109D/CY7C1009D is a high-performance CMOS static RAM organized as 131,072 words by 8 bits. Easy memory expansion is provided by an active LOW Chip Enable (CE₁), an active HIGH Chip Enable (CE₂), an active LOW Output Enable (OE), and tri-state drivers.     

Features

• High speed
  • tAA = 10 ns
• Low active power
  • ICC = 175 mA at 10 ns
• Low CMOS standby power
  • ISB2 = 25 mA
• Operating voltages of 3.3 ± 0.3V
• 2.0V data retention
• Automatic power down when deselected
• TTL compatible inputs and outputs
• Easy memory expansion with CE1, CE2, and CE3 features
• Available in Pb-free 119-ball PBGA package

Functional Description

The CY7C1062DV33 is a high performance CMOS Static RAM organized as 524,288 words by 32 bits.      More...

• High speed
  • 20 ns
• Automatic power-down when deselected
• Low active power
  • 935 mW
• Low standby power
  • 83 mW
• CMOS for optimum speed/power
• TTL-compatible inputs and outputs
• Easy memory expansion with CE₁, CE₂, and OE features
• Available in non Pb-free 32-Lead (300-Mil) Molded SOJ
   

Functional Description

Features

• High speed
  • tAA = 10 ns
• Low active power
  • ICC = 175 mA at 10 ns
• Low CMOS standby power
  • ISB2 = 25 mA
• Operating voltages of 3.3 ± 0.3V
• 2.0V data retention
• Automatic power down when deselected
• TTL compatible inputs and outputs
• Easy memory expansion with CE1 and CE2 features
• Available in Pb-free 54-Pin TSOP II and 48-Ball VFBGA packages

Functional Description

The CY7C1069DV33 is a high performance CMOS Static RAM organized as 2,097,152 words by 8 bits.

To write to the device, take Chip Enables (CE1 LOW and CE2 HIGH) and Write Enable (WE) input LOW. Data on the eight IO pins (IO0 through IO7) is then written into the location specified on the address pins (A0 through A20). 

Features

• High speed
  • tAA = 10 ns
• Low active power
  • ICC = 175 mA at 100 MHz
• Low CMOS standby power
  • ISB2 = 25 mA
• Operating voltages of 3.3 ± 0.3 V
• 2.0 V data retention
• Automatic power down when deselected
• TTL compatible inputs and outputs
• Easy memory expansion with CE1 and CE2 features
• Available in Pb-free 54-pin TSOP II and 48-ball VFBGA packages
• Offered in single CE and dual CE options

Functional Description

The CY7C1061DV33 is a high performance CMOS Static RAM organized as 1,048,576 words by 16 bits.

To write to the device, take Chip Enables (CE1 LOW and CE2 HIGH) and Write Enable (WE) input LOW. If Byte Low Enable (BLE) is LOW, then data from I/O pins (I/O0 through I/O7), is written into the location specified on the address pins (A0 through A19). If Byte High Enable (BHE) is LOW, then data from I/O pins (I/O8 through I/O15) is written into the location specified on the address pins (A0 through A19).

Features

• Pin- and function-compatible with CY7C107B/CY7C1007B
• High speed
  • tAA = 10 ns
• Low active power
  • ICC = 80 mA @ 10 ns
• Low complementary metal oxide semiconductor (CMOS) standby power
  • ISB2 = 3 mA
• 2.0 V data retention
• Automatic power-down when deselected
• CMOS for optimum speed/power
• Transistor transistor logic (TTL) compatible inputs and outputs
• CY7C107D available in Pb-free 28-pin 400-Mil wide Molded SOJ package. CY7C1007D available in Pb-free 28-pin 300-Mil wide Molded SOJ package
   

Functional Description

The CY7C107D and CY7C1007D are high-performance CMOS static RAMs organized as 1,048,576 words by 1 bit. Easy memory expansion is provided by an active LOW Chip Enable (CE) and tri-state drivers. These devices have an automatic power-down feature that reduces power consumption by more than 65% when deselected.

Features

• Temperature Ranges
  • Commercial: 0°C to 70°C
  • Industrial: –40°C to 85°C
  • Automotive-A: –40°C to 85°C
• High speed
  • t_AA = 15 ns
• Low active power
  • 1540 mW (max.)
• Low CMOS standby power (L version)
• For more, see pdf
   

Functional Description

The CY7C1041BN is a high-performance CMOS static RAM organized as 262,144 words by 16 bits.

Writing to the device is accomplished by taking Chip Enable (CE) and Write Enable (WE) inputs LOW. If Byte Low Enable (BLE) is LOW, then data from I/O pins (I/O₀ through I/O₇), is written into the location specified on the address pins (A₀ through A₁₇).

• Automatic power-down when deselected
• Complementary metal oxide semiconductor (CMOS) for optimum speed/power
• High speed
  • t_AA = 20 ns
• Low active power
  • 495 mW
• Low standby power
  • 110 mW
• TTL-compatible inputs and outputs
• V_IH of 2.2V
• Capable of withstanding greater than 2001V electrostatic discharge
   

Functional Description

The CY7C168A is a high-performance CMOS static RAM organized as 4096 by 4-bits. Easy memory expansion is provided by an active LOW chip enable (CE) and three-state drivers. The CY7C168A has an automatic power-down feature, reducing the power consumption by 77% when deselected.

Features

• High speed
  • t_AA = 8 ns
• Low active power
  • 1080 mW (max.)
• Operating voltages of 3.3 ± 0.3V
• 2.0V data retention
• Automatic power-down when deselected
• TTL-compatible inputs and outputs
• Easy memory expansion with CE0, CE1 and CE2 features
• Available in non Pb-free 119 ball PBGA.
   

Functional Description

The CY7C1012AV33 is a high-performance CMOS static RAM organized as 512K words by 24 bits. Each data byte is separately controlled by the individual chip selects (CE0, CE1, CE2). CE0 controls the data on the I/O0–I/O7, while CE1 controls the data on I/O8–I/O15, and CE2 controls the data on the data pins I/O16–I/O23. This device has an automatic power-down feature that significantly reduces power consumption when deselected.

Features

• Temperature Range
  • Automotive: –40°C to 125°C
• High speed
  • t_AA = 15 ns
• Optimized voltage range: 2.5V – 2.7V
• Low active power: 220 mW (Max.)
• Automatic power-down when deselected
• Independent control of upper and lower bits
• CMOS for optimum speed/power
• Available in Pb-free and non Pb-free 44-pin TSOP II , 44-pin (400-Mil) Molded SOJ and Pb-free 48-ball FPBGA packages
   

Functional Description

The CY7C1021CV26 is a high-performance CMOS static RAM organized as 65,536 words by 16 bits. This device has an automatic power-down feature that significantly reduces power consumption when deselected.

Writing to the device is accomplished by taking Chip Enable (CE) and Write Enable (WE) inputs LOW. If Byte Low Enable (BLE) is LOW, then data from I/O pins (I/O1 through I/O8), is written into the location specified on the address pins (A0 through A15). If Byte High Enable (BHE) is LOW, then data from I/O pins (I/O9 through I/O16) is written into the location specified on the address pins (A0 through A15).

Features

• Temperature range
  • Automotive: –40°C to 125°C
• High speed
  • t_AA = 15 ns
• Optimized voltage range: 2.5V to 2.7V
• Automatic power down when deselected
• Independent control of upper and lower bits
• CMOS for optimum speed and power
• Package offered: 44-pin TSOP II
   

Functional Description

The CY7C1020CV26 is a high performance CMOS static RAM organized as 32,768 words by 16 bits. This device has an automatic power down feature that significantly reduces power consumption when deselected.  Writing to the device is accomplished by taking Chip Enable (CE) and Write Enable (WE) inputs LOW. If Byte Low Enable (BLE) is LOW, then data from I/O pins (I/O1 through I/O8), is written into the location specified on the address pins (A0 through A14). If Byte High Enable (BHE) is LOW, then data from I/O pins (I/O9 through I/O16) is written into the location specified on the address pins (A0 through A14).

Features

• High speed
  • tAA = 12 ns
• Low active power
  • ICC = 250 mA at 83.3 MHz
• Low Complementary Metal Oxide Semiconductor (CMOS) standby power
  • ISB2 = 50 mA
• Operating voltages of 3.3 ± 0.3 V
• 2.0 V data retention
• Automatic power down when deselected
• TTL compatible inputs and outputs
• Available in Pb-free 48-ball FBGA package

Functional Description

The CY7C1071DV33 is a high performance CMOS Static RAM organized as 2,097,152 words by 16 bits. The input and output pins (I/O0 through I/O15) are placed in a high impedance state when:

• Deselected (CE HIGH)
• Outputs are disabled (OE HIGH)
• Both byte high enable and byte low enable are disabled (BHE, BLE HIGH)
• The write operation is active (CE LOW and WE LOW)

Features

• High Speed
  • tAA = 15 ns
• Low Active Power
  • ICC = 150 mA at 67 MHz
• Low CMOS Standby Power
  • ISB2 = 25 mA
• Operating Voltages of 1.7V to 2.2V
• 1.5V Data Retention
• Automatic Power Down when deselected
• TTL-compatible Inputs and Outputs
• Easy Memory Expansion with CE1 and CE2 Features
• Available in Pb-free 54-Pin Thin Small Outline Package (TSOP) II Package

Functional Description

The CY7C1061DV18 is a high performance CMOS Static RAM (SRAM) organized as 1,048,576 words by 16 bits.

To write to the device, enable the chip (CE1 LOW and CE2 HIGH) while forcing the Write Enable (WE) input LOW. If Byte Low Enable (BLE) is LOW, then data from I/O pins (I/O0 through I/O7), is written into the location specified on the address pins (A0 through A19).

• Fast access time: 12 ns
• Wide voltage range: 5.0 V ± 10% (4.5 V to 5.5 V)
• Complementary metal oxide semiconductor (CMOS) for optimum speed and power
• Transistor-transistor logic (TTL) compatible inputs and outputs
• Low CMOS standby power
• Automated power down when deselected
• Available in 28-pin Molded SOJ package

General Description

The CY7C199CN Automotive is a high performance CMOS Asynchronous SRAM organized as 32 K by 8 bits that supports an asynchronous memory interface. The device features an automatic power down feature that reduces power consumption when deselected.

Features

• Temperature ranges
  • Automotive-A: –40°C to 85°C
  • Automotive-E: –40°C to 125°C
• Pin and function compatible with CY7C1021BV33
• High speed
  • tAA = 10 ns (Automotive-A)
  • tAA = 12 ns (Automotive-E)
• For more, see pdf
   

Functional Description

The CY7C1021CV33 is a high performance CMOS static RAM organized as 65,536 words by 16 bits. This device has an automatic power down feature that significantly reduces power consumption when deselected.

Features

• Temperature ranges
  • Industrial: –40°C to 85°C
• Pin and function compatible with CY7C1041BV33
• High speed
  • tAA = 8 ns
• For more, see pdf
   

Functional Description

The CY7C1041CV33 is a high performance CMOS static RAM organized as 262,144 words by 16 bits.

To write to the device, take Chip Enable (CE) and Write Enable (WE) inputs LOW. If Byte Low Enable (BLE) is LOW, then data from IO pins (IO0 through IO7), is written into the location specified on the address pins (A0 through A17).

Features

• High speed
  • tAA = 10 ns
• Low active power
  • ICC = 175 mA at f = 100 MHz
• Low CMOS standby power
  • ISB2 = 25 mA
• Operating voltages of 3.3 ± 0.3V
• 2.0V data retention
• Automatic power down when deselected
• For more, see pdf
   

Functional Description

The CY7C1034DV33 is a high performance CMOS static RAM organized as 256K words by 24 bits. This device has an automatic power down feature that significantly reduces power consumption when deselected.      More...

Features

• Pin- and function-compatible with CY7C1020B
• High speed
  • tAA = 10 ns
• Low active power
  • ICC = 80 mA @ 10ns
• Low complementary metal oxide semiconductor (CMOS) standby power
  • ISB2 = 3 mA
• 2.0 V data retention
• Automatic power-down when deselected
• CMOS for optimum speed/power
• Independent control of upper and lower bits
• Available in Pb-free 44-pin 400-Mil wide Molded SOJ and 44-pin thin small outline package (TSOP) II packages

Functional Description

The CY7C1020D is a high-performance CMOS static RAM organized as 32,768 words by 16 bits. This device has an automatic power-down feature that significantly reduces power consumption when deselected.

Features

• Temperature Ranges:
  • Industrial: –40°C to 85°C
  • Automotive-A: –40°C to 85°C
• Pin and Function Compatible with CY7C1021B
• High Speed
  • t_AA = 10 ns
• Low Active Power
  • I_CC = 80 mA at 10 ns
• For more, see pdf
   

Functional Description

The CY7C1021D is a high performance CMOS static RAM organized as 65,536 words by 16 bits. This device has an automatic power down feature that significantly reduces power consumption when deselected. The input and output pins (IO₀ through IO₁₅) are placed in a high impedance state when the device is deselected (CE HIGH), outputs are disabled (OE HIGH), BHE and BLE are disabled (BHE, BLE HIGH), or during a write operation (CE LOW and WE LOW).

Features

• Temperature ranges
  • Automotive -A: –40 °C to 85 °C
  • Automotive-E: –40 °C to 125 °C
• High speed
  • tAA = 10 ns
• Low active power
  • 360 mW (max)
• 2.0 V data retention
• Automatic power down when deselected
• TTL-compatible inputs and outputs
• Easy memory expansion with CE and OE features

Functional Description

The CY7C1049CV33 Automotive is a high performance CMOS Static RAM organized as 524,288 words by eight bits. Easy memory expansion is provided by an active LOW Chip Enable (CE), an active LOW Output Enable (OE), and three-state drivers. Writing to the device is accomplished by taking Chip Enable (CE) and Write Enable (WE) inputs LOW. Data on the eight I/O pins (I/O0 through I/O7) is then written into the location specified on the address pins (A0 through A18).

Features

• Async SRAMs, Dual ports, FIFOs, Micropower SRAMs, PROMs, Sync SRAMs wafer and die, WirelessUSB LP wafer
• Wafer
  • Standard wafer 25 to 30 mil thick
  • Background wafer to 14 mil thick
  • Background wafer to 11 mil thick
• Die
  • Die in wafer form 25 to 30 mil thick
  • Background die to 14 mil thick
  • Background die to 11 mil thick
  • Known good die (KGD) levels 1, 2, 3, and 4
• Temperature ranges
  • Commercial, Industrial, and Automotive
• Waffle pack packages

Wafer and Die Classification

Cypress’s package products are sold in both wafer and die form. Cypress classifies them as follows:

Wafer

Wafers are probed at room temperature and high temperature to guarantee full functionality. Other parameters are guaranteed based on the level of product that is supplied to the customer. Details of product levels are described later in this document.

Known Good Die (KGD)

KGD is available in both die in wafer form and background die. Product in wafer form is not background and is anywhere from 25 to 30 mil thick. Background die are 14 or 11 mil thick, sawed, and shipped in waffle packs. The product in either form is tested at four different levels.

Level 1

Wafers are probed to guarantee full functionality and all static DC parameters. Other parameters are not guaranteed and warranted, including device reliability.

Level 2

Wafers are probed to guarantee full functionality to all static DC and partial AC parameters. Other parameters are not guaranteed and warranted, including device reliability.

Level 3

Wafers are probed to guarantee full functionality and all static DC and AC parameters. All parameters are guaranteed and warranted, including device reliability.

Wafers and die in wafer form are shipped in jars with die maps. Background die are shipped as die in waffle packs.

Level 4

Wafers are probed to guarantee all static DC parameters. RF testing guidelines and statistical data of packaged parts are provided.

Background die are shipped as die in waffle packs.

We have created a html tools for the same and are attached below. One is for Sync SRAMs and other one is for Async and NVSRAMs. You can use it to find Maximum Power Consumption and Maximum Junction Temperature for a Cypress SRAM part. 

The following is the absolute maximum junction temperatures for the SRAM families:

Sync SRAM: 125°C
Async SRAM: 150°C
nvSRAM: 150°C