Cypress.com: Documentation http://www.cypress.com/?app=search&searchType=advanced&id%3D86 AN4011 - Choosing The Right Cypress Synchronous SRAM http://www.cypress.com/?rID=13042 The purpose of this application note is to provide a means to determine which architecture is right for a particular application. A brief description of each architecture and comparison by address/data relationships and performance characteristics is also included.

The table below shows the architecture comparison for the different options:                                                                            


Parameter

Std. Sync

NoBLTM

DDR-II/DDR-II+

QDRTM-II/ QDRTM-II+

Data Rate

Single

Single

Double

Double

Data Bus

Common I/O

Common I/O

Common and Separate I/O

Separate I/O

VDD

3.3V/2.5V

3.3V/2.5V

1.8V

1.8V

VDDQ

LVTTL 3.3V/2.5V

LVTTL 3.3V/3.5V

HSTL (1.5V/1.8V)

HSTL (1.5V/1.8V)

Clock Frequency

250 MHz

250 MHz

333 MHz / 550 MHz

333 MHz / 550 MHz
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Tue, 22 Apr 2014 06:59:38 -0600
CY7C1441AV25, CY7C1447AV25: 36-Mbit (1 M × 36/512 K × 72) Flow-Through SRAM http://www.cypress.com/?rID=60162 36-Mbit (1 M × 36/512 K × 72) Flow-Through SRAM

Features

  • Supports 133 MHz bus operations
  • 1 M × 36/512 K × 72 common I/O
  • 2.5 V core power supply
  • 2.5 V and 1.8 V I/O power supply
  • Fast clock-to-output times
  • Provide high performance 2-1-1-1 access rate
  • User selectable burst counter supporting Intel® Pentium® interleaved or linear burst sequences
  • Separate processor and controller address strobes
  • Synchronous self timed write
  • For more, see pdf
     

Functional Description

The CY7C1441AV25/CY7C1447AV25 are 2.5 V, 1 M × 36/512 K × 72 Synchronous Flow-Through SRAMs, designed to interface with high speed microprocessors with minimum glue logic. Maximum access delay from clock rise is 6.5 ns (133 MHz version). A 2-bit on-chip counter captures the first address in a burst and increments the address automatically for the rest of the burst access. All synchronous inputs are gated by registers controlled by a positive edge-triggered Clock Input (CLK).

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Thu, 27 Mar 2014 07:07:24 -0600
CY7C1384D: 18-Mbit (512 K × 32) Pipelined SRAM http://www.cypress.com/?rID=62954 18-Mbit (512 K × 32) Pipelined SRAM

Features

  • Supports bus operation up to 166 MHz
  • Available speed grades are 166 MHz
  • Registered inputs and outputs for pipelined operation
  • 3.3 V core power supply
  • 2.5 V or 3.3 V I/O power supply
  • Fast clock-to-output times
  • Provides high performance 3-1-1-1 access rate
  • For more, see pdf


Functional Description

The CY7C1384D SRAM integrates 524,288 × 32 SRAM cells with advanced synchronous peripheral circuitry and a two-bit counter for internal burst operation. All synchronous inputs are gated by registers controlled by a positive edge triggered clock input (CLK).

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Thu, 27 Mar 2014 06:13:49 -0600
CY7C1484BV25: 72-Mbit (2 M × 36) Pipelined DCD Sync SRAM http://www.cypress.com/?rID=70320 72-Mbit (2 M × 36) Pipelined DCD Sync SRAM

Features

  • Supports bus operation up to 250 MHz
  • Available speed grades are 250 MHz
  • Registered inputs and outputs for pipelined operation
  • Optimal for performance (double cycle deselect)
  • Depth expansion without wait state
  • 2.5 V core power supply (VDD)
  • 2.5 V I/O supply (VDDQ)
  • Fast clock to output times
    • 3.0 ns (for 250 MHz device)
  • Provide high performance 3-1-1-1 access rate
  • For more, see pdf

Functional Description

The CY7C1484BV25 SRAM integrates 2 M × 36 SRAM cells with advanced synchronous peripheral circuitry and a 2-bit counter for internal burst operation. All synchronous inputs are gated by registers controlled by a positive edge triggered Clock Input (CLK).

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Wed, 26 Mar 2014 01:49:03 -0600
CY7C1481BV25: 72-Mbit (2 M × 36) Flow-Through SRAM http://www.cypress.com/?rID=63896 72-Mbit (2 M × 36) Flow-Through SRAM

Features

  • Supports 133 MHz bus operations
  • 2 M × 36 common I/O
  • 2.5 V core power supply (VDD)
  • 2.5 V I/O supply (VDDQ)
  • Fast clock to output time
  • Provide high performance 2-1-1-1 access rate
  • User selectable burst counter supporting Intel® Pentium® interleaved or linear burst sequences
  • Separate processor and controller address strobes
  • For more, see pdf


Functional Description

The CY7C1481BV25 is a 2.5 V, 2 M × 36 synchronous flow through SRAM designed to interface with high speed microprocessors with minimum glue logic. Maximum access delay from clock rise is 6.5 ns (133 MHz version). A 2-bit on-chip counter captures the first address in a burst and increments the address automatically for the rest of the burst access. All synchronous inputs are gated by registers controlled by a positive edge triggered Clock Input (CLK).

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Wed, 26 Mar 2014 01:17:23 -0600
CY7C1385D: 18-Mbit (512 K × 32) Flow-Through SRAM http://www.cypress.com/?rID=63871 18-Mbit (512 K × 32) Flow-Through SRAM

Features

  • Supports 133 MHz bus operations
  • 512 K × 32 common I/O
  • 3.3 V core power supply (VDD)
  • 2.5 V or 3.3 V I/O supply (VDDQ)
  • Fast clock-to-output time
  • Provides high performance 2-1-1-1 access rate
  • User selectable burst counter supporting Intel Pentium interleaved or linear burst sequences
  • Separate processor and controller address strobes
  • Synchronous self-timed write
  • Asynchronous output enable
  • For more, see pdf


Functional Description

The CY7C1385D is a 3.3 V, 512 K × 32 synchronous flow through SRAMs, designed to interface with high speed microprocessors with minimum glue logic. Maximum access delay from clock rise is 6.5 ns (133 MHz version). A 2-bit on-chip counter captures the first address in a burst and increments the address automatically for the rest of the burst access. All synchronous inputs are gated by registers controlled by a positive edge triggered clock input (CLK).

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Wed, 26 Mar 2014 01:14:10 -0600
CY7C1325H: 4-Mbit (256 K × 18) Flow-Through Sync SRAM http://www.cypress.com/?rID=76992 4-Mbit (256 K × 18) Flow-Through Sync SRAM

Features

  • 256 K × 18 common I/O
  • 3.3 V core power supply (VDD)
  • 2.5 V or 3.3 V I/O power supply (VDDQ)
  • Fast clock-to-output times
  • 6.5 ns (133 MHz version)
  • Provide high performance 2-1-1-1 access rate
  • User selectable burst counter supporting Intel Pentium interleaved or linear burst sequences
  • For more, see pdf

Functional Description

The CY7C1325H is a 256 K × 18 synchronous cache RAM designed to interface with high speed microprocessors with minimum glue logic. Maximum access delay from clock rise is 6.5 ns (133 MHz version). A 2 bit on-chip counter captures the first address in a burst and increments the address automatically for the rest of the burst access. All synchronous inputs are gated by registers controlled by a positive-edge-triggered Clock Input (CLK).

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Wed, 26 Mar 2014 01:08:31 -0600
CY7C1364CV33: 9-Mbit (256 K × 32) Pipelined Sync SRAM http://www.cypress.com/?rID=58794 9-Mbit (256 K × 32) Pipelined Sync SRAM

 Features

  • Registered inputs and outputs for pipelined operation
  • 256 K × 32 common I/O architecture
  • 3.3 V core power supply (VDD)
  • 2.5 V/3.3 V I/O power supply (VDDQ)
  • Fast clock-to-output times
    • 3.5 ns (for 166-MHz device)
  • Provide high-performance 3-1-1-1 access rate
  • User-selectable burst counter supporting Intel® Pentium® interleaved or linear burst sequences
  • Separate processor and controller address strobes
  • Synchronous self-timed writes
  • Asynchronous output enable
  • Available in JEDEC-standard lead-free 100-pin TQFP package
  • TQFP Available with 3-Chip Enable
  • “ZZ” Sleep Mode Option

Functional Description

The CY7C1364CV33 SRAM integrates 256 K × 32 SRAM cells with advanced synchronous peripheral circuitry and a two-bit counter for internal burst operation. All synchronous inputs are gated by registers controlled by a positive-edge-triggered Clock Input (CLK). The synchronous inputs include all addresses, all data inputs, address-pipelining Chip Enable (CE1), depth-expansion Chip Enables (CE2 and CE3), Burst Control inputs (ADSC, ADSP, and ADV), Write Enables (BW[A:D], and BWE), and Global Write (GW). Asynchronous inputs include the Output Enable (OE) and the ZZ pin.

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Wed, 26 Mar 2014 01:00:32 -0600
CY7C1440AV25, CY7C1446AV25: 36-Mbit (1 M × 36/512 K × 72) Pipelined Sync SRAM http://www.cypress.com/?rID=59417 36-Mbit (1 M × 36/512 K × 72) Pipelined Sync SRAM

Features

  • Supports bus operation up to 250 MHz
  • Available speed grades are 250 and 167 MHz
  • Registered inputs and outputs for pipelined operation
  • 2.5 V core power supply
  • 2.5 V/1.8 V I/O power supply
  • Fast clock-to-output times
  • Provide high-performance 3-1-1-1 access rate
  • For more, see pdf.


Functional Description

The CY7C1440AV25/CY7C1446AV25 SRAM integrates 1 M × 36/512 K × 72 SRAM cells with advanced synchronous peripheral circuitry and a two-bit counter for internal burst operation. All synchronous inputs are gated by registers controlled by a positive-edge-triggered Clock Input (CLK).

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Wed, 26 Mar 2014 00:26:40 -0600
CY7C1481BV33: 72-Mbit (2 M × 36) Flow-Through SRAM http://www.cypress.com/?rID=58790 72-Mbit (2 M × 36) Flow-Through SRAM

Features

  • Supports 133 MHz bus operations
  • 2 M × 36 common I/O
  • 3.3 V core power supply (VDD)
  • 2.5 V or 3.3 V I/O supply (VDDQ)
  • Fast clock to output time
    • 6.5 ns (133 MHz version)
  • Provide high performance 2-1-1-1 access rate
  • User selectable burst counter supporting Intel® Pentium® interleaved or linear burst sequences
  • Separate processor and controller address strobes
  • Synchronous self timed write
  • Asynchronous output enable
  • CY7C1481BV33 available in JEDEC standard Pb-free 100-pin TQFP, Pb-free and non Pb-free 165-ball FBGA package.
  • IEEE 1149.1 JTAG compatible boundary scan
  • ZZ sleep mode option
  • For more, See pdf
     

Functional Description

The CY7C1481BV33 is a 3.3 V, 2 M × 36 synchronous flow through SRAM designed to interface with high speed microprocessors with minimum glue logic. Maximum access delay from clock rise is 6.5 ns (133 MHz version). A 2-bit on-chip counter captures the first address in a burst and increments the address automatically for the rest of the burst access. All synchronous inputs are gated by registers controlled by a positive edge triggered Clock Input (CLK).

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Wed, 26 Mar 2014 00:25:43 -0600
CY7C1484BV33: 72-Mbit (2 M × 36) Pipelined DCD Sync SRAM http://www.cypress.com/?rID=58864 72-Mbit (2 M × 36) Pipelined DCD Sync SRAM

Features

  • Supports bus operation up to 250 MHz
  • Available speed grade is 250 MHz
  • Registered inputs and outputs for pipelined operation
  • Optimal for performance (double cycle deselect)
  • Depth expansion without wait state
  • 3.3 V core power supply (VDD)
  • 2.5 V and 3.3 V I/O operation
  • Fast clock to output times
  • For more, see pdf.
     

Functional Description

The CY7C1484BV33 SRAM integrates 2 M × 36 SRAM cells with advanced synchronous peripheral circuitry and a 2-bit counter for internal burst operation. All synchronous inputs are gated by registers controlled by a positive edge triggered Clock Input (CLK). The synchronous inputs include all addresses, all data  inputs, address pipelining Chip Enable (CE1), depth expansion Chip Enables (CE2 and CE3), Burst Control inputs (ADSC, ADSP, and ADV), Write Enables (BWX, and BWE), and Global Write (GW). Asynchronous inputs include the Output Enable  (OE) and the ZZ pin.

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Wed, 26 Mar 2014 00:19:16 -0600
CY7C1364C: 9-Mbit (256 K × 32) Pipelined Sync SRAM http://www.cypress.com/?rID=58869 9-Mbit (256 K × 32) Pipelined Sync SRAM

Features

  • Registered inputs and outputs for pipelined operation
  • 256 K × 32 common I/O architecture
  • 3.3 V core power supply (VDD)
  • 2.5 V/3.3 V I/O power supply (VDDQ)
  • Fast clock-to-output times
  • Provide high-performance 3-1-1-1 access rate
  • For more, see pdf.
     

Functional Description

The CY7C1364C SRAM integrates 256 K × 32 SRAM cells with advanced synchronous peripheral circuitry and a two-bit counter for internal burst operation. All synchronous inputs are gated by registers controlled by a positive-edge-triggered Clock Input (CLK).
 

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Wed, 26 Mar 2014 00:17:11 -0600
CY7C1365C: 9-Mbit (256 K × 32) Flow-Through Sync SRAM http://www.cypress.com/?rID=58518 9-Mbit (256 K × 32) Flow-Through Sync SRAM

Features

  • 256 K × 32 common I/O
  • 3.3 V core power supply (VDD)
  • 2.5 V/3.3 V I/O power supply (VDDQ)
  • Fast clock-to-output times
    • 6.5 ns (133-MHz version)
  • Provide high-performance 2-1-1-1 access rate
  • User-selectable burst counter supporting Intel® Pentium® interleaved or linear burst sequences
  • Separate processor and controller address strobes
  • Synchronous self-timed write
  • Asynchronous output enable
  • Supports 3.3 V I/O level
  • Available in 165-Ball FBGA package
  • “ZZ” Sleep Mode option
  • IEEE 1149.1 JTAG-compatible boundary scan

 

Functional Description

The CY7C1365C is a 256 K × 32 synchronous cache RAM designed to interface with high-speed microprocessors with minimum glue logic. Maximum access delay from clock rise is 6.5 ns (133-MHz version). A 2-bit on-chip counter captures the first address in a burst and increments the address automatically for the rest of the burst access. All synchronous inputs are gated by registers controlled by a positive-edge-triggered Clock Input (CLK).

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Wed, 26 Mar 2014 00:08:03 -0600
AN4017 - Understanding Temperature Specifications: An Introduction http://www.cypress.com/?rID=12896 The following application note is intended to give the reader a basic understanding of the temperature specifications found in Cypress's product datasheets. There are many factors that affect the thermal operation of a device. This application note provides the reader with enough background to understand the thermal parameters and temperature specifications of the device.   

This document describes the various thermal parameters namely Ambient Temperature (Ta), Case Temperature (Tc), Junction Temperature(Tj), Thermal Resistance, Power Dissipation etc.

Details on calculating Junction Temperature are provided in this application note.

Clicking on the link below provides a tool which enables calculation of the I/O Switching Current (Iddq) for desired frequency, Total Power Consumption and Junction Temperature for Sync SRAMs

http://www.cypress.com/?docID=23984

Please refer to the respective product datasheets to get the Vdd voltage and Idd current used in the formula.

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Mon, 13 Jan 2014 00:49:58 -0600
QTP 044403: 72 Meg Synchronous SRAM Family (CY7C147*/148*) Technology R9T-3R, Fab4 http://www.cypress.com/?rID=35790 Tue, 10 Dec 2013 00:54:58 -0600 Knowledge Base – Cypress Semiconductor Cage Code – KBA89258 http://www.cypress.com/?rID=86132 Answer: The Commercial and Government Entity Code, or CAGE Code, is a unique identifier assigned to suppliers to various government or defense agencies, as well as to government agencies themselves and also various organizations.

CAGE codes provide a standardized method of identifying a given facility at a specific location.

Cypress Semiconductor’s Cage Code is 65786.

Cypress Minnesota - Fab4 who ship wafers has Cage Code 5AZZ0.

Ramtron International who specialized memory who and was acquired by Cypress Semiconductor has a CAGE code OJP56.

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Fri, 27 Sep 2013 02:08:09 -0600
Product Selector Guide (PSG) - All Cypress Products - Japanese http://www.cypress.com/?rID=53204 Thu, 29 Aug 2013 04:18:19 -0600 Product Selector Guide (PSG) - All Cypress Products http://www.cypress.com/?rID=41004 Tue, 20 Aug 2013 01:54:18 -0600 QTP 033302: 18 MEG SYNCHRONOUS SRAM FAMILY, TECHNOLOGY R9T-3R, FAB4 http://www.cypress.com/?rID=35681 Fri, 05 Jul 2013 08:25:06 -0600 Product Selector Guide (PSG) - All Cypress Products - Chinese http://www.cypress.com/?rID=47398 Mon, 01 Apr 2013 04:35:52 -0600 QTP 034503: ALL PLASTIC & THERMALLY ENHANCED QUAD FLATPACKS , PB-FREE, MSL3 260C REFLOW, ASEK-TAIWAN http://www.cypress.com/?rID=35693 Mon, 16 Jul 2012 03:46:30 -0600 CY7C1481BV25 - VERILOG http://www.cypress.com/?rID=63802 Tue, 05 Jun 2012 07:18:35 -0600 CY7C1481BV25 - IBIS http://www.cypress.com/?rID=63801 Tue, 05 Jun 2012 07:14:20 -0600 CY7C1384D - VERILOG http://www.cypress.com/?rID=63800 Tue, 05 Jun 2012 07:09:53 -0600 CY7C1384D - IBIS http://www.cypress.com/?rID=63798 Tue, 05 Jun 2012 07:05:38 -0600 CY7C1385D - VERILOG http://www.cypress.com/?rID=63797 Tue, 05 Jun 2012 06:59:00 -0600 CY7C1385D - IBIS http://www.cypress.com/?rID=63796 Tue, 05 Jun 2012 06:54:22 -0600 CY7C1380DV33 - IBIS http://www.cypress.com/?rID=60418 Wed, 14 Mar 2012 01:29:30 -0600 CY7C1380DV33 - BSDL http://www.cypress.com/?rID=60417 Wed, 14 Mar 2012 01:27:17 -0600 CY7C1380DV33 - Verilog http://www.cypress.com/?rID=60416 Wed, 14 Mar 2012 01:24:30 -0600 CY7C1440AV25 - IBIS http://www.cypress.com/?rID=60414 Wed, 14 Mar 2012 01:07:06 -0600 CY7C1440AV25 - BSDL http://www.cypress.com/?rID=60413 Wed, 14 Mar 2012 01:04:43 -0600 CY7C1440AV25 - Verilog http://www.cypress.com/?rID=60411 Wed, 14 Mar 2012 01:00:43 -0600 CY7C1447AV25 - IBIS http://www.cypress.com/?rID=60410 Wed, 14 Mar 2012 00:32:46 -0600 CY7C1447AV25 - BSDL http://www.cypress.com/?rID=60409 Wed, 14 Mar 2012 00:30:45 -0600 CY7C1447AV25 - Verilog http://www.cypress.com/?rID=60408 Wed, 14 Mar 2012 00:24:57 -0600 CY7C1365C - BSDL http://www.cypress.com/?rID=59237 Tue, 14 Feb 2012 06:21:53 -0600 CY7C1364C - BSDL http://www.cypress.com/?rID=59235 Tue, 14 Feb 2012 06:07:33 -0600 CY7C1364CV33 - IBIS http://www.cypress.com/?rID=59229 Tue, 14 Feb 2012 05:54:24 -0600 CY7C1364CV33 - Verilog http://www.cypress.com/?rID=59228 Tue, 14 Feb 2012 05:49:46 -0600 CY7C1484BV33 - Verilog http://www.cypress.com/?rID=59226 Tue, 14 Feb 2012 05:24:21 -0600 CY7C1484BV33 - IBIS http://www.cypress.com/?rID=59225 Tue, 14 Feb 2012 05:22:10 -0600 CY7C1484BV33 - BSDL http://www.cypress.com/?rID=59224 Tue, 14 Feb 2012 05:20:50 -0600 CY7C1482BV33 - Verilog http://www.cypress.com/?rID=59223 Tue, 14 Feb 2012 04:54:04 -0600 CY7C1482BV33 - IBIS http://www.cypress.com/?rID=59222 Tue, 14 Feb 2012 04:53:04 -0600 CY7C1482BV33 - BSDL http://www.cypress.com/?rID=59221 Tue, 14 Feb 2012 04:51:18 -0600 CY7C1481BV33 - Verilog http://www.cypress.com/?rID=59216 Tue, 14 Feb 2012 03:57:12 -0600 CY7C1481BV33 - IBIS http://www.cypress.com/?rID=59215 Tue, 14 Feb 2012 03:53:49 -0600 CY7C1481BV33 - BSDL http://www.cypress.com/?rID=59214 Tue, 14 Feb 2012 03:50:30 -0600 CY7C1382DV33 - BSDL http://www.cypress.com/?rID=59213 Tue, 14 Feb 2012 03:39:18 -0600 CY7C1382DV33 - IBIS http://www.cypress.com/?rID=59212 Tue, 14 Feb 2012 03:36:35 -0600 CY7C1382DV33 - Verilog http://www.cypress.com/?rID=59211 Tue, 14 Feb 2012 03:32:03 -0600 CY7C1480BV33 - BSDL http://www.cypress.com/?rID=59210 Tue, 14 Feb 2012 03:28:02 -0600 CY7C1365C - IBIS http://www.cypress.com/?rID=59200 Tue, 14 Feb 2012 01:58:01 -0600 CY7C1365C - Verilog http://www.cypress.com/?rID=59199 Tue, 14 Feb 2012 01:53:40 -0600 CY7C1360D-1XWI - Verilog http://www.cypress.com/?rID=58434 Thu, 19 Jan 2012 04:04:28 -0600 CY7C1623KV18 - Verilog http://www.cypress.com/?rID=58432 Thu, 19 Jan 2012 03:46:24 -0600 CY7C1480BV25 - BSDL http://www.cypress.com/?rID=58430 Thu, 19 Jan 2012 02:53:18 -0600