Features

• 256 K × 18 common I/O
• 3.3 V core power supply (VDD)
• 2.5 V or 3.3 V I/O power supply (VDDQ)
• Fast clock-to-output times
• 6.5 ns (133 MHz version)
• Provide high performance 2-1-1-1 access rate
• User selectable burst counter supporting Intel Pentium interleaved or linear burst sequences
• For more, see pdf

Functional Description

The CY7C1325H is a 256 K × 18 synchronous cache RAM designed to interface with high speed microprocessors with minimum glue logic. Maximum access delay from clock rise is 6.5 ns (133 MHz version). A 2 bit on-chip counter captures the first address in a burst and increments the address automatically for the rest of the burst access. All synchronous inputs are gated by registers controlled by a positive-edge-triggered Clock Input (CLK).

• Supports 133 MHz bus operations
• 1 M × 36/512 K × 72 common I/O
• 2.5 V core power supply
• 2.5 V and 1.8 V I/O power supply
• Fast clock-to-output times
• Provide high performance 2-1-1-1 access rate
• User selectable burst counter supporting Intel® Pentium® interleaved or linear burst sequences
• Separate processor and controller address strobes
• Synchronous self timed write
• For more, see pdf
   

Functional Description

The CY7C1441AV25/CY7C1447AV25 are 2.5 V, 1 M × 36/512 K × 72 Synchronous Flow-Through SRAMs, designed to interface with high speed microprocessors with minimum glue logic. Maximum access delay from clock rise is 6.5 ns (133 MHz version). A 2-bit on-chip counter captures the first address in a burst and increments the address automatically for the rest of the burst access. All synchronous inputs are gated by registers controlled by a positive edge-triggered Clock Input (CLK).

• Supports bus operation up to 250 MHz
• Available speed grade is 250 MHz
• Registered inputs and outputs for pipelined operation
• Optimal for performance (double cycle deselect)
• Depth expansion without wait state
• 3.3 V core power supply (VDD)
• 2.5 V and 3.3 V I/O operation
• Fast clock to output times
• For more, see pdf.
   

Functional Description

The CY7C1484BV33 SRAM integrates 2 M × 36 SRAM cells with advanced synchronous peripheral circuitry and a 2-bit counter for internal burst operation. All synchronous inputs are gated by registers controlled by a positive edge triggered Clock Input (CLK). The synchronous inputs include all addresses, all data  inputs, address pipelining Chip Enable (CE1), depth expansion Chip Enables (CE2 and CE3), Burst Control inputs (ADSC, ADSP, and ADV), Write Enables (BWX, and BWE), and Global Write (GW). Asynchronous inputs include the Output Enable  (OE) and the ZZ pin.

Features

• Supports 133 MHz bus operations
• 2 M × 36 common I/O
• 3.3 V core power supply (VDD)
• 2.5 V or 3.3 V I/O supply (VDDQ)
• Fast clock to output time
  • 6.5 ns (133 MHz version)
• Provide high performance 2-1-1-1 access rate
• User selectable burst counter supporting Intel® Pentium® interleaved or linear burst sequences
• Separate processor and controller address strobes
• Synchronous self timed write
• Asynchronous output enable
• CY7C1481BV33 available in JEDEC standard Pb-free 100-pin TQFP, Pb-free and non Pb-free 165-ball FBGA package.
• IEEE 1149.1 JTAG compatible boundary scan
• ZZ sleep mode option
• For more, See pdf
   

Functional Description

The CY7C1481BV33 is a 3.3 V, 2 M × 36 synchronous flow through SRAM designed to interface with high speed microprocessors with minimum glue logic. Maximum access delay from clock rise is 6.5 ns (133 MHz version). A 2-bit on-chip counter captures the first address in a burst and increments the address automatically for the rest of the burst access. All synchronous inputs are gated by registers controlled by a positive edge triggered Clock Input (CLK).

Features

• Supports bus operation up to 250 MHz
• Available speed grades are 250 MHz
• Registered inputs and outputs for pipelined operation
• Optimal for performance (double cycle deselect)
• Depth expansion without wait state
• 2.5 V core power supply (VDD)
• 2.5 V I/O supply (VDDQ)
• Fast clock to output times
  • 3.0 ns (for 250 MHz device)
• Provide high performance 3-1-1-1 access rate
• For more, see pdf

Functional Description

The CY7C1484BV25 SRAM integrates 2 M × 36 SRAM cells with advanced synchronous peripheral circuitry and a 2-bit counter for internal burst operation. All synchronous inputs are gated by registers controlled by a positive edge triggered Clock Input (CLK).

Features

• Registered inputs and outputs for pipelined operation
• 256 K × 32 common I/O architecture
• 3.3 V core power supply (VDD)
• 2.5 V/3.3 V I/O power supply (VDDQ)
• Fast clock-to-output times
• Provide high-performance 3-1-1-1 access rate
• For more, see pdf.
   

Functional Description

The CY7C1364C SRAM integrates 256 K × 32 SRAM cells with advanced synchronous peripheral circuitry and a two-bit counter for internal burst operation. All synchronous inputs are gated by registers controlled by a positive-edge-triggered Clock Input (CLK).
 

• 256 K × 32 common I/O
• 3.3 V core power supply (VDD)
• 2.5 V/3.3 V I/O power supply (VDDQ)
• Fast clock-to-output times
  • 6.5 ns (133-MHz version)
• Provide high-performance 2-1-1-1 access rate
• User-selectable burst counter supporting Intel® Pentium® interleaved or linear burst sequences
• Separate processor and controller address strobes
• Synchronous self-timed write
• Asynchronous output enable
• Supports 3.3 V I/O level
• Available in 165-Ball FBGA package
• “ZZ” Sleep Mode option
• IEEE 1149.1 JTAG-compatible boundary scan

Functional Description

The CY7C1365C is a 256 K × 32 synchronous cache RAM designed to interface with high-speed microprocessors with minimum glue logic. Maximum access delay from clock rise is 6.5 ns (133-MHz version). A 2-bit on-chip counter captures the first address in a burst and increments the address automatically for the rest of the burst access. All synchronous inputs are gated by registers controlled by a positive-edge-triggered Clock Input (CLK).

• Registered inputs and outputs for pipelined operation
• 256 K × 32 common I/O architecture
• 3.3 V core power supply (VDD)
• 2.5 V/3.3 V I/O power supply (VDDQ)
• Fast clock-to-output times
  • 3.5 ns (for 166-MHz device)
• Provide high-performance 3-1-1-1 access rate
• User-selectable burst counter supporting Intel® Pentium® interleaved or linear burst sequences
• Separate processor and controller address strobes
• Synchronous self-timed writes
• Asynchronous output enable
• Available in JEDEC-standard lead-free 100-pin TQFP package
• TQFP Available with 3-Chip Enable
• “ZZ” Sleep Mode Option

Functional Description

The CY7C1364CV33 SRAM integrates 256 K × 32 SRAM cells with advanced synchronous peripheral circuitry and a two-bit counter for internal burst operation. All synchronous inputs are gated by registers controlled by a positive-edge-triggered Clock Input (CLK). The synchronous inputs include all addresses, all data inputs, address-pipelining Chip Enable (CE1), depth-expansion Chip Enables (CE2 and CE3), Burst Control inputs (ADSC, ADSP, and ADV), Write Enables (BW[A:D], and BWE), and Global Write (GW). Asynchronous inputs include the Output Enable (OE) and the ZZ pin.

The table below shows the architecture comparison for the different options:                                                                            

This document describes the various thermal parameters namely Ambient Temperature (T_a), Case Temperature (T_c), Junction Temperature(T_j), Thermal Resistance, Power Dissipation etc.

Details on calculating Junction Temperature are provided in this application note.

Clicking on the link below provides a tool which enables calculation of the I/O Switching Current (I_ddq) for desired frequency, Total Power Consumption and Junction Temperature for Sync SRAMs

http://www.cypress.com/?docID=23984

Please refer to the respective product datasheets to get the V_dd voltage and I_dd current used in the formula.

Features

• Supports 133 MHz bus operations
• 2 M × 36 common I/O
• 2.5 V core power supply (VDD)
• 2.5 V I/O supply (VDDQ)
• Fast clock to output time
• Provide high performance 2-1-1-1 access rate
• User selectable burst counter supporting Intel® Pentium® interleaved or linear burst sequences
• Separate processor and controller address strobes
• For more, see pdf

Functional Description

The CY7C1481BV25 is a 2.5 V, 2 M × 36 synchronous flow through SRAM designed to interface with high speed microprocessors with minimum glue logic. Maximum access delay from clock rise is 6.5 ns (133 MHz version). A 2-bit on-chip counter captures the first address in a burst and increments the address automatically for the rest of the burst access. All synchronous inputs are gated by registers controlled by a positive edge triggered Clock Input (CLK).

• Supports 133 MHz bus operations
• 512 K × 32 common I/O
• 3.3 V core power supply (VDD)
• 2.5 V or 3.3 V I/O supply (VDDQ)
• Fast clock-to-output time
• Provides high performance 2-1-1-1 access rate
• User selectable burst counter supporting Intel Pentium interleaved or linear burst sequences
• Separate processor and controller address strobes
• Synchronous self-timed write
• Asynchronous output enable
• For more, see pdf

Functional Description

The CY7C1385D is a 3.3 V, 512 K × 32 synchronous flow through SRAMs, designed to interface with high speed microprocessors with minimum glue logic. Maximum access delay from clock rise is 6.5 ns (133 MHz version). A 2-bit on-chip counter captures the first address in a burst and increments the address automatically for the rest of the burst access. All synchronous inputs are gated by registers controlled by a positive edge triggered clock input (CLK).

• Supports bus operation up to 166 MHz
• Available speed grades are 166 MHz
• Registered inputs and outputs for pipelined operation
• 3.3 V core power supply
• 2.5 V or 3.3 V I/O power supply
• Fast clock-to-output times
• Provides high performance 3-1-1-1 access rate
• For more, see pdf

Functional Description

The CY7C1384D SRAM integrates 524,288 × 32 SRAM cells with advanced synchronous peripheral circuitry and a two-bit counter for internal burst operation. All synchronous inputs are gated by registers controlled by a positive edge triggered clock input (CLK).

• Supports bus operation up to 250 MHz
• Available speed grades are 250 and 167 MHz
• Registered inputs and outputs for pipelined operation
• 2.5 V core power supply
• 2.5 V/1.8 V I/O power supply
• Fast clock-to-output times
• Provide high-performance 3-1-1-1 access rate
• For more, see pdf.

Functional Description

The CY7C1440AV25/CY7C1446AV25 SRAM integrates 1 M × 36/512 K × 72 SRAM cells with advanced synchronous peripheral circuitry and a two-bit counter for internal burst operation. All synchronous inputs are gated by registers controlled by a positive-edge-triggered Clock Input (CLK).