Features

• True Dual-Ported memory cells which allow simultaneous access of the same memory location
• 32K x 16 organization (CY7C027V/027VN/027AV)
• 64K x 16 organization (CY7C028V)
• 32K x 18 organization (CY7C037V/037AV)
• 64K x 18 organization (CY7C038V)
• 0.35 micron CMOS for optimum speed and power
• High speed access: 15, 20, and 25 ns
• Low operating power
• Active: I_CC = 115 mA (typical)
• For more, see pdf
   

Functional Description

The CY7C027V/027AV/028V and CY7037AV/038V are low power CMOS 32K, 64K x 16/18 dual-port static RAMs. Various arbitration schemes are included on the devices to handle situations when multiple processors access the same piece of data. Two ports are provided, permitting independent, asynchronous access for reads and writes to any location in memory. 

Cypress's FLEx18 / FLEx36® / FLEx72™ portfolio of highdensity, high-performance synchronous Dual-Port SRAMs can operate at speeds up to 167 MHz. In the fast growing data communications market, the bandwidth requirements have increased. Cypress addresses these demands with its FullFlex Dual-Port SRAMs, which can operate up to 200 MHz.

Features

• True dual port memory enables simultaneous access to the shared array from each port
• Synchronous pipelined operation with single data rate (SDR) operation on each port
  • SDR interface at 200 MHz
  • Up to 28.8 Gb/s bandwidth (200 MHz × 72-bit × 2 ports)
• Selectable pipelined or flow-through mode
• 1.5 V or 1.8 V core power supply
• Commercial and Industrial temperature
• IEEE 1149.1 JTAG boundary scan
• Available in 484-ball PBGA (× 72) and 256-ball FBGA (× 36 and × 18) packages
• For more, see pdf

Functional Description

The FullFlex™ dual port SRAM families consist of 2-Mbit, 4-Mbit, 9-Mbit, 18-Mbit, and 36-Mbit synchronous, true dual port static RAMs that are high speed, low power 1.8 V or 1.5 V CMOS. Two ports are provided, enabling simultaneous access to the array. Simultaneous access to a location triggers deterministic access control. For FullFlex72 these ports operate independently with 72-bit bus widths and each port is independently configured for two pipelined stages. Each port is also configured to operate in pipelined or flow through mode.

Features

• True Dual-Ported memory cells which enable simultaneous access of the same memory location
• Flow-through and Pipelined devices
• 32 K × 9 organizations (CY7C09179V)
• 64 K × 8 organizations (CY7C09089V)
• 128 K × 8/9 organizations (CY7C09099V/199V)
• 3 Modes
• Flow-Through
• Pipelined
• Burst
• For more, see pdf
   

Functional Description

The CY7C09089V/99V and CY7C09179V/99V are high speed synchronous CMOS 64 K/128 K × 8 and 32 K/128 K × 9 dual-port static RAMs. Two ports are provided, permitting independent, simultaneous access for reads and writes to any location in memory. Registers on control, address, and data lines enable minimal setup and hold times.

Features

• True dual-ported memory cells that allow simultaneous access of the same memory location
• Synchronous pipelined operation
• Family of 4 Mbit, 9 Mbit, and 18 Mbit devices
• Pipelined output mode allows fast operation
• 0.18-micron complmentary metal oxide semiconductor (CMOS) for optimum speed and power
• High-speed clock to data access
• 3.3 V low power
  • Active as low as 225 mA (typ)
  • Standby as low as 55 mA (typ)
• For more, see pdf

Functional Description

The FLEx72 family includes 4 Mbit, 9 Mbit and 18 Mbit pipelined, synchronous, true dual-port static RAMs that are high-speed, low-power 3.3 V CMOS. Two ports are provided, permitting independent, simultaneous access to any location in memory. The result of writing to the same location by more than one port at the same time is undefined. Registers on control, address, and data lines allow for minimal set-up and hold time.

Features

• True dual-ported memory cells that allow simultaneous access of the same memory location
• Six flow through/pipelined devices:
  • 16 K × 16 / 18 organization (CY7C09269V/369V)
  • 32 K × 16 organization (CY7C09279V)
  • 64 K × 16 / 18 organization (CY7C09289V/389V)
• Three modes:
  • Flow through
  • Pipelined
  • Burst
• For more, see pdf
   

Functional Description

The CY7C09269V/79V/89V and CY7C09369V/89V are high speed 3.3 V synchronous CMOS 16 K, 32 K, and 64 K × 16 and 16 K and 64 K × 18 dual-port static RAMs. Two ports are provided, permitting independent, simultaneous access for reads and writes to any location in memory.

Features

• True dual-ported memory cells which allow simultaneous access of the same memory location
• Two Flow-Through/Pipelined devices
  • 16K x 36 organization (CY7C09569V)
  • 32K x 36 organization (CY7C09579V)
• 0.25-micron CMOS for optimum speed/power
• Three modes
  • Flow-Through
  • Pipelined
  • Burst
• For more, see pdf

Functional Description

The CY7C09569V and CY7C09579V are high-speed 3.3V synchronous CMOS 16K and 32K x 36 dual-port static RAMs. Two ports are provided, permitting independent, simultaneous access for reads and writes to any location in memory. Registers on control, address, and data lines allow for minimal set-up and hold times. In pipelined output mode, data is registered for decreased cycle time.

Features

• True dual-ported memory cells that allow simultaneous reads of the same memory location
• 4K ×16 organization (CY7C024E)
• 4K × 18 organization (CY7C0241E)
• 8K × 16 organization (CY7C025E)
• 8K × 18 organization (CY7C0251E)
• 0.35-μ complementary metal oxide semiconductor (CMOS) for optimum speed and power
• High-speed access: 15 ns
• Low operating power: ICC = 180 mA (typ), ISB3 = 0.05 mA (typ)
• Fully asynchronous operation
• For more, see pdf
   

Functional Description

The CY7C024E/CY7C0241E and CY7C025E/CY7C0251E are low-power CMOS 4K × 16/18 and 8K × 16/18 dual-port static RAMs. Various arbitration schemes are included on the CY7C024E/CY7C0241E and CY7C025E/CY7C0251E to handle situations when multiple processors access the same piece of data. Two ports are provided, permitting independent,  asynchronous access for reads and writes to any location in memory.

Features

• True dual-ported memory cells which allow simultaneous access of the same memory location
• 32 K × 16 organization (CY7C027)
• 64 K × 16 organization (CY7C028)
• 0.35 micron CMOS for optimum speed and power
• High speed access: 15 and 20 ns
• Low operating power
• Active: ICC = 180 mA (typical)
• Standby: ISB3 = 0.05 mA (typical)
• Fully asynchronous operation
• For more, see pdf

Functional Description

The CY7C027 and CY7C028 are low power CMOS 32 K, 64 K × 16 dual-port static RAMs. Various arbitration schemes are included on the devices to handle situations when multiple processors access the same piece of data. Two ports are provided, permitting independent, asynchronous access for reads and writes to any location in memory.

Features

• True dual-ported memory cells that allow simultaneous access of the same memory location
• 16K x 36 organization (CY7C056V)
• 32K x 36 organization (CY7C057V)
• 0.25-micron CMOS for optimum speed/power
• High-speed access: 12/15 ns
• Low operating power
  • Active: I_CC = 250 mA (typical)
  • Standby: I_SB3 = 10 µA (typical)
• Fully asynchronous operation
• For more, see pdf

Functional Description

The CY7C056V and CY7C057V are low-power CMOS 16K and 32K x 36 dual-port static RAMs. Various arbitration schemes are included on the devices to handle situations when multiple processors access the same piece of data. Two ports are provided, permitting independent, asynchronous access for reads and writes to any location in memory.

Features

• True dual-ported memory cells that allow simultaneous access of the same memory location
• Synchronous pipelined operation
• Organization of 2-Mbit, 4-Mbit, and 9-Mbit devices
• Pipelined output mode allows fast operation
• 0.18-micron Complimentary metal oxide semiconductor (CMOS) for optimum speed and power
• High-speed clock to data access
• 3.3V low power
  • Active as low as 225 mA (typ)
  • Standby as low as 55 mA (typ)
• For more, see pdf
   

Functional Description

The FLEx36™ family includes 2M, 4M, and 9M pipelined, synchronous, true dual-port static RAMs that are high-speed, low-power 3.3V CMOS. Two ports are provided, permitting independent, simultaneous access to any location in memory. The result of writing to the same location by more than one port at the same time is undefined. Registers on control, address, and data lines allow for minimal setup and hold time.

Features

• True dual-ported memory cells which allow simultaneous access of the same memory location
• 128 K × 8 organization (CY7C009)
• 0.35-micron CMOS for optimum speed/power
• High-speed access: 15/20/25 ns
• Low operating power
  • Active: ICC = 115 mA (typical)
  • Standby: ISB3 = 10 μA (typical)
• Fully asynchronous operation
• Automatic power-down
• For more, see pdf.

Functional Description

The CY7C009V is a low-power CMOS 64 K, 128 K × 8 dual-port static RAM. Various arbitration schemes are included on the devices to handle situations when multiple processors access the same piece of data. Two ports are provided permitting independent, asynchronous access for reads and writes to any location in memory. The devices can be utilized as standalone 8/9-bit dual-port static RAMs or multiple devices can be combined in order to function as a 16/18-bit or wider master/slave dual-port static RAM.

Features

• True dual-ported memory cells, which allow simultaneous reads of the same memory location
• 4K x 8 organization
• 0.65 micron CMOS for optimum speed and power
• High speed access: 15 ns
• Low operating power: ICC = 160 mA (max)
• Fully asynchronous operation
• Automatic power down
• Semaphores included on the 7C1342 to permit software handshaking between ports
• Available in 52-pin plastic leaded chip carrier (PLCC)
• Pb-free packages available

Functional Description

The CY7C135/135A and CY7C1342 are high speed CMOS 4K x 8 dual-port static RAMs. The CY7C1342 includes semaphores that provide a means to allocate portions of the dual-port RAM or any shared resource. Two ports are provided permitting independent, asynchronous access for reads and writes to any location in memory. Application areas include interprocessor/multiprocessor designs, communications status buffering, and dual-port video/graphics memory.

Features

• True dual-ported memory cells that allow simultaneous access of the same memory location
• 16K x 16 organization (CY7C026A)
• 0.35 micron CMOS for optimum speed and power
• High speed access: 15, and 20 ns
• Low operating power
• Active: ICC = 180 mA (typical)
• Standby: ISB3 = 0.05 mA (typical)
• Fully asynchronous operation
• Automatic power-down
• For more, see pdf

Functional Description

The CY7C026A is a low power CMOS 16K x 16 dual-port static RAM. Various arbitration schemes are included on the devices to handle situations when multiple processors access the same piece of data. Two ports are provided, permitting independent, asynchronous access for reads and writes to any location in memory. The device can be utilized as standalone 16-bit dual-port static RAM or multiple devices can be combined to function as a 32-bit or wider master/slave dual-port static RAM.

Features

• True dual-ported memory cells, which allow simultaneous reads of the same memory location
• 1 K × 8 organization
• 0.65 micron CMOS for optimum speed and power
• High speed access: 55 ns
• Low operating power: ICC = 110 mA (maximum)
• Fully asynchronous operation
• Automatic power-down
• BUSY output flag on CY7C130
• INT flag for port-to-port communication
• Available in 48-pin DIP (CY7C130)

Functional Description

The CY7C130 is a high speed CMOS 1 K by 8 dual-port static RAMs. Two ports are provided permitting independent access to any location in memory. The CY7C130 can be used as a standalone 8-bit dual-port static RAM. It is the solution to applications requiring shared or buffered data, such as cache memory for DSP, bit-slice, or multiprocessor designs.

Features

• True dual-ported memory cells which allow simultaneous access of the same memory location
• 8K/16K x 8 organizations (CY7C144AV/006AV)
• 0.35-micron complementary metal oxide semiconductor (CMOS) for optimum speed/power
• High-speed access: 25 ns
• Low operating power
  • Active: ICC = 115 mA (typical)
  • Standby: ISB3 = 10 µA (typical)
• Fully asynchronous operation
• For more, see pdf

Functional Description

The CY7C144AV and CY7C006AV are low-power CMOS 8 K / 16 K × 8 dual-port static RAMs. Various arbitration schemes are included on the devices to handle situations when multiple processors access the same piece of data. Two ports are provided, permitting independent, asynchronous access for reads and writes to any location in memory. The devices can be utilized as standalone 8-bit dual-port static RAMs or multiple devices can be combined in order to function as a 16-bit or wider master/slave dual-port static RAM.

Features

• True dual-ported memory cells which enable simultaneous access of the same memory location
• 4, 8 or 16 K × 16 organization (CY7C024AV/025AV/026AV)
• 0.35 micron CMOS for optimum speed and power
• High speed access: 20 ns and 25 ns
• Low operating power
  • Active: ICC = 115 mA (typical)
  • Standby: ISB3 = 10 μA (typical)
• For more, see pdf

Functional Description

The CY7C024AV/025AV/026AV are low power CMOS 4 K, 8 K, and 16 K × 16 dual port static RAMs. Various arbitration schemes are included on the devices to handle situations when multiple processors access the same piece of data. There are two ports ermitting independent, asynchronous access for reads and writes to any location in memory.

Features

• True Dual-Ported Memory Cells that Allow Simultaneous Access of the Same Memory Location
• Synchronous Pipelined Operation
• Family of 2 Mbit, 4 Mbit, and 9 Mbit Devices
• Pipelined Output Mode Allows Fast Operation
• 0.18 micron CMOS for Optimum Speed and Power
• High Speed Clock to Data Access
• 3.3V Low Power
  • Active as Low as 225 mA (typ)
  • Standby as Low as 55 mA (typ)
• For more, see pdf

Functional Description

The FLEx18™ family includes 2 Mbit, 4 Mbit, and 9 Mbit pipelined, synchronous, true dual port static RAMs that are high speed, low power 3.3V CMOS. Two ports are provided, permitting independent, simultaneous access to any location in memory. The result of writing to the same location by more than one port at the same time is undefined. Registers on control, address, and data lines allow for minimal setup and hold time.

Features

• True dual-ported memory cells which allow simultaneous access of the same memory location
• Two Flow-through/Pipelined devices
  • 8K x 9 organization (CY7C09159AV)
  • 16K x 9 organization (CY7C09169AV)
• Three Modes
  • Flow-through
  • Pipelined
  • Burst
• Pipelined output mode on both ports allows fast 83-MHz operation
• For more, see pdf

Functional Description

The CY7C09159AV is a high-speed synchronous CMOS 8 K × 9 dual-port static RAM. Two ports are provided, permitting independent, simultaneous access for reads and writes to any location in memory.[1] Registers on control, address, and data lines allow for minimal setup and hold times. In pipelined output mode, data is registered for decreased cycle time. Clock to data valid tCD2 = 9 ns (pipelined). 

Features

• True Dual-Ported memory cells that allow simultaneous access of the same memory location
• 64K x 8 organization (CY7C008)
• 128K x 8 organization (CY7C009)
• 64K x 9 organization (CY7C018)
• 128K x 9 organization (CY7C019)
• 0.35-micron CMOS for optimum speed/power
• High-speed access: 12[1]/15/20 ns
• Low operating power
  • Active: ICC = 180 mA (typical)
• For more, see pdf

Functional Description

The CY7C008/009 and CY7C018/019 are low-power CMOS 64K, 128K x 8/9 dual-port static RAMs. Various arbitration schemes are included on the devices to handle situations when multiple processors access the same piece of data. Two ports are provided permitting independent, asynchronous access for reads and writes to any location in memory.

Features

• True dual-ported memory cells which allow simultaneous access of the same memory location
• 16K x 8 organization (CY7C006A)
• 32K x 8 organization (CY7C007A)
• 16K x 9 organization (CY7C016A)
• 32K x 9 organization (CY7C017A)
• 0.35-micron CMOS for optimum speed/power
• High-speed access: 12[1]/15/20 ns
• Low operating power
  • Active: ICC = 180 mA (typical)
  • Standby: ISB3 = 0.05 mA (typical)
• For more, see pdf

Functional Description

The CY7C006A, CY7C007A, CY7C016A, and CY7C017A are low-power CMOS 32K x 8/9 and 16K x 8/9 dual-port static RAMs. Various arbitration schemes are included on the devices to handle situations when multiple processors access the same piece of data.

Features

• True dual-ported memory cells, which allow simultaneous reads of the same memory location
• 1 K / 2 K × 8 organization
• 0.35 micron complementary metal oxide semiconductor (CMOS) for optimum speed and power
• High speed access: 15 ns
• Low operating power: ICC = 110 mA (typical), Standby: ISB3 = 0.05 mA (typical)
• Fully asynchronous operation
• Automatic power down
• For more, see pdf
   

Functional Description

CY7C131E / CY7C131AE / CY7C136E / CY7C136AE are high-speed, low-power CMOS 1 K / 2 K × 8 dual-port static RAMs. Two ports are provided permitting independent access to any location in memory. The CY7C131E / CY7C131AE / CY7C136E / CY7C136AE can be used as a standalone 8-bit dual-port static RAM. It is the solution to applications requiring shared or buffered data, such as cache memory for DSP, bit-slice, or multiprocessor designs.

Features

• True dual ported memory cells which allow simultaneous access of the same memory location
• Two flow-through/pipelined devices
  • 4 K × 18 organization (CY7C09349AV)
  • 8 K × 18 organization (CY7C09359AV)
• Three modes
  • Flow-through
  • Pipelined
  • Burst
• Pipelined output mode on both ports allows fast 83-MHz operation
• For more, see pdf
   

Functional Description

The CY7C09349AV and CY7C09359AV are high-speed 3.3 V synchronous CMOS 4 K and 8 K × 18 dual-port static RAMs. Two ports are provided, permitting independent, simultaneous access for reads and writes to any location in memory. Registers on control, address, and data lines allow for minimal set-up and hold times. In pipelined output mode, data is registered for decreased cycle time.

Features

• True dual-ported memory cells which allow simultaneous access of the same memory location
• 4/8/16 K × 16 and 8/16 K × 8 organization
• High speed access: 40 ns
• Ultra low operating power
  • Active: ICC = 15 mA (typical) at 55 ns
  • Active: ICC = 25 mA (typical) at 40 ns
  • Standby: ISB3 = 2 μA (typical)
• Port-independent 1.8 V, 2.5 V, and 3.0 V I/Os
• Pb-free 14 × 14 × 1.4 mm 100-pin Thin Quad Flat Pack (TQFP) Package
• For more, see pdf

Functional Description

The CYDC128B16 is a low power complementary metal oxide semiconductor (CMOS) 4k, 8k,16k x 16, and 8/16k x 8 dual-port static RAM. Arbitration schemes are included on the devices to handle situations when multiple processors access the same piece of data. Two ports are provided, permitting independent, asynchronous access for reads and writes to any location in memory. The devices can be used as standalone 16-bit dual-port static RAMs or multiple devices can be combined in order to function as a 32-bit or wider master/slave dual-port static RAM.

Features

• True dual ported memory cells that allow simultaneous access of the same memory location
• 4, 8, or 16K × 16 organization
• Ultra Low operating power
  • Active: ICC = 15 mA (typical) at 55 ns
  • Standby: ISB3 = 2 μA (typical)
• Small footprint: available in a 6x6 mm 100-pin Pb-free vfBGA
• Port independent 1.8V, 2.5V, and 3.0V I/Os
• Full asynchronous operation
• Automatic power down
• For more, see pdf

Functional Description

The CYDM256B16, CYDM128B16, and CYDM064B16 are low power CMOS 4K, 8K,16K x 16 dual-port static RAMs. Arbitration schemes are included on the devices to handle situations when multiple processors access the same piece of data. Two ports are provided that permit independent, asynchronous access for reads and writes to any location in memory.

Features

• QuadPort™ datapath switching element (DSE) family allows four independent ports of access for data path management and switching
• High-bandwidth data throughput up to 10 Gb/s
• 133-MHz port speed x 18-bit-wide interface × 4 ports
• High-speed clock to data access 4.2 ns (maximum)
• Synchronous pipelined device
  • 1 Mb (64K × 18) switch array
• 0.25-micron CMOS for optimum speed/power
• IEEE 1149.1 JTAG boundary scan
• Width and depth expansion capabilities
• For more, see pdf

Functional Description

The Quadport Datapath Switching Element (DSE) family offers four ports that may be clocked at independent frequencies from one another. Each port can read or write up to 133 MHz, giving the device up to 10 Gb/s of data throughput. The device is 1-Mb (64K × 18) in density. Simultaneous reads are allowed for accesses to the same address location; however, simultaneous reading and writing to the same address is not allowed.

Features

• True dual-ported memory cells that allow simultaneous reads of the same memory location
• Automotive temperature operation: -40°C to +115°C
  2K x 8 organization
• High-speed access: 55 ns
• Low operating power: ICC = 120 mA (max.)
• Fully asynchronous operation
• Automatic power-down
• Master CG5982AF easily expands data bus width to 16 or more bits using slave
• BUSY output flag
• INT flag for port-to-port communication
   

Functional Description

The CG5982AF are high-speed CMOS 2K x 8 dual-port static RAMs. Two ports are provided to permit independent access to any location in memory. The CG5982AF can be utilized as either a standalone 8-bit dual-port static RAM or as a MASTER dual-port RAM in conjunction with the CG5982AF SLAVE dual-port device in systems requiring 16-bit or greater word widths. It is the solution to applications requiring shared or buffered data such as cache memory for DSP, bit-slice, or multiprocessor designs.

Each port has independent control pins; chip enable (CE), write enable (R/W), and output enable (OE). BUSY flags are provided on each port. In addition, an interrupt flag (INT) is provided on each port of the 52-pin PLCC version. BUSY signals that the port is trying to access the same location currently being accessed by the other port. On the PLCC version, INT is an interrupt flag indicating that data has been placed in a unique location (7FF for the left port and 7FE for the right port). An automatic power-down feature is controlled independently on each port by the chip enable (CE) pins. The CG5982AF is available in a 52-pin PLCC package.

Features

• True dual-ported memory cells that enable simultaneous reads of the same memory location
• 8 K × 8 organization (CY7C144E)
• 0.35-micron CMOS for optimum speed and power
• High-speed access: 15 ns
• Low operating power: ICC = 180 mA (typical), standby ISB3 = 0.05 mA (typical)
• Fully asynchronous operation
• Automatic power-down
• TTL compatible
• Master / slave
   

Functional Description

The CY7C144E is a high speed CMOS 8 K × 8 dual port static RAM. Various arbitration schemes are included on the CY7C144E to handle situations when multiple processors access the same piece of data. Two ports are provided permitting independent, asynchronous access for reads and writes to any location in memory. 

Features

• True Dual-Ported Memory Cells that Enable Simultaneous Reads of the same Memory Location
• 8K x 8 Organization (CY7C144)
• 8K x 9 Organization (CY7C145)
• 0.65-Micron CMOS for optimum Speed and Power
• High Speed Access: 15 ns
• Low Operating Power: ICC = 160 mA (max.)
• Fully Asynchronous Operation
• Automatic Power Down
• TTL Compatible
• For more, see pdf

Functional Description

The CY7C144 and CY7C145 are high speed CMOS 8K x 8 and 8K x 9 dual-port static RAMs. Various arbitration schemes are included on the CY7C144/5 to handle situations when multiple processors access the same piece of data. Two ports are provided permitting independent, asynchronous access for reads and writes to any location in memory. The CY7C144/5 can be used as a standalone 64/72-Kbit dual-port static RAM or multiple devices can be combined in order to function as a 16/18-bit or wider master/slave dual-port static RAM.

Features  

• True dual-ported memory cells that enable simultaneous access of the same memory location
• Synchronous pipelined operation
• Pipelined output mode allows fast operation
• 0.18 micron CMOS for optimum speed and power
• High speed clock to data access
• 3.3V low power
  • Active as low as 225 mA (typ.)
  • Standby as low as 55 mA (typ.)
• For more, see pdf

Functional Description

The FLEx36™ family includes 2-Mbit pipelined, synchronous, true dual-port static RAMs that are high speed, low power 3.3V CMOS. Two ports are provided, permitting independent, simultaneous access to any location in memory. A particular port can write to a certain location while another port is reading that location. The result of writing to the same location by more than one port at the same time is undefined. Registers on control, address, and data lines allow for minimal setup and hold time.      More...

Features

• Async SRAMs, Dual ports, FIFOs, Micropower SRAMs, PROMs, Sync SRAMs wafer and die, WirelessUSB LP wafer
• Wafer
  • Standard wafer 25 to 30 mil thick
  • Background wafer to 14 mil thick
  • Background wafer to 11 mil thick
• Die
  • Die in wafer form 25 to 30 mil thick
  • Background die to 14 mil thick
  • Background die to 11 mil thick
  • Known good die (KGD) levels 1, 2, 3, and 4
• Temperature ranges
  • Commercial, Industrial, and Automotive
• Waffle pack packages

Wafer and Die Classification

Cypress’s package products are sold in both wafer and die form. Cypress classifies them as follows:

Wafer

Wafers are probed at room temperature and high temperature to guarantee full functionality. Other parameters are guaranteed based on the level of product that is supplied to the customer. Details of product levels are described later in this document.

Known Good Die (KGD)

KGD is available in both die in wafer form and background die. Product in wafer form is not background and is anywhere from 25 to 30 mil thick. Background die are 14 or 11 mil thick, sawed, and shipped in waffle packs. The product in either form is tested at four different levels.

Level 1

Wafers are probed to guarantee full functionality and all static DC parameters. Other parameters are not guaranteed and warranted, including device reliability.

Level 2

Wafers are probed to guarantee full functionality to all static DC and partial AC parameters. Other parameters are not guaranteed and warranted, including device reliability.

Level 3

Wafers are probed to guarantee full functionality and all static DC and AC parameters. All parameters are guaranteed and warranted, including device reliability.

Wafers and die in wafer form are shipped in jars with die maps. Background die are shipped as die in waffle packs.

Level 4

Wafers are probed to guarantee all static DC parameters. RF testing guidelines and statistical data of packaged parts are provided.

Background die are shipped as die in waffle packs.

To improve user experience, the content of this application note has been captured in a training module. This introductory audio visual tutorial covers basics of Dual Port SRAM operation, types of Dual Ports(Asynchronous & Synchronous), and in the later sections focuses on the features and functionality of Synchronous Dual port SRAMs. A brief introduction to Cypress’s Fullflex™ family of Synchronous Dual Port SRAMs is also included.

Training Module: View Download

Included in this kit are Windows drivers, demonstration applications, and documentation of the software provided. The applications themselves serve as documentation on how to interface with the drivers, and also may be used to test the Peripheral Component Interface-Dual Port (PCI-DP(R)) on the user's target board.

The supplied Windows drivers are not production quality and not tested except to function with the provided PC demonstration programs, TEST0449, and Perf42.

Installation Instructions

This version of the CY7C09449PV SDK is for Windows 95/98/2000/NT users.

1. Download the file CY7C09449PV_SDK.zip [13.3 MB].
2. Locate the file on your PC and extract the file to a folder on your desktop.
3. Make sure to read the readme.txt file before using the software.

If you are installing a board in Windows 95/98 or Windows 2000, install the board and start your system. The Windows wizard will prompt you for an installation disk. Reference the folder where you saved the SDK and it will automatically install the kernel driver. To install in the Windows 95/98 or Windows 2000 development environment, run the Install.exe application located in the root directory of the folder and follow the directions. If you are installing a board in Windows NT, install the board and start your system. To install the kernel driver and/or the Windows NT development environment, run the Install.exe application located in the root directory of the folder and follow the directions.

Using the Software After Setup is Complete

Once setup is complete, you can run the Test0449.exe file from the directory where you installed the development environment. Test0449 is a baseline application intended to illustrate the use of the Cypress-provided drivers. It exercises the PCI-DP by using each of the functions in the (minimal) driver library. It functions properly with a PCI-DP connected to the PCI bus and does not require a target CPU on the PCI add-in card itself. This is the first application the user should run to test the operation of the PCI-DP and to make sure the software and hardware are installed properly. The Test0449 application tests all the major functions of the CY7C09449PV-AC and is a very good example of how to get started using the chip. It shows how to use the library to interface to the hardware driver.

Run Perf42 by selecting perf42.exe from the directory where you installed the development environment. Perf42 is an application that continuously tests direct memory access (DMA) performance on the PCI add-in card. Its operation is described in the documentation. It is a good demonstration application to show the PCI-DP in continuous operation and it features an animated front-end application. Various parameters of the DMA transfers may be adjusted through a graphical user interface.

For Eg. - 'T' in CY7C1021DV33-10ZSXIT implies Tape and Reel.

You can avail the packaging details of a part in the Ordering information section of the datasheet.

Cypress has added five new products to its FLEx18(TM) family of dual-port RAMs; all of them in the world's smallest package - a 144-pin fine-pitch ball-grid array (FBGA). The devices enable designers a shrink board space and increase reliability by reducing pin count.

FLEx72™18 Mbit dual-port RAM targets high-performance wireless basestations, wide-area and storage-area networks, and image processing equipment.

New multimedia functions and wireless standards call for a high-throughput, low-power interconnect in dual-processor mobile handsets. With access times as low as 65 ns, MoBL ADM Dual Ports can provide up to 246 Mbps throughput - the highest in the industry. Cypress's low-power MoBL technology enables the interconnects to operate with only 2 uA typical standby current, providing up to 50% power savings during inter-processor communication over traditional interconnects such as UART, I2C and USB1.1 technology. The MoBL family of dual-port interconnects is the most flexible in the industry with 64 Kb, 128 Kb and 256 Kb densities. The devices come in ultra-small 6 mm x 6 mm, 0.5 mm pitch, 100-ball vfBGA (very fine Ball Grid Array) packages.

Click below for a high-resolution photo of a MoBL ADM dual port.

1. Go to www.cypress.com.  On the top right, you will see a “Keyword / Part Number” search box (adjacent to “Contact Us.”) 

2. Select the “Part Number” tab above this text box.

3. Type the exact part number, for example CY8C29466-12PVXE.

4. The part number will be listed in the search results page.

5. Click on the part number link (1st column starting from the left). This will open a new web page.

Moisture Sensitivity Level (MSL) can be found by clicking the “Quality & Pb-free Data” link on the top, or by just scrolling down to the Quality & Pb-free Data” section about half way down the page.

All other Quality information for this part number (e.g., RoHS compliance, Lead/Ball Finish, Qualification Reports, IPC reports) can also be found on this web page. 

In case of any questions, or if the information is not available for a particular part number, please create a support case at www.cypress.com/support

If you do not know the Cypress part number: 

1. Go to www.cypress.com.  Browse the different products (“Products” tab on the top navigation menu) by family.

2. Once you choose the relevant product family (e.g., “Clocks and Buffers->Clock Distribution,” “Memory->FIFOs”), scroll down the particular page to get to the “Parametric Product Selector.”

3. Use this tool to find the part number by function/feature, and click on the part number you are interested in. This will lead you directly to step # 5 above.

This tutorial will cover the following topics:

An Overview of dual port where we present the definition and the basic operations of a Dual port SRAM. We will then cover the common features in Synchronous Dual Port SRAMs like timing modes, depth & width configurations, bus matching, mailbox operations etc. The third section provides a brief overview of the unique fetures found in Cypress's Fullflex families of Synchronous Dual Port SRAMs. In the last section we present examples of applications where these devices can be used.

space to a particular port. If one port requires the use of a particular

address it writes a '0' to a semaphore latch which represents that address

space. Once written, that port will read the same latch to determine if

it gained access. If that port reads a '0' the attempt was successful and

that port now has access. A '1' represents a failed attempt. To effectively

utilize the semaphores, both ports must use the semaphores in a friendly

fashion. The dual port does not “enforce” the semaphores active state since

the part does not know which portion of memory is being allocated. Each

port must monitor the semaphores to make them effective.

Semaphores are implemented in hardware as a latch. There are eight

such latches, one for each semaphore that is available on the chip. The

semaphore that is being addressed is determined by the value of A₀ - A₂.

It is important to note that when accessing a semaphore, the SEM signal

must be held low, otherwise the operation will be interpreted as an access

of the memory array. Detailed information on semaphore implementation

is available in Cypress Asynchronous Dual-Ports Datasheets.

The value of the semaphore will only be driven out of the first byte of I/O

lines. In dual-ports with a bus width of x8 and x16, the native byte length

is 8 bits. In dual-ports with a bus width of x9, x18 or x36, the native byte

length is 9 bits.

For example, in dual-ports with a bus width of x36, I/O lines 0-8 will output

the semaphore value. I/O lines 9-35 will be in a high impedance (High-Z)

state. The table below shows other examples.

FIFOs and dual-ports are both two-port SRAMs, except that FIFOs are specifically designed for sequential data, such as video or speech. Dual-ports, on the other hand, are more versatile in that writes and reads are allowed on both ports and not limited to sequential data. This is because the memory spaces in dual-ports are addressable. There is no address in a FIFO memory. However, a dual-port can be designed to work as a FIFO if needed, especially if the dual-port has burst mode features. 

Aggregate bandwidth is the total data transfer rate of both device ports. Aggregate Bandwidth = N * W * fmax

Aggregate throughput is the total data transfer rate through the device.  Aggregate Throughput = (N * W * fmax) / 2 --> N = Number of Ports = 2 --> W = Port Width --> fmax = maximum port operating frequency

For synchronous, pipelined dual-ports, the aggregate throughput equation above is the best-case that occurs when one port is dedicated to writing and the other is dedicated to reading. Turning around a port from reading-to-writing or writing-to-reading typically results in NOP cycles that degrade throughput. As long as read and writes occur in large bursts, the reduction in throughput is relatively small.

Below is the full list:

Both ports reading at the same time: This is a perfectly legal operation. Both ports can access the same address at the same time and the data read will be valid.

Both ports writing at the same time: When trying to write to the same data locaction at the same time from both ports, the integrity of the data written depends on the skew between the clocks of each port. If the skew between the two clocks is at least tCCS (defined in the datasheet), then the last data written will be valid. Otherwise, the integrity of the data written is not guaranteed.

One port reading, one port writing: Similar to the case when both ports are writing, what value is read will depend on the skew between the two port clocks. For example, if the read operation from one port occurs at least tCCS after the write operation, then the data read will be valid. tCCS is the minimum amount of skew required between right and left port operations to guarantee that the data read is successful. By successful, we mean that both the data that was writtern to the dual-port and the data read from the dual-port is the same. However, if the read operation occurs less than tCCS after the write operation, thereby violating tCCS, then the data read will either not be valid at all (CY7C08xxV) or it won't be valid for an additional amount of time (CY7C09xxx and CY7C09xxxV). This is sometimes called tCWDD. If both port clocks are tied together, you will violate the clock to clock setup tCCS. This means that you cannot write to and read from the same address at the same time. If you do so, the read data will be invalid. The write data will always successfully complete. This means that for this configuration, a read may be conducted from the same address on the cycle following the write operation.

CY7C09xxx(V): In these dual-ports, the internal address counter is read out onto the I/O lines. Depending on the depth of the device, the number of I/O's used will differ. Most times, though, only the most significant bits of the I/O bus will be used. For example, the CY7C09569V is a 16K x 36 dual-port. It is addressed by 14 address bits A[13:0]. These are read out only on the most significant bits. Since there are only 14 address bits to read out, it is read out only from IO[17:4]. The request for address readback is: OE# = L, R/W# = H, ADS# = L, CNTEN# = H, CNTRST# = H

CY7C08x1V / CY7C08x2V: In these dual-ports, the internal address counter is read out onto the address lines. So this family of dual-ports has bi-directional address and data lines. Because they are evenly matched, the number of bits in the address counter are the same number of bits in the address bus. The request for address readback is: CNT/MSK# = H, CNTRST# = H, ADS# = L, CNTEN# = H

As the table above shows, you end up reading out every other word.

The FLEx72 Dual Port RAM (CYD18S72V) is an 18Mb Dual Port with a 256Kx72 configuration The FLEx72-E (CYD18S72V18) Dual Port RAM is also an 18Mb Dual Port device with additional features and will be offered mid-2004.

The FLEx72 device is a 3.3V device with an LVTTL I/O standard. The FLEx72-E is a drop in replacement for the FLEx72 device. Outlined in the current CYD18S72V datasheet are connections for the balls that represent the additional features in the FLEx72-E Dual Port RAM. These connections essentially disable the additional features. If the CYD18S72V device meets the needs for your system, no changes need to be made for the FLEx72-E to be a drop in replacement.

If you would like to take advantage of the additional features in the FLEx72-E Dual Port RAM, there is an application note titled "Migration from the FLEx72^TM 18Mb Dual Port to the FLEx72-E^TM 18Mb Dual Port RAM" to explain the features and how to implement them. Please contact Cypress sales for more information.


 

There are 2 cases to be considered during this kind of simultaneous access:

Case 1: The write happens clock skew time (t_CCS) ahead of the read (timing diagram in datasheet)

1) When t_CCS >= minimum specified value, the data can be read out (t_CYC+t_CD2) time after the positive edge of the read clock.
2) When t_CCS < minimum specified value, the data is read one extra clock cycle later, (2*t_CYC+t_CD2) after the positive edge of read clock (given that all control signals are held for the read). In this case, t_CCS is violated, because at the "expected" time of (t_CYC+t_CD2), indeterminate data (that is not necessarily either the old or the new data) is available to the read port and valid data appears only an extra clock cycle later.

Case 2: The read happens clock skew time (t_CCS) ahead of the write

1) If t_CCS >= minimum specified, the OLD data will be read out at time t_CYC+t_CD2 after rising edge of read clock.

2) If t_CCS < minimum specified value ( that is the write occurs less than minimum specified clock skew time after the read), valid data can be read out of the read port 2*t_CYC+t_CD2 after the rising edge of the read clock (given that all control signals are held for the read). At time t_CYC+t_CD2 after rising edge of read clock, indeterminate data is across the read port.

BE (Big Endian) selects the order that the data will be read out. This can either be Big Endian (MSB first) or Little Endian (LSB first).

All three of these pins must be set to their wanted values during initial power-up. Normally, all three of these pins must be static throughout normal device operation. However, it is sometimes necessary to change the inputs BM, SIZE , or BE while the device is "deselected" (CE# = high). If so, these inputs must be reconfigured at least 1 clock cycle before the device is "selected" again so that the new setup can take into effect. This is not recommended, though. It is better to keep these inputs static.

For more information regarding the bus matching feature available on these dual-ports, please reveiw the application note, Understanding the FLEx36 Dual-Port SRAMs

Impedance matching between device pins and transmission lines on the board is conventionally done using separate resistors in each trace. The board space required, would then, be unwarranted. The VIM is a method by which we match the impedance of a group of device pins (I/O drivers) with their corresponding signal trace using a single resistor. VIM eliminates the transmission line effects improving signal integrity, I/O bandwidth and system reliability without excessive board space.

How VIM works.

The calibrating resistor is connected between pins ZQ<1:0> (ZQ in case of 18M) on the corresponding port and ground. The resistor must be 5 times larger than the intended line impedance driven by the dual port. The VIM or VIS circuit can set the impedance of both or either ports using the corresponding ZQ<1:0> pins. The two pins must be tied to the same setting.

The configured ports' O/P impedance is corrected for drifts in V and T every 1024 clock cycles and in case of significant changes in V and T the recalibration period is multiples of 1024. The VIM/VIS circuit gets reset when the master reset is asserted and takes 1024 cycles to update after a reset operation. To disable VIM, pin ZQ is connected to Vdd and with this all the output drivers are turned on and the output is configured for minimum impedance. Using VIM the impedance of all the output pins can be configured except the JTAG.

Resistor tolerances:

For accurate and reliable operation the resistor values and tolerances should be as given:

Resistor values: 100-350 W, tolerance ?2%, temperature co-efficient: 200pmm/?C 

The impedance at the ports should be as given:

O/P impedance: 20-75 W with a ?15% tolerance.

The Application Note for Variable Impedance mathcing with Fullflex Dual Ports can be accessed here:  Using Variable Impedance Matching with FullFlex Dual-Ports 

Echo clocks and why we need them:

With high speeds driving the electronic industry, on board delays (clock skew) caused by parasitic make accurate clock trees extremely difficult. In particular, the Dual Data rate (DDR) environment requires tighter timing control. Echo clocks were designed to counter this problem.

How does it work?

The Dual port receives input clock (C for SDR and C, C# for DDR) at its corresponding pins. On a read operation the input clock is used to clock in the address and the control signals. The dual port then buffers this clock and retransmits it synchronous to the data output. Each port has 2 pairs of echo clocks. The CQ1 and CQ1# outputs are associated with data pins [71:36] and the CQ0 and the CQ0# is associated with data [35:0]. The DP also has echo clock enable (CQEN) at both the ports. So, the option can be set on a per port basis by tying the corresponding CQEN pin to Vdd. Echo clocks are Hi-Z in the flow through mode (Flow through mode works only with SDR). The figures attached show the echo clock delay for SDR and DDR modes. 

There is no power on sequence requirements for the Fullflex dual ports. For the 1.5V/1.8V devices, there is one pin (VC_SEL) to select the external core power between 1.5V and 1.8V. The default value for the pin is LOW which selects 1.8V core supply. Devices without the VC_SEL pin have the core voltage to be equal to 1.2V.

Table 1 shows the power supply requirement details and table 2 shows external power supply values for the Fullflex dual ports.

Table 1: Power supply requirements

Table 2: External Power Supply Values.