Features

• 3.3 V operation for low-power consumption and easy integration into low-voltage systems
• High-speed, low-power, first-in first-out (FIFO) memories
• 16 K × 9 (CY7C4261V)
• 32 K × 9 (CY7C4271V)
• 64 K × 9 (CY7C4281V)
• 128 K × 9 (CY7C4291V)
• 0.35-micron CMOS for optimum speed or power
• High-speed 100-MHz operation (10-ns read/write cycle times)
• Low power
• For more, see pdf
   

Functional Description

The CY7C4261/71/81/91V are high-speed, low-power FIFO memories with clocked read and write interfaces. All are nine bits wide. The CY7C4261/71/81/91V are pin-compatible to the CY7C42x1V Synchronous FIFO family. Programmable features include Almost Full/Almost Empty flags. These FIFOs provide solutions for a wide variety of data buffering needs, including high-speed data acquisition, multiprocessor interfaces, and communications buffering.

Features

• High-speed, low-power, first-in, first-out (FIFO) memories
  • 256 x 9 (CY7C4201V)
  • 512 x 9 (CY7C4211V)
• High-speed 66-MHz operation (15-ns read/write cycle time)
• Low power (I_CC = 20 mA)
• 3.3V operation for low power consumption and easy integration into low-voltage systems
• 5V-tolerant inputs V_{IH max} = 5 V
• Fully asynchronous and simultaneous read and write operation
• Empty, full, and programmable almost empty and almost full status flags
• For more, see pdf
   

Functional Description

The CY7C42X1V are high-speed, low-power, FIFO memories with clocked read and write interfaces. All are nine bits wide. Programmable features include Almost Full/Almost Empty flags. These FIFOs provide solutions for a wide variety of data buffering needs, including high-speed data acquisition, multiprocessor interfaces, and communications buffering.

Features

• High speed, low power, first-in first-out (FIFO) memories
• 256 x 18 (CY7C4205)
• 512 x 18 (CY7C4215)
• 1K x 18 (CY7C4225)
• 4K x 18 (CY7C4245)
• High speed 100 MHz operation (10 ns read/write cycle time)
• Low power (ICC = 45 mA)
• Fully asynchronous and simultaneous read and write operation
• For more, see pdf
   

Functional Description

The CY7C42X5 are high speed, low power, first-in first-out (FIFO) memories with clocked read and write interfaces. All are 18 bits wide and are pin/functionally compatible to IDT722X5. The CY7C42X5 can be cascaded to increase FIFO depth. Programmable features include Almost Full/Almost Empty flags.      More...

This document describes the errata for the 18 Mbit, 36 Mbit, and 72 Mbit programmable FIFOs. Details include errata trigger conditions, scope of impact, available workarounds, and silicon revision applicability. Compare this document to the device’s datasheet for a complete functional description.

Features

• Memory organization
  • Industry's largest first in first out (FIFO) memory densities: 18 Mbit, 36 Mbit, and 72 Mbit
  • Selectable memory organization: x9, x12, x16, x18, x20, x24, x32, x36
• Up to 133-MHz clock operation
• Unidirectional operation
• Independent read and write ports
  • Supports simultaneous read and write operations
  • Reads and writes operate on independent clocks, upto a maximum ratio of two, enabling data buffering across clock domains.
  • Supports multiple I/O voltage standard: low voltage complementary metal oxide semiconductor (LVCMOS) 3.3 V and 1.8 V voltage standards.
• For more, see pdf.
   

Functional Description

The Cypress programmable FIFO family offers the industry’s highest-density programmable FIFO memory device. It has independent read and write ports, which can be clocked up to 133 MHz. User can configure input and output bus sizes. The maximum bus size of 36 bits enables a maximum data throughput of 4.8 Gbps.

Features

• Memory organization
  • Industry’s largest first in first out (FIFO) memory densities: 144-Mbit
  • Selectable memory organization: × 9, × 12, × 16, × 18, × 20, × 24, × 32, × 36
• Up to 100-MHz clock operation
• Unidirectional operation
• Independent read and write ports
  • Supports simultaneous read and write operations
  • Reads and writes operate on independent clocks, upto a maximum ratio of two, enabling data buffering across clock domains.
  • Supports multiple I/O voltage standard: Low voltage complementary metal oxide semiconductor (LVCMOS) 3.3 V and 1.8 V voltage standards.
• For more, see pdf.

Functional Description

The Cypress programmable FIFO family offers the industry’s highest-density programmable FIFO memory device. It has independent read and write ports, which can be clocked up to 100 MHz. User can configure input and output bus sizes. The maximum bus size of 36 bits enables a maximum data throughput of 3.6 Gbps. The read and write ports can support multiple I/O voltage standards. The user-programmable registers enable user to configure the device operation as desired.

Features

• Memory organization
  • Industry’s largest first in first out (FIFO) memory density: 144-Mbit
  • Selectable memory organization: × 9, × 12, × 16, × 18, × 20, × 24, × 32, × 36
• Up to 133-MHz clock operation
• Unidirectional operation
• Independent read and write ports
  • Supports simultaneous read and write operations
  • Reads and writes operate on independent clocks upto a maximum ratio, of two enabling data buffering across clock domains.
  • Supports multiple I/O voltage standard: low voltage complementary metal oxide semiconductor (LVCMOS) 3.3 V and 1.8 V voltage standards.
• For more, see pdf.

Functional Description

The Cypress programmable FIFO family offers the industry’s highest-density programmable FIFO memory device. It has independent read and write ports, which can be clocked up to 133 MHz. User can configure input and output bus sizes. The maximum bus size of 36 bits enables a maximum data throughput of 4.8 Gbps. The read and write ports can support multiple I/O voltage standards.

• Very high speed: 70 ns
• Temperature ranges:
  • Industrial: –40 °C to +85 °C
• Wide voltage range: 1.65 V to 2.25 V
• Pin compatible with CY62256N
• Ultra low standby power
  • Typical standby current: 1 μA
  • Maximum standby current: 4 μA
• Ultra low active power
  • Typical active current: 1.3 mA at f = 1 MHz
     

Functional Description

The CY62256EV18 is a high performance CMOS static RAM module organized as 32 K words by 8-bits. This device features advanced circuit design to provide ultra low active current. This is ideal for providing More Battery Life™ (MoBL®) in portable applications such as cellular telephones. The device also has anautomatic power-down feature that significantly reduces power consumption when addresses are not toggling. Placing the device in standby mode reduces power consumption by more than 99 percent when deselected (CE HIGH). The eight input and output pins (I/O0 through I/O7) are placed in a high impedance state when the device is deselected (CE HIGH), the outputs are disabled (OE HIGH), or a write operation is in progress (CE LOW and WE LOW).

Features

• Asynchronous First-In First-Out (FIFO) Buffer Memories
  • 512 x 9 (CY7C421)
• Dual-Ported RAM Cell
• High Speed 50 MHz Read and Write Independent of Depth and Width
• Low Operating Power: ICC = 35 mA
• Empty and Full Flags (Half Full Flag in Standalone)
• TTL Compatible
• Retransmit in Standalone
• Expandable in Width
• For more, see pdf

Functional Description

The CY7C421 is a first-in first-out (FIFO) memory offered in 300-mil wide SOJ, TQFP & PLCC packages and it is 512 words by 9 bits wide. Each FIFO memory is organized such that the data is read in the same sequential order that it was written. Full and empty flags are provided to prevent overrun and underrun. Three additional pins are also provided to facilitate unlimited expansion in width, depth, or both. The depth expansion technique steers the control signals from one device to another in parallel. This eliminates the serial addition of propagation delays, so that throughput is not reduced. Data is steered in a similar manner.

Features

• Memory organization
  • Industry’s largest first in first out (FIFO) memory densities: 18-Mbit, 36-Mbit and 72-Mbit
  • Selectable memory organization: × 9, × 12, × 16, × 18, × 20, × 24, × 32, × 36
• Up to 100-MHz clock operation
• Unidirectional operation
• Independent read and write ports
  • Supports simultaneous read and write operations
  • Reads and writes operate on independent clocks upto a maximum ratio of two enabling data buffering across clock domains
  • Supports multiple I/O voltage standard: Low voltage complementary metal oxide semiconductor (LVCMOS) 3.3 V and 1.8 V  voltage standards.
• For more, see pdf
   

Functional Description

The Cypress programmable FIFO family offers the industry’s highest-density programmable FIFO memory device. It has independent read and write ports, which can be clocked up to 100 MHz. User can configure input and output bus sizes. The maximum bus size of 36 bits enables a maximum data throughput of 3.6 Gbps. The read and write ports can support multiple I/O voltage standards.

Features

• 3.3V operation for low power consumption and easy integration into low voltage systems
• High speed, low power, first-in first-out (FIFO) memories
• 8K x 18 (CY7C4255V)
• 16K x 18 (CY7C4265V)
• 32K x 18 (CY7C4275V)
• 64K x 18 (CY7C4285V)
• 0.35 micron CMOS for optimum speed and power
• High speed 100 MHz operation (10 ns read/write cycle times)
• Low power
• For more, see pdf
   

Functional Description

The CY7C4255/65/75/85V are high speed, low power, first-in first-out (FIFO) memories with clocked read and write interfaces. All are 18 bits wide and are pin and functionally compatible to the CY7C42X5V Synchronous FIFO family. The CY7C4255/65/75/85V can be cascaded to increase FIFO depth. Programmable features include Almost Full/Almost Empty flags.

Features

• High speed, low power, first-in first-out (FIFO) memories
• 16 K × 9 (CY7C4261)
• 32 K × 9 (CY7C4271)
• 0.5 micron CMOS for optimum speed and power
• High speed 100 MHz operation (10 ns read/write cycle times)
• Low power — ICC = 35 mA
• Fully asynchronous and simultaneous read and write operation
• Empty, full, half full, and programmable almost empty and almost full status flags
• TTL compatible
• For more, see pdf
   

Functional Description

The CY7C4261/71 are high speed, low power FIFO memories with clocked read and write interfaces. All are nine bits wide. The CY7C4261/71 are pin compatible to the CY7C42X1 synchronous FIFO family. The CY7C4261/71 can be cascaded to increase FIFO width. Programmable features include almost full/almost empty flags. These FIFOs provide solutions for a wide variety of data buffering needs, including high speed data acquisition, multiprocessor interfaces, and communications buffering.

Features

• High Speed, Low Power, First-In First-Out (FIFO) Memories
  • 16K x 18 (CY7C4265)
• 0.5 Micron CMOS for Optimum Speed and Power
• High Speed 100 MHz Operation (10 ns read/write cycle times)
• Low Power — ICC = 45 mA
• Fully Asynchronous and Simultaneous Read and Write Operation
• Empty, Full, Half Full, and Programmable Almost Empty and Almost Full Status Flags
• TTL compatible
• Retransmit Function
• For more, see pdf

Functional Description

The CY7C4265 are high speed, low power, first-in first-out (FIFO) memories with clocked read and write interfaces. All are 18 bits wide and are pin/functionally compatible to the CY7C42X5 Synchronous FIFO family. The CY7C4265 can be cascaded to increase FIFO depth. Programmable features include Almost Full/Almost Empty flags.

Features

• Async SRAMs, Dual ports, FIFOs, Micropower SRAMs, PROMs, Sync SRAMs wafer and die, WirelessUSB LP wafer
• Wafer
  • Standard wafer 25 to 30 mil thick
  • Background wafer to 14 mil thick
  • Background wafer to 11 mil thick
• Die
  • Die in wafer form 25 to 30 mil thick
  • Background die to 14 mil thick
  • Background die to 11 mil thick
  • Known good die (KGD) levels 1, 2, 3, and 4
• Temperature ranges
  • Commercial, Industrial, and Automotive
• Waffle pack packages

Wafer and Die Classification

Cypress’s package products are sold in both wafer and die form. Cypress classifies them as follows:

Wafer

Wafers are probed at room temperature and high temperature to guarantee full functionality. Other parameters are guaranteed based on the level of product that is supplied to the customer. Details of product levels are described later in this document.

Known Good Die (KGD)

KGD is available in both die in wafer form and background die. Product in wafer form is not background and is anywhere from 25 to 30 mil thick. Background die are 14 or 11 mil thick, sawed, and shipped in waffle packs. The product in either form is tested at four different levels.

Level 1

Wafers are probed to guarantee full functionality and all static DC parameters. Other parameters are not guaranteed and warranted, including device reliability.

Level 2

Wafers are probed to guarantee full functionality to all static DC and partial AC parameters. Other parameters are not guaranteed and warranted, including device reliability.

Level 3

Wafers are probed to guarantee full functionality and all static DC and AC parameters. All parameters are guaranteed and warranted, including device reliability.

Wafers and die in wafer form are shipped in jars with die maps. Background die are shipped as die in waffle packs.

Level 4

Wafers are probed to guarantee all static DC parameters. RF testing guidelines and statistical data of packaged parts are provided.

Background die are shipped as die in waffle packs.

The content of the application note has been captured in a training module. This audio visual tutorial provides an introduction to FIFO architecture & its functionality. It explains the features of asynchronous FIFOs such as flags, retransmit functionality & expansion logic. It also briefly discusses the applications of Asynchronous FIFOs.

Training Module: View Download

The content of the application note has also been captured in a training module. This audio visual tutorial provides an introduction to FIFO architecture & its functionality. It also explains basic FIFO features such as flags, expansion logic, timing specifications and some additional features specific to Synchronous FIFOs. A brief introduction to Cypress’s portfolio of Synchronous FIFOs & its applications is also included.

Training Module: View Download

For Eg. - 'T' in CY7C1021DV33-10ZSXIT implies Tape and Reel.

You can avail the packaging details of a part in the Ordering information section of the datasheet.

1. Go to www.cypress.com.  On the top right, you will see a “Keyword / Part Number” search box (adjacent to “Contact Us.”) 

2. Select the “Part Number” tab above this text box.

3. Type the exact part number, for example CY8C29466-12PVXE.

4. The part number will be listed in the search results page.

5. Click on the part number link (1st column starting from the left). This will open a new web page.

Moisture Sensitivity Level (MSL) can be found by clicking the “Quality & Pb-free Data” link on the top, or by just scrolling down to the Quality & Pb-free Data” section about half way down the page.

All other Quality information for this part number (e.g., RoHS compliance, Lead/Ball Finish, Qualification Reports, IPC reports) can also be found on this web page. 

In case of any questions, or if the information is not available for a particular part number, please create a support case at www.cypress.com/support

If you do not know the Cypress part number: 

1. Go to www.cypress.com.  Browse the different products (“Products” tab on the top navigation menu) by family.

2. Once you choose the relevant product family (e.g., “Clocks and Buffers->Clock Distribution,” “Memory->FIFOs”), scroll down the particular page to get to the “Parametric Product Selector.”

3. Use this tool to find the part number by function/feature, and click on the part number you are interested in. This will lead you directly to step # 5 above.

The architecture, features & expansion logic of Cypress’s Asynchronous FIFOs are presented in this training module. A brief note on the applications of these devices is also included. The topics covered are:

• Overview - Asynchronous FIFOs
  • Definition
  • Basic Operations
• Features of Asynchronous FIFOs
  • Introduction
  • Read & Write operations
  • Status flags
  • Retransmit functionality
  • Common FIFO Configurations
    • Width Expansion Configuration
    • Depth Expansion Configuration
• Applications of Asynchronous FIFOs

This self paced training module provides a general introduction to the features & functionality of Cypress’s Synchronous FIFOs. It includes a brief discussion on Cypress’s portfolio of Synchronous FIFOs and their applications.

The topics covered in the training module are:

• FIFO Overview
  • Definition
  • Basic Operations
• Operations & Features of Synchronous FIFOs
  • Architecture
  • Write / Read operations
  • Status flags
  • Expansion Logic
  • Retransmit
  • Cypress Synchronous FIFO portfolio
    • Cypress’s CY7C42x1 family of Synchronous FIFOs
    • Cypress’s CY7C42x5 family of Synchronous FIFOs
• Applications of Synchronous FIFOs

the clock cycle which updates the synchronous flags at a boundary. The

empty flag gets updated by the read clock (RCLK) and the full flag gets

updated by the write clock (WCLK).

You don't have to read data from the FIFO to update /EF as long as you

keep the RCLK running at all times. The empty flag (/EF) will get updated

when the first piece of data is written into the FIFO regardless of whether

you're reading from the FIFO. When starting with an empty FIFO it essentially

takes two read clocks to read the first word from the device. The first read

clock rising edge updates the Empty Flag (assuming a write has been

performed). This update cycle occurs whether the read is enabled or not.

The second read clock rising edge (enabled) will read the first word from

the device. Without asserting the read enable (REN) a read will not be

performed.

The same applies to the full flag (/FF). Keeping the WCLK running at all

times will make sure the /FF is updated right away. When the device is

full, a write clock is needed to update the full flag (FF). In this case it takes

two write cycles to write into a device which just became not full.

This type of flag operation is necessary to ensure that the empty and full

flags will be valid and usable for a minimum of one clock cycle. This

architecture eliminates short flag pulses characteristic of an asynchronous

FIFO. This concept is the same for devices that have dual-function pins.

EF#/OR and AE# should be synchronized to CLKB, whereas FF#/IR and

AF# are synchronized to CLKA.

- How is the Vcc/SMODE# pin used?

- What should I do with the SMODE pin?

- What is the difference between tying this pin to Vcc or ground?

Response:

In the CY7C42x5 and CY7C42x5V families of synchronous FIFOs, there is a pin labeled Vcc/SMODE# that is used to change the way the programmable flags work. If this particular pin is tied to Vcc, then the Almost Empty (PAE#) and Almost Full (PAF#) flags will respond asynchronously to a particular clock. If this pin is tied to ground, then the flag will respond synchronously to a clock edge which is why it is called SMODE = synchronous mode. Specifically, in SMODE, the Almost Empty flag will update after the next RCLK rising edge while the Almost Full flag will update after the next WCLK rising edge. Otherwise the Almost Empty flag will update a certain time after the last write operation and the Almost Full flag will update after the last read operation. Depending on how the external devices will react to the flag, there is an argument to using either mode. If comparing to other Cypress synchronous FIFOs (like the CY7C436xx family) this pin should be tied to ground. More recent synchronous FIFOs have synchronous mode only flags.

The FIFOs need a proper Master Reset after turning on the power. A reset pulse

empties the device and sets the flags to represent the empty state. If a complete

and correct master reset cycle is not accomplished, the FIFO will not work properly.

The exact constraints of a reset cycle are defined in the datasheets. Usually there is

a minimum reset pulse which must be met. Giving the device a reset pulse includes

both an assertion and de-assertion edge to the reset pin. In addition, the read and

write enable signals for all FIFO's normally must be disabled during the reset pulse

except with some devices when programming the PAE and PAF flags. Also, one needs

to make sure that there is no noise pulse on the /MR signal when interfacing with

other devices. Any noise on reset may lead to an improper reset which may result in

some problems.

2. OE# is an asynchronous signal which means it is not tied to a clock. The FIFO will react to the state of the OE# signal asynchronously. This means that even if there is a valid read operation on the reading port, if OE# is high, no data will come out. However, the read operation does occur. That means the next read operation will actually point to the next word in the FIFO.

3. When OE# is not asserted, all data outputs still remain in a high-impedence state, even when RS# is asserted. All data outputs go LOW after the falling edge of RS only if OE is asserted.

4. If the FIFO outputs are not connected to a bidirectional bus, it will be fine to have the OE# pin asserted at all times (tied to ground) since this pin only controls the tristate buffer at the outputs.

After a FIFO reset, if OE# is enabled, then the data lines will all go low t_RSF after the assertion of the reset signal.

If there is a need for the data outputs to be driven logically high after reset, the only way to work around this behavior is to write a dummy character of all 1's into the FIFO and read that value out.  This will keep the data outputs high until the next character is read.

Based on the table above, all 5V FIFOs can accept 3.3V inputs as long as the device driving it has outputs of greater than 2.0V to meet the Vih minimum, and do not swing below the minimum specified Vil which differs from FIFO to FIFO. Cypress can only guarantee operation of the FIFOs if they are used within specification.

It is also important to note that the 3.3V device must be able to tolerate the 5V outputs coming from the FIFO for this system to work.

FIFOs and dual-ports are both two-port SRAMs, except that FIFOs are specifically designed for sequential data, such as video or speech. Dual-ports, on the other hand, are more versatile in that writes and reads are allowed on both ports and not limited to sequential data. This is because the memory spaces in dual-ports are addressable. There is no address in a FIFO memory. However, a dual-port can be designed to work as a FIFO if needed, especially if the dual-port has burst mode features. 

San Jose, Calif., June 2, 2011- Cypress Semiconductor Corp. (Nasdaq: CY), today announced First-In, First-Out (FIFO) memories with densities up to 72 Mbit. The new High-Density (HD) FIFOs from Cypress are particularly well-suited for video and imaging applications which require high density and high frequency for effective buffering.  More information about the HD FIFO is available at http://www.cypress.com/go/HDFIFO.

The HD FIFO is an advanced buffering alternative to standard synchronous DRAM memories used in combination with large FPGAs. Cypress’s HD FIFOs offer enhanced signal integrity compared to a DRAM based solution, and operate at 133MHz frequency which is well-suited for buffering video frames. The HD FIFO offers up to eight separate directly addressable queues to enable designers to stream multiple video channels simultaneously. Using an HD FIFO enables designers to use a smaller FPGA, resulting in overall system cost reduction.  Cypress’s HD FIFO also reduces design complexity, thus speeding time-to-market for video and imaging systems in broadcast, military, medical and BTS segments.

The new HD FIFOs are available in 18-, 36- and 72-Mbit densities. They support multiple I/O standards, including 3.3V and 1.8V LVCMOS and HSTL1. The HD FIFO solution also provides user-selectable memory organization and can be configured as a x9, x12, x16, x18, x20, x24, x32 or x36 device, providing designers flexibility to choose optimal depth and width. All of the HD FIFO densities are offered in the 209-ball BGA package, which ensures scalability.

“We’ve developed a FIFO product with sufficient bandwidth and density to enable high bandwidth buffered links between highly specialized sub-systems in the video broadcasting, military and medical space,” said Dinesh Maheshwari, Chief Technology Advisor at Cypress. “Features such as multi queuing allow for multiple logical streams between the sub-systems. In addition, multiple I/O standards with configurable width support allow the highly specialized sub-systems to evolve at their natural pace. HD FIFOs will help system designers get their products to market faster and with improved product performance.”

Availability
The new FIFOs are available for sampling today in 209-ball BGA package of 14mm x 22mm x 1.86mm dimension from Cypress and its authorized distributors. They are expected to reach production in August 2011. A high-resolution photo is available for download at www.cypress.com/go/HDFIFOPhoto.

About Cypress
Cypress delivers high-performance, mixed-signal, programmable solutions that provide customers with rapid time-to-market and exceptional system value. Cypress offerings include the flagship PSoC® programmable system-on-chip families and derivatives such as PowerPSoC® solutions for high-voltage and LED lighting applications, CapSense® touch sensing and TrueTouch™ solutions for touchscreens. Cypress is the world leader in USB controllers, including the high-performance West Bridge® solution that enhances connectivity and performance in multimedia handsets. Cypress is also a leader in high-performance memories and programmable timing devices. Cypress serves numerous markets including consumer, mobile handsets, computation, data communications, automotive, industrial and military. Cypress trades on the Nasdaq Global Select Market under the ticker symbol CY. Visit Cypress online at www.cypress.com.

# # #

 
Cypress, the Cypress logo, PSoC, PowerPSoC, CapSense and West Bridge are registered trademarks, and FleXo and TrueTouch are trademarks of Cypress Semiconductor Corp. All other trademarks are property of their owners.

Datasheet can be found at : http://www.cypress.com/?docID=14141
 

Response: In most cases "Qualification report" will be available in the part number page. If it is not available, check for the following methods below.

Option-1:

1. Go to www.cypress.com

2. Enter the part number whose "Qualification Report" is needed in the "Keyword" search.

3. All the related document to this part will be displayed.

4. In the "Resource Type" select "Qualification Report", all related qualification report will be displayed.

Option-2:

1. Go to www.cypress.com,

2. Select "Design Support",

3. Select "Quality & Reliability"

4. Now in the "Qualification Report" Tab, there are two option.

a) Drop down menu to select the product family eg: Memory (All QTP related to Memory will be shown)

b) Search the QTP with a part number (eg: CY7B923) . All the related QTP will be shown.

Option-3:

1. Go to www.cypress.com

2. Select "Part Number" search.

3. Search for the part whose qualification report is required.

4. Click on the Base/Root Part.

5. Now the Qual Report download will be shown, sometimes it may require to login.

If none of the above procedure works, then create a support case to get the Qualification Report.

When the read pointer catches up with the write pointer, the FIFO is empty and when the write pointer catches up with read pointer, then the FIFO is full.

One way this is accomplished is by making each counter one bit wider than required.  All counter bits except the MSB are used to address the FIFO array.  In this configuration, every location in the FIFO is accessed twice before the counter rolls over.  When the MSB of the write counter is equal to the read counter, the FIFO is empty.  When the MSB's are not equal, the FIFO is full.  This scheme makes it relatively simple to generate the empty and full flags.  Since the FIFO logic prevents additional writes to a full FIFO and also prevents reads from an empty FIFO, the counters can never get further apart than the depth of the FIFO.  This prevents reading old data or overwriting new data.  

There are requirements and conditions for the Pb-Free devices reflow process and are tabulated in the Cypress Pb-Free reflow profile shown below. The product must meet two stringent requirements, zero lead and high temperature (260 ?C) reflow capability. Higher temperature reflow capability is needed because Pb-Free solder pastes melt at higher temperatures. The Pb-Free devices are marked with an 'X' on the package in the standard parts number.

For leadframe-based packages, Nickel Palladium Gold (Ni-Pd-Au) and Matte Tin (Sn) are the primary options. Nickel Palladium Gold (Ni-Pd-Au) for internally manufactured product and Tin (Sn) for subcontract manufactured products.

BGA packages will use Tin-Silver-Copper (SnAgCu) instead of Tin-Lead (SnPb) balls 

Cypress Semiconductor 260 Pb-Free Reflow Profile

However, the models can be searched on the link given below.
http://www.cypress.com/?app=search&searchType=advanced&keyword=&rtID=114&id=0&applicationID=0&l=0
 
 
 

It's common to encounter race conditions when operating the FIFO at the boundary. Referring to the switching waveform for "Empty Flag and Read Data Flow-Through Mode" in the data sheets of certain asynchronous FIFO's, notice that when there is only ONE word in the FIFO, the falling edge of /R will cause /EF to get asserted, while the rising edge of /W will cause /EF to de-assert. Thus, if these two edges are too close to one another, a "race condition" will occur, where /EF will not truly reflect the state of the FIFO for a short period of time.

That's part of the reason why newer generation FIFOs have programmable flags, which signals the write and read interfaces when the FIFO is almost full or almost empty, so as to avoid such boundary condition. More information regarding this race condition is described in detail in the application note "Understanding Large FIFO's" (Understanding Large FIFO's App Note).

For example, a 32-bit data width FIFO has 20 of its data input pins connected to a device with the other 12 pins left floating. When data is written into the FIFO from the 20 data pins, that 20-bit data is stored in 20-bits of a 32-bit wide memory location. Unknown "Data" from the 12 floating pins is written into the other 12-bits in the 32-bit memory location. As a result, the 32-bit word of data in that specific memory location has 12 of its bits which have unknown values, which can cause data to be "corrupt".

A general rule that should never be broken is that input signals should not be left floating. Depending on what that input signal is, you should pull the input to a known value (either Vcc or GND). This is also true of I/Os (signals that are both input and output). These signals should be pulled high or low with a resistor to some known value if you are not going to be using it.

On the other hand, output only pins like the data out pins of the FIFO can indeed be left floating. Data outputs (Q) are in high-impedance state when R# is high or when the FIFO is empty. It is ok to attach weak pull up/down resistors at the system designer's choice.

The above discussion applies only to unidirectional FIFOs.