Features

• 256-Kbit nonvolatile static random access memory (nvSRAM)
  • Internally organized as 32 K × 8
  • STORE to QuantumTrap nonvolatile elements initiated automatically on power-down (AutoStore) or by using I2C command (Software STORE) or HSB pin (Hardware STORE)
  • RECALL to SRAM initiated on power-up (Power-Up RECALL) or by I²C command (Software RECALL)
  • Automatic STORE on power-down with a small capacitor (except for CY14MX256J1)
• High reliability
  • Infinite read, write, and RECALL cycles
  • 1 million STORE cycles to QuantumTrap
  • Data retention: 20 years at 85°C
• For more, see pdf

Overview

The Cypress CY14MC256J/CY14MB256J/CY14ME256J combines a 256-Kbit nvSRAM with a nonvolatile element in each memory cell. The memory is organized as 32 K words of 8 bits each. The embedded nonvolatile elements incorporate the QuantumTrap technology, creating the world’s most reliable nonvolatile memory. The SRAM provides infinite read and write cycles, while the QuantumTrap cells provide highly reliable nonvolatile storage of data.

High Integration Device Replaces Multiple Parts

• Serial Nonvolatile Memory
• Real-time Clock (RTC)
• Low Voltage Reset
• Watchdog Timer
• Early Power-Fail Warning/NMI
• Two 16-bit Event Counters
• Serial Number with Write-lock for Security
• For more, see pdf.

Description

The FM31xx is a family of integrated devices that includes the most commonly needed functions for processor-based systems. Major features include nonvolatile memory available in various sizes, real-time clock, low-VDD reset, watchdog timer, nonvolatile event counter, lockable 64-bit serial number area, and general purpose comparator that can be used for an early power-fail (NMI) interruptor other purpose. The family operates from 2.7 to 5.5V.

Features

• Supports bus operation up to 200 MHz
• Available speed grades are 200 and 167 MHz
• Registered inputs and outputs for pipelined operation
• 3.3 V core power supply
• 2.5 V/3.3 V I/O operation
• Fast clock-to-output times
  • 3.0 ns (for 200 MHz device)
• Provide high performance 3-1-1-1 access rate
• User selectable burst counter supporting Intel® Pentium® interleaved or linear burst sequences
• For more, see pdf
   

Functional Description

The CY7C1480V33 SRAM integrates 2 M × 36 SRAM cells with advanced synchronous peripheral circuitry and a two-bit counter for internal burst operation. All synchronous inputs are gated by registers controlled by a positive-edge-triggered Clock Input (CLK).

Features

• 256-Kbit nonvolatile static random access memory (nvSRAM)
  • Internally organized as 32 K × 8
  • STORE to QuantumTrap nonvolatile elements initiated automatically on power-down (AutoStore) or by using I²C command (Software STORE) or HSB pin (Hardware STORE)
  • RECALL to SRAM initiated on power-up (Power-Up RECALL) or by I²C command (Software RECALL)
  • Automatic STORE on power-down with a small capacitor
• High reliability
  • Infinite read, write, and RECALL cycles
  • 1 million STORE cycles to QuantumTrap
  • Data retention: 20 years at 85 °C
• For more, see pdf

Overview

The Cypress CY14C256I/CY14B256I/CY14E256I combines a 256-Kbit nvSRAM with a full-featured RTC in a monolithic integrated circuit with serial I2C interface. The memory is organized as 64 K words of 8 bits each. The embedded nonvolatile elements incorporate the QuantumTrap technology, creating the world’s most reliable nonvolatile memory. The SRAM provides infinite read and write cycles, while the QuantumTrap cells provide highly reliable nonvolatile storage of data. Data transfers from SRAM to the nonvolatile elements (STORE operation) takes place automatically at power-down. On power-up, data is restored to the SRAM from the nonvolatile memory (RECALL operation). The STORE and RECALL operations can also be initiated by the user through I2C commands.

Features

• 1-Mbit nonvolatile static random access memory (nvSRAM)
  • Internally organized as 128 K × 8
  • STORE to QuantumTrap nonvolatile elements initiated automatically on power-down (AutoStore) or by using I²C command (Software STORE) or HSB pin (Hardware STORE)
  • RECALL to SRAM initiated on power-up (Power-Up RECALL) or by I²C command (Software RECALL)
  • Automatic STORE on power-down with a small capacitor (except for CY14X101J1)
• High reliability
  • Infinite read, write, and RECALL cycles
  • 1 million STORE cycles to QuantumTrap
  • Data retention: 20 years at 85 °C
• For more, see pdf
   

Overview

The Cypress CY14C101J/CY14B101J/CY14E101J combines a 1-Mbit nvSRAM with a nonvolatile element in each memory cell. The memory is organized as 128 K words of 8 bits each. The embedded nonvolatile elements incorporate the QuantumTrap technology, creating the world’s most reliable nonvolatile memory. The SRAM provides infinite read and write cycles, while the QuantumTrap cells provide highly reliable nonvolatile storage of data.

Features

• 64-Kbit nonvolatile static random access memory (nvSRAM)
  • Internally organized as 8 K × 8
  • STORE to QuantumTrap nonvolatile elements initiated automatically on power-down (AutoStore) or by using I2C command (Software STORE) or HSB pin (Hardware STORE)
  • RECALL to SRAM initiated on power-up (Power-Up RECALL) or by I2C command (Software RECALL)
  • Automatic STORE on power-down with a small capacitor (except for CY14MX064J1)
• High reliability
  • Infinite read, write, and RECALL cycles
  • 1 million STORE cycles to QuantumTrap
  • Data retention: 20 years at 85° C
• For more, see pdf

Overview

The Cypress CY14MB064J/CY14ME064J combines a 64-Kbit nvSRAM with a nonvolatile element in each memory cell. The memory is organized as 8 K words of 8 bits each. The embedded nonvolatile elements incorporate the QuantumTrap technology, creating the world’s most reliable nonvolatile memory. The SRAM provides infinite read and write cycles, while the QuantumTrap cells provide highly reliable nonvolatile storage of data.

Features

• 512-Kbit nonvolatile static random access memory (nvSRAM)
  • Internally organized as 64 K × 8
  • STORE to QuantumTrap nonvolatile elements initiated automatically on power-down (AutoStore) or by using I2C command (Software STORE) or HSB pin (Hardware STORE)
  • RECALL to SRAM initiated on power-up (Power-Up RECALL) or by I²C command (Software RECALL)
  • Automatic STORE on power-down with a small capacitor (except for CY14X512J1)
• High reliability
  • Infinite read, write, and RECALL cycles
  • 1 million STORE cycles to QuantumTrap
  • Data retention: 20 years at 85 °C
• For more, see pdf
   

Overview

The Cypress CY14C512J/CY14B512J/CY14E512J combines a 512-Kbit nvSRAM with a nonvolatile element in each memory cell. The memory is organized as 64 K words of 8 bits each. The embedded nonvolatile elements incorporate the QuantumTrap technology, creating the world’s most reliable nonvolatile memory. The SRAM provides infinite read and write cycles, while the QuantumTrap cells provide highly reliable nonvolatile storage of data. Data transfers from SRAM to the nonvolatile elements (STORE operation) takes place automatically at power-down (except for CY14X512J1). On power-up, data is restored to the SRAM from the nonvolatile memory (RECALL operation). The STORE and RECALL operations can also be initiated by the user through I2C commands.

Features

• 512-Kbit nonvolatile static random access memory (nvSRAM)
  • Internally organized as 64 K × 8
  • STORE to QuantumTrap nonvolatile elements initiated automatically on power-down (AutoStore) or by using I2C command (Software STORE) or HSB pin (Hardware STORE)
  • RECALL to SRAM initiated on power-up (Power-Up RECALL) or by I2C command (Software RECALL)
  • Automatic STORE on power-down with a small capacitor
• High reliability
  • Infinite read, write, and RECALL cycles
  • 1 million STORE cycles to QuantumTrap
  • Data retention: 20 years at 85 °C
• For more, see pdf
   

Overview

The Cypress CY14C512I/CY14B512I/CY14E512I combines a 512-Kbit nvSRAM with a full-featured RTC in a monolithic integrated circuit with serial I2C interface. The memory is organized as 64 K words of 8 bits each. The embedded nonvolatile elements incorporate the QuantumTrap technology, creating the world’s most reliable nonvolatile memory. The SRAM provides infinite read and write cycles, while the QuantumTrap cells provide highly reliable nonvolatile storage of data. Data transfers from SRAM to the nonvolatile elements (STORE operation) takes place automatically at power-down. On power-up, data is restored to the SRAM from the nonvolatile memory (RECALL operation). The STORE and RECALL operations can also be initiated by the user through I2C commands.

Features

• Supports up to 100-MHz bus operations with zero wait states
  • Data is transferred on every clock
• Pin compatible and functionally equivalent to ZBT™ devices
• Internally self timed output buffer control to eliminate the need to use OE
• Registered inputs for flow-through operation
• Byte write capability
• 256 K × 18 common IO architecture
• 2.5 V / 3.3 V IO power supply (VDDQ)
• Fast clock-to-output times
• For more, see pdf
   

Functional Description

The CY7C1353G is a 3.3 V, 256 K × 18 synchronous flow-through burst SRAM designed specifically to support unlimited true back-to-back read/write operations without the insertion of wait states. The CY7C1353G is equipped with the advanced No Bus Latency™ (NoBL™) logic required to enable consecutive read/write operations with data being transferred on every clock cycle. This feature dramatically improves the throughput of data through the SRAM, especially in systems that require frequent write-read transitions.

Features

• Supports bus operation up to 250 MHz
• Available speed grades are 250, 200, and 167 MHz
• Registered inputs and outputs for pipelined operation
• 3.3V core power supply
• 2.5V or 3.3V I/O power supply
• Fast clock-to-output times
  • 2.6 ns (for 250 MHz device)
• Provides high performance 3-1-1-1 access rate
• User selectable burst counter supporting Intel Pentium® interleaved or linear burst sequences
• For more, see pdf

Functional Description

The CY7C1380D/CY7C1380F/CY7C1382D SRAM integrates 524,288 × 36 and 1,048,576 × 18 SRAM cells with advanced synchronous peripheral circuitry and a two-bit counter for internal burst operation. All synchronous inputs are gated by registers controlled by a positive edge triggered clock input (CLK). The synchronous inputs include all addresses, all data inputs, address-pipelining chip enable (CE1), depth-expansion chip enables (CE2 and CE3), burst control inputs (ADSC, ADSP, and ADV), write enables (BWX, and BWE), and global write (GW). Asynchronous inputs include the output enable (OE) and the ZZ pin. 

Features

• Can support up to 133-MHz bus operations with zero wait states
  • Data is transferred on every clock
• Pin compatible and functionally equivalent to ZBT™ devices
• Internally self-timed output buffer control to eliminate the need to use OE
• Registered inputs for flow-through operation
• Byte write capability
• 128 K × 36 common I/O architecture
• 2.5 V/3.3 V I/O power supply (VDDQ)
• Fast clock-to-output times
• For more, see pdf

Functional Description

The CY7C1351G is a 3.3 V, 128 K × 36 synchronous flow-through burst SRAM designed specifically to support unlimited true back-to-back read/write operations without the insertion of wait states. The CY7C1351G is equipped with the advanced No Bus Latency™ (NoBL™) logic required to enable consecutive Read/Write operations with data being transferred on every clock cycle. This feature dramatically improves the throughput of data through the SRAM, especially in systems that require frequent write-read transitions.

Features

• Supports 133 MHz bus operations
• 512K × 36 and 1M × 18 common I/O
• 3.3V core power supply (VDD)
• 2.5V or 3.3V I/O supply (VDDQ)
• Fast clock-to-output time
  • 6.5 ns (133 MHz version)
• Provides high performance 2-1-1-1 access rate
• User selectable burst counter supporting Intel Pentium interleaved or linear burst sequences
• Separate processor and controller address strobes
• For more, see pdf
   

Functional Description

The CY7C1381D/CY7C1383D/CY7C1383F is a 3.3 V, 512 K × 36 and 1 M × 18 synchronous flow through SRAMs, designed to interface with high speed microprocessors with minimum glue logic. Maximum access delay from clock rise is 6.5 ns (133 MHz version). A 2-bit on-chip counter captures the first address in a burst and increments the address automatically for the rest of the burst access. All synchronous inputs are gated by registers controlled by a positive edge triggered clock input (CLK).

Features

• 64-Kbit nonvolatile static random access memory (nvSRAM)
  • Internally organized as 8 K × 8
  • STORE to QuantumTrap nonvolatile elements initiated automatically on power-down (AutoStore) or by using SPI instruction (Software STORE) or HSB pin (Hardware STORE)
  • RECALL to SRAM initiated on power-up (Power Up RECALL) or by SPI instruction (Software RECALL)
  • Automatic STORE on power-down with a small capacitor
• High reliability
  • Infinite read, write, and RECALL cycles
  • 1 million STORE cycles to QuantumTrap
  • Data retention: 20 years at 85 °C
• For more, see pdf
   

Overview

The Cypress CY14X064PA combines a 64 Kbit nvSRAM with a full-featured RTC in a monolithic integrated circuit with serial SPI interface. The memory is organized as 8 K words of 8 bits each. The embedded nonvolatile elements incorporate the QuantumTrap technology, creating the world’s most reliable nonvolatile memory. The SRAM provides infinite read and write cycles, while the QuantumTrap cells provide highly reliable nonvolatile storage of data. Data transfers from SRAM to the nonvolatile elements (STORE operation) takes place automatically at power-down. On power-up, data is restored to the SRAM from the nonvolatile memory (RECALL operation). You can also initiate the STORE and RECALL operations through SPI instruction.

High Integration Device Replaces Multiple Parts

• Serial Nonvolatile Memory
• Real-time Clock (RTC)
• Low Voltage Reset
• Watchdog Timer
• Early Power-Fail Warning/NMI
• Two 16-bit Event Counters
• Serial Number with Write-lock for Security
• For more, see pdf.

Description

The FM3127x is a family of integrated devices that includes the most commonly needed functions for processor-based systems. Major features include nonvolatile memory available in various sizes, real-time clock, low-VDD reset, watchdog timer, nonvolatile event counter, lockable 64-bit serial number area, and general purpose comparator that can be used for an early power-fail (NMI) interrupt or other purpose. The family operates from 4.0 to 5.5V.

Features

• Pin compatible and functionally equivalent to ZBT™ devices
• Internally self-timed output buffer control to eliminate the need to use OE
• Byte write capability
• 256 K × 18 common I/O architecture
• 3.3 V core power supply (VDD)
• 2.5 V/3.3 V I/O power supply (VDDQ)
• Fast clock-to-output times
  • 4.0 ns (for 133-MHz device)
• Clock enable (CEN) pin to suspend operation
• For more, see pdf

Functional Description

The CY7C1352G is a 3.3 V, 256 K × 18 synchronous-pipelined burst SRAM designed specifically to support unlimited true back-to-back read/write operations without the insertion of wait states. The CY7C1352G is equipped with the advanced No Bus atency™ (NoBL™) logic required to enable consecutive read/write operations with data being transferred on every clock cycle. This feature dramatically improves the throughput of the SRAM, especially in systems that require frequent write/read transitions.

Features

• 256-Kbit nonvolatile static random access memory (nvSRAM)
  • Internally organized as 32 K × 8
  • STORE to QuantumTrap nonvolatile elements initiated automatically on power-down (AutoStore) or by using SPI instruction (Software STORE) or HSB pin (Hardware STORE)
  • RECALL to SRAM initiated on power-up (Power Up RECALL) or by SPI instruction (Software RECALL)
  • Automatic STORE on power-down with a small capacitor
• High reliability
  • Infinite read, write, and RECALL cycles
  • 1 million STORE cycles to QuantumTrap
  • Data retention: 20 years at 85 °C
• For more, see pdf

Overview

The Cypress CY14X256PA combines a 256-Kbit nvSRAM with a full-featured RTC in a monolithic integrated circuit with serial SPI interface. The memory is organized as 32 K words of 8 bits each. The embedded nonvolatile elements incorporate the QuantumTrap technology, creating the world’s most reliable nonvolatile memory. The SRAM provides infinite read and write cycles, while the QuantumTrap cells provide highly reliable nonvolatile storage of data. Data transfers from SRAM to the nonvolatile elements (STORE operation) takes place automatically at power-down. On power-up, data is restored to the SRAM from the nonvolatile memory (RECALL operation). You can also initiate the STORE and RECALL operations through SPI instruction.

Features

• 64-Kbit nonvolatile static random access memory (nvSRAM)
  • Internally organized as 8 K × 8
  • STORE to QuantumTrap nonvolatile elements initiated automatically on power-down (AutoStore) or by using I2C command (Software STORE) or HSB pin (Hardware STORE)
  • RECALL to SRAM initiated on power-up (Power-Up RECALL) or by I2C command (Software RECALL)
  • Automatic STORE on power-down with a small capacitor
• High reliability
  • Infinite read, write, and RECALL cycles
  • 1 million STORE cycles to QuantumTrap
  • Data retention: 20 years at 85 °C
• For more, see pdf

Overview

The Cypress CY14C064I/CY14B064I/CY14E064I combines a 64-Kbit nvSRAM with a full-featured RTC in a monolithic integrated circuit with serial I2C interface. The memory is organized as 8 K words of 8 bits each. The embedded nonvolatile elements incorporate the QuantumTrap technology, creating the world’s most reliable nonvolatile memory. The SRAM provides infinite read and write cycles, while the QuantumTrap cells provide highly reliable nonvolatile storage of data. Data transfers from SRAM to the nonvolatile elements (STORE operation) takes place automatically at power-down. On power-up, data is restored to the SRAM from the nonvolatile memory (RECALL operation). The STORE and RECALL operations can also be initiated by the user through I2C commands.

This application note provides a few example circuits, design guidelines, and PSoC®3 based sample code snippets to help users understand and design with Cypress I²C nvSRAM.

An "I²C nvRAM" component library is also created using Cypress PSoC®3 device as a reference design project and attached to this Application Note. The PSoC®3 component library configures Cypress PSoC®3 device as a standard I²C master controller and also provides the list of APIs which can directly be called in an application firmware to access the I²C nvSRAM functions.

Features

• 512-Kbit nonvolatile static random access memory (nvSRAM)
  • Internally organized as 64 K × 8
  • STORE to QuantumTrap nonvolatile elements initiated automatically on power-down (AutoStore) or by using SPI instruction (Software STORE) or HSB pin (Hardware STORE)
  • RECALL to SRAM initiated on power-up (Power-Up RECALL) or by SPI instruction (Software RECALL)
  • Automatic STORE on power-down with a small capacitor
• High reliability
  • Infinite read, write, and RECALL cycles
  • 1 million STORE cycles to QuantumTrap
  • Data retention: 20 years at 85° C
• For more, see pdf
   

Overview

The Cypress CY14X512PA combines a 512-Kbit nvSRAM with a full-featured RTC in a monolithic integrated circuit with serial SPI interface. The memory is organized as 64 K words of 8 bits each. The embedded nonvolatile elements incorporate the QuantumTrap technology, creating the world’s most reliable nonvolatile memory. The SRAM provides infinite read and write cycles, while the QuantumTrap cells provide highly reliable nonvolatile storage of data.

Features

• 1-Mbit nonvolatile static random access memory (nvSRAM)
  • Internally organized as 128 K x 8
  • STORE to QuantumTrap nonvolatile elements initiated automatically on power-down (AutoStore) or by using I2C command (Software STORE) or HSB pin (Hardware STORE)
  • RECALL to SRAM initiated on power-up (Power Up RECALL) or by I2C command (Software RECALL)
  • Automatic STORE on power-down with a small capacitor
• High reliability
  • Infinite read, write, and RECALL cycles
  • 1 million STORE cycles to QuantumTrap
  • Data retention: 20 years at 85 °C
• For more, see pdf

Overview

The Cypress CY14C101I/CY14B101I/CY14E101I combines a 1-Mbit nvSRAM[1] with a full-featured RTC in a monolithic integrated circuit with serial I2C interface. The memory is organized as 128 K words of 8 bits each. The embedded nonvolatile elements incorporate the QuantumTrap technology, creating the world’s most reliable nonvolatile memory. The SRAM provides infinite read and write cycles, while the QuantumTrap cells provide highly reliable nonvolatile storage of data. Data transfers from SRAM to the nonvolatile elements (STORE operation) takes place automatically at power-down.

Features

• 1-Mbit nonvolatile static random access memory (nvSRAM)
  • Internally organized as 128 K × 8
  • STORE to QuantumTrap nonvolatile elements initiated automatically on power-down (AutoStore) or by using SPI instruction (Software STORE) or HSB pin (Hardware STORE)
  • RECALLto SRAM initiated on power-up (Power Up RECALL) or by SPI instruction (Software RECALL)
  • Automatic STORE on power-down with a small capacitor
• High reliability
  • Infinite read, write, and RECALL cycles
  • 1 million STORE cycles to QuantumTrap
  • Data retention: 20 years at 85°C
• For more, see pdf

Overview

The Cypress CY14X101PA combines a 1 Mbit nvSRAM with a full-featured RTC in a monolithic integrated circuit with serial SPI interface. The memory is organized as 128 K words of 8 bits each. The embedded nonvolatile elements incorporate the QuantumTrap technology, creating the world’s most reliable nonvolatile memory. The SRAM provides infinite read and write cycles, while the QuantumTrap cells provide highly reliable nonvolatile storage of data.

Features

• Pin-compatible and functionally equivalent to ZBT™
• Supports 200-MHz bus operations with zero wait states
  • Available speed grades are 200 and 167 MHz
• Internally self-timed output buffer control to eliminate the need to use asynchronous OE
• Fully registered (inputs and outputs) for pipelined operation
• Byte write capability
• Single 2.5 V power supply
• 2.5 V/1.8 V I/O supply (V_DDQ)
• Fast clock-to-output times
• For more, see pdf

Functional Description

The CY7C1470V25/CY7C1472V25/CY7C1474V25 are 2.5 V, 2 M × 36/4 M × 18/1 M × 72 synchronous pipelined burst SRAMs with No Bus Latency™ (NoBL™logic, respectively. They are designed to support unlimited true back-to-back read/write operations with no wait states. The CY7C1470V25/CY7C1472V25/CY7C1474V25 are equipped with the advanced (NoBL) logic required to enable consecutive read/write operations with data being transferred on every clock cycle.

Features

• Pin compatible and functionally equivalent to ZBT
• Supports 200 MHz Bus operations with zero wait states
  • Available speed grades are 200 and 167 MHz
• Internally self timed output buffer control to eliminate the need to use asynchronous OE
• Fully registered (inputs and outputs) for pipelined operation
• Byte write capability
• Single 3.3 V power supply
• 3.3 V/2.5 V I/O power supply
• Fast clock-to-output time
• For more, see pdf

Functional Description

The CY7C1470V33, CY7C1472V33, and CY7C1474V33 are 3.3 V, 2 M x 36/4 M x 18/1 M x 72 synchronous pipelined burst SRAMs with No Bus Latency™ (NoBL™) logic, respectively. They are designed to support unlimited true back-to-back read/write operations with no wait states. The CY7C1470V33, CY7C1472V33, and CY7C1474V33 are equipped with the advanced (NoBL) logic required to enable consecutive read/write operations with data being transferred on every clock cycle.

Features

• No Bus Latency™ (NoBL™) architecture eliminates dead cycles between write and read cycles
• Supports up to 133 MHz bus operations with zero wait states
• Data is transferred on every clock
• Pin compatible and functionally equivalent to ZBT™ devices
• Internally self timed output buffer control to eliminate the need to use OE
• Registered inputs for flow through operation
• Byte Write capability
• 3.3 V/2.5 V IO supply (VDDQ)
• Fast clock-to-output times
• For more, see pdf

Functional Description

The CY7C1471V33 is 3.3 V, 2 M × 36 synchronous flow through burst SRAMs designed specifically to support unlimited true back-to-back read or write operations without the insertion of wait states. The CY7C1471V33 is equipped with the advanced No Bus Latency (NoBL) logic required to enable consecutive read or write operations with data being transferred on every clock cycle. This feature dramatically improves the throughput of data through the SRAM, especially in systems that require frequent write-read transitions.

Features

• No Bus Latency™ (NoBL™) architecture eliminates dead cycles between write and read cycles
• Supports up to 133 MHz bus operations with zero wait states
• Data is transferred on every clock
• Pin compatible and functionally equivalent to ZBT™ devices
• Internally self timed output buffer control to eliminate the need to use OE
• Registered inputs for flow through operation
• Byte write capability
• 2.5 V/1.8 V IO supply (VDDQ)
• Fast clock-to-output times
• For more, see pdf

Functional Description

The CY7C1471V25 are 2.5 V, 2 M × 36 synchronous flow through burst SRAMs designed specifically to support unlimited true back-to-back read or write operations without the insertion of wait states. The CY7C1471V25 are equipped with the advanced No Bus Latency (NoBL) logic required to enable consecutive read or write operations with data transferred on every clock cycle.

128K bit Ferroelectric Nonvolatile RAM
 

• Organized as 16,384 x 8 bits
• High Endurance 100 Trillion (10¹⁴) Read/Writes
• 10 year Data Retention
• NoDelay™ Writes
• Advanced High-Reliability Ferroelectric Process
• For more, see pdf.

Description

The FM24V01 is a 128Kbit nonvolatile memory employing an advanced ferroelectric process. A ferroelectric random access memory or F-RAM is nonvolatile and performs reads and writes like a RAM. It provides reliable data retention for 10 years while eliminating the complexities, overhead, and system level reliability problems caused by EEPROM and other nonvolatile memories.

64K x 4 Static RAM with Separate IO

Features

• High speed
  • 15 ns
• CMOS for optimum speed/power
• Low active power
  • 860 mW
• Low standby power
  • 55 mW
• TTL-compatible inputs and outputs
• Automatic power down when deselected
• Available in Pb-free and non Pb-free 28-Pin Molded SOJ package

Functional Description

The CY7C192 is a high performance CMOS static RAM organized as 65,536 x 4 bits with separate IO. Easy memory expansion is provided by active LOW Chip Enable (CE) and tri-state drivers. It has an automatic power down feature that reduces power consumption by 75% when deselected.

The I²C nvSRAM offers all four standard I²C-bus modes (Standard-mode - 100KHz, Fast-mode - 400 KHz, Fast-mode plus - 1 MHz, and High-speed mode - 3.4 MHz) through a single solution. As a result, Cypress has standardized someof the I/O specifications across all modes to offer consistent I/O behavior across the modes. This standardization causes some ofits I/O specifications slightly differ than NXP I²C standard. This application note highlights the I²C nvSRAM spec differences from the standard NXP I²C-bus specification. 

Features

• 72-Mbit density (4 M × 18)
• 250 MHz clock for high bandwidth
• Two-word burst for reducing address bus frequency
• Double data rate (DDR) interfaces (data transferred at 500 MHz) at 250 MHz
• Two input clocks (K and K) for precise DDR timing
  • SRAM uses rising edges only
• Two input clocks for output data (C and C) to minimize clock skew and flight time mismatches
• Echo clocks (CQ and CQ) simplify data capture in high speed systems
• Synchronous internally self timed writes
• For more, see pdf.

Functional Description

The CY7C1523KV18 is a1.8 V Synchronous Pipelined SRAMs, equipped with DDR II SIO (Double Data Rate Separate I/O) architecture. The DDR II SIO consists of two separate ports: the read port and the write port to access the memory array. The read port has data outputs to support read operations and the write port has data inputs to support write operations. The DDR II SIO has separate data inputs and data outputs to completely eliminate the need to “turnaround” the data bus required with common I/O devices.

• 144-Mbit density (8 M × 18)
• 333 MHz clock for high bandwidth
• Two-word burst for reducing address bus frequency
• Double Data Rate (DDR) interfaces (data transferred at 666 MHz) at 333 MHz
• Two input clocks (K and K) for precise DDR timing
  • SRAM uses rising edges only
• Two input clocks for output data (C and C) to minimize clock skew and flight time mismatches
• Echo clocks (CQ and CQ) simplify data capture in high speed systems
• Synchronous internally self timed writes
• For more, see pdf.

Functional Description

The CY7C1623KV18 is 1.8 V Synchronous Pipelined SRAM, equipped with DDR-II SIO (Double Data Rate Separate I/O) architecture. The DDR-II SIO consists of two separate ports: the read port and the write port to access the memory array. The read port has data outputs to support read operations and the write port has data inputs to support write operations. The DDR-II SIO has separate data inputs and data outputs to completely eliminate the need to ‘turnaround’ the data bus required with common I/O devices. Access to each port is accomplished through a common address bus.

16K bit Ferroelectric Nonvolatile RAM
 

• Organized as 2,048 x 8 bits
• High Endurance 100 Trillion (10¹⁴) Read/Writes
• 38 Year Data Retention (@ +75ºC)
• NoDelay™ Writes
• Advanced High-Reliability Ferroelectric Process
• For more, see pdf.

Description

The FM25L16B is a 16-kilobit nonvolatile memory employing an advanced ferroelectric process. A ferroelectric random access memory or F-RAM is nonvolatile and performs reads and writes like a RAM. It provides reliable data retention for 38 years while eliminating the complexities, overhead, and system level reliability problems caused by EEPROM and other nonvolatile memories.

Features

• Very high speed: 45 ns
• Temperature ranges
  • Industrial: –40 °C to 85 °C
  • Automotive-A: –40 °C to 85 °C
• Wide voltage range: 2.20 V to 3.60 V
• Pin compatible with CY62146DV30
• Ultra low standby power
  • Typical standby current: 1 μA
  • Maximum standby current: 7 μA
• For more, see pdf
   

Functional Description

The CY62146EV30 is a high performance CMOS static RAM organized as 256K words by 16 bits. This device features an advanced circuit design designed to provide an ultra low active current. Ultra low active current is ideal for providing More Battery Life™ (MoBL®) in portable applications such as cellular telephones. The device also has an automatic power down feature that significantly reduces power consumption by 80 percent when addresses are not toggling.

This application note describes the internal architecture of Cypress’ asynchronous FIFO CY7C421. A summary of key device features, applications, failure modes, typical problem symptoms and solutions is also included.

The content of the application note has been captured in a training module. This audio visual tutorial provides an introduction to FIFO architecture & its functionality. It explains the features of asynchronous FIFOs such as flags, retransmit functionality & expansion logic. It also briefly discusses the applications of Asynchronous FIFOs.

Training Module: View Download

Refer to the application note AN4065 - QDR™-II, QDR-II+, DDR-II, and DDR-II+ Design Guide for different termination schemes, designs, and signal integrity guidelines. For more information on the QDR-DDR II/II+/Xtreme SRAMs, refer to the respective datasheets in the Sync SRAM category.

Reference Schematic for QDR-DDR II/II+/Xtreme SRAMs (from internal characterization board)

Figure 1. (a) QDRII/II+/II+Xtreme-DDRII/II+/II+Xtreme (Non ODT) Reference Schematic

Figure 1. (b) QDRII/II+/II+Xtreme-DDRII/II+/II+Xtreme (ODT) Reference Schematic

Figure 2. QDRII/II+/II+Xtreme-DDRII/II+/II+Xtreme (Supply Pins) Reference Schematic

Assumptions

• The reference schematics provided in the previous section are from an internal characterization board. Cypress recommends that you perform signal integrity simulations with specific board conditions before finalizing your design.
• Figure 1 (a) and (b) are the reference schematics for all on-die termination (ODT) and Non ODT QDR-DDR II/II+/Xtreme SRAMs respectively. For example, if the part is an x18 device, then the data pin notation D_[x:0] will be interpreted as D_[17:0].
• QDRII+/II+Xtreme-DDRII+/II+Xtreme devices do not have the input clocks C and C#.
• Non ODT QDRII+/II+Xtreme-DDRII/II+/II+Xtreme devices do not contain the ODT pin.
• ODT devices have an ODT feature for Data inputs (D_[x:0]), Byte Write Selects (BWS_[x:0]), and Input Clocks (K and K#). Hence, there is no termination for the D_[x:0], BWS_[x:0] , K, and K# pins shown in Figure 1 (b). Refer to the application note AN42468 - On-Die Termination for QDR™II+/DDRII+ SRAMs that discusses the ODT scheme, implementation, advantages, and power calculation for the QDRII+ and DDRII+ family of Synchronous SRAMs on 65-nm technology devices.
• Data output (Q_[x:0]) and Echo clock (CQ/CQ#) signals drive FPGA/ASIC without termination, considering the inputs of the FPGA/ASIC that supports ODT. In the case of FPGA/ASIC without ODT, Cypress recommends that you terminate (pull-up to V_TT) Data output (Q_[x:0]) and Echo clock (CQ/CQ#) signals to reduce signal integrity issues.
• The value of the termination resistor (R) is 50Ω, because most designs have a trace characteristic impedance of 50Ω. The termination resistor value must be equal to the characteristic impedance of the trace.
• An external resistor, RQ, must be connected between the ZQ pin on the SRAM and V_SS to allow the SRAM to adjust its output driver impedance. The value of RQ must be five times the value of the intended line impedance driven by the SRAM. As a result, the value of RQ is 250Ω to match the output impedance of 50Ω in Figure 1 (a) and (b). The acceptable range of RQ that guarantees impedance matching with a tolerance of ±15% is between 175Ω and 350Ω, with V_DDQ = 1.5V. The output impedance is adjusted every 1024 cycles upon power-up to account for drifts in supply voltage and temperature.
• Keep termination resistors as close to the device as possible to reduce the stub length, and thereby, reduce reflections.

Decoupling Capacitor Recommendations for Power Supply Pins

• Decoupling capacitors on power-supply pins play a significant role in filtering noise in the power supply.
• Cypress recommends that you place the decoupling capacitors close to the memory devices for best results.
• The following decoupling capacitor recommendations are from an internal characterization board:

Figure 3. Decoupling Capacitor Recommendation for V_DD

Figure 4. Decoupling Capacitor Recommendation for V_DDQ

Note Refer to the datasheets for V_DDQ value

Figure 5. Decoupling Capacitor Recommendation for V_TT

Figure 6. Decoupling Capacitor Recommendation for V_REF

If you face any issue while creating your design or if you would like Cypress to do a schematic review, create a technical support case at www.cypress.com.

This document describes the recommendations for byte enable pins for certain Cypress MoBL SRAM devices from old inventory. If you have any queries about the content in this document, please contact us at www.cypress.com/support.

Note that you must read the datasheet before implementing the timing recommendations provided in this document.

Figure 1. Read and Write Pointers

The FIFO is empty when the read pointer catches up with the write pointer, and full when the write pointer catches up with read pointer.

One way of accomplishing this is by making each counter one bit wider than required. All counter bits except the MSB are used to address the FIFO array. In this configuration, every location in the FIFO is accessed twice before the counter rolls over. When the MSBs of the write counter equal those of the read counter, the FIFO is empty. When the MSBs are not equal and the actual count value is same, then the FIFO is full. This scheme makes it relatively simple to generate the empty and full flags. Since the FIFO logic prevents additional writes to a full FIFO and also prevents reads from an empty FIFO, the counters can never get further apart than the depth of the FIFO. This prevents reading old data or overwriting new data.

Features

• Separate independent read and write data ports
  • Supports concurrent transactions
• 250 MHz clock for high bandwidth
• 4-word burst for reducing address bus frequency
• Double data rate (DDR) interfaces on both read and write ports at 250 MHz (data transferred at 500 MHz)
• Two input clocks (K and K) for precise DDR timing
  • SRAM uses rising edges only
• Echo clocks (CQ and CQ) simplify data capture in high speed systems
• Single multiplexed address input bus latches address inputs for read and write ports
• Separate port selects for depth expansion
• For more, see pdf
   

Functional Description

The CYRS1543AV18 and CYRS1545AV18 are synchronous pipelined SRAMs, equipped with 1.8 V QDR II+ architecture with RadStop™ technology. Cypress’s state-of-the-art RadStop Technology is radiation hardened through proprietary design and process hardening techniques.

Features

• Separate independent read and write data ports
  • Supports concurrent transactions
• 250-MHz clock for high bandwidth
• 2-word burst on all accesses
• Double data rate (DDR) interfaces on both read and write ports at 250 MHz (data transferred at 500 MHz)
• Two input clocks (K and K) for precise DDR timing
  • SRAM uses rising edges only
• Echo clocks (CQ and CQ) simplify data capture in high speed systems
• Single multiplexed address input bus latches address inputs for both read and write ports
• Separate port selects for depth expansion
• For more, see pdf
   

Functional Description

The CYRS1542AV18 and CYRS1544AV18 are synchronous pipelined SRAMs, equipped with 1.8-V QDR II+ architecture with RadStop™ technology. Cypress’s state-of-the-art RadStop Technology is radiation hardened through proprietary design and process hardening techniques.

The rest of this document describes the timing recommendations for byte enable pins and chip enables for Cypress MoBL SRAM devices from old inventory. If you have any queries about the content in this document, please contact us at www.cypress.com/support.

Note that you must read the datasheet before implementing the timing recommendations mentioned in this document.

1. All datasheet parameters are as specified provided the operating temperature is ≥ -15°C.
2. If -25°C minimum operating temperature is required, then you must comply with a minimum VDD Fall Time (tVF) of 200μs/V.

There is a design change in process to improve the cold temperature performance. An update will be issued when the design change has been verified.

1. All datasheet parameters are as specified provided the operating temperature is ≥ -15°C.
2. If -25°C minimum operating temperature is required, then you must comply with a minimum VDD Fall Time (tVF) of 200μs/V.

There is a design change in process to improve the cold temperature performance. An update will be issued when the design change has been verified.

1. All datasheet parameters are as specified provided the operating temperature is ≥ -15°C.
2. If -25°C minimum operating temperature is required, then you must comply with a minimum VDD Fall Time (tVF) of 200μs/V.

There is a design change in process to improve the cold temperature performance. An update will be issued when the design change has been verified.

Fix: The /S pin should be pulled up with a resistor to Vdd and the /HOLD pin can also be pulled up or simply tied to VDD. When the device is powered up, these pins must be inactive.

1. All datasheet parameters are as specified provided the operating temperature is ≥ -15°C.
2. If -25°C minimum operating temperature is required, then you must comply with a minimum VDD Fall Time (tVF) of 200μs/V.

There is a design change in process to improve the cold temperature performance. An update will be issued when the design change has been verified.

1. All datasheet parameters are as specified provided the operating temperature is ≥ -15°C.
2. If -25°C minimum operating temperature is required, then you must comply with a minimum VDD Fall Time (tVF) of 200μs/V.

There is a design change in process to improve the cold temperature performance. An update will be issued when the design change has been verified.

1. All datasheet parameters are as specified provided the operating temperature is ≥ -15°C.
2. If -25°C minimum operating temperature is required, then you must comply with a minimum VDD Fall Time (tVF) of 200μs/V.

There is a design change in process to improve the cold temperature performance. An update will be issued when the design change has been verified.