Features

• True Dual-Ported memory cells which allow simultaneous access of the same memory location
• 32K x 16 organization (CY7C027V/027VN/027AV)
• 64K x 16 organization (CY7C028V)
• 32K x 18 organization (CY7C037V/037AV)
• 64K x 18 organization (CY7C038V)
• 0.35 micron CMOS for optimum speed and power
• High speed access: 15, 20, and 25 ns
• Low operating power
• Active: I_CC = 115 mA (typical)
• For more, see pdf
   

Functional Description

The CY7C027V/027AV/028V and CY7037AV/038V are low power CMOS 32K, 64K x 16/18 dual-port static RAMs. Various arbitration schemes are included on the devices to handle situations when multiple processors access the same piece of data. Two ports are provided, permitting independent, asynchronous access for reads and writes to any location in memory. 

Cypress's FLEx18 / FLEx36® / FLEx72™ portfolio of highdensity, high-performance synchronous Dual-Port SRAMs can operate at speeds up to 167 MHz. In the fast growing data communications market, the bandwidth requirements have increased. Cypress addresses these demands with its FullFlex Dual-Port SRAMs, which can operate up to 200 MHz.

The nvSRAM architecture uses a one-to-one pairing of a nonvolatile bit and a fast SRAM bit in each memory cell. During normal operation, the IC behaves exactly as a standard fast asynchronous SRAM and is easy to interface with the microprocessor or microcontroller. When IC power is disrupted or lost, the event is detected and all the SRAM bits are saved into the nonvolatile part (within 8 ms) using the stored energy in a small capacitor (VCAP). This operation is called AutoStore and is described in more detail in the next section. When power is restored, data is automatically recalled from the nonvolatile part to SRAM on power restore and this operation is called Power Up RECALL (Hardware RECALL).
 

Features

• True dual port memory enables simultaneous access to the shared array from each port
• Synchronous pipelined operation with single data rate (SDR) operation on each port
  • SDR interface at 200 MHz
  • Up to 28.8 Gb/s bandwidth (200 MHz × 72-bit × 2 ports)
• Selectable pipelined or flow-through mode
• 1.5 V or 1.8 V core power supply
• Commercial and Industrial temperature
• IEEE 1149.1 JTAG boundary scan
• Available in 484-ball PBGA (× 72) and 256-ball FBGA (× 36 and × 18) packages
• For more, see pdf

Functional Description

The FullFlex™ dual port SRAM families consist of 2-Mbit, 4-Mbit, 9-Mbit, 18-Mbit, and 36-Mbit synchronous, true dual port static RAMs that are high speed, low power 1.8 V or 1.5 V CMOS. Two ports are provided, enabling simultaneous access to the array. Simultaneous access to a location triggers deterministic access control. For FullFlex72 these ports operate independently with 72-bit bus widths and each port is independently configured for two pipelined stages. Each port is also configured to operate in pipelined or flow through mode.

• 18 Mbit density (1 M x 18, 512 K x 36)
• 450-MHz clock for high bandwidth
• Two-word burst for reducing address bus frequency
• Double data rate (DDR) interfaces (data transferred at 900 MHz) at 450 MHz
• Available in 2.0 clock cycle latency
• For more, see pdf
   

Functional Description

The CY7C1148KV18, and CY7C1150KV18 are 1.8 V Synchronous Pipelined SRAMs equipped with DDR II+ architecture. The DDR II+ consists of an SRAM core with advanced synchronous peripheral circuitry. Addresses for read and write are latched on alternate rising edges of the input (K) clock.

• Separate independent read and write data ports
  • Supports concurrent transactions
• 550-MHz clock for high bandwidth
• Four-word burst for reducing address bus frequency
• Double data rate (DDR) interfaces on both read and write ports (data transferred at 1100 MHz) at 550 MHz
• Available in 2.5 clock cycle latency
• For more, see pdf
   

Functional Description

The CY7C1163KV18, and CY7C1165KV18 are 1.8 V Synchronous Pipelined SRAMs, equipped with QDR II+ architecture. Similar to QDR II architecture, QDR II+ architecture consists of two separate ports: the read port and the write port to access the memory array. The read port has dedicated data outputs to support read operations and the write port has dedicated data inputs to support write operations. QDR II+ architecture has separate data inputs and data outputs to completely eliminate the need to ‘turnaround’ the data bus that exists with common I/O devices. Each port is accessed through a common address bus. Addresses for read and write addresses are latched on alternate rising edges of the input (K) clock.

• 18-Mbit density (1 M × 18, 512 K × 36)
• 550-MHz clock for high bandwidth
• Two-word burst for reducing address bus frequency
• Double data rate (DDR) interfaces (data transferred at 1100 MHz) at 550 MHz
• Available in 2.5 clock cycle latency
• Two input clocks (K and K) for precise DDR timing
• Echo clocks (CQ and CQ) simplify data capture in high-speed systems
• For more, see pdf

Functional Description

The CY7C1168KV18, and CY7C1170KV18 are 1.8 V synchronous pipelined SRAMs equipped with DDR II+ architecture. The DDR II+ consists of an SRAM core with advanced synchronous peripheral circuitry. Addresses for read and write are latched on alternate rising edges of the input (K) clock.

• 18 Mbit density (2 M x 8, 1 M x 18)
• 333-MHz clock for high bandwidth
• Two-word burst for reducing address bus frequency
• Double data rate (DDR) interfaces (data transferred at 666 MHz) at 333 MHz
• For more, see pdf
   

Functional Description

The CY7C1392KV18 and CY7C1393KV18 are 1.8 V Synchronous Pipelined SRAMs, equipped with DDR II SIO (double data rate separate I/O) architecture. The DDR II SIO consists of two separate ports: the read port and the write port to access the memory array. The read port has data outputs to support read operations and the write port has data inputs to support write operations. The DDR II SIO has separate data inputs and data outputs to completely eliminate the need to ‘turnaround’ the data bus required with common I/O devices. Access to each port is accomplished through a common address bus. Addresses for read and write are latched on alternate rising edges of the input (K) clock.

• 18 Mbit density (1 M x 18, 512 K x 36)
• 333-MHz clock for high bandwidth
• Four-word burst for reducing address bus frequency
• Double data rate (DDR) interfaces (data transferred at 666 MHz) at 333 MHz
• Two input clocks (K and K) for precise DDR timing
• Two input clocks for output data (C and C) to minimize clock skew and flight time mismatches
• For more, see pdf
   

Functional Description

CY7C1319KV18 and CY7C1321KV18 are 1.8 V Synchronous Pipelined SRAMs equipped with DDR II architecture. The DDR II consists of an SRAM core with advanced synchronous peripheral circuitry and a two-bit burst counter. Addresses for read and write are latched on alternate rising edges of the input (K) clock.

• Separate independent read and write data ports
  • Supports concurrent transactions
• 450-MHz clock for high bandwidth
• Four-word burst for reducing address bus frequency
• Double data rate (DDR) Interfaces on both read and write ports (data transferred at 900 MHz) at 450 MHz
• Available in 2.0 clock cycle latency
• For more, see pdf
   

Functional Description

The CY7C1143KV18, and CY7C1145KV18 are 1.8 V Synchronous Pipelined SRAMs, equipped with QDR II+ architecture. Similar to QDR II architecture, QDR II+ architecture consists of two separate ports: the read port and the write port to access the memory array. The read port has dedicated data outputs to support read operations and the write port has dedicated data inputs to support write operations. QDR II+ architecture has separate data inputs and data outputs to completely eliminate the need to “turnaround” the data bus that exists with common I/O devices. Each port is accessed through a common address bus. Addresses for read and write addresses are latched on alternate rising edges of the input (K) clock.
 

• 18 Mbit density (1 M x 18, 512 K x 36)
• 550-MHz clock for high bandwidth
• Two-word burst for reducing address bus frequency
• Double data rate (DDR) interfaces (data transferred at 1100 MHz) at 550 MHz
• Available in 2.5 clock cycle latency
• Two input clocks (K and K) for precise DDR timing
  • SRAM uses rising edges only
• Echo clocks (CQ and CQ) simplify data capture in high-speed systems
• Data valid pin (QVLD) to indicate valid data on the output
• For more, see pdf

Functional Description

The CY7C2168KV18, and CY7C2170KV18 are 1.8 V Synchronous Pipelined SRAMs equipped with DDR II+ architecture. The DDR II+ consists of an SRAM core with advanced synchronous peripheral circuitry. Addresses for read and write are latched on alternate rising edges of the input (K) clock.

• Separate independent read and write data ports
  • Supports concurrent transactions
• 450 MHz clock for high bandwidth
• Four-word burst for reducing address bus frequency
• Double Data Rate (DDR) interfaces on both read and write ports (data transferred at 900 MHz) at 450 MHz
• Available in 2.0 clock cycle latency
• Two input clocks (K and K) for precise DDR timing
  • SRAM uses rising edges only
• Echo clocks (CQ and CQ) simplify data capture in high speed systems
• For more, see pdf
   

Features

• Very high speed: 45 ns
• Wide voltage range: 2.2V to 3.6V and 4.5V to 5.5V
• Ultra low standby power
  • Typical standby current: 1 μA
  • Maximum standby current: 7 μA
• Ultra low active power
  • Typical active current: 2 mA at f = 1 MHz
• Easy memory expansion with CE and OE features
• Automatic power-down when deselected
• Complementary metal oxide semiconductor (CMOS) for optimum speed and power
• Available in Pb-free 44-pin thin small outline package (TSOP) II package
   

Functional Description

The CY62136ESL is a high performance CMOS static RAM organized as 128K words by 16 bits. This device features advanced circuit design to provide ultra low active current. This is ideal for providing More Battery Life™ (MoBL®) in portable applications such as cellular telephones. The device also has an automatic power down feature that reduces power consumption when addresses are not toggling.

Features

• True Dual-Ported memory cells which enable simultaneous access of the same memory location
• Flow-through and Pipelined devices
• 32 K × 9 organizations (CY7C09179V)
• 64 K × 8 organizations (CY7C09089V)
• 128 K × 8/9 organizations (CY7C09099V/199V)
• 3 Modes
• Flow-Through
• Pipelined
• Burst
• For more, see pdf
   

Functional Description

The CY7C09089V/99V and CY7C09179V/99V are high speed synchronous CMOS 64 K/128 K × 8 and 32 K/128 K × 9 dual-port static RAMs. Two ports are provided, permitting independent, simultaneous access for reads and writes to any location in memory. Registers on control, address, and data lines enable minimal setup and hold times.

Features

• True dual-ported memory cells that allow simultaneous access of the same memory location
• Synchronous pipelined operation
• Family of 4 Mbit, 9 Mbit, and 18 Mbit devices
• Pipelined output mode allows fast operation
• 0.18-micron complmentary metal oxide semiconductor (CMOS) for optimum speed and power
• High-speed clock to data access
• 3.3 V low power
  • Active as low as 225 mA (typ)
  • Standby as low as 55 mA (typ)
• For more, see pdf

Functional Description

The FLEx72 family includes 4 Mbit, 9 Mbit and 18 Mbit pipelined, synchronous, true dual-port static RAMs that are high-speed, low-power 3.3 V CMOS. Two ports are provided, permitting independent, simultaneous access to any location in memory. The result of writing to the same location by more than one port at the same time is undefined. Registers on control, address, and data lines allow for minimal set-up and hold time.

Features

• True dual-ported memory cells that allow simultaneous access of the same memory location
• Six flow through/pipelined devices:
  • 16 K × 16 / 18 organization (CY7C09269V/369V)
  • 32 K × 16 organization (CY7C09279V)
  • 64 K × 16 / 18 organization (CY7C09289V/389V)
• Three modes:
  • Flow through
  • Pipelined
  • Burst
• For more, see pdf
   

Functional Description

The CY7C09269V/79V/89V and CY7C09369V/89V are high speed 3.3 V synchronous CMOS 16 K, 32 K, and 64 K × 16 and 16 K and 64 K × 18 dual-port static RAMs. Two ports are provided, permitting independent, simultaneous access for reads and writes to any location in memory.

Features

• True dual-ported memory cells which allow simultaneous access of the same memory location
• Two Flow-Through/Pipelined devices
  • 16K x 36 organization (CY7C09569V)
  • 32K x 36 organization (CY7C09579V)
• 0.25-micron CMOS for optimum speed/power
• Three modes
  • Flow-Through
  • Pipelined
  • Burst
• For more, see pdf

Functional Description

The CY7C09569V and CY7C09579V are high-speed 3.3V synchronous CMOS 16K and 32K x 36 dual-port static RAMs. Two ports are provided, permitting independent, simultaneous access for reads and writes to any location in memory. Registers on control, address, and data lines allow for minimal set-up and hold times. In pipelined output mode, data is registered for decreased cycle time.

Features

• True dual-ported memory cells that allow simultaneous reads of the same memory location
• 4K ×16 organization (CY7C024E)
• 4K × 18 organization (CY7C0241E)
• 8K × 16 organization (CY7C025E)
• 8K × 18 organization (CY7C0251E)
• 0.35-μ complementary metal oxide semiconductor (CMOS) for optimum speed and power
• High-speed access: 15 ns
• Low operating power: ICC = 180 mA (typ), ISB3 = 0.05 mA (typ)
• Fully asynchronous operation
• For more, see pdf
   

Functional Description

The CY7C024E/CY7C0241E and CY7C025E/CY7C0251E are low-power CMOS 4K × 16/18 and 8K × 16/18 dual-port static RAMs. Various arbitration schemes are included on the CY7C024E/CY7C0241E and CY7C025E/CY7C0251E to handle situations when multiple processors access the same piece of data. Two ports are provided, permitting independent,  asynchronous access for reads and writes to any location in memory.

Features

• 3.3 V operation for low-power consumption and easy integration into low-voltage systems
• High-speed, low-power, first-in first-out (FIFO) memories
• 16 K × 9 (CY7C4261V)
• 32 K × 9 (CY7C4271V)
• 64 K × 9 (CY7C4281V)
• 128 K × 9 (CY7C4291V)
• 0.35-micron CMOS for optimum speed or power
• High-speed 100-MHz operation (10-ns read/write cycle times)
• Low power
• For more, see pdf
   

Functional Description

The CY7C4261/71/81/91V are high-speed, low-power FIFO memories with clocked read and write interfaces. All are nine bits wide. The CY7C4261/71/81/91V are pin-compatible to the CY7C42x1V Synchronous FIFO family. Programmable features include Almost Full/Almost Empty flags. These FIFOs provide solutions for a wide variety of data buffering needs, including high-speed data acquisition, multiprocessor interfaces, and communications buffering.

Features

• High-speed, low-power, first-in, first-out (FIFO) memories
  • 256 x 9 (CY7C4201V)
  • 512 x 9 (CY7C4211V)
• High-speed 66-MHz operation (15-ns read/write cycle time)
• Low power (I_CC = 20 mA)
• 3.3V operation for low power consumption and easy integration into low-voltage systems
• 5V-tolerant inputs V_{IH max} = 5 V
• Fully asynchronous and simultaneous read and write operation
• Empty, full, and programmable almost empty and almost full status flags
• For more, see pdf
   

Functional Description

The CY7C42X1V are high-speed, low-power, FIFO memories with clocked read and write interfaces. All are nine bits wide. Programmable features include Almost Full/Almost Empty flags. These FIFOs provide solutions for a wide variety of data buffering needs, including high-speed data acquisition, multiprocessor interfaces, and communications buffering.

Features

• High speed, low power, first-in first-out (FIFO) memories
• 256 x 18 (CY7C4205)
• 512 x 18 (CY7C4215)
• 1K x 18 (CY7C4225)
• 4K x 18 (CY7C4245)
• High speed 100 MHz operation (10 ns read/write cycle time)
• Low power (ICC = 45 mA)
• Fully asynchronous and simultaneous read and write operation
• For more, see pdf
   

Functional Description

The CY7C42X5 are high speed, low power, first-in first-out (FIFO) memories with clocked read and write interfaces. All are 18 bits wide and are pin/functionally compatible to IDT722X5. The CY7C42X5 can be cascaded to increase FIFO depth. Programmable features include Almost Full/Almost Empty flags.      More...

Features

• Temperature ranges
  • Industrial: –40°C to 85°C
  • Automotive-A: –40°C to 85°C
  • Automotive-E: –40°C to 125°C
• Pin and function compatible with CY7C1011BV33
• High speed
  • tAA = 10 ns (Industrial and Automotive-A)
  • tAA = 12 ns (Automotive-E)
• Low active power
  • 360 mW (max) (Industrial and Automotive-A)
• For more, see pdf

Functional Description

The CY7C1011CV33 is a high performance complementary metal oxide semiconductor (CMOS) static RAM organized as 131,072 words by 16 bits. This device has an automatic power down feature that significantly reduces power consumption when deselected.

Features

• Temperature Ranges
  • Industrial: –40°C to 85°C
  • Automotive: –40°C to 125°C
• Very high speed: 45 ns
• Wide voltage range: 2.2V to 3.6V
• Pin compatible with CY62127BV
• Ultra-low active power
  • Typical active current: 0.85 mA @ f = 1 MHz
  • Typical active current: 5 mA @ f = fMAX
• For more, see pdf

Functional Description

The CY62127DV30 is a high-performance CMOS static RAM organized as 64K words by 16 bits. This device features advanced circuit design to provide ultra-low active current. This is ideal for providing More Battery Life™ (MoBL^®) in portable applications such as cellular telephones. The device also has an automatic power-down feature that significantly reduces power consumption by 90% when addresses are not toggling.