General Description

With its unique array of configurable blocks, PSoC® 5LP is a true system-level solution providing microcontroller unit (MCU), memory, analog, and digital peripheral functions in a single chip. The CY8C52LP family offers a modern method of signal acquisition, signal processing, and control with high accuracy, high bandwidth, and high flexibility. Analog capability spans the range from thermocouples (near DC voltages) to ultrasonic signals.

The CY8C52LP family can handle dozens of data acquisition channels and analog inputs on every GPIO pin. The CY8C52LP family is also a high-performance configurable digital system with some part numbers including interfaces such as USB and multimaster I2C. In addition to communication interfaces, the CY8C52LP family has an easy to configure logic array, flexible routing to all I/O pins, and a high-performance 32-bit ARM®Cortex™-M3 microprocessor core.

Designers can easily create system level designs using a rich library of prebuilt components and boolean primitives using PSoC Creator™, a hierarchical schematic design entry tool. The CY8C52LP family provides unparalleled opportunities for digital bill of materials integration while easily accommodating last minute design changes through simple firmware updates.

Features

• 32-bit ARM Cortex-M3 CPU core
• Low voltage, ultra low power
• Versatile I/O system
• Digital peripherals
• Analog peripherals (1.71 V ≤ VDDA ≤ 5.50 V)
• Programming, debug, and trace
• Precision, programmable clocking
• Temperature and packaging
• For more, see data sheet pdf

General Description

With its unique array of configurable blocks, PSoC® 5LP is a true system-level solution providing microcontroller unit (MCU), memory, analog, and digital peripheral functions in a single chip. The CY8C58LP family offers a modern method of signal acquisition, signal processing, and control with high accuracy, high bandwidth, and high flexibility. Analog capability spans the range from thermocouples (near DC voltages) to ultrasonic signals.

The CY8C58LP family can handle dozens of data acquisition channels and analog inputs on every GPIO pin. The CY8C58LP family is also a high-performance configurable digital system with some part numbers including interfaces such as USB, multimaster I2C, and controller area network (CAN). In addition to communication interfaces, the CY8C58LP family has an easy to configure logic array, flexible routing to all I/O pins, and a high-performance 32-bit ARM® Cortex™-M3 microprocessor core.

Designers can easily create system-level designs using a rich library of prebuilt components and boolean primitives using PSoC Creator™, a hierarchical schematic design entry tool. The CY8C58LP family provides unparalleled opportunities for analog and digital bill of materials integration while easily accommodating last minute design changes through simple firmware updates.

Features

• 32-bit ARM Cortex-M3 CPU core
• Low voltage, ultra low power
• Versatile I/O system
• Digital peripherals
• Analog peripherals (1.71 V ≤ VDDA ≤ 5.5 V)
• Programming, debug, and trace
• Precision, programmable clocking
• Temperature and packaging
• For more, see data sheet pdf

General Description

With its unique array of configurable blocks, PSoC® 5LP is a true system level solution providing microcontroller unit (MCU), memory, analog, and digital peripheral functions in a single chip. The CY8C54LP family offers a modern method of signal acquisition, signal processing, and control with high accuracy, high bandwidth, and high flexibility. Analog capability spans the range from thermocouples (near DC voltages) to ultrasonic signals.

The CY8C54LP family can handle dozens of data acquisition channels and analog inputs on every GPIO pin. The CY8C54LP family is also a high-performance configurable digital system with some part numbers including interfaces such as USB and multi-master I2C. In addition to communication interfaces, the CY8C54LP family has an easy to configure logic array, flexible routing to all I/O pins, and a high-performance 32-bit ARM® Cortex™-M3 microprocessor core.

Designers can easily create system-level designs using a rich library of prebuilt components and boolean primitives using PSoC® Creator™, a hierarchical schematic design entry tool. The CY8C54LP family provides unparalleled opportunities for digital and analog bill of materials integration while easily accommodating last minute design changes through simple firmware updates.

Features

• 32-bit ARM Cortex-M3 CPU core
• Low voltage, ultra low power
• Versatile I/O system
• Digital peripherals
• Analog peripherals (1.71 V ≤ VDDA ≤ 5.5 V)
• Programming, debug, and trace
• Precision, programmable clocking
• Temperature and packaging
• For more, see data sheet pdf

General Description

With its unique array of configurable blocks, PSoC® 5LP is a true system level solution providing MCU, memory, analog, and digital peripheral functions in a single chip. The CY8C56LP family offers a modern method of signal acquisition, signal processing, and control with high accuracy, high bandwidth, and high flexibility. Analog capability spans the range from thermocouples (near DC voltages) to ultrasonic signals.

The CY8C56LP family can handle dozens of data acquisition channels and analog inputs on every GPIO pin. The CY8C56LP family is also a high performance configurable digital system with some part numbers including interfaces such as USB and multimaster I2C, and controller area network (CAN). In addition to communication interfaces, the CY8C56LP family has an easy to configure logic array, flexible routing to all I/O pins, and a high performance 32-bit ARM® Cortex™-M3 microprocessor core.

Designers can easily create system level designs using a rich library of prebuilt components and boolean primitives using PSoC Creator™, a hierarchical schematic design entry tool. The CY8C56LP family provides unparalleled opportunities for analog and digital bill of materials integration while easily accommodating last minute design changes through simple firmware updates.

Features

• 32-bit ARM Cortex-M3 CPU core
• Low voltage, ultra low power
• Versatile I/O system
• Digital peripherals
• Analog peripherals (1.71 V ≤ VDDA ≤ 5.5 V)
• Programming, debug, and trace
• Precision, programmable clocking
• Temperature and packaging
• For more, see pdf.

The video describes the case of using a DMA to buffer ADC data. Buffering of 20 bit ADC data is taken as an example and discussed. The video also gives a preview of the project implementing the 20 bit data buffering and explains the DMA configuration in code.

The following table indicates the PSoC devices, PSoC Creator versions, compilers, and development kits that will work with this application note project:

*Refer to Migrating CY8CKIT-001 DVK project to CY8CKIT 030/ 050. 

Notes:

1. Click on AN84741 - PSoC® 5 to PSoC 5LP Migration Guide to learn differences between PSoC 5 and PSoC 5LP.
2. Click on AN77835 - PSoC® 3 to PSoC 5LP Migration Guide to learn differences between PSoC 3 and PSoC 5LP.
3. For PSoC 5 project and related document, please download file AN61102_Archive.zip.

Projects associated with this application note can be downloaded from the ‘Related Files’ section below. For your convenience, we have provided projects that are compatible with the two most recent versions of PSoC Creator:

• AN61102.zip is used with PSoC Creator 2.1 SP1
• AN61102_Archive.zip is used with PSoC Creator 2.1/2.0

The project’s default settings may not be compatible with your device or kit, and you may need to change your project settings. For more information, see:

The TMP05 Digital Temperature Sensor Interface Component is a building block for thermal management applications. It enables designers using PSoC 3 to quickly and easily interface with Analog Devices’ TMP05 or TMP06 digital temperature sensors through a simple, serial 2-wire digital interface. The sensors can be daisy-chained together, minimizing I/O requirements on the controller. For more details on the specific functions of the TMP05 Digital Temperature Sensor Interface Component, refer to the component datasheet.

Notes:

1. Click on AN84741 - PSoC® 5 to PSoC 5LP Migration Guide to learn differences between PSoC 5 and PSoC 5LP.
2. For PSoC 5 project and related document, please download file AN65977_Archive.zip.

Projects associated with this application note can be downloaded from the 'Related Files' section below. For your convenience, we have provided projects that are compatible with the two most recent versions of PSoC Creator:

• AN65977.zip is used with PSoC Creator 2.1 SP1
• AN65977_Archive.zip is used with PSoC Creator 2.1/2.0

The project’s default settings may not be compatible with your device or kit, and you may need to change your project settings. For more information, see:

The document AN66477 - PSoC® 3 and PSoC 5 Temperature Measurement with Thermistor is currently being reviewed and updated to support the new Thermistor Component available in PSoC Creator 2.1. The updated application note is expected by 11/30/2012. The below abstract describes what this application note covers. If you have an immediate need for this document, please click here to create a technical support case requesting this material. 

Please note that the Thermistor Component is now provided in PSoC Creator 2.1. Please access the Thermistor Component Datasheet for features and configuration details. 

AN66477 Abstract:

AN66477 explains how to measure temperature with a thermistor using PSoC® 3 or PSoC 5LP®. This application note describes the PSoC Creator™ Thermistor Calculator Component, which simplifies the math-intensive resistance-to-temperature conversion. In addition, we discuss a PSoC Creator thermistor measurement project.

1. Click on AN84741 - PSoC® 5 to PSoC 5LP Migration Guide to learn differences between PSoC 5 and PSoC 5LP.
2. Click on AN77835 - PSoC® 3 to PSoC 5LP Migration Guide to learn differences between PSoC 3 and PSoC 5LP.

• 8-, 16-, 24-bit address bus width
• 8-, 16-bit data bus width
• Supports external synchronous memory
• Supports external asynchronous memory
• Supports custom interface for memory
• Supports a range of speeds of external memories (from 5 to 200 ns)
• Supports external memory power-down, sleep, and wakeup modes

General Description

The EMIF component enables access by the CPU or DMA to memory ICs external to the PSoC 3/5LP. It facilitates setup of the EMIF hardware, as well as UDBs and GPIOs as required. The EMIF can control synchronous and asynchronous memories without the need to configure any UDBs in synchronous and asynchronous modes. In UDB mode, UDBs must be configured to generate external memory control signals.

1. Click on AN84741 - PSoC® 5 to PSoC 5LP Migration Guide to learn differences between PSoC 5 and PSoC 5LP.

In addition, this application note walks you through an example project for PSoC 5LP. Through this project example, PSoC Creator is introduced. The first part of the project guides you on how to blink an LED like a typical MCU. In the second part you develop a "breathing" LED using the Programmable-System-On-Chip concept.

An additional bonus project is included with this application note that takes a design example a little farther than simply blinking LEDs. The bonus project uses some of the mixed signal functionality of PSoC 5LP to create an ambient light/dark detector using one of the LEDs on the CY8CKIT-050 demonstration board. 

The following table indicates the PSoC devices, PSoC Creator versions, compilers, and development kits that will work with this application note project:

*Refer to Migrating CY8CKIT-001 DVK project to CY8CKIT 030/050.

1. Click on AN84741 - PSoC® 5 to PSoC 5LP Migration Guide to learn differences between PSoC 5 and PSoC 5LP.
2. For PSoC 5 project and related document, please download file AN77759_Archive.zip.
3. Click on AN77835, PSoC 3 to PSoC 5LP Migration Guide. to learn differences between PSoC 3 and PSoC 5LP

Projects associated with this application note can be downloaded from the 'Related Files' section below. For your convenience, we have provided projects that are compatible with the two most recent versions of PSoC Creator:

• AN77759.zip is used with PSoC Creator 2.1 SP1
• AN77759_Archive.zip is used with PSoC Creator 2.1/2.0

The project’s default settings may not be compatible with your device or kit, and you may need to change your project settings. For more information, see:

Architecture:

PSoC 3/PSoC 5/PSoC 5LP has total of 24 UDBs. Each UDB mainly consists of: 8 macrocells, PLA (which can implement 16 Product terms), 1 datapath cell, 1 Control cell and 1 Status cell.

Altera MAXV 570ZM device has a total of 570 Logic elements. Each logic element consists of: One 4-input LUT and One register (D flip-flop).

Lattice MACHXO2 256HC device has a total of 128 slices. Each slice consists of: Two 4-input LUTs and Two registers (D flip-flop).

Xilinx XC2C384 consists of 24 Function blocks. Each function block consists of 16 Macrocells and a PLA (which can implement 56 Pterms).

Conclusion:

Data from the above table shows that the PSoC 3/PSoC 5/PSoC 5LP UDB utilization is comparable to:

Mid to higher end CPLDs from Altera MAXV series

Mid to higher end CPLDs from Xilinx Cool runner series

Lower end to mid range FPGAs from Lattice’s MACHXO2 series

Introduction

PSoC® 3 and PSoC 5LP have a powerful clocking system. This system offers the flexibility and performance to suit the needs of most embedded applications. It is comprised of clock sources and a clock distribution network. The clock sources available are the internal main oscillator (IMO), external crystal oscillators (ECO) and internal low-speed oscillator (ILO). This application note describes the IMO and ILO as well a method to improve their accuracy through run-time calibration.

The following table indicates the PSoC devices, PSoC Creator versions, compilers, and development kits that will work with this application note project:

Notes:

1. Click on AN84741 - PSoC® 5 to PSoC 5LP Migration Guide to learn differences between PSoC 5 and PSoC 5LP.
2. Click on AN77835 - PSoC® 3 to PSoC 5LP Migration Guide to learn differences between PSoC 3 and PSoC 5LP.
3. For PSoC 5 project and related document, please download file AN80248_Archive.zip.

Projects associated with this application note can be downloaded from the 'Related Files' section below. For your convenience, we have provided projects that are compatible with the two most recent versions of PSoC Creator:

• AN80248.zip is used with PSoC Creator 2.1 SP1
• AN80248_Archive.zip is used with PSoC Creator 2.1/2.0

The project’s default settings may not be compatible with your device or kit, and you may need to change your project settings. For more information, see:

CAN (Controller Area Network) is a serial communication protocol developed by Robert Bosch GmbH in the early 1980s. This protocol was initially developed for automotive applications to communicate between subsystems without a central control. CAN is also being adopted in areas such as embedded systems (CANOpen) and factory automation (DeviceNet). CAN was standardized by ISO in 2003 (ISO 11898-1:2003).

This application note introduces the basic concepts of CAN protocol and demonstrates how CAN bus communication can be implemented using PSoC® 3 and PSoC 5LP (hereafter referred to as PSoC). Four code examples are included with this application note. Examples 1 and 2 together illustrate a simplex communication between two PSoCs. Examples 3 and 4 together demonstrate the Remote Transmission Request (RTR) feature of CAN.

The video talks about how to transmit and receive messages using CAN controller available in PSoC3.

The following table indicates the PSoC devices, PSoC Creator versions, compilers, and development kits that will work with this application note project:

*Refer to Migrating CY8CKIT-001 DVK project to CY8CKIT 030/ 050.

1. Click on AN84741 - PSoC® 5 to PSoC 5LP Migration Guide to learn differences between PSoC 5 and PSoC 5LP.
2. Click on AN77835 - PSoC® 3 to PSoC 5LP Migration Guide to learn differences between PSoC 3 and PSoC 5LP.
3. For PSoC 5 project and related document, please download file AN52701_Archive.zip.

Projects associated with this application note can be downloaded from the ‘Related Files’ section below. For your convenience, we have provided projects that are compatible with the two most recent versions of PSoC Creator:

• AN52701.zip is used with PSoC Creator 2.1 SP1
• AN52701_Archive.zip is used with PSoC Creator 2.1/2.0

The project’s default settings may not be compatible with your device or kit, and you may need to change your project settings. For more information, see:

Introduction

The DMA controller (DMAC) in PSoC 3 and PSoC 5LP can transfer data from a source to a destination with no CPU intervention. This allows the CPU to handle other tasks while the DMA does data transfers, thereby achieving a „multiprocessing‟ environment.

The PSoC DMA Controller (DMAC) is highly flexible – it can seamlessly transfer data between memory and on chip peripherals including ADCs, DACs, Filter, USB, UART, and SPI. There are 24 independent DMA channels.

 The following video gives the user a brief description of how to use the DMA on PSoC3 and the different parameters related to it:

The following table indicates the PSoC devices, PSoC Creator versions, compilers, and development kits that will work with this application note project:

 *Refer to Migrating CY8CKIT-001 DVK project to CY8CKIT 030/ 050. 

1. Click on AN84741 - PSoC® 5 to PSoC 5LP Migration Guide to learn differences between PSoC 5 and PSoC 5LP.
2. For PSoC 5 project and related document, please download file AN52705_Archive.zip.

Projects associated with this application note can be downloaded from the ‘Related Files’ section below. For your convenience, we have provided projects that are compatible with the two most recent versions of PSoC Creator:

• AN52705.zip is used with PSoC Creator 2.1 SP1
• AN52705_Archive.zip is used with PSoC Creator 2.1/2.0

The project’s default settings may not be compatible with your device or kit, and you may need to change your project settings. For more information, see:

• Eliminates unwanted “glitch” pulses on digital input lines
• Programmable filtering length and bypass option
  
   

General Description

Glitch filtering is the process of removing unwanted pulses from a digital input signal that is usually high or low. Glitches frequently occur on lines carrying signals from sources such as RF receivers. Electrical or in some cases even mechanical interference can trigger an unwanted glitch pulse from the receiver.

This design outputs a ‘1’ only when the current and previous N samples are ‘1’, and a ‘0’ only when the current and previous N samples are ‘0’. Otherwise the output is unchanged from its current value.

For more details on glitch filtering please see application note AN60024.

Required Software: PSoC Creator 2.1 Component Pack 4 and above.

PSoC 1, PSoC 3, and PSoC 5LP are all true programmable embedded system-on-chips that integrate configurable analog, programmable digital, memory, and a central processor on a single chip.

PSoC contains a processor, but it is not an MCU. The name PSoC (Programmable-System-on-Chip) defines its true identity. AN54181 introduces the Programmable-System-on-Chip concept with specific emphasis on PSoC 3. Here, you learn about PSoC 3 and what it can do for you and your projects. It also introduces PSoC Creator™, a powerful IDE development tool for PSoC 3 and PSoC 5LP.

The following video gives brief introduction for PSoC3:

The following video guides how to create projects using PSoC3:

The following table indicates the PSoC devices, PSoC Creator versions, compilers, and development kits that will work with this application note project:

*Refer to Migrating CY8CKIT-001 DVK project to CY8CKIT 030/050. 

1. Click on AN84741 - PSoC® 5 to PSoC 5LP Migration Guide to learn differences between PSoC 5 and PSoC 5LP.
2. Click on AN77835 - PSoC® 3 to PSoC 5LP Migration Guide to learn differences between PSoC 3 and PSoC 5LP.
3. For PSoC 5 project and related document, please download file AN54181_Archive.zip.

Projects associated with this application note can be downloaded from the ‘Related Files’ section below. For your convenience, we have provided projects that are compatible with the two most recent versions of PSoC Creator:

• AN54181.zip is used with PSoC Creator 2.1 SP1
• AN54181_Archive.zip is used with PSoC Creator 2.1/2.0.

The project’s default settings may not be compatible with your device or kit, and you may need to change your project settings. For more information, see:

To get introduced to basics of PSoC 3 and PSoC 5LP Bootloader please refer  AN73854 - PSoC® 3 and PSoC 5LP - Introduction to Bootloaders. If you intend to learn how to develop I2C Bootloader for PSoC 3 and PSoC 5LP,  AN60317 - PSoC® 3/PSoC 5LP I2C Bootloader  should get you going. 

Since the projects involve the use of USB component, in case of PSoC 5LP it is mandatory to use an external 24 MHz crystal.

The Bootloader GUI provided with this App Note has been tested to work on full-fledged Windows operating system only.
The GUI is not tested and not guaranteed to work on Virtual machines.
 

*Refer to Migrating CY8CKIT-001 DVK project to CY8CKIT 030/ 050. 

Notes:

1. Click on AN84741 - PSoC® 5 to PSoC 5LP Migration Guide to learn differences between PSoC 5 and PSoC 5LP.
2. Click on AN77835 - PSoC® 3 to PSoC 5LP Migration Guide to learn differences between PSoC 3 and PSoC 5LP.
3. For PSoC 5 project and related document, please download file AN73503_Archive.zip.

Projects associated with this application note can be downloaded from the ‘Related Files’ section below. For your convenience, we have provided projects that are compatible with the two most recent versions of PSoC Creator:

• AN73503.zip is used with PSoC Creator 2.1 SP1
• AN73503_Archive.zip is used with PSoC Creator 2.1/2.0

The project’s default settings may not be compatible with your device or kit, and you may need to change your project settings. For more information, see:

• Asynchronous reset or preset
• Synchronous reset, preset, or both
• Configurable width for array of D Flip Flops

General Description

The D Flip Flop stores a digital value.

Required Software: PSoC Creator v1.0 Beta 5 and above

• Gain steps from -1 to -49
• High input impedance
• Adjustable power settings

General Description

The Inverting Programmable Gain Amplifier (PGA_Inv) component implements an opamp-based inverting amplifier with user-programmable gain. It is derived from the switched capacitor/continuous time (SC/CT) block.

The inverting gain can be between -1.0 (0 dB) and -49.0 (+33.8 dB). The gain can be selected using the configuration window or changed at run time using the provided API. The maximum bandwidth is limited by the gain-bandwidth of the opamp and is reduced as the gain is increased. The input of the PGA_Inv operates from rail to rail, but the maximum input swing (difference between Vin and Vref) is limited to V_DDA/Gain. The output of the PGA_Inv is class A, and is rail to rail for sufficiently high load resistance.

Required Software: PSoC Creator v1.0 Beta 5 and above

• Interfaces to up to 32 DC-DC power converters
• Measures power converter output voltages and load currents using a DelSig-ADC
• Monitors the health of the power converters generating warnings and faults based on user-defined thresholds
• Support for measuring other auxiliary voltages in the system
• Support 3.3V and 5V chip power supply

General Description

Power Converter Voltage Measurements:

For power converter voltage measurements, the ADC can be configured into single-ended mode (0-4.096 V range or 0-2.048 V range). The ADC can also be configurable into differential mode (±2.048 V range) to support remote sensing of voltages where the remote ground reference is returned to PSoC over a PCB trace. In cases where the analog voltage to be monitored equals or exceeds Vdda or the ADC range, external resistor dividers are recommended to scale the monitored voltages down to an appropriate range.

Power Converter Current Measurements:

For power converter load current measurements, the ADC can be configured into differential mode (+/- 64 mV or +/- 128 mV range) to support voltage measurement across a high-side series shunt resistor on the outputs of the power converters. Firmware APIs convert the measured differential voltage into the equivalent current based on the external resistor component value used. The ADC can also be configured into single-ended mode (0-4.096V range or 0-2.048 V range) to support connection to external current sense amplifiers (CSAs) that convert the differential voltage drop across the shunt resistor into a single ended voltage or to support power converters or hot-swap controllers that integrate similar functionality.

Required Software: PSoC Creator 2.0 Component Pack 3 and above

PSoC Creator Power Monitor Component Video
 

• Programmable flicker-free dimming resolution from 2 to 32 bit
• Two pulse density outputs
• Programmable output signal density
• Serial output bit stream
• Continuous run mode
• User-configurable sequence start value
• Standard or custom polynomials provided for all sequence lengths
• Kill input disables pulse density outputs and forces them low
• Enable input provides synchronized operation with other components
• Reset input allows restart at sequence start value for synchronization with other components
• Terminal Count Output for 8-, 16-, 24-, and 32-bit sequence lengths.

General Description

The Precision Illumination Signal Modulation (PrISM) component uses a linear feedback shift register (LFSR) to generate a pseudo random sequence. The sequence outputs a pseudo random bit stream, as well as up to two user-adjustable pseudo random pulse densities. The pulse densities may range from 0 to 100 percent.

Required Software: PSoC Creator v1.0 Beta 5 and above

• 2 to 768 pixels or symbols
• 1/3, 1/4 and 1/5 bias supported
• 10 to 150 Hz refresh rate
• Integrated bias generation between 2.0 V and 5.2 V with up to 128 digitally controlled bias levels for dynamic contrast control
• Supports both type A (standard) and type B (low power) waveforms
• Pixel state of the display may be inverted for negative image
• 256 bytes of display memory (frame buffer)
• User-defined pixel or symbol map with optional 7-, 14-, or 16-segment character; 5x7 or 5x8 dot matrix; and bar graph calculation routines.
• Supports PSoC 3 ES3 silicon revisions and above.

General Description

The Segment LCD (LCD_Seg) component can directly drive a variety of LCD glass at different voltage levels with multiplex ratios up to 16x. This component provides an easy method of configuring the PSoC device to drive your custom or standard glass. 

Required Software: PSoC Creator v1.0 Beta 5 and above

• SMBus Slave mode
• PMBus Slave mode
• SMBALERT# pin support
• 25 ms Timeout
• Fixed Function (FF) and UDB implementations
• Configurable SM/PM Bus commands
   

General Description

The System Management Bus (SMBus) and Power Management Bus (PMBus) Slave component provides a simple way to add an I2C physical layer interface to a PSoC 3 or PSoC 5 design with either SMBus or PMBus protocol running on top of it.

The SMBus is a two-wire interface with various System Management chips that can communicate with the system host. It uses I2C as a physical layer. The SMBus Slave component implements most of the SMBus Slave device specifications and provides options for configuring the slave device parameters. The slave device can communicate with the SMBus Master using the provided APIs.

The PMBus protocol is a specific implementation of the more generic SMBus protocol. With the PMBus, the component presents all the possible PMBus commands and allows you to select which commands are relevant to your application.

Required Software: PSoC Creator 2.1 Component Pack 4 and above.
 

• Conforms to IEC-60958, AES/EBU, AES3 standards for Linear PCM Audio Transmission
• Sample rate support for clock/128 (up to 192 kHz)
• Configurable audio sample length (8/16/24)
• Channel status bits generator for consumer applications
• DMA support
• Independent left and right channel FIFOs or interleaved stereo FIFOs

General Description

The SPDIF_Tx component provides a simple way to add digital audio output to any design. It formats incoming audio data and metadata to create the S/PDIF bit stream appropriate for optical or coaxial digital audio. The component supports interleaved and separated audio.

Required Software: PSoC Creator v1.0 Beta 5 and above

Features

• 3- to 16-bit data width
• Four SPI operating modes
• Bit Rate up to 18 Mbps

General Description

The SPI Master component provides an industry-standard, 4-wire master SPI interface. It can also provide a 3-wire (bidirectional) SPI interface. Both interfaces support all four SPI operating modes, allowing communication with any SPI slave device. In addition to the standard 8-bit word length, the SPI Master supports a configurable 3- to 16-bit word length for communicating with nonstandard SPI word lengths.     

Required Software: PSoC Creator v1.0 Beta 5 and above 

PSoC Creator SPI Master Component video

• Calculation accuracy 0.01 °C for -200 °C to 850 °C temperature range
• Provides simple API function for resistance to temperature conversion
• Displays Error Vs Temperature graph

General Description

The Resistance Temperature Detector (RTD) Calculator component generates a polynomial approximation for calculating the RTD Temperature in terms of RTD resistance for a PT100, PT500 or PT1000 RTD. Calculation error budget is user-selectable, and determines the order of the polynomial that will be used for the calculation (from 1 to 5). A lower calculation error budget will result in a more computation intensive calculation. For example, a fifth order polynomial will give a more accurate temperature calculation than lower order polynomials, but will take more time for execution. After maximum and minimum temperatures and error budget are selected, the component generates the maximum temperature error, and an error vs. temperature graph for all temperatures in the range, along with an estimate of the number of CPU cycles necessary for calculation using the selected polynomial. Selecting the lowest error budget will choose the highest degree polynomial. For the whole RTD temperature range, -200 °C to 850 °C, the component can provide a maximum error of <0.01 °C using a fifth order polynomial.

Required Software: PSoC Creator 2.1 Component Pack 4 and above
 

• Provides an editor to enter the assembler instructions to configure the DFB block and an assembler that converts the assembly instructions to instruction words.
• Supports simulation of the assembly instructions.
• Supports a code optimization option that provides a mechanism to incorporate up to 128 very large instruction words inside the DFB Code RAM.
• Provides hardware signals such as DMA requests, DSI inputs and outputs, and interrupt lines.
• Supports semaphores to interact with the system software and the option to tie the semaphores to hardware signals.

General Description

The digital filter block (DFB) in PSoC 3 and PSoC 5 can be used as mini DSP processor and allows you to configure the DFB using assembly instructions. The component assembles the instructions entered in the editor and generates the corresponding hex code words, which can be loaded into the DFB. It also includes a simulator, which helps the user to simulate and debug the assembly instructions.

The DFB consists of a programmable 24*24 multiplier/accumulator (MAC), an arithmetic logic unit (ALU), shifter, and various program and data memory to store instructions and data. The DFB runs on the bus clock, and can interface with both CPU and DMA. It can be used to offload the CPU and can speed up arithmetic calculations that involve intensive multiply accumulate operations. Typical operations you can use the DFB component to implement include: vector operations, matrix operations, filtering operations, and signal processing.

• Easy user configuration of filters running on the Digital Filter Block (DFB) available in some PSoC 3, PSoC 5 and PSoC5 LP devices.
• Supports two separate filter channels, each one constructed as a cascade of up to four separately designed stages.
• Multiple FIR and IIR (Biquad) filter methods (including user coefficient entry) give great flexibility
• Final coefficient values can be extracted for further analysis

General Description

The customizer for the Filter component allows you to configure digital filters on one or two data streams passed to the Digital Filter Block (DFB), using DMA, interrupts, or polling to manage data flow. The DFB’s 128 data and coefficient locations are shared as needed between the two filter channels. The customizer reports (but does not set) the minimum bus clock frequency required to execute the filtering within the user-declared sample interval.

This component supports a huge number of use cases. If you encounter something unusual when using it, report it (with a good description of what you did to cause it) to psoc_creator_fb@cypress.com so Cypress can investigate. 

Required Software: PSoC Creator v1.0 Beta 5 and above

• Accuracy of /-5° C
• Range -40° C to 140° C (0xFFD8 to 0x008C)
• Blocking and non-blocking API
• Does not support PSoC 5 silicon

General Description

The Die Temperature (DieTemp) component provides an API to acquire the temperature of the die. The System Performance Controller (SPC) is used to get the die temperature. The API includes blocking and nonblocking calls.

Required Software: PSoC Creator v1.0 Beta 5 and above

Features

• Industry-standard NXP® I2C bus interface
• Supports Slave, Master, Multi-Master and Multi-Master-Slave operation
• Requires only two pins (SDA and SCL) to interface to I2C bus
• Supports standard data rates of 100/400/1000 kbps
• High level APIs require minimal user programming

General Description

The I2C component supports I2C slave, master, and multi-master configurations. The I2C bus is an industry-standard, two-wire hardware interface developed by Philips. The master initiates all communication on the I2C bus and supplies the clock for all slave devices.

The I2C component supports standard clock speeds up to 1000 kbps. It is compatible with I2C Standard-mode, Fast-mode, and Fast-mode Plus devices as defined in the NXP I2C-bus specification. The I2C component is compatible with other third-party slave and master devices.

Note: This version of the component datasheet covers both the fixed hardware I2C block and the UDB version.

Features

• Master only
• 8 to 32 data bits per sample
• 16-, 32-, 48-, or 64-bit word select period
• Data rate up to 96 kHz with 64-bit word select period: 6.144 MHz
• Tx and Rx FIFO interrupts
• DMA support
• Independent left and right channel FIFOs or interleaved stereo FIFOs
• Independent enable of Rx and Tx

General Description

The Integrated Inter-IC Sound Bus (I2S) is a serial bus interface standard used for connecting digital audio devices together. The specification is from Philips® Semiconductor (I2S bus specification; February 1986, revised June 5, 1996).

PSoC Creator I2S Component Video

Required Software: PSoC Creator v1.0 Beta 5 and above

• USB Full Speed device interface driver
• Support for interrupt, control, bulk, and isochronous transfer types
• Runtime support for descriptor set selection
• Optional USB string descriptors
• Optional USB HID class support
• Optional Bootloader support
• Optional Audio class support
• Optional MIDI devices support
• Optional CDC class support

General Description

The USBFS component provides a USB full-speed Chapter 9 compliant device framework. It provides a low-level driver for the control endpoint that decodes and dispatches requests from the USB host. Additionally, this component provides a USBFS customizer to make it easy to construct your descriptor.   

Required Software: PSoC Creator v1.0 Beta 5 and above

PSoC Creator USB FS Component Video

• 2 to 64 bits PRS sequence length
• Time Division Multiplexing mode
• Serial output bit stream
• Continuous or single-step run modes
• Standard or custom polynomial
• Standard or custom seed value
• Enable input provides synchronized operation with other components
• Computed pseudo random number can be read directly from the Linear Feedback Shift Register (LFSR)

General Description

The Pseudo Random Sequence (PRS) component uses an LFSR to generate a pseudo random sequence, which outputs a pseudo random bit stream. The LFSR is of the Galois form (sometimes known as the modular form) and uses the provided maximal code length, or period. The PRS component runs continuously after starting as long as the Enable Input is held high. The PRS number generator can be started with any valid seed value other than 0.

Required Software: PSoC Creator v1.0 Beta 5 and above

• 8- or 16-bit resolution
• Multiple pulse width output modes
• Configurable trigger
• Configurable capture
• Configurable hardware/software enable
• Configurable dead band
• Multiple configurable kill modes
• Customized configuration tool

General Description

The PWM component provides compare outputs to generate single or continuous timing and control signals in hardware. The PWM is designed to provide an easy method of generating complex real-time events accurately with minimal CPU intervention. PWM features may be combined with other analog and digital components to create custom peripherals.

Required Software: PSoC Creator v1.0 Beta 5 and above

• Available for PSoC 5 devices only (For PSoC 3 and PSoC 5LP devices, use the Segment LCD version 3.10 component)
• 2 to 768 pixels or symbols
• 1/3, 1/4, and 1/5 bias supported
• 10- to 150-Hz refresh rate
• Integrated bias generation between 2.0 V and 5.2 V with up to 128 digitally controlled bias levels for dynamic contrast control
• Supports both type A (standard) and type B (low power) waveforms
• Pixel state of the display may be inverted for negative image
• 256 bytes of display memory (frame buffer)
• User-defined pixel or symbol map with optional 7-, 14-, or 16-segment character; 5x7 or 5x8 dot matrix; and bar graph calculation routines

General Description

The Segment Display (Seg_Display) component can directly drive 3.3-V and 5.0-V LCD glass at multiplex ratios up to 16x. This component provides an easy method of configuring the PSoC device to drive your custom or standard glass.

PSoC® 3 and PSoC 5LP (hereafter referred to as PSoC) are more than just microcontrollers. With PSoC you can integrate the functions of a microcontroller, complex programmable logic device (CPLD) and high-performance analog with unmatched flexibility. This saves cost, board space, power and development time.

This application note introduces the PLDs in the PSoC Universal Digital Block (UDB), and then teaches how to use them by creating PSoC Creator components. It is an effective first step in porting complex programmable logic device (CPLD) functionality to PSoC. After reading this application note, you should be familiar with PSoC PLDs, and be able to create your own custom Verilog-based components using PSoC Creator™.

* Refer to Migrating CY8CKIT-001 DVK project to CY8CKIT 030/ 050.

Notes:

1. Click on AN84741 - PSoC® 5 to PSoC 5LP Migration Guide to learn differences between PSoC 5 and PSoC 5LP.
2. For PSoC 5 project and related document, please download file AN82250_Archive.zip.

Projects associated with this application note can be downloaded from the 'Related Files' section below. For your convenience, we have provided projects that are compatible with the two most recent versions of PSoC Creator:

• AN82250.zip is used with PSoC Creator 2.1 SP1
• AN82250_Archive.zip is used with PSoC Creator 2.1/2.0

The project’s default settings may not be compatible with your device or kit, and you may need to change your project settings. For more information, see:

• 9-bit address mode with hardware address detection
• Baud rates from 110 to 921600 bps or arbitrary up to 4 Mbps
• RX and TX buffers = 4 to 65535
• Detection of Framing, Parity, and Overrun errors
• Full Duplex, Half Duplex, TX only, and RX only optimized hardware
• Two out of three voting per bit
• Break signal generation and detection
• 8x or 16x oversampling

General Description

The UART provides asynchronous communications commonly referred to as RS232 or RS485. The UART component can be configured for Full Duplex, Half Duplex, RX only, or TX only versions. All versions provide the same basic functionality. They differ only in the amount of resources used.

Required Software: PSoC Creator v1.0 Beta 5 and above

• Voltage output ranges: 1.020-V and 4.080-V full scale
• Software or clock driven output strobe
• Data source can be CPU, DMA, or Digital components

General Description

The VDAC8 component is an 8-bit voltage output Digital to Analog Converter (DAC). The output range can be from 0 to 1.020 V (4 mV/bit) or from 0 to 4.08 V (16 mV/bit). The VDAC8 can be controlled by hardware, software, or a combination of both hardware and software.

Required Software: PSoC Creator v1.0 Beta 5 and above

• Support for up to 16 PWM controlled, 4-wire brushless DC fans
• Individual or banked PWM outputs with tachometer inputs
• Supports 25 kHz, 50 kHz or user-specified PWM frequencies
• Supports fan speeds up to 25,000 RPM
• Supports 4-pole and 6-pole motors
• Supports fan stall / rotor lock detection on all fans
• Supports firmware controlled or hardware controlled fan speed regulation
• Customizable alert pin for fan fault reporting

General Description

The Fan Controller component enables designers to quickly and easily develop fan controller solutions using PSoC. The component is a system-level solution that encapsulates all necessary hardware blocks including PWMs, tachometer input capture timer, control registers, status registers and a DMA controller reducing development time and effort.

The component is customizable through a graphical user interface enabling designers to enter fan electromechanical parameters such as duty cycle-to-RPM mapping and physical fan bank organization. Performance parameters including PWM frequency and resolution as well as open or closed loop control methodology can be configured through the same user interface. Once the system parameters are entered, the component delivers the most optimal implementation saving resources within PSoC to enable integration of other thermal management and system management functionality. Easy-to-use APIs are provided to enable firmware developers to get up and running quickly.

Required Software: PSoC Creator 2.0 Component Pack 3 and above

PSoC Creator Fan Controller Component Video

Features

• Full LIN 2.1 or 2.0 Slave Node implementation
• Supports compliance with SAE J2602-1 specification
• Automatic baud rate synchronization
• Fully implements a Diagnostic Class I Slave Node
• Full transport layer support
• Automatic detection of bus inactivity
• Full error detection
• Automatic configuration services handling
• Customizer for fast and easy configuration
• Import of *.ncf/*.ldf files and *.ncf file export
• Editor for *.ncf/*.ldf files with syntax checking

General Description

The LIN Slave component implements a LIN 2.1 slave node on PSoC 3 and PSoC 5 devices. Options for LIN 2.0 or SAE J2602-1 compliance are also available. This component consists of the hardware blocks necessary to communicate on the LIN bus, and an API to allow the application code to easily interact with the LIN bus communication. The component provides an API that conforms to the API specified by the LIN 2.1 Specification.

Required Software: PSoC Creator v1.0 Beta 5 and above

• CAN2.0 A/B protocol implementation, ISO 11898-1 compliant
• Programmable bit rate up to 1 Mbps @ 8 MHz (BUS_CLK)
• Two or three wire interface to external transceiver (Tx, Rx, and Tx Enable)
• Driver provided and supported by Vector

General Description

The Vector CANbedded environment consists of a number of adaptive source code components that cover the basic communication and diagnostic requirements in automotive applications.

The Vector CANbedded software suite is customer specific and its operation will vary according to application and OEM. This component for the Vector CANbedded suite is written to generically support the CANbedded structure regardless of the flavor of the particular OEM application. 

• 3- to 16-bit data width
• 4 SPI modes
• Bit Rate up to 5 Mbps

General Description

The SPI Slave provides an industry-standard, 4-wire slave SPI interface. It can also provide a 3-wire (bidirectional) SPI interface. Both interfaces support all four SPI operating modes, allowing communication with any SPI master device. In addition to the standard 8-bit word length, the SPI Slave supports a configurable 3- to 16-bit word length for communicating with nonstandard SPI word lengths.

Required Software: PSoC Creator v1.0 Beta 5 and above

• 1 to 61 pixels or symbols
• 10- to 150-Hz refresh rate
• User-defined pixel or symbol map with optional 7-segment, 14-segment, 16-segment and bar graph calculation routines
• Direct drive static (one common) LCDs

General Description

The Static Segment LCD (LCD_SegStatic) component can directly drive 3.3-V and 5.0-V LCD glass. This component provides an easy method of configuring the PSoC device for your custom or standard glass.

Each LCD pixel/symbol may be either on or off. The Static Segment LCD component also provides advanced support to simplify the following types of display structures within the glass:

• 7-Segment numeral
• 14-Segment alphanumeric
• 16-Segment alphanumeric
• 1- to 255-element bar graphs

Required Software: PSoC Creator v1.0 Beta 5 and above

• Adaptable for majority of negative temperature coefficient (NTC) thermistors
• Look-Up-Table (LUT) or equation implementation methods
• Selectable reference resistor, based on thermistor value
• Selectable temperature range
• Selectable calculation resolution for LUT method

General Description

The Thermistor Calculator component calculates the temperature based on a provided voltage measured from a thermistor. The component is adaptable to most NTC thermistors. It calculates the Steinhart-Hart equation coefficients based on the temperature range and corresponding user-provided reference resistances. The component provides API functions that use the generated coefficients to return the temperature value based on measured voltage values.

This component doesn't use an ADC or AMUX inside and thus requires those components to be placed separately in your projects.

Required Software: PSoC Creator 2.1 Component Pack 4 and above.
 

• Supports B, E, J, K, N, R, S, and T Type Thermocouples
• Provides functions for thermo-emf to temperature and temperature to voltage conversions
• Displays Calculation Error Vs. Temperature graph

General Description

In thermocouple temperature measurement, the thermocouple temperature is calculated based on the measured thermo-emf voltage. The voltage to temperature conversion is characterized by the National Institute of Standards and Technology (NIST), and NIST provides tables and polynomial coefficients for thermo-emf to temperature conversion. The NIST tables and polynomial coefficients can be found in the following link:

http://srdata.nist.gov/its90/download/download.html

Thermocouple temperature measurement also involves measuring the thermocouple reference junction temperature and converting it into a voltage. The Thermocouple Calculator component simplifies the thermocouple temperature measurement process by providing APIs for thermo-emf to temperature conversion and vice versa for all thermocouple types mentioned above, using polynomials generated at compile time. The thermocouple component evaluates the polynomial in an efficient way to reduce computation time.

Required Software: PSoC Creator 2.1 Component Pack 4 and above.

• Fixed-function (FF) and universal digital block (UDB) implementations
• 8-, 16-, 24-, or 32-bit timer
• Optional capture input
• Enable, trigger, and reset inputs, for synchronizing with other components
• Continuous or one shot run modes

Symbol Diagram

General Description

The Timer component provides a method to measure intervals. It can implement a basic timer function and offers advanced features such as capture with capture counter and interrupt/DMA generation.

Required Software: PSoC Creator v1.0 Beta 5 and above

*Refer to Migrating CY8CKIT-001 DVK project to CY8CKIT 030/ 050.

1. Click on AN84741 - PSoC® 5 to PSoC 5LP Migration Guide to learn differences between PSoC 5 and PSoC 5LP.
2. Click on AN77835 - PSoC® 3 to PSoC 5LP Migration Guide to learn differences between PSoC 3 and PSoC 5LP.
3. For PSoC 5 project and related document, please download file AN77900_Archive.zip.

Projects associated with this application note can be downloaded from the 'Related Files' section below. For your convenience, we have provided projects that are compatible with the two most recent versions of PSoC Creator:

• AN77900.zip is used with PSoC Creator 2.1 SP1
• AN77900_Archive.zip is used with PSoC Creator 2.1/2.0

The project’s default settings may not be compatible with your device or kit, and you may need to change your project settings. For more information, see:

• Single-ended mixer
• Continuous-time up mixing:
  • Input frequencies up to 500 kHz
  • Sample clock up to 1 MHz
• Discrete-time, sample-and-hold down mixing:
  • Input frequencies up to 14 MHz
  • Sample clock up to 4 MHz
• Adjustable power settings
• Selectable reference voltage

General Description

The Mixer component provides a single-ended modulator. The Mixer component can be used for frequency conversion of an input signal using a fixed Local Oscillator (LO) signal as the sampling clock. The manipulations of signal frequencies that a mixer performs can be used to move signals between frequency bands or to encode and decode signals. A mixer can be used to convert signal power at one frequency into power at another frequency to make signal processing easier, typically shifting higher frequencies to baseband.

Required Software: PSoC Creator v1.0 Beta 5 and above

• Two operating modes: Sample and Hold, Track and Hold
• Four power mode settings

General Description

The Sample/Track and Hold component provides a way to sample a continuously varying analog signal and to hold or freeze its value for a finite period of time. It supports both Track and Hold and Sample and Hold functions, which can be selected in the customizer.

Features

• Follower or Opamp configuration
• Unity gain bandwidth > 3.0 MHz
• Input offset voltage 2.0 mV max
• Rail-to-rail inputs and output
• Output direct low resistance connection to pin
• 25 mA output current
• Programmable power and bandwidth
• Internal connection for follower (saves pin)

General Description

The Opamp component provides a low-voltage, low-power operational amplifier and may be internally connected as a voltage follower. The inputs and output may be connected to internal routing nodes, directly to pins, or a combination of internal and external signals. The Opamp is suitable for interfacing with high-impedance sensors, buffering the output of voltage DACs, driving up to 25 mA; and building active filters in any standard topology.   

Required Software: PSoC Creator v1.0 Beta 5 and above 

• Three ranges 2040 μA, 255 μA, and 31.875 μA
• Current sink or source selectable
• Software or clock driven output strobe
• Data source may be CPU, DMA, or Digital components

General Description

The IDAC8 component is an 8-bit current output DAC (Digital to Analog Converter). The output can source or sink current in three ranges. The IDAC8 can be controlled by hardware, software, or by a combination of both hardware and software.

Required Software: PSoC Creator v1.0 Beta 5 and above

• Wakes up devices from low-power modes: Alternate Active and Sleep
• Contains configurable option for issuing interrupt
• Generates periodic interrupts while the device is in Active mode
• Supports twelve discrete intervals: 2, 4, 8, 16, 32, 64, 128, 256, 512, 1024, 2048, and 4096 ms
   

The Sleep Timer component can be used to wake the device from Alternate Active and Sleep modes at a configurable interval. It can also be configured to issue an interrupt at a configurable interval. For PSoC 5 architectures, an interrupt is required for the CPU to wake up.

For PSoC 5, the supported intervals are restricted to: 4, 8, 16, 32, 64, 128 or 256 ms. Refer to the CyPmSleep() function description in the System Reference Guide for details about this restriction. The PSoC 5LP device supports the full set of intervals.

Required Software: PSoC Creator v1.0 Beta 5 and above

• Monitor up to 32 voltage inputs
• User-defined over and under voltage limits
• Simply outputs a good/bad status result

General Description

The Voltage Fault Detector component provides a simple way to monitor up to 32 voltage inputs against user-defined over and under voltage limits without using the ADC and without having to write any firmware. The component simply outputs a good/bad status result (“power good” or pgood[x]) for each voltage being monitored.

The component operates entirely in hardware without any intervention from PSoC’s CPU core resulting in known, fixed fault detection latency.

Note: This component supports PSoC 3 and PSoC 5LP devices only.

• Supports sequencing and monitoring of up to 32 power converter rails
• Supports power converter circuits with logic-level enable inputs and logic-level power good (pgood) status outputs
• Autonomous (standalone) or host driven operation
• Sequence order, timing and inter-rail dependencies can be configured through an intuitive, easy-to-use graphical configuration GUI

General Description

The Voltage Sequencer component provides a simple way to define power-up and power-down sequencing of up to 32 power converters to meet user-defined system requirements. Once the sequencing requirements have been entered into the easy-to-use graphical configuration GUI, the component will automatically take care of the sequencing implementation without requiring any firmware development by the user.

Features

• Gain steps from 1 to 50
• High input impedance
• Selectable input reference
• Adjustable power settings

General Description

The PGA implements an opamp-based, non-inverting amplifier with user-programmable gain. This amplifier has high input impedance, wide bandwidth and selectable input voltage reference. It is derived from the switched capacitor/continuous time (SC/CT) block.

The gain can be between 1 (0 dB) and 50 (+34 dB). The gain can be selected using the configuration window or changed at run time using the provided API. The maximum bandwidth is limited by the gain-bandwidth product of the opamp and is reduced as the gain is increased. The input of the PGA operates from rail to rail, but the maximum input swing (difference between Vin and Vref) is limited to V_DDA/Gain. The output of the PGA is class A, and is rail to rail for sufficiently high load resistance.

Required Software: PSoC Creator v1.0 Beta 5 and above

• 512 B to 2 KB EEPROM memory
• 1,000,000 cycles, 20-year retention
• Read/Write 1 byte at a time
• Program 16 bytes (a row) at a time

General Description

The EEPROM component provides a set of APIs to erase and write data to nonvolatile EEPROM memory. The term write implies that it will erase and then program in one operation.

An EEPROM memory in PSoC devices is organized in arrays. PSoC 3 and PSoC 5 devices offer an EEPROM array of size 512 bytes, 1 KB or 2 KB depending on the device. This array is divided into rows of size 16 bytes each. The API set of the EEPROM component supports write operations at the byte and row levels and erase operation at the sector level. A sector in EEPROM has 64 rows.

Required Software: PSoC Creator v1.0 Beta 5 and above

• Up to four Secure Digital (SD) cards in SPI mode
• FAT12/16 or FAT32 format
• Optional integration with an Operating System (OS)
• Optional Long File Name (LFN) handling

General Description

The emFile component provides an interface to SD cards formatted with a FAT file system. The SD card specification includes multiple hardware interface options for communication with an SD card. This component uses the SPI interface method for communication. Up to four independent SPI interfaces can be used for communication with one SD card each. Both FAT12/16 and FAT32 file system formats are supported. This component provides the physical interface to the SD card and works with the emFile library licensed from SEGGER Microcontroller to provide a library of functions to manipulate a FAT file system.

Required Software

Firmware Installation:  The firmware files for this component are not distributed with PSoC Creator and can be downloaded below. Please refer to the component datasheet for installation instructions.

IMPORTANT NOTICE REGARDING LONG FILE NAMES:  If you configure the software to support long file names on FAT file systems, you should review the information at http://www.microsoft.com/about/legal/en/us/IntellectualProperty/IPLicensing/Programs/FATFileSystem.aspx to determine whether a license from Microsoft is required. Cypress and its suppliers grant no license under Microsoft's intellectual property rights and assume no liability for any use of the software without obtaining any license that may be required.

PSoC^® Creator^™ emFile Component Video

• Industry standard NXP® I2C bus interface
• Emulates common I2C EEPROM interface
• Only two pins (SDA and SCL) required to interface to I2C bus
• Standard data rates of 50/100/400/1000 kbps
• High level APIs require minimal user programming
• Supports one or two address decoding with independent memory buffers
• Memory buffers provide configurable Read/Write and Read Only regions

General Description

The EZI2C Slave component implements an I2C register-based slave device. It is compatible with I2C Standard-mode, Fast-mode, and Fast-mode Plus devices as defined in the NXP I2C-bus specification.The master initiates all communication on the I2C bus and supplies the clock for all slave devices. The EZI2C Slave supports standard data rates up to 1000 kbps and is compatible with multiple devices on the same bus.
 

Required Software: PSoC Creator v1.0 Beta 5 and above 

• Up to 8-bit Status Register
• Interrupt support

General Description

The Status Register allows the firmware to read digital signals.

Required Software: PSoC Creator v1.0 Beta 5 and above

The PSoC 3 device supports eight hardware program address breakpoints and one data address watch point.

PSoC 5 and PSoC 5LP support six hardware program address breakpoints and four data address watch points.

However, PSoC Creator reserves one breakpoint to use it to perform operations such as step, jump, and run-to-cursor. After all the hardware breakpoints are exhausted, PSoC Creator automatically uses software breakpoints for all future breakpoints, which is implemented on the host PC side.

A breakpoint is used to cause the debugger to halt the next time its location is reached. If you set a hardware breakpoint, a red dot appears in the left margin of the source/disassembly corresponding to the line in which the breakpoint is assigned. If the number of hardware breakpoints has been exhausted, and if you attempt to add another, the debugger displays an information message to announce that the maximum number of breakpoints has been reached. You will be prompted to place a software breakpoint instead. Software breakpoint is indicated by a green dot in the left margin of the source/disassembly corresponding to the line in which the breakpoint is assigned.

A watchpoint is used to set a breakpoint on a place in data memory as opposed to the standard breakpoint, which is used for program memory. Instead of setting the breakpoint on a line of code, you set it on a variable in the code. This watchpoint is hit each time the address that the variable is located at is read, written, or accessed based on your selection for Break on.

Documentation

The following application notes guide you through the process of component development:

1. AN82250 - PSoC® 3 and PSoC 5LP Implementing Programmable Logic Designs with Verilog
2. AN82156 - PSoC® 3 and PSoC 5LP - Designing PSoC Creator™ Components With UDB Datapaths

The Component Author Guide included with PSoC Creator provides instructions and information on how to create components for PSoC Creator. To open the component guide from PSoC Creator, select Help > Documentation > Component Author Guide.
To download from the website, browse to: PSoC Creator Component Author Guide

The Component Development Kit installed with PSoC Creator includes additional documents. To open from your desktop, select
Start > All Programs > Cypress > PSoC Creator > Component Development Kit.
 

The Component Development kit contains the following:
 

• Component Author Guide: Provides instructions and information on how to create components for PSoC Creator.
• Customizer API Reference Guide: Provides API reference information for PSoC Creator Extensions code.
• Datapath Configuration Tool: Used to edit datapath instance configurations in a Verilog implementation of a PSoC component.
• Tuner API Reference Guide: Provides API reference information for PSoC Creator Tuner code.
• Warp Verilog Reference Guide: The Warp synthesis tool is a Verilog compiler used by PSoC Creator to design with PSoC devices.
   

Training
 

Cypress also has a series of instructional videos for component development.
 

Basic Component Trainings

PSoC Creator 110: Schematic Components
PSoC Creator 111: Component Parameters
PSoC Creator 112: Introduction to Component API Generation
PSoC Creator 113: PLD Based Verilog Components
 

Advanced Component Trainings

PSoC Creator 210: Intro to Datapath Components
PSoC Creator 211: Datapath Computation
PSoC Creator 212: Datapath FIFOs
PSoC Creator 213: Multi-Byte Datapath Components
PSoC Creator 214: Datapath API Generation

Introduction

Have you maxed out your CPU bandwidth? PSoC 3 and PSoC 5LP UDBs can lighten the load on your CPU by creating intelligent custom peripherals. The datapaths in those UDBs can be used to create sophisticated multiprocessor-based designs.

Many PSoC customers have experience writing HDL code for CPLDs or FPGAs. PSoC 3 and PSoC 5LP support Verilog for PLDs. However, PSoC 3 and PSoC 5LP PLDs are smaller than full-fledged CPLDs or FPGAs, and many designs are too large for PSoC 3 and PSoC 5LP. PSoC’s unique datapath modules remove this obstacle by integrating one or more small 8-bit processors into PLD-based designs.

1. Click on AN84741 - PSoC® 5 to PSoC 5LP Migration Guide to learn differences between PSoC 5 and PSoC 5LP.
2. Click on AN77835 - PSoC® 3 to PSoC 5LP Migration Guide to learn differences between PSoC 3 and PSoC 5LP.
3. For PSoC 5 project and related document, please download file AN82156_Archive.zip.

Projects associated with this application note can be downloaded from the 'Related Files' section below. For your convenience, we have provided projects that are compatible with the two most recent versions of PSoC Creator:

• AN82156.zip is used with PSoC Creator 2.1 SP1
• AN82156_Archive.zip is used with PSoC Creator 2.1/2.0

The project’s default settings may not be compatible with your device or kit, and you may need to change your project settings. For more information, see:

The following table provides the list of devices, the supported Creator version, Development kit and Compiler for this application note project:

*Refer to Migrating CY8CKIT-001 DVK project to CY8CKIT 030/ 050.

1. Click on AN84741 - PSoC® 5 to PSoC 5LP Migration Guide to learn differences between PSoC 5 and PSoC 5LP.
2. Click on AN77835 - PSoC® 3 to PSoC 5LP Migration Guide to learn differences between PSoC 3 and PSoC 5LP.
3. For PSoC 5 project and related document, please download file AN58726_Archive.zip.

Projects associated with this application note can be downloaded from the ‘Related Files’ section below. For your convenience, we have provided projects that are compatible with the two most recent versions of PSoC Creator:

• AN58726.zip is used with PSoC Creator 2.1 SP1
• AN58726_Archive.zip is used with PSoC Creator 2.1/2.0

The project’s default settings may not be compatible with your device or kit, and you may need to change your project settings. For more information, see:

• Eliminates unwanted oscillations on digital input lines
   

General Description

Mechanical switches and relays tend to make and break connections for a finite time before settling down to a stable state. Within this settling time, the digital circuit can see multiple transitions as the switch contacts bounce between make or break conditions.

The Debouncer component takes an input signal from a bouncing contact and generates a clean output for digital circuits. The component will not pass the signal to the output until the predetermined period of time when the switch bouncing settles down. In this way, the circuit will respond to only one pulse generation performed by the pressing or releasing of the switch and not several state transitions caused by contact bouncing.

For more details on switch debouncing please see application note AN60024.

Required Software: PSoC Creator 2.1 Component Pack 4 and above.

Below are some of videos demonstrating  how to impliment bulk transfers and vendor commands which are discussed in this application note.

The following table indicates the PSoC devices, PSoC Creator versions, compilers, and development kits that will work with this application note project:

*Refer to Migrating CY8CKIT-001 DVK project to CY8CKIT 030/ 050. 

Notes:

1. Click on AN84741 - PSoC® 5 to PSoC 5LP Migration Guide to learn differences between PSoC 5 and PSoC 5LP.
2. For PSoC 5 project and related document, please download file AN56377_Archive.zip.

Projects associated with this application note can be downloaded from the ‘Related Files’ section below. For your convenience, we have provided projects that are compatible with the two most recent versions of PSoC Creator:

• AN56377.zip is used with PSoC Creator 2.1 SP1
• AN56377_Archive.zip is used with PSoC Creator 2.1/2.0

The project’s default settings may not be compatible with your device or kit, and you may need to change your project settings. For more information, see:
Information on application note projects compatible with PSoC Creator 1.0 SP2
PSoC® 3 and PSoC 5 AN/CE project file naming convention and usage

If instead of PSoC 3 you want to migrate a PSoC 5 design to PSoC 5LP, please see AN84741, PSoC 5 to PSoC 5LP Migration Guide, instead of this application note.

The PSoC 3 and PSoC 5LP devices are designed for easy migration from PSoC 3 to PSoC 5LP. Although there are some differences such as the CPU cores, the programmable analog, programmable digital, programmable routing, pin functions, and other features are quite similar. Furthermore, the PSoC Creator IDE handles a lot of the migration issues for you, automatically. Often, migrating a PSoC Creator design is as simple as specifying a new part then rebuilding the project.

If, instead of PSoC 5, you want to migrate from a PSoC 3 design to PSoC 5LP, see AN77835, PSoC 3 to PSoC 5LP Migration Guide.

The PSoC 5 and PSoC 5LP devices are designed for easy migration from PSoC 5 to PSoC 5LP. Although there are some differences such as additional features in PSoC 5LP, the programmable analog, programmable digital, programmable routing, pin functions, and other features are quite similar. Furthermore, the PSoC Creator IDE handles a lot of the migration issues for you, automatically. Often, migrating a PSoC Creator design is as simple as specifying a new part and then rebuilding the project.

There are generally two types of PLC systems: high-bandwidth (video, audio, and so on) and low-bandwidth (command and control). This application note describes how to implement a low-bandwidth, half-duplex PLC solution with the PSoC 5LP family of devices.

The following table indicates the PSoC devices, PSoC Creator versions, compilers, and development kits that will work with this application note project:

1. Click on AN84741 - PSoC® 5 to PSoC 5LP Migration Guide to learn differences between PSoC 5 and PSoC 5LP.
2. For PSoC 5 project and related document, please download file AN76458_Archive.zip.

Projects associated with this application note can be downloaded from the 'Related Files' section below. For your convenience, we have provided projects that are compatible with the two most recent versions of PSoC Creator:

• AN76458.zip is used with PSoC 5LP and PSoC Creator 2.1 SP1
• AN76458_Archive.zip is used with PSoC 5 and PSoC Creator 2.1/2.1 SP1.

The project’s default settings may not be compatible with your device or kit, and you may need to change your project settings. For more information, see:

Features Works with most adjustable DC-DC converters or regulators including LDOs, switchers and modules Supports up to 24 DC-DC converters 8 to 10-bit resolution PWM pseudo-DAC outputs Supports real-time, closed-loop active trimming when used in conjunction with the Power Monitor component Built-in support for margining	Symbol Diagram
General Description The Trim and Margin component provides a simple way to adjust and control the output voltage of up to 24 DC-DC converters to meet system power supply requirements.

Required Software: PSoC Creator v1.0 Beta 5 and above 

• Selectable conversion gain
• Selectable corner frequency
• Compensated for capacitive input sources
• Adjustable power settings
• Selectable input reference voltage

General Description

The Trans-Impedance Amplifier (TIA) component provides an opamp-based current to voltage conversion amplifier with resistive gain and user-selected bandwidth. It is derived from the SC/CT block. 

Required Software: PSoC Creator v1.0 Beta 5 and above

• Adjustable shift register size: 2 to 32 bits
• Simultaneous shift in and shift out
• Right shift or left shift
• Reset input forces shift register to all 0s
• Shift register value readable by CPU or DMA
• Shift register value writable by CPU or DMA 

The Shift Register (ShiftReg) component provides synchronous shifting of data into and out of a parallel register. The parallel register can be read or written to by the CPU or DMA. The Shift Register component provides universal functionality similar to standard 74xxx series logic shift registers including: 74164, 74165, 74166, 74194, 74299, 74595 and 74597. In most applications the Shift Register component will be used in conjunction with other components and logic to create higher level application-specific functionality, such as a counter to count the number of bits shifted.   

Required Software: PSoC Creator v1.0 Beta 5 and above

• Supports 4-wire resistive touchscreen interface
• Supports the Delta Sigma Converter for both the PSoC 3 and PSoC 5 devices
• Supports the ADC Successive Approximation Register for PSoC 5 devices

This resistive touchscreen component is used to interface with a 4-wire resistive touch screen. The component provides a method to integrate and configure the resistive touch elements of a touchscreen with the emWin Graphics library. It integrates hardware-dependent functions that are called by the touchscreen driver supplied with emWin when polling the touch panel.

• Adjustable counter size: 8, 16, or 32 bits
• Counter resolution of 1x, 2x, or 4x the frequency of the A and B inputs, for more accurate determination of position or speed
• Optional index input to determine absolute position
• Optional glitch filtering to reduce the impact of system-generated noise on the inputs

General Description

The Quadrature Decoder (QuadDec) component provides the ability to count transitions on a pair of digital signals. The signals are typically provided by a speed/position feedback system mounted on a motor or trackball.

The signals – typically called A and B – are positioned 90° out-of-phase, which results in a Gray code output. A Gray code is a sequence where only one bit changes on each count. This is essential to avoid glitches. It also allows detection of direction and relative position. A third optional signal, named index, is used as a reference to establish an absolute position once per rotation.

Required Software: PSoC Creator v1.0 Beta 5 and above

• Constant digital high or low signal

General Description

The Logic High and Logic Low components provide constant digital values and are used to hard code digital inputs. Hard coding of static inputs results in optimized resource usage and is the preferred method of providing a constant input state.

Required Software: PSoC Creator v1.0 Beta 5 and above

• Industry standard logic gates
• Configurable number of inputs up to 8
• Optional array of gates

General Description

Logic gates provide basic boolean operations. The output of a logic gate is a boolean combinatorial function of the inputs. There are seven basic logic gates: AND, OR, Inverter (NOT), NAND, NOR, XOR, and XNOR.

Required Software: PSoC Creator v1.0 Beta 5 and above

• Digital Multiplexer
• Digital De-Multiplexer
• Up to 16 channels>

General Description

The Multiplexer component is used to select 1 of n inputs while the De-Multiplexer component is used to route 1 signal to n outputs.

The Multiplexer component implements a 2-16 input mux providing a single output, based on hardware control signals. The De-Multiplexer component implements a 2-16 output demux from a single input, based on hardware control signals. Only 1 input or output connection may be made at a time.

Required Software: PSoC Creator v1.0 Beta 5 and above

• 1 to 5 Inputs
• 1 to 8 Outputs
• Configuration Tool
• Optionally Registered Outputs

General Description

You can set up the Lookup Table (LUT) component to perform any logic function with up to five inputs and eight outputs. This is done by generating logic equations that are realized in the UDB PLDs. Optionally, the outputs can be registered. These registers are implemented in PLD macrocells. All macrocell flip-flops are initialized to a 0 value at power up and after any reset of the device.

Required Software: PSoC Creator v1.0 Beta 5 and above

• 8 or 16 bit interface to Graphic LCD Controller
• Compatible with many graphic controller devices
• Interfaces with SEGGER emWin graphics library
• Performs Read and write transaction
• 2-255 cycles for Read Low Pulse Width
• 1-255 cycles for Read High Pulse Width
• Implements typical i8080 interface

The Graphic LCD Interface (GraphicLCDIntf) component provides the interface to a graphic LCD controller and driver device. These devices are commonly integrated into an LCD panel. The interface to these devices is commonly referred to as an i8080 interface. This is a reference to the historic parallel bus interface protocol of the Intel 8080 microprocessor.    

Required Software: PSoC Creator v1.0 Beta 5 and above

• Fully programmable screen size support up to HVGA resolution including:
  • QVGA (320x240) @ 60 Hz 16 bpp
  • WQVGA (480x272) @ 60 Hz 16 bpp
  • HVGA (480x320) @ 60 Hz 16 bpp
• Supports virtual screen operation
• Interfaces with SEGGER emWin graphics library
•  Performs read and write transactions during the blanking intervals
• Generation of continuous timing signals to the panel without CPU intervention
• Supports up to a 23-bit address and a 16-bit data async SRAM device used as externally provided frame buffer
• Generates a selectable interrupt pulse at the entry and exit of the horizontal and vertical blanking intervals

General Description

The Graphic LCD Controller (GraphicLCDCtrl) component provides the interface to an LCD panel that has an LCD driver, but not an LCD controller. This type of panel does not include a frame buffer. The frame buffer must be provided externally.

This component also interfaces to an externally provided frame buffer implemented using a 16-bit wide async SRAM device.

Required Software: PSoC Creator v1.0 Beta 5 and above

• Up to 8-bit Control Register

General Description

The Control Register allows the firmware to output digital signals.

Required Software: PSoC Creator v1.0 Beta 5 and above

• Voltage references and supplies
• Multiple options
• Bandgap principle to achieve timer, temperature, and voltage stability

General Description

This description applies to PSoC 3 and PSoC 5 devices. The Voltage Reference (Vref) component provides one of several voltage reference outputs. The 1.024 V and 0.256 V outputs are temperature compensated using the bandgap principle to achieve excellent stability.

Required Software: PSoC Creator v1.0 Beta 5 and above