Cypress.com: Documentation http://www.cypress.com/?app=search&searchType=advanced&id%3D3522 Add P1[4] for R<sub>b</sub> in CY8C21234B SmartSense™ Version 1.30 - KBA83339 http://www.cypress.com/?rID=62400 Answer: This is a defect in PSoC Designer™ version 5.2 Service Pack 1(and earlier). For the SmartSense version 1.30, the CapSense® configuration wizard allows only one configuration for Rb, that is, to connect it to P1[1]. But since P1[1] is used as SCL (ISSP clock) line, it is not always possible to use it for Rb.

The defect will be fixed in the future versions of PSoC Designer but for the current version the following workaround can be used:

  1. Download the attached “SmartSense.asm”.
  2. Copy this file (and replace the old SmartSense.asm) to the following folder:
    C:\Program Files\Cypress\PSoC Designer\5.2\Common\CypressSemiDeviceEditor\Data\Stdum\SmartSense\Ver_1_30\CY8C21034

It should be noted that the configuration wizard will still show the Rb connection to P1[1]. But the hardware connection for Rb gets modified when the API SmartSense_Start() is called in “main.c” of the project. This workaround modifies ACE00CR2, ACE00CR1, ALT_CR0, CMP_GO_EN, PRT1DM0, PRT1DM1, and PRT1DM2 registers in the SmartSense_Start() API. The details of these registers can be found in the Technical Reference Manual (TRM) for CY8C21x34.

]]> Thu, 27 Dec 2012 02:46:53 -0600 QTP 111811: SmartSense&trade; Device Family, S4AD-5, Fab4 http://www.cypress.com/?rID=62409 Wed, 20 Jun 2012 02:09:15 -0600 QTP 111808: SmartSense&trade; Device Family, S4AD-5, Fab4 http://www.cypress.com/?rID=62408 Wed, 20 Jun 2012 02:06:58 -0600 CY8C21x34B - IBIS http://www.cypress.com/?rID=61504 The zip file contains following IBIS models

cy8c21234B_27v.ibs
cy8c21234B_33v.ibs
cy8c21234B_5v.ibs
cy8c21334B_27v.ibs
cy8c21334B_33v.ibs
cy8c21334B_5v.ibs
cy8c21434B_32qfn_27v.ibs
cy8c21434B_32qfn_33v.ibs
cy8c21434B_32qfn_5v.ibs
cy8c21534B_27v.ibs
cy8c21534B_33v.ibs
cy8c21534B_5v.ibs
cy8c21634B_32qfn_27v.ibs
cy8c21634B_32qfn_33v.ibs
cy8c21634B_32qfn_5v.ibs

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