Features

• One input to four output buffer/driver
• General-purpose or PCI-X clock buffer
• Buffers all frequencies from DC to 140 MHz
• Output-to-output skew less than 100 ps
• Space-saving 8-pin TSSOP package
• 3.3V operation
• 60 ps typical output-output skew
   

Functional Description

The CY2304NZ is a low-cost buffer designed to distribute high-speed clocks for PCI-X and other applications. The device operates at 3.3V and outputs can run up to 140 MHz.

The CY3672-USB programming kit enables any user with a PC to quickly and easily program Field-programmable Clock Gener­ators. Set-up requires a power connection and either a parallel port or USB port (CY3672-USB) connection directly to the PC.

Using CyClocksRT™ (embedded in CyberClocks software) or CyberClocks Online, users can configure their parts to a given specification and generate the corresponding JEDEC file. In addition, CyClocksRT software provides PPM optimization and power calculations.

The JEDEC file is then loaded into CY3672 software that communicates with the programmer. The CY3672 software has the ability to read and view the EPROM table from a programmed device.

CY3672-USB is the programming base unit only that does not include any socket adapter. Based on the part number that needs to be programmed, the respective socket adapter has to be ordered and purchased separately.

• CY3672-USB Programming Base Module
• Power Adapter:
  • Input: AC 100V to 240V, 0.8A, 50 to 60Hz.
  • Output: DC-12V/2.0A (24W Max)
• 1 USB Cable (Type A to Type B), 1.0M in length
• 1 Parallel Port Cable
• User Manual
• CD-ROM with software and driver files

The following socket adapters support the associated press programming device.

You can order samples of desired devices Online.

Related Documents:

Datasheet: CY3672-USB

Note: This is a programming kit base only. This kit is not designed and intended to be used for device evaluation or testing purposes. Uncompress the CD contents to install the programming software.

This document describes the errors, workaround solution and silicon design fixes for Cypress zero delay clock buffers belonging to the families CY2300/03/04/05/08/09. Details include errata trigger conditions, scope of impact, available workarounds, and silicon revision applicability. Compare this document to the device’s data sheet for a complete functional description.

Answer: Cypress’s CY2305 part family has approximately 5200 transistors or 1300 gates.

Features

• Select one of two differential (LVPECL, LVDS, HCSL, or CML) input pairs to distribute to four LVDS output pairs
• 30-ps maximum output-to-output skew
• 480-ps maximum propagation delay
• 0.11-ps maximum additive RMS phase jitter at 156.25 MHz (12-kHz to 20-MHz offset)
• Up to 1.5-GHz operation
• Output enable and synchronous clock enable functions
• 20-pin thin shrunk small outline package (TSSOP)
• 2.5-V or 3.3-V operating voltage
• Commercial and industrial operating temperature range

Functional Description

The CY2DL1504 is an ultra-low noise, low-skew, low-propagation delay 1:4 differential LVDS fanout buffer targeted to meet the requirements of high-speed clock distribution applications. The CY2DL1504 can select between LVPECL or LVDS input clock pairs using the IN_SEL pin. The synchronous clock enable function ensures glitch-free output transitions during enable and disable periods. The output enable function allows the outputs to be asynchronously driven to a high-impedance state. The device has a fully differential internal architecture that is optimized to achieve low-additive jitter and low-skew at operating frequencies of up to 1.5 GHz.

Features

• Internal digital controlled crystal oscillator (DCXO) for continuous glitch-free operation
• Zero input-output propagation delay
• Low-jitter (35 ps max RMS) outputs
• Low output-to-output skew (200 ps max)
• 4.17 MHz to 166.7 MHz reference input
• Supports industry standard input crystals
• 166.7 MHz outputs
• 5V-tolerant inputs
• Phase-locked loop (PLL) bypass mode
• Dual reference inputs
• For more, see pdf

Functional Description

The CY23FS04-3 is a FailSafe™ zero delay buffer with two reference clock inputs and four phase-aligned outputs. The device provides an optimum solution for applications where continuous operation is required in the event of a primary clock failure. The continuous, glitch-free operation is achieved by using a DCXO, which serves as a redundant clock source in the event of a reference clock failure by maintaining the last frequency and phase information of the reference clock.

• One differential (LVPECL, LVDS, HCSL, or CML) input pair distributed to two LVPECL output pairs
• Translates any single-ended input signal to 3.3 V LVPECL levels with resistor bias on INx# input
• 20-ps maximum output-to-output skew
• 480-ps maximum propagation delay
• 0.15-ps maximum additive RMS phase jitter at 156.25 MHz (12-kHz to 20-MHz offset)
• Up to 1.5-GHz operation
• 8-pin SOIC or 8-pin TSSOP package
• 2.5-V or 3.3-V operating voltage
• Commercial and industrial operating temperature range
   

Functional Description

The CY2DP1502 is an ultra-low noise, low-skew, low-propagation delay 1:2 LVPECL fanout buffer targeted to meet the requirements of high-speed clock distribution applications. The device has a fully differential internal architecture that is optimized to achieve low additive jitter and low skew at operating frequencies of up to 1.5 GHz.    

Features

• Low-voltage operation VDD = 3.3V
• 1:8 fanout
• Operation to 350 MHz
• Single input configurable for LVDS, LVPECL, or LVTTL
• 8 pair of LVPECL outputs
• Drives a 50 ohm load
• Low input capacitance
• Low output skew
• Low propagation delay (tpd = 4 ns, typical)
• Commercial and Industrial temperature ranges
• 38-Pin TSSOP Package
• For more, see pdf
   

Description

The Cypress CY2DP818 fanout buffer features a single LVDS or a single ended LVTTL compatible input and eight LVPECL output pairs.

Designed for data-communications clock management applications, the large fanout from a single input reduces loading on the input clock.

The CY2DP818 is ideal for both level translations from single ended to LVPECL and/or for the distribution of LVPECL based clock signals.

The Cypress CY2DP818 has configurable input functions. The input is user configurable via the InConfig pin for single ended or differential input.

Features

• 10 MHz to 100/133 MHz operating range, compatible with CPU and PCI bus frequencies
• Zero input-output propagation delay
• 60-ps typical cycle-to-cycle jitter (high drive)
• Multiple low skew outputs
  • 85 ps typical output-to-output skew
  • One input drives five outputs (CY2305)
  • One input drives nine outputs, grouped as 4 4 1 (CY2309)
• Compatible with Pentium-based systems
• Test Mode to bypass phase-locked loop (PLL) (CY2309)
• Packages:
  • 8-pin, 150-mil SOIC package (CY2305)
  • 16-pin 150-mil SOIC or 4.4-mm TSSOP (CY2309)
• 3.3-V operation
• Commercial and industrial temperature ranges
   

Functional Description

The CY2309 is a low-cost 3.3-V zero delay buffer designed to distribute high speed clocks and is available in a 16-pin SOIC or TSSOP package. The CY2305 is an 8-pin version of the CY2309. It accepts one reference input, and drives out five low skew clocks. The -1H versions of each device operate at up to 100-/133 MHz frequencies, and have higher drive than the -1 devices. All parts have on-chip PLLs which lock to an input clock on the REF pin. The PLL feedback is on-chip and is obtained from the CLKOUT pad.

Features

• 2.5V or 3.3V operation
• 200-MHz clock support
• LVPECL or LVCMOS/LVTTL clock input
• LVCMOS-/LVTTL-compatible inputs
• 12 clock outputs: drive up to 24 clock lines
• Synchronous Output Enable
• Output three-state control
• 150 ps typical output-to-output skew
• Pin compatible with MPC948, MPC948L, MPC9448
• Available in Commercial and Industrial temp. range
• 32-pin TQFP package
   

Description

The CY29948 is a low-voltage 200-MHz clock distribution buffer with the capability to select either a differential LVPECL or a LVCMOS/LVTTL compatible input clock. The two clock sources can be used to provide for a test clock as well as the primary system clock. All other control inputs are LVCMOS/LVTTL compatible.

Features

• 12–100 MHz (CY7B9930V), or 24–200 MHz (CY7B9940V) input/output operation
• Matched pair output skew < 200 ps
• Zero input-to-output delay
• 10 LVTTL 50% duty-cycle outputs capable of driving 50ω terminated lines
• Commercial temperature range with eight outputs at 200 MHz
• Industrial temperature range with eight outputs at 200 MHz
• 3.3V LVTTL/LV differential (LVPECL), fault-tolerant and hot insertable reference inputs
• Multiply ratios of (1–6, 8, 10, 12)
• Operation up to 12x input frequency
• For more, see pdf

Functional Description

The CY7B9930V and CY7B9940V High-Speed Multifrequency PLL Clock Buffers offer user-selectable control over system clock functions. This multiple output clock driver provides the system integrator with functions necessary to optimize the timing of high performance computer or communication systems.

Features

• 10 MHz to 100–133 MHz operating range
• Zero input and output propagation delay
• Multiple low skew outputs
• One input drives five outputs (CY2305C)
• One input drives nine outputs, grouped as 4 4 1 (CY2309C)
• 50 ps typical cycle-to-cycle jitter (15 pF, 66 MHz)
• Test mode to bypass phase locked loop (PLL) (CY2309C) only
• Available in space saving 16-pin 150 Mil small outline integrated circuit (SOIC) or 4.4 mm thin shrunk small outline package (TSSOP) packages (CY2309C), and 8-pin, 150 Mil SOIC package (CY2305C)
• 3.3 V operation
• Commercial, industrial and automotive-A flows available

Functional Description

The CY2305C and CY2309C are die replacement parts for CY2305 and CY2309.

The CY2309C is a low-cost 3.3 V zero delay buffer designed to distribute high speed clocks and is available in a 16-pin SOIC or TSSOP package. The CY2305C is an 8-pin version of the CY2309C. It accepts one reference input and drives out five low skew clocks. The -1H versions of each device operate up to 100–133 MHz frequencies and have higher drive than the -1 devices. All parts have on-chip phase locked loops (PLLs) which lock to an input clock on the REF pin. The PLL feedback is on-chip and is obtained from the CLKOUT pad.

Features

• Select one of two low-voltage differential signal (LVDS) input pairs to distribute to 10 LVDS output pairs
• 40-ps maximum output-to-output skew
• 600-ps maximum propagation delay
• 0.11-ps maximum additive RMS phase jitter at 156.25 MHz (12-kHz to 20-MHz offset)
• Up to 1.5-GHz operation
• Asynchronous output enable function
• 32-pin thin quad flat pack (TQFP) package
• 2.5-V or 3.3-V operating voltage [1]
• Commercial and industrial operating temperature range

Functional Description

The CY2DL15110 is an ultra-low noise, low skew, low propagation delay 1:10 LVDS fanout buffer targeted to meet the requirements of high speed clock distribution applications. The CY2DL15110 can select between two separate LVDS input clock pairs using the IN_SEL pin. The output enable function allows the outputs to be asynchronously driven to a high-impedance state. The device has a fully differential internal architecture that is optimized to achieve low additive jitter and low skew at operating frequencies of up to 1.5 GHz.

The CY23FP12 is a field programmable zero delay buffer. It is a high performance clock distribution device that can be customized for a wide range of applications. The CY23FP12, which integrates the functionalities of complete clock distribution solutions, takes advantage of Cypress' proprietary non-volatile memory technology to provide a fully programmable device. For prototypes, programmers are used else Cypress distributors take responsibility of programming in large volumes. 

Features

• Internal DCXO for continuous glitch-free operation
• Zero input-output propagation delay
• 100 ps typical output cycle-to-cycle jitter
• 110 ps typical output-output skew
• 1 MHz to 200 MHz reference input
• Supports industry standard input crystals
• 200 MHz (commercial), 166 MHz (industrial) outputs
• 5V-tolerant inputs
• Phase-locked loop (PLL) bypass mode
• For more, see pdf
   

Functional Description

The CY23FS08 is a FailSafe™ Zero Delay Buffer with two reference clock inputs and eight phase-aligned outputs. The device provides an optimum solution for applications where continuous operation is required in the event of a primary clock failure.

Features

• Output frequency range: 16.67 MHz to 200 MHz
• Input frequency range: 16.67 MHz to 200 MHz
• 2.5V or 3.3V operation
• Split 2.5V and 3.3V outputs
• ±2% maximum output duty cycle variation
• 11 clock outputs: drive up to 22 clock lines
• LVCMOS reference clock input
• 125 ps maximum output-output skew
• PLL bypass mode
• For more, see pdf
   

Description

The CY29352 is a low voltage high performance 200 MHz PLL based zero delay buffer designed for high speed clock distribution applications.      More...

Features

• Fully Field-Programmable
  • Input and output dividers
  • Inverting/noninverting outputs
  • Phase-locked loop (PLL) or fanout buffer configu­ration
• 10-MHz to 200-MHz Operating Range
• Split 2.5V or 3.3V Outputs
• Two LVCMOS Reference Inputs
• Twelve Low Skew Outputs
  • 35 ps typical output-to-output skew (same frequency)
• For more, see pdf
   

Functional Description

Features

• 2.5V or 3.3V operation
• 200-MHz clock support
• LVCMOS-/LVTTL-compatible inputs
• 9-clock outputs: drive up to 18-clock lines
• Synchronous Output Enable
• Output three-state control
• 250 ps max. output-to-output skew
• Pin compatible with MPC947, MPC9447
• Available in Industrial and Commercial temp. range
• 32-pin TQFP package
   

Description

The CY29947 is a low-voltage 200-MHz clock distribution buffer with the capability to select one of two LVCMOS/LVTTL compatible clock inputs. The two clock sources can be used to provide for a test clock as well as the primary system clock. All other control inputs are LVCMOS/LVTTL compatible. The 9 outputs are LVCMOS or LVTTL compatible and can drive 50-ohm series or parallel terminated transmission lines.For series terminated transmission lines, each output can drive one or two traces giving the device an effective fanout of 1:18. The outputs can also be three-stated via the three-state input TS#. Low output-to-output skews make the CY29947 an ideal clock distribution buffer for nested clock trees in the most demanding of synchronous systems.

The CY29947 also provides a synchronous output enable input for enabling or disabling the output clocks. Since this input is internally synchronized to the input clock, potential output glitching or runt pulse generation is eliminated.

Features

• 2.5 V or 3.3 V operation
• 200-MHz clock support
• Two LVCMOS-/LVTTL-compatible inputs
• Ten clock outputs: drive up to 20 clock lines
• 1× or 1/2× configurable outputs
• Output three-state control
• 250-ps max output-to-output skew
• Pin-compatible with MPC946, MPC9446
• Available in commercial and industrial temperature range
• 32-pin TQFP package
   

Description

The CY29946 is a low-voltage 200-MHz clock distribution buffer with the capability to select one of two LVCMOS/LVTTL compatible input clocks. These clock sources can be used to provide for test clocks as well as the primary system clocks. All other control inputs are LVCMOS/LVTTL compatible. The 10 outputs are LVCMOS or LVTTL compatible and can drive 50Ω series or parallel terminated transmission lines. For series terminated transmission lines, each output can drive one or two traces giving the device an effective fanout of 1:20.

Features

• Output frequency up to 125 MHz
• 12 Clock outputs: frequency configurable
• 350 ps max. output-to-output skew
• Configurable output disable
• Two reference clock inputs for dynamic toggling
• Oscillator or crystal reference input
• Spread-spectrum-compatible
• Glitch-free output clocks transitioning
• 3.3V power supply
• Pin-compatible with MPC972
• Industrial temperature range: -40°C to +85°C
• 52-pin TQFP package
   

Description

The CY29972 has an integrated PLL that provides low skew and low jitter clock outputs for high-performance microprocessors. Three independent banks of four outputs and an independent PLL feedback output (FB_OUT) provide exceptional flexibility for possible output configurations. The PLL is ensured stable operation given that the VCO is configured to run between 200 MHz and 480 MHz. This allows a wide range of output frequencies up to125 MHz.

The phase detector compares the input reference clock to the external feedback input. For normal operation, the external feedback input (FB_IN) is connected to the feedback output (FB_OUT). The internal VCO is running at multiples of the input reference clock set by FB_SEL(0:2) and VCO_SEL select inputs (refer to Frequency Table). The VCO frequency is then divided to provide the required output frequencies. These dividers are set by SELA(0,1), SELB(0,1), SELC(0,1) select inputs (see Table 2 below). For situations were the VCO needs to run at relatively low frequencies and hence might not be stable, assert VCO_SEL low to divide the VCO frequency by 2. This will maintain the desired output relationships but will provide an enhanced PLL lock range.

Features

• Output Frequency up to 125 MHz
• 12 Clock Outputs: Frequency Configurable
• 350 ps max. Output to Output Skew
• Configurable Output Disable
• Two Reference Clock Inputs for Dynamic Toggling
• Oscillator or PECL Reference Input
• Spread Spectrum Compatible
• Glitch-free Output Clocks Transitioning
• 3.3V Power Supply
• Pin Compatible with MPC973
• Industrial Temperature Range: - 40°C to 85°C
• 52-Pin TQFP Package
   

Description

The CY29973 has an integrated PLL that provides low-skew and low-jitter clock outputs for high-performance microprocessors. Three independent banks of four outputs and an independent PLL feedback output, FB_OUT, provide exceptional flexibility for possible output configurations. The PLL is ensured stable operation given that the VCO is configured to run between 200 MHz to 480 MHz. This allows a wide range of output frequencies up to125 MHz.

• 2.5V or 3.3V operation
• 200-MHz clock support
• LVPECL or LVCMOS/LVTTL clock input
• LVCMOS/LVTTL compatible outputs
• 15 clock outputs: drive up to 30 clock lines
• 1X and 1/2X configurable outputs
• Output three-state control
• 350 ps maximum output-to-output skew
• Pin compatible with MPC949, MPC9449
• Available in Commercial and Industrial temperature range
• 52-pin TQFP package
   

Description

The CY29949 is a low voltage 200 MHz clock distribution buffer with the capability to select either a differential LVPECL or LVCMOS/LVTTL compatible input clocks. These clock sources are used to provide for test clocks and primary system clocks.      More...

Features

• 3-Multiplier configuration (1x, 2x, 4x ref)
• 10 MHz to 166.67 MHz operating range (reference input from 10 MHz to 41.67 MHz)
• Phase alignment
• 80 ps typical period jitter
• Output enable pin
• 3.3 V operation
• 5 V tolerant input
• 8-pin 150-mil small-outline integrated circuit (SOIC) package
• Commercial temperature range
   

Functional Description

The CY2303 is a 3 output 3.3 V phase-aligned system clock designed to distribute high-speed clocks in PC, workstation, datacom, telecom, and other high-performance applications.

The part allows user to obtain 1x, 2x, and 4x REFIN output frequencies on respective output pins.

Features

• 4-multiplier configuration
• Single PLL architecture
• Phase alignment
• Low jitter, high accuracy outputs
• Output enable pin
• 3.3 V operation
• 5 V tolerant input
• Internal loop filter
• 8-pin 150-mil small-outline integrated circuit (SOIC) package
• Commercial temperature
   

Functional Description

The CY2300 is a 4 output 3.3 V phase-aligned system clock designed to distribute high-speed clocks in PC, workstation, datacom, telecom, and other high-performance applications.

The part allows the user to obtain 1/2x, 1x, 1x and 2x REFIN output frequencies on respective output pins.

Features

• Spread Aware™—designed to work with SSFTG reference signals
• 90ps typical jitter OUT2
• 200ps typical jitter OUT1
• 65ps typical output-to-output skew
• 90ps typical propagation delay
• Voltage range: 3.3V±5%, or 5V±10%
• Output frequency range: 20MHz-133MHz
• Two outputs
• Configuration options allow various multiplication of the reference frequency.
• Available in 8-pin SOIC package
   

Overview

The CY23S02 is a two-output zero delay buffer and frequency multiplier. It provides an external feedback path allowing maximum flexibility when implementing the Zero Delay feature. This is explained further in the sections of this data sheet titled “How to Implement Zero Delay,” and “Inserting Other Devices in Feedback Path.”

Features

• 90 ps Typical Jitter OUT2
• 200 ps Typical Jitter OUT1
• 65 ps Typical Output-to-output Skew
• 90ps Typical Propagation Delay
• Voltage range: 3.3V±5%, or 5V±10%
• Output Frequency Range: 5 MHz to 133 MHz
• Two Outputs
• Configuration options allow various multiplications of the reference frequency.
• Available in 8-pin SOIC Package
   

Overview

The CY2302 is a two-output zero delay buffer and frequency multiplier. It provides an external feedback path allowing maximum flexibility when implementing the Zero Delay feature. This is explained further in the sections of this datasheet titled “How to Implement Zero Delay,” and “Inserting Other Devices in Feedback Path.”

The CY2302 is a pin-compatible upgrade of the Cypress W42C70-01. The CY2302 addresses some application dependent problems experienced by users of the older device.

Features

• Zero input-output propagation delay, adjustable by capacitive load on FBK input
• Multiple configurations
• Multiple low skew outputs
• Two banks of four outputs, three-stateable by two select inputs
• 10 MHz to 133 MHz operating range
• 75 ps typical cycle-to-cycle jitter (15 pF, 66 MHz)
• Space saving 16-pin 150 mil SOIC package or 16-pin TSSOP
• 3.3 V operation
• Industrial temperature available
   

Functional Description

The CY2308 is a 3.3 V Zero Delay Buffer designed to distribute high speed clocks in PC, workstation, datacom, telecom, and other high performance applications.

The part has an on-chip PLL that locks to an input clock presented on the REF pin. The PLL feedback is driven from external FBK pin, so user has flexibility to choose any one of the outputs as feedback input and connect it to FBK pin. The input-to-output skew is less than 250 ps and output-to-output skew is less than 200 ps.

Features

• All output pair skew <100 ps typical (250 ps maximum)
• 3.75 MHz to 80 MHz output operation
• User selectable output functions
  • Selectable skew to 18 ns
  • Inverted and non-inverted
  • Operation at 1⁄2 and 1⁄4 input frequency
  • Operation at 2x and 4x input frequency (input as low as 3.75 MHz)
• Zero input to output delay
• 50% duty cycle outputs
• Outputs drive 50Ω terminated lines
• Low operating current
• 32-pin PLCC/LCC package
• Jitter <200 ps peak-to-peak (< 25 ps RMS)

Functional Description

The CY7B991 and CY7B992 Programmable Skew Clock Buffers (PSCB) offer user selectable control over system clock functions. These multiple output clock drivers provide the system integrator with functions necessary to optimize the timing of high performance computer systems. Each of the eight individual drivers, arranged in four pairs of user controllable outputs, can drive terminated transmission lines with impedances as low as 50Ω. They can deliver minimal and specified output skews and full swing logic levels (CY7B991 TTL or CY7B992 CMOS).

Features

• Select one of two low-voltage positive emitter-coupled logic (LVPECL) input pairs to distribute to four LVPECL output pairs
• 30 ps maximum output-to-output skew
• 480-ps maximum propagation delay
• 0.15-ps maximum additive RMS phase jitter at 156.25 MHz (12-kHz to 20-MHz offset)
• Up to 1.5-GHz operation
• Synchronous clock enable function
• 20-pin thin shrunk small outline package (TSSOP)
• 2.5-V or 3.3-V operating voltage[1]
• Commercial and industrial operating temperature range

Functional Description

The CY2DP1504 is an ultra-low noise, low-skew, low-propagation delay 1:4 LVPECL fanout buffer targeted to meet the requirements of high-speed clock distribution applications. The CY2DP1504 can select between two separate LVPECL input clock pairs using the IN_SEL pin. The synchronous clock enable function ensures glitch-free output transitions during enable and disable periods. The device has a fully differential internal architecture that is optimized to achieve low additive jitter and low skew at operating frequencies of up to 1.5 GHz.

Features

• Select one of two low-voltage positive emitter-coupled logic (LVPECL) input pairs to distribute to 10 LVPECL output pairs
• 40-ps maximum output-to-output skew
• 600-ps maximum propagation delay
• 0.11-ps maximum additive RMS phase jitter at 156.25 MHz (12-kHz to 20-MHz offset)
• Up to 1.5-GHz operation
• 32-pin thin quad flat pack (TQFP) package
• 2.5-V or 3.3-V operating voltage
• Commercial and industrial operating temperature range

Functional Description

The CY2DP1510 is an ultra-low noise, low skew, low-propagation delay 1:10 LVPECL fanout buffer targeted to meet the requirements of high-speed clock distribution applications. The CY2DP1510 can select between two separate LVPECL input clock pairs using the IN_SEL pin. The device has a fully differential internal architecture that is optimized to achieve low additive jitter and low skew at operating frequencies of up to 1.5 GHz.

Features

• 10 MHz to 220 MHz maximum operating range
• Zero input-output propagation delay, adjustable by loading on CLKOUT in
• Multiple low-skew outputs
  • 45 ps typical output-output skew-
  • One input drives nine outputs, grouped as 4 4 1
• 25 ps typical cycle-to-cycle jitter
• 15 ps typical period jitter
• Standard and High drive strength options
• Available in space-saving 16-pin 150-mil SOIC or 4.4-mm TSSOP packages
• 3.3V or 2.5V operation
• Industrial temperature available

Functional Description

The CY23EP09 is a 2.5V or 3.3V zero delay buffer designed to distribute high-speed clocks and is available in a 16-pin SOIC or TSSOP package. The -1H version operates up to 220 (200) MHz frequencies at 3.3V (2.5V), and has higher drive than the -1 devices. All parts have on-chip PLLs that lock to an input clock on the REF pin. The PLL feedback is on-chip and is obtained from the CLKOUT pad.

Features

• One current mode logic (CML) or low-voltage positive emitter-coupled logic (LVPECL) input pair distributed to two CML output pairs
• 20-ps maximum output-to-output skew
• 480-ps maximum propagation delay
• 0.15-ps maximum additive RMS phase jitter at 156.25 MHz (12-kHz to 20-MHz offset)
• Up to 1.5 GHz operation
• 8-Pin thin shrunk small outline package (TSSOP) package
• 2.5-V or 3.3-V operating voltage[1]
• Commercial and industrial operating temperature range

Functional Description

The CY2DM1502 is an ultra-low noise, low-skew, low-propagation delay 1:2 CML or LVPECL to CML fanout buffer targeted to meet the requirements of high-speed clock distribution applications. The device has a fully differential internal architecture that is optimized to achieve low additive jitter and low skew at operating frequencies of up to 1.5 GHz.

Features

• Low-voltage differential signal (LVDS) input with on-chip 100-Ω input termination resistor
• Ten differential LVDS outputs
• 40-ps maximum output-to-output skew
• 600-ps maximum propagation delay
• 0.11-ps maximum additive RMS phase jitter at 156.25 MHz (12-kHz to 20-MHz offset)
• Up to 1.5-GHz operation
• Synchronous clock enable function
• 32-pin thin quad flat pack (TQFP) package
• 2.5-V or 3.3-V operating voltage[1]
• Commercial and industrial operating temperature range

Functional Description

The CY2DL1510 is an ultra-low noise, low-skew, low-propagation delay 1:10 differential LVDS fanout buffer targeted to meet the requirements of high-speed clock distribution applications. The on-chip 100-Ω input termination resistor reduces board component count, while the synchronous clock enable function ensures glitch-free output transitions during enable and disable periods. The device has a fully differential internal architecture that is optimized to achieve low-additive jitter and low-skew at operating frequencies of up to 1.5 GHz..

Features
 

• Select one of two low-voltage complementary metal oxide semiconductor (LVCMOS) inputs to distribute to four low-voltage positive emitter-coupled logic (LVPECL) output pairs
• 30-ps maximum output-to-output skew
• 480-ps maximum propagation delay
• 0.15-ps maximum additive RMS phase jitter at 156.25 MHz (12-kHz to 20-MHz offset)
• Up to 250 MHz operation
• Synchronous clock enable function
• 20-Pin thin shrunk small outline package (TSSOP) package
• 2.5-V or 3.3-V operating voltage[1]
• Commercial and industrial operating temperature range

Functional Description

The CY2CP1504 is an ultra-low noise, low-skew, low-propagation delay 1:4 LVCMOS to LVPECL fanout buffer targeted to meet the requirements of high-speed clock distribution applications. The CY2CP1504 can select between two separate LVCMOS input clocks using the IN_SEL pin. The synchronous clock enable function ensures glitch-free output transitions during enable and disable periods. The device has a fully differential internal architecture that is optimized to achieve low additive jitter and low skew at operating frequencies of up to 250 MHz.

Features

• Spread Aware™ designed to work with spread spectrum frequency timing generator (SSFTG) reference signals
• Well suited to both 100- and 133-MHz designs Ten (CY2509) or eleven (CY2510) low-voltage complementary metal oxide semiconductor (LVCMOS) / low-voltage transistortransistor logic (LVTTL) outputs.
• 50 ps typical peak cycle-to-cycle jitter
• Single output enable pin for CY2510 version, dual pins on CY2509 devices allow shutting down a portion of the outputs
• 3.3 V power supply
• On-chip 25 Ω damping resistors
• Available in 24-pin thin shrunk small outline package (TSSOP) package
• Improved tracking skew, but narrower frequency support limit when compared to W132-09B/10B

Overview

The CY2509/10 is a PLL-based clock driver designed for use in dual inline memory modules. The clock driver has output frequencies of up to 133 MHz and output to output skews of less than 250 ps. The CY2509/10 provides minimum cycle-to-cycle and long-term jitter, which is of significant importance to meet the tight input-to-input skew budget in DIMM applications.

Features

• Zero input-output propagation delay, adjustable by capacitive load on FBK input
• Multiple configurations
• Multiple low-skew outputs
• 10 MHz to 133 MHz operating range
• 90 ps typical peak cycle-to-cycle jitter at 15 pF, 66 MHz
• Space-saving 8-pin 150-mil SOIC package
• 3.3V operation
• Industrial temperature available
   

Functional Description

The CY2304 is a 3.3V zero delay buffer designed to distribute high-speed clocks in PC, workstation, datacom, telecom, and other high performance applications.

The part has an on-chip phase-locked loop (PLL) that locks to an input clock presented on the REF pin. The PLL feedback is required to be driven into the FBK pin, and can be obtained from one of the outputs. The input-to-output skew is guaranteed to be less than 250 ps, and output-to-output skew is guaranteed to be less than 200 ps.

Features

• One-input to nine-output buffer/driver
• Supports two DIMMs or four SO-DIMMs with one additional output for feedback to an external or chipset phase-locked loop (PLL)
• Low power consumption for mobile applications
  • Less than 32 mA at 66.6 MHz with unloaded outputs
• 1-ns Input-output delay
• Buffers all frequencies from DC to 133.33 MHz
• Output-output skew less than 250 ps
• Multiple VDD and VSS pins for noise and electromagnetic interference (EMI) reduction
• Space-saving 16-pin 150-mil small-outline integrated circuit (SOIC) package
• 3.3 V operation
• Industrial temperature available
   

Functional Description

The CY2309NZ is a low-cost buffer designed to distribute high-speed clocks in mobile PC systems and desktop PC systems with SDRAM support. The part has nine outputs, eight of which can be used to drive two DIMMs or four SO-DIMMs, and the remaining can be used for external feedback to a PLL. The device operates at 3.3V and outputs can run up to 133.33 MHz.

Features

• Zero input output propagation delay, adjustable by capacitive load on FBK input
• Multiple configurations
• Multiple low-skew outputs
  • 45-ps typical output-output skew (–1)
  • Two banks of four outputs that can be tristated by two select inputs
• 10 MHz to 140 MHz operating range
• 65-ps typical cycle-to-cycle jitter (–1, –1H)
• Advanced 0.65-μm complementary metal oxide semiconductor (CMOS) technology
• Space-saving 16-pin small outline integrated circuit (SOIC) package
• 3.3-V operation
• Spread Aware
   

Functional Description

The CY23S08 is a 3.3-V zero delay buffer designed to distribute high-speed clocks in PC, workstation, datacom, telecom, and other high-performance applications.

The part has an on-chip PLL which locks to an input clock presented on the REF pin. The PLL feedback must be driven into the FBK pin, and obtained from one of the outputs. The input-to-output propagation delay is less than 350 ps and output-to-output skew is less than 250 ps.

Features

• One input to 13 output buffer/driver
• Supply voltage: 3.3 V
• Supports up to three SDRAM DIMMs
• SMBus serial interface for output control
• Low skew outputs
• Up to 100-MHz operation
• Multiple VDD and VSS pins for noise reduction
• Low EMI outputs
• Package: 28-pin small-outline integrated circuit (SOIC)
   

Functional Description

The CY2313ANZ is a 3.3 V clock buffer. While originally designed to distribute clocks in desktop PC applications - hence the signal names - it is a general purpose device suitable to a wide variety of clock buffering applications. The part has thirteen outputs. In a PC application, twelve of which can be used to drive up to three SDRAM DIMMs, and the remaining output can be used for external feedback to a PLL. The device operates at 3.3 V and outputs can run up to 100 MHz.

Features

• 10 MHz to 220 MHz maximum operating range
• Zero input-output propagation delay, adjustable by loading on CLKOUT pin
• Multiple low-skew outputs
  • 30 ps typical output-output skew
  • One input drives five outputs
• 22 ps typical cycle-to-cycle jitter
• 13 ps typical period jitter
• Standard- and high-drive strength options
• Available in space-saving 150-mil SOIC package
• 3.3V or 2.5V operation
• Industrial temperature available
   

Functional Description

The CY23EP05 has 2.5V or 3.3V zero delay buffer designed to distribute low-jitter high-speed clocks and is available in a 8-pin SOIC package. It accepts one reference input, and drives out five low-skew clocks. The -1H version operates at up to 220 (200) MHz frequencies at 3.3V (2.5V), and has higher drive strength than the -1 device. All parts have on-chip PLLs that lock to an input clock on the REF pin. The PLL feedback is on-chip and is obtained from the CLKOUT pad.

The CY23EP05 PLLs enter a power-down mode when there are no rising edges on the REF input (<~2 MHz). In this state, the outputs are three-stated and the PLL is turned off, resulting in less than 25 µA of current draw.

The CY23EP05 is available in different configurations, as shown in the Ordering Information table. The CY23EP05-1 is the base part. The CY23EP05-1H is the high-drive version of the -1, and its rise and fall times are much faster than the -1.

These parts are not intended for 5V input-tolerant applications.

Features

• 10 MHz to 100 and 133 MHz Operating Range, compatible with CPU and PCI bus frequencies
• Zero Input-output Propagation Delay
• Multiple Low Skew Outputs
  • Output-output skew less than 250 ps
  • Device-device skew less than 700 ps
  • One input drives five outputs (CY23S05)
  • One input drives nine outputs, grouped as 4 4 1 (CY23S09)
• Less than 200 ps Cycle-to-cycle jitter is compatible with Pentium based systems
• Test mode to bypass PLL
• Available in space saving 16-pin, 150-mil SOIC, 4.4 mm TSSOP, and 150-mil SSOP (CY23S09) or 8-pin, 150-mil SOIC package (CY23S05)
• 3.3V operation, advanced 0.65μ CMOS Technology
• Spread Aware
   

Functional Description

The CY23S09 is a low cost 3.3V zero delay buffer designed to distribute high speed clocks and is available in a 16-pin SOIC package. The CY23S05 is an 8-pin version of the CY23S09. It accepts one reference input, and drives out five low skew clocks.

Features

• Low-voltage operation
• VDD = 3.3V
• 1:4 Fanout
• Single-input configurable for
  • LVDS, LVPECL, or LVTTL
  • Four differential pairs of LVDS outputs
• Drives 50- or 100-ohm load (selectable)
• Low input capacitance
• 85 ps typical output-to-output skew
• For more, see pdf
   

Description

The Cypress CY2 series of network circuits is produced using advanced 0.35-micron CMOS technology, achieving the industry’s fastest logic.

The Cypress CY2DL814 fanout buffer features a single LVDS, LVPECL, or LVTTL compatible input and four LVDS output pairs.

• All Output Pair Skew <100 ps Typical (250 max)
• 3.75 MHz to 100 MHz Output Operation
• User Selectable Output Functions
  • Selectable Skew to 18 ns
  • Inverted and Non-inverted
  • Operation at ½ and ¼ Input Frequency
  • Operation at 2x and 4x Input Frequency (input as low as 3.75 MHz)
• Zero Input to Output Delay
• 50% Duty Cycle Outputs
• For more, see pdf
   

Functional Description

The CY7B9911 High Speed Programmable Skew Clock Buffer (PSCB) offers user selectable control over system clock functions. This multiple output clock driver provides the system integrator with functions necessary to optimize the timing of high performance computer systems. Each of the eight individual TTL drivers, arranged in four pairs of user controllable outputs, can drive terminated transmission lines with impedances as low as 50Ω. They deliver minimal and specified output skews and full swing logic levels.

Features

• Pre-programmed Configuration
• Fully Field-Programmable
  • Input and output dividers
  • Inverting/noninverting outputs
  • Phase-locked loop (PLL) or fanout buffer configuration
• 10-MHz to 200-MHz Operating Range
• Split 2.5V or 3.3V Outputs
• Two LVCMOS Reference Inputs
• Twelve Low-skew Outputs
• For more, see pdf
   

Functional Description

Features

• 500 ps max Total Timing Budget (TTB™) window
• 24 MHz –200 MHz input and Output Operation
• Low Output-output skew <200 ps
• 10 1 LVTTL Outputs driving 50Ω terminated lines
• Dedicated feedback output
• Phase adjustments in 625ps/1300 ps steps up to 10.4 ns
• 3.3V LVTTL/LVPECL, Fault Tolerant, and Hot Insertable Reference Inputs
• Multiply or Divide Ratios of 1 through 6, 8, 10, and 12
• Individual Output Bank Disable
• For more, see pdf

Functional Description

The CY7B9945V high speed multi-phase PLL clock buffer offers user selectable control over system clock functions. This multiple output clock driver provides the system integrator with functions necessary to optimize the timing of high performance computer and communication systems.

Features

• All output pair skew <100 ps typical (250 ps max)
• 3.75 MHz to 80 MHz output operation
• User-selectable output functions:
  • Selectable skew up to 18 ns
  • Inverted and non-inverted
  • Operation at one-half and one-quarter input frequency
  • Operation at 2× and 4× input frequency (input as low as 3.75 MHz)
• Zero input to output delay
• 50% duty cycle outputs
• For more, see pdf

Functional Description

The CY7B991V 3.3-V RoboClock® low-voltage programmable skew clock buffer (LVPSCB) offers user-selectable control over system clock functions. These multiple output clock drivers provide the system integrator with functions necessary to optimize the timing of high-performance computer systems. Each of the eight individual drivers – arranged in four pairs of user controllable outputs – can drive terminated transmission lines with impedances as low as 50 Ω. This delivers minimal output skews and full-swing logic levels (LVTTL).

Features

• 500 ps Max Total Timing Budget (TTB™) window
• 12 MHz to 100 MHz (CY7B993V), or 24 MHz to 200 MHz (CY7B994V) Input/Output Operation
• Matched Pair Output Skew < 200 ps
• Zero Input-to-Output Delay
• 18 LVTTL Outputs Driving 50Ω Terminated Lines
• 16 Outputs at 200 MHz: Commercial Temperature
• 6 Outputs at 200 MHz: Industrial Temperature
• 3.3V LVTTL/LVPECL, Fault-tolerant, and Hot Insertable Reference Inputs
• Phase Adjustments in 625 ps/1300 ps Steps Up to ± 10.4 ns
• For more, see pdf

Functional Description

The CY7B993V and CY7B994V High-speed Multi-phase PLL Clock Buffers offer user selectable control over system clock functions. This multiple output clock driver provides the system integrator with functions necessary to optimize the timing of high-performance computer and communication systems.These devices feature a guaranteed maximum TTB window specifying all occurrences of output clocks with respect to the input reference clock across variations in output frequency, supply voltage, operating temperature, input edge rate, and process.

Features

• Low voltage operation
• Full range support:
  • 3.3V
  • 2.5V
  • 1.8V
• Over voltage tolerant input hot swappable
• 1:10 Fanout
• Drives either a 50-Ohm or 75-Ohm load
• Low input capacitance
• For more, see pdf
   

Description

The Cypress series of network circuits are produced using advanced 0.35 micron CMOS technology, achieving the industry’s fastest logic and buffers.

The Cypress CY2CC910 fanout buffer features one input and 10 outputs. It is ideal for conversion from and to 3.3V, 2.5V, and 1.8V Designed for Data Communications clock management applications, the large fanout from a single input reduces loading on the input clock.

Features

• All outputs skew < 100 ps typical (250 max)
• 15 to 80 MHz output operation
• Zero input to output delay
• 50% duty cycle outputs
• Outputs drive 50 Ωterminated lines
• Low operating current
• 24-pin small-outline integrated circuit (SOIC) package
• Jitter: < 200 ps peak-to-peak, < 25 ps RMS

Functional Description

The CY7B9910 and CY7B9920 low skew clock buffers offer low skew system clock distribution. These multiple output clock drivers optimize the timing of high performance computer systems. Each of the eight individual drivers can drive terminated transmission lines with impedances as low as 50Ω. They deliver minimal and specified output skews and full swing logic levels (CY7B9910 TTL or CY7B9920 CMOS).

Features

• Low-voltage operation
• VDD = 3.3V
• 1:4 fanout
• Single input configurable for LVDS, LVPECL, or LVTTL
• Four differential pairs of LVPECL outputs
• Drives 50-ohm load
• Low input capacitance
• Less than 4 ns typical propagation delay
• 85 ps typical output-to-output skew
• Commercial temperature range
• Available in TSSOP package
   

Description

The Cypress CY2 series of network circuits are produced using advanced 0.35-micron CMOS technology, achieving the industry’s fastest logic.

The Cypress CY2DP814 fanout buffer features a single LVDSor a single LVPECL-compatible input and four LVPECL output pairs.

Features

• 2.5V or 3.3V operation
• Split output bank power supplies
• Output frequency range: 6 MHz to 200 MHz
• 45 ps typical cycle-cycle jitter
• ± 2% max output duty cycle
• Selectable output drive strength
• Selectable positive or negative edge synchronization
• Eight LVTTL outputs driving 50 Ω terminated lines
• LVCMOS/LVTTL over-voltage tolerant reference input
• For more, see pdf

Description

The CY7B995 RoboClock(R) is a low voltage, low power, eight-output, 200 MHz clock driver. It features output phase programmability which is necessary to optimize the timing of high performance computer and communication systems.

The user can program both the frequency and the phase of the output banks through nF[0:1] and DS[0:1] pins. The adjustable phase feature allows the user to skew the outputs to lead or lag the reference clock. Any one of the outputs can be connected to feedback to achieve different reference frequency multiplication, and divide ratios and zero input-output delay.      More...

Features

• 2.5 V or 3.3 V operation
• Split output bank power supplies
• Output frequency range: 6 MHz to 200 MHz
• 50 ps typical matched-pair output-output skew
• 50 ps typical cycle-cycle jitter
• 49.5 / 50.5% typical output duty cycle
• Selectable output drive strength
• Selectable positive or negative edge synchronization
• Eight LVTTL outputs driving 50Ω terminated lines
• For more, see pdf

Description

The CY7B9950 RoboClock® is a low voltage, low power, eight-output, 200 MHz clock driver. It features output phase programmability which is necessary to optimize the clock tree design of high performance computer and communication systems.

Features

• 10 MHz to 200 MHz output operation
• Output-to-output skews < 350 ps
• 13 LVTTL 50% duty cycle outputs capable of driving 50Ω terminated lines
• Phase-locked loop (PLL) LOCK indicator
• 3.3V LVTTL/LV differential (LVPECL) hot insertable reference inputs
• Multiply/divide ratios of (4, 6, 8, 10, 12, 16, 20) : (2, 4, 6, 8, 10, 12, 16, 20)
• Operation with outputs operating at up to 10x input frequency
• Low cycle-to-cycle jitter (< ±75 ps peak-peak)
• Single 3.3V ± 10% supply
• 52-pin TQFP package

Functional Description

The CY7B9973V Low Voltage PLL Clock Buffer offers user-selectable frequency control over system clock functions. This twelve output clock driver provides the system integrator with selectable frequency ratios of 1:1, 2:1, 3:1, 3:2, 4:3, 5:1, 5:2, 5:3, 6:1 and 6:5 between outputs. An additional output is dedicated to providing feedback information to allow the internal PLL to multiply an external reference frequency by 4, 6, 8, 10, 12, 16 or 20. The completely integrated PLL reduces jitter and simplifies board layout.

Features

• All output pair skew <100 ps typical (250 max)
• 3.75 to 110 MHz output operation
• User selectable output functions
  • Selectable skew to 18 ns
  • Inverted and non-inverted
  • Operation at 1⁄2 and 1⁄4 input frequency
  • Operation at 2x and 4x input frequency (input as low as 3.75 MHz)
• Zero input-to-output delay
• 50% duty cycle outputs
• For more, see pdf

Functional Description

The CY7B9911V 3.3V RoboClock ™ High Speed Low Voltage Programmable Skew Clock Buffer (LVPSCB) offers user selectable control over system clock functions. These multiple output clock drivers provide the system integrator with functions necessary to optimize the timing of high performance computer systems.

Features

• Output frequency range: 8.3 MHz to 125 MHz
• Input frequency range: 4.2 MHz to 62.5 MHz
• 2.5V or 3.3V operation
• Split 2.5V/3.3V outputs
• 14 Clock outputs: Drive up to 28 clock lines
• 1 Feedback clock output
• 2 LVCMOS reference clock inputs
• 150 ps max output-output skew
• PLL bypass mode
• Spread Aware(TM)
• Output enable/disable
• Pin compatible with MPC9774
• Industrial temperature range: -40°C to +85°C
• 52-Pin 1.0-mm TQFP package
   

Description

The CY29774 is a low-voltage high-performance 125-MHz PLL-based zero delay buffer designed for high-speed clock distribution applications.

The CY29774 features two reference clock inputs and provides 14 outputs partitioned in 3 banks of 5, 5, and 4 outputs. Bank A and Bank B divide the VCO output by 4 or 8 while Bank C divides by 8 or 12 per SEL(A:C) settings, see Functional Table. These dividers allow output to input ratios of 6:1, 4:1, 3:1, 2:1, 3:2, 4:3, 1:1, and 2:3. Each LVCMOS compatible output can drive 50-ohm series or parallel terminated transmission lines. For series terminated transmission lines, each output can drive one or two traces giving the device an effective fanout of 1:28.

The PLL is ensured stable given that the VCO is configured to run between 200 MHz to 500 MHz. This allows a wide range of output frequencies from 8.3 MHz to 125 MHz. For normal operation, the external feedback input, FB_IN, is connected to the feedback output, FB_OUT. The internal VCO is running at multiples of the input reference clock set by the feedback divider, see Frequency Table.

When PLL_EN is LOW, PLL is bypassed and the reference clock directly feeds the output dividers. This mode is fully static and the minimum input clock frequency specification does not apply.

Features

• Output frequency range: 25 MHz to 200 MHz
• Input frequency range: 6.25 MHz to 31.25 MHz
• 2.5 V or 3.3 V operation
• Split 2.5 V/3.3 V outputs
• ±2.5% max Output duty cycle variation
• Nine Clock outputs: Drive up to 18 clock lines
• Two reference clock inputs: Xtal or LVCMOS
• 150-ps max output-output skew
• Phase-locked loop (PLL) bypass mode
• For more, see pdf
   

Functional Description

The CY29350 is a low-voltage high-performance 200-MHz PLL-based clock driver designed for high speed clock distribution applications.

The CY29350 features Xtal and LVCMOS reference clock inputs and provides nine outputs partitioned in four banks of 1, 1, 2, and 5 outputs. Bank A divides the VCO output by 2 or 4 while the other banks divide by 4 or 8 per SEL(A:D) settings, see . These dividers allow output to input ratios of 16:1, 8:1, 4:1, and 2:1. Each LVCMOS compatible output can drive 50Ω series or parallel terminated transmission lines. For series terminated transmission lines, each output can drive one or two traces giving the device an effective fanout of 1:18.

Features

• 200-MHz clock support
• LVPECL or LVCMOS/LVTTL clock input
• LVCMOS/LVTTL compatible inputs
• 18 clock outputs: drive up to 36 clock lines
• 60 ps typical output-to-output skew
• Dual or single supply operation:
  • 3.3 V core and 3.3 V outputs
  • 3.3 V core and 2.5 V outputs
  • 2.5 V core and 2.5 V outputs
• Pin compatible with MPC940L, MPC9109
• Available in Commercial and Industrial temperature
• 32-pin TQFP package

Description

The CY29940 is a low-voltage 200-MHz clock distribution buffer with the capability to select either a differential LVPECL or a  LVCMOS/LVTTL compatible input clock. The two clock sources  can be used to provide for a test clock as well as the primary  system clock. All other control inputs are LVCMOS/LVTTL compatible. The eighteen outputs are 2.5 V or 3.3 V  LVCMOS/LVTTL compatible and can drive 50 O series or parallel  terminated transmission lines. For series terminated  transmission lines, each output can drive one or two traces giving  the device an effective fanout of 1:36. Low output-to-output  skews make the CY29940 an ideal clock distribution buffer for  nested clock trees in the most demanding of synchronous  systems.
 

Features

• Operational range: Up to 200 MHz
• LVCMOS/LVTTL clock input
• LVCMOS-/LVTTL-compatible logic input
• 18 clock outputs: Drive up to 36 clock lines
• Output-to-output Skew: 110 ps (typical)
• Output enable control
• Supply voltage: 2.5 V or 3.3 V
• Temperature range: Commercial and Industrial
• 32-pin LQFP package
• Pin compatible with MPC942C
   

Functional Description

The CY29942 is a low voltage clock distribution buffer with an LVCMOS or LVTTL compatible clock input. The output enable control input is LVCMOS/LVTTL compatible. The eighteen outputs are 2.5 V or 3.3 V LVCMOS or LVTTL compatible, operate up to 200 MHz, and can drive 50 O series or parallel terminated transmission lines. For series terminated transmission lines, each output can drive one or two traces, giving the devices an effective fanout of 1:36.
 

Features

• Output frequency up to 125 MHz
• Supports PowerPC®, and Pentium® processors
• 12 clock outputs: frequency configurable
• Configurable Output Disable
• Two reference clock inputs for dynamic toggling
• Oscillator or PECL reference input
• Spread spectrum compatible
• Glitch-free output clocks transitioning
• 3.3V power supply
• Pin compatible with SC973X
• Industrial temperature range: –40°C to +85°C
• 52-Pin TQFP package

Description

The CY29976 has an integrated PLL that provides low-skew and low-jitter clock outputs for high-performance microprocessors. Three independent banks of four outputs and an independent PLL feedback output, FB_OUT, provide exceptional flexibility for possible output configurations. The PLL is ensured stable operation given that the VCO is configured to run between 200 MHz to 480 MHz. This allows a wide range of output frequencies up to125 MHz.

Features

• Low-voltage operation
• VDD range from 2.5V to 3.3V
• 1:10 fanout
• Over voltage tolerant input hot swappable
• Drives either a 50-Ohm or 75-Ohm transmission line
• Low-input capacitance
• 250 ps typical output-to-output skew
• 19 ps typical DJ jitter
• Typical propagation delay < 3.5 ns
• High-speed operation > 500 MHz
• Industrial temperature range
• Available packages include: SSOP
   

Description

The Cypress series of network circuits are produced using advanced 0.35-micron CMOS technology, achieving the industry’s fastest logic and buffers.

The Cypress CY2CC810 fanout buffer features one input and ten outputs. Designed for data communications clock management applications, the large fanout from a single input reduces loading on the input clock.

AVCMOS-type outputs dynamically adjust for variable impedance matching and reduce noise overall.

Features

• Internal digital controlled crystal oscillator (DCXO) for continuous glitch-free operation
• Zero input-output propagation delay
• Low jitter (35 ps max RMS) outputs
• Low output-to-output skew (200 ps max)
• 4.17 MHz to 166.7 MHz reference input
• Supports industry standard input crystals
• 166.7-MHz outputs
• 5 V-tolerant Inputs
• Phase-locked loop (PLL) bypass mode
• For more, see pdf
   

Functional Description

The CY23FS04 is a FailSafe™ zero delay buffer with two reference clock inputs and four phase-aligned outputs. The device provides an optimum solution for applications where continuous operation is required in the event of a primary clock failure.

The continuous, glitch-free operation is achieved by using a DCXO. This serves as a redundant clock source in the event of a reference clock failure by maintaining the last frequency and phase information of the reference clock.

Overview:
The CY3692 socket adapter plugs into the CY3672 programmer, and is used to program the CY23FP12.

The CY3672 programming kit enables any user with a PC to quickly and easily program Field-programmable Clock Gener­ators. The only set-up requirements are a power connection and USB port (CY3672-USB) connection with the PC.

Using CyClocksRT(TM) (embedded in CyberClocks software) or CyberClocks Online, users can configure their parts to a given specification and generate the corresponding JEDEC file. In addition, CyClocksRT software provides PPM optimization and power calculations.

The JEDEC file is then loaded into CY3672 software that communicates with the programmer. The CY3672 software has the ability to read and view the EPROM table from a programmed device.

Hardware Description

The following socket adapters support the associated programming device.

Spread Aware ZDBs: CY23S02, CY23S05, CY23S08, CY23S09, CY29350/1/2, CY29774, CY29972/3/6

Theta JA = 119 °C/W
Theta JC = 44 °C/W

The voltage levels are VIHH, VIMM, and VILL on the data sheet. The ranges for the CY7B993/4V are from 0.87*VCC to V CC for VIHH, from 0.47*VCC to 0.53*VCC for V IMM, and 0.0V to 0.13*VCC for VILL. These values guarantee that the correct value will be detected. The actual thresholds (high threshold = VTHH, low threshold = VTHL) will be between the specified ranges. The voltage thresholds of typical silicon are also shown here. A MID input will typically be detected anywhere from 1.2V to 2.2V, for a 3.3V VCC.

A pull-up and pull-down resistor can model the three-level inputs of the RoboClockII family. The internal resistor values for the three-level inputs are approximately a 30-Kohm. pull-up and 30-Kohm pull-down.