The architecture TRM contains complete and detailed information about how to use and design with the IP blocks that construct a PSoC device. This document describes the analog and digital architecture to give the designer a better understanding of features and limitations.

The registers TRM covers the registers of the device. The document lists all the registers in mapping tables, in address order.

The programming specifications documents explain the hardware connections, programming protocol, programming vectors, and the timing information for developing programming solutions for a PSoC device.

Cypress’s PSoC programmable system-on-chip architecture gives you the freedom to not only imagine revolutionary new products, but the capability to also get those products to market faster than anyone else.

Hardware Description

The kit contains:

• PT100 Class B Resistive Temperature Detector (RTD)
• Type K Thermocouple
• NTC Thermistor
• 2 Temperature Diodes (2N3904 transistors)
• DS600 IC temperature sensor
• Examples projects for temperature sensing measurement, combined temperature and voltage measurement and fan control
• Includes a bonus CY8CKIT-012 PSoC Prototyping and Development Expansion Board
• Quick Start Guide
• Resource CD 

For PSoC training, please visit http://www.cypress.com/go/training

Software Title	Description	Link
PSoC Creator	This kit requires PSoC Creator for development

Introduction

PSoC 3, PSoC 4 and PSoC 5LP (hereafter referred to as "PSoC") support a wide variety of functions, called components. Many of these components are implemented using the programmable logic inside the PSoC. As a result, you can create your own components and use them in PSoC Creator projects.

1. Click on AN84741 - PSoC® 5 to PSoC 5LP Migration Guide to learn differences between PSoC 5 and PSoC 5LP.
2. Click on AN77835 - PSoC® 3 to PSoC 5LP Migration Guide to learn differences between PSoC 3 and PSoC 5LP.
3. For PSoC 5 project and related document, please download file AN82156_Archive.zip.
    

Projects associated with this application note can be downloaded from the 'Related Files' section below. For your convenience, we have provided projects that are compatible with the two most recent versions of PSoC Creator:

• AN82156.zip is used with PSoC Creator 2.1 SP1
• AN82156_Archive.zip is used with PSoC Creator 2.1/2.0

The project’s default settings may not be compatible with your device or kit, and you may need to change your project settings. For more information, see:

Notes:

1. Click on AN84741 - PSoC® 5 to PSoC 5LP Migration Guide to learn differences between PSoC 5 and PSoC 5LP.
2. Click on AN77835 - PSoC® 3 to PSoC 5LP Migration Guide to learn differences between PSoC 3 and PSoC 5LP.

The following table indicates the PSoC devices, PSoC Creator versions, compilers, and development kits that will work with this application note project:

*Refer to Migrating CY8CKIT-001 DVK project to CY8CKIT 030/ 050. 

1. Click on AN84741 - PSoC® 5 to PSoC 5LP Migration Guide to learn differences between PSoC 5 and PSoC 5LP.
2. For PSoC 5 project and related document, please download file AN60590_Archive.zip.

Projects associated with this application note can be downloaded from the ‘Related Files’ section below. For your convenience, we have provided projects that are compatible with the two most recent versions of PSoC Creator:

• AN60590.zip is used with PSoC Creator 2.1 SP1.
• AN60590_Archive.zip is used with PSoC Creator 2.1/2.0.

The project’s default settings may not be compatible with your device or kit, and you may need to change your project settings. For more information, see:

Kit Upgrade: Now it’s time to make the upgrade to PSoC® 5LP Processor Module and take advantage of all that PSoC has to offer.

These upgrades are FREE to our valued customers. Log on to http://www.cypress.com/go/psockitupgrade to know more details. Cypress appreciates your business and continued loyalty.

Kit Contents:

• PSoC Development Board 
• PSoC 1 CY8C28 Family Processor Module
• PSoC 3 CY8C38 Family Processor Module
• PSoC 5 CY8C58LP Family Processor Module
• MiniProg3 Program/Debug Device
• Program/Debug Ribbon Cable
• USB Cable
• 12V AC Power Adapter
• Quick Start Guide
• Kit CDs, which includes: PSoC Creator™, PSoC Designer™, PSoC Programmer, Projects, and Documentation

For PSoC training, please visit http://www.cypress.com/go/training.

Software Title	Description	Link
PSoC Creator	This kit requires PSoC Creator for development
PSoC Designer	This kit requires PSoC Designer for development
PSoC Programmer	This kit requires PSoC Programmer for programming

Each user module is a combination of information on the interconnections of PSoC resources and the software used to control them. It is possible to generate new UMs or customize existing UMs. Different UMs can be combined to produce a new UM. These new UMs can be similar to the old ones, with no hardware changes and only with API changes.

• Limits analog routing of a signal to a specific routing resource
• All terminals on the signal must connect directly to the routing resource

Note: Routing is strict. All of the devices connected to the net with the resource constraint must have a direct hardware connection to the resource. Refer to the Analog Routing Diagram in the applicable Technical Reference Manual (TRM), which is available from the Cypress website, www.cypress.com. If the resources do not have a hardware connection to the specified constraint, an error will occur.

General Description

The Analog Resource Constraint component allows you to define the route of the analog signal to which it is connected. This is an advanced feature that is not needed for most designs, and should be used with caution. 

Required Software: PSoC Creator 2.2 and above

• Limits analog routing of an switchable mux connection to a specific routing resource
• All terminals on the signal must connect directly to the routing resource

Note: Routing is strict. All of the devices connected to the net with the resource constraint must have a direct hardware connection to the resource. Refer to the Analog Routing Diagram in the applicable Technical Reference Manual (TRM), which is available from the Cypress website, www.cypress.com. If the resources do not have a hardware connection to the specified constraint, an error will occur.


General Description

The Analog Mux Constraint component allows you to define the route of the analog signal on the switchable mux connection to which it is connected. This is an advanced feature that is not needed for most designs, and should be used with caution.

Required Software: PSoC Creator 2.2 and above

• Connects two analog routes
• Connects a constrained analog route with an unconstrained analog route
• Connects two analog routes with different routing resource constraints

General Description

The Net Tie component connects two analog routes to each other. Each of the routes may have a different analog resource constraint.
 

Required Software: PSoC Creator 2.2 and above

• Monitor up to 32 voltage inputs
• User-defined over and under voltage limits
• Simply outputs a good/bad status result

General Description

The Voltage Fault Detector component provides a simple way to monitor up to 32 voltage inputs against user-defined over and under voltage limits without using the ADC and without having to write any firmware. The component simply outputs a good/bad status result (“power good” or pgood[x]) for each voltage being monitored.

The component operates entirely in hardware without any intervention from PSoC’s CPU core resulting in known, fixed fault detection latency.

Note: This component supports PSoC 3 and PSoC 5LP devices only.

Required Software: PSoC Creator 2.1 and above

• Supports sequencing and monitoring of up to 32 power converter rails
• Supports power converter circuits with logic-level enable inputs and logic-level power good (pgood) status outputs
• Autonomous (standalone) or host driven operation
• Sequence order, timing and inter-rail dependencies can be configured through an intuitive, easy-to-use graphical configuration GUI

General Description

The Voltage Sequencer component provides a simple way to define power-up and power-down sequencing of up to 32 power converters to meet user-defined system requirements. Once the sequencing requirements have been entered into the easy-to-use graphical configuration GUI, the component will automatically take care of the sequencing implementation without requiring any firmware development by the user.

Required Software: PSoC Creator 2.1 and above

• Provides an editor to enter the assembler instructions to configure the DFB block and an assembler that converts the assembly instructions to instruction words.
• Supports simulation of the assembly instructions.
• Supports a code optimization option that provides a mechanism to incorporate up to 128 very large instruction words inside the DFB Code RAM.
• Provides hardware signals such as DMA requests, DSI inputs and outputs, and interrupt lines.
• Supports semaphores to interact with the system software and the option to tie the semaphores to hardware signals.

General Description

The digital filter block (DFB) in PSoC 3 and PSoC 5 can be used as mini DSP processor and allows you to configure the DFB using assembly instructions. The component assembles the instructions entered in the editor and generates the corresponding hex code words, which can be loaded into the DFB. It also includes a simulator, which helps the user to simulate and debug the assembly instructions.

The DFB consists of a programmable 24*24 multiplier/accumulator (MAC), an arithmetic logic unit (ALU), shifter, and various program and data memory to store instructions and data. The DFB runs on the bus clock, and can interface with both CPU and DMA. It can be used to offload the CPU and can speed up arithmetic calculations that involve intensive multiply accumulate operations. Typical operations you can use the DFB component to implement include: vector operations, matrix operations, filtering operations, and signal processing.

Required Software: PSoC Creator 2.0 Component Pack 2 and above

• Up to four Secure Digital (SD) cards in SPI mode
• FAT12/16 or FAT32 format
• Optional integration with an Operating System (OS)
• Optional Long File Name (LFN) handling

General Description

The emFile component provides an interface to SD cards formatted with a FAT file system. The SD card specification includes multiple hardware interface options for communication with an SD card. This component uses the SPI interface method for communication. Up to four independent SPI interfaces can be used for communication with one SD card each. Both FAT12/16 and FAT32 file system formats are supported. This component provides the physical interface to the SD card and works with the emFile library licensed from SEGGER Microcontroller to provide a library of functions to manipulate a FAT file system.

Required Software: PSoC Creator 2.0 Component Pack 1 and above

Firmware Installation:  The firmware files for this component are not distributed with PSoC Creator and can be downloaded below. Please refer to the component datasheet for installation instructions.

IMPORTANT NOTICE REGARDING LONG FILE NAMES:  If you configure the software to support long file names on FAT file systems, you should review the information at http://www.microsoft.com/about/legal/en/us/IntellectualProperty/IPLicensing/Programs/FATFileSystem.aspx to determine whether a license from Microsoft is required. Cypress and its suppliers grant no license under Microsoft's intellectual property rights and assume no liability for any use of the software without obtaining any license that may be required.

PSoC^® Creator^™ emFile Component Video

• Supports 4-wire resistive touchscreen interface
• Supports the Delta Sigma Converter for both the PSoC 3 and PSoC 5 devices
• Supports the ADC Successive Approximation Register for PSoC 5 devices

This resistive touchscreen component is used to interface with a 4-wire resistive touch screen. The component provides a method to integrate and configure the resistive touch elements of a touchscreen with the emWin Graphics library. It integrates hardware-dependent functions that are called by the touchscreen driver supplied with emWin when polling the touch panel.

Required Software: PSoC Creator 2.0 Component Pack 1 and above.

• The component integrates emWin 8051 Graphic Library for PSoC3 and full-featured emWin Graphic Library V5.02 for PSoC 5
• The libraries can be used with the Keil_PK51, GCC, Keil MDK, and Keil RVDS toolchains
• Drivers are available for Graphics LCD Interface and Graphics LCD Controller components

General Description

emWin is an embedded graphic library and graphical user interface (GUI) designed to provide an efficient, processor- and LCD controller-independent GUI for any application that operates with a graphical display. It is compatible with single-task and multitask environments. Developed by SEGGER Microcontroller, emWin is extremely popular in the embedded industry. Cypress has licensed the emWin library from SEGGER and offers a full-featured graphic library free to customers.

Required Software: PSoC Creator 2.0 Component Pack 1 and above

• Use routes which remain active during sleep

General Description

To protect against unintended shorts, the SC/CT and SAR blocks disconnect their terminals when the block goes to sleep. This will also disconnect any routes (static or dynamic) which use the block terminal as a via, or use the block terminal for track jumping.

We allow the user to identify those routes which must stay awake during device sleep using the Stay Awake component, which has a single connection and no parameters. The net to which the stay_awake component is attached will be routed without using the SC/CT or SAR block terminals.

Required Software: PSoC Creator 2.0 and above

• Prevents an analog router from using an analog block terminal routing resource
• Allows safe firmware access to an analog block terminal routing resource

General Description

The Terminal Reserve component reserves the analog routing resource connected to a component, such as the analog wire connected to a comparator or pin. This is an advanced feature that is not needed for most designs, and should be used with caution.

Required Software: PSoC Creator 2.0 and above
 

• 8-, 16-, 24-bit address bus width
• 8-, 16-bit data bus width
• Supports external synchronous memory
• Supports external asynchronous memory
• Supports custom interface for memory
• Supports a range of speeds of external memories (from 5 to 200 ns)
• Supports external memory power-down, sleep, and wakeup modes

General Description

The EMIF component enables access by the CPU or DMA to memory ICs external to the PSoC 3/5LP. It facilitates setup of the EMIF hardware, as well as UDBs and GPIOs as required. The EMIF can control synchronous and asynchronous memories without the need to configure any UDBs in synchronous and asynchronous modes. In UDB mode, UDBs must be configured to generate external memory control signals.

Required Software: PSoC Creator 2.0 and above

Features

• Industry-standard NXP® I2C bus interface
• Supports Slave, Master, Multi-Master and Multi-Master-Slave operation
• Requires only two pins (SDA and SCL) to interface to I2C bus
• Supports standard data rates of 100/400/1000 kbps
• High level APIs require minimal user programming

General Description

The I2C component supports I2C slave, master, and multi-master configurations. The I2C bus is an industry-standard, two-wire hardware interface developed by Philips. The master initiates all communication on the I2C bus and supplies the clock for all slave devices.

The I2C component supports standard clock speeds up to 1000 kbps. It is compatible with I2C Standard-mode, Fast-mode, and Fast-mode Plus devices as defined in the NXP I2C-bus specification. The I2C component is compatible with other third-party slave and master devices.

Note: This version of the component datasheet covers both the fixed hardware I2C block and the UDB version.

Required Software: PSoC Creator 2.0 and above

• Available for PSoC 5 devices only (For PSoC 3 and PSoC 5LP devices, use the Segment LCD version 3.10 component)
• 2 to 768 pixels or symbols
• 1/3, 1/4, and 1/5 bias supported
• 10- to 150-Hz refresh rate
• Integrated bias generation between 2.0 V and 5.2 V with up to 128 digitally controlled bias levels for dynamic contrast control
• Supports both type A (standard) and type B (low power) waveforms
• Pixel state of the display may be inverted for negative image
• 256 bytes of display memory (frame buffer)
• User-defined pixel or symbol map with optional 7-, 14-, or 16-segment character; 5x7 or 5x8 dot matrix; and bar graph calculation routines

General Description

The Segment Display (Seg_Display) component can directly drive 3.3-V and 5.0-V LCD glass at multiplex ratios up to 16x. This component provides an easy method of configuring the PSoC device to drive your custom or standard glass.

Required Software: PSoC Creator 2.0 and above

• CAN2.0 A/B protocol implementation, ISO 11898-1 compliant
• Programmable bit rate up to 1 Mbps @ 8 MHz (BUS_CLK)
• Two or three wire interface to external transceiver (Tx, Rx, and Tx Enable)
• Driver provided and supported by Vector

General Description

The Vector CANbedded environment consists of a number of adaptive source code components that cover the basic communication and diagnostic requirements in automotive applications.

The Vector CANbedded software suite is customer specific and its operation will vary according to application and OEM. This component for the Vector CANbedded suite is written to generically support the CANbedded structure regardless of the flavor of the particular OEM application. 

Required Software: PSoC Creator 2.0 and above

• Two operating modes: Sample and Hold, Track and Hold
• Four power mode settings

General Description

The Sample/Track and Hold component provides a way to sample a continuously varying analog signal and to hold or freeze its value for a finite period of time. It supports both Track and Hold and Sample and Hold functions, which can be selected in the customizer.

Required Software: PSoC Creator 2.0 and above

• Connects two analog routes
• Connects a constrained analog route with an unconstrained analog route
• Connects two analog routes with different routing resource constraints

General Description

The Net Join component connects two analog routes to each other. Each of the routes may have a different analog resource constraint.

Required Software: PSoC Creator 2.0 and above

• Allows access to device level global signals of various types

General Description

This is the GlobalSignal reference component. It allows access to device level global signals.

Required Software: PSoC Creator 2.0 and above

• Limits analog routing of a signal to a specific routing resource
• All terminals on the signal must connect directly to the routing resource

Note: Routing is strict. All of the devices connected to the net with the resource constraint must have a direct hardware connection to the resource. Refer to the Analog Routing Diagram in the applicable Technical Reference Manual (TRM), which is available from the Cypress website, www.cypress.com. If the resources do not have a hardware connection to the specified constraint, an error will occur.


General Description

The Analog Net Constraint component allows you to define the route of the analog signal to which it is connected. This is an advanced feature that is not needed for most designs, and should be used with caution.

Required Software: PSoC Creator 2.0 and above

• Digital Multiplexer
• Digital De-Multiplexer
• Up to 16 channels>

General Description

The Multiplexer component is used to select 1 of n inputs while the De-Multiplexer component is used to route 1 signal to n outputs.

The Multiplexer component implements a 2-16 input mux providing a single output, based on hardware control signals. The De-Multiplexer component implements a 2-16 output demux from a single input, based on hardware control signals. Only 1 input or output connection may be made at a time.

Required Software: PSoC Creator v2.0 and above

• 1 to 5 Inputs
• 1 to 8 Outputs
• Configuration Tool
• Optionally Registered Outputs

General Description

You can set up the Lookup Table (LUT) component to perform any logic function with up to five inputs and eight outputs. This is done by generating logic equations that are realized in the UDB PLDs. Optionally, the outputs can be registered. These registers are implemented in PLD macrocells. All macrocell flip-flops are initialized to a 0 value at power up and after any reset of the device.

Required Software: PSoC Creator v2.0 and above

• Industry standard logic gates
• Configurable number of inputs up to 8
• Optional array of gates

General Description

Logic gates provide basic boolean operations. The output of a logic gate is a boolean combinatorial function of the inputs. There are seven basic logic gates: AND, OR, Inverter (NOT), NAND, NOR, XOR, and XNOR.

Required Software: PSoC Creator v2.0 and above

• 8 or 16 bit interface to Graphic LCD Controller
• Compatible with many graphic controller devices
• Interfaces with SEGGER emWin graphics library
• Performs Read and write transaction
• 2-255 cycles for Read Low Pulse Width
• 1-255 cycles for Read High Pulse Width
• Implements typical i8080 interface

The Graphic LCD Interface (GraphicLCDIntf) component provides the interface to a graphic LCD controller and driver device. These devices are commonly integrated into an LCD panel. The interface to these devices is commonly referred to as an i8080 interface. This is a reference to the historic parallel bus interface protocol of the Intel 8080 microprocessor.    

Required Software: PSoC Creator v2.0 and above

• Fully programmable screen size support up to HVGA resolution including:
  • QVGA (320x240) @ 60 Hz 16 bpp
  • WQVGA (480x272) @ 60 Hz 16 bpp
  • HVGA (480x320) @ 60 Hz 16 bpp
• Supports virtual screen operation
• Interfaces with SEGGER emWin graphics library
•  Performs read and write transactions during the blanking intervals
• Generation of continuous timing signals to the panel without CPU intervention
• Supports up to a 23-bit address and a 16-bit data async SRAM device used as externally provided frame buffer
• Generates a selectable interrupt pulse at the entry and exit of the horizontal and vertical blanking intervals

General Description

The Graphic LCD Controller (GraphicLCDCtrl) component provides the interface to an LCD panel that has an LCD driver, but not an LCD controller. This type of panel does not include a frame buffer. The frame buffer must be provided externally.

This component also interfaces to an externally provided frame buffer implemented using a 16-bit wide async SRAM device.

Required Software: PSoC Creator v2.0 and above

• Constant digital high or low signal

General Description

The Logic High and Logic Low components provide constant digital values and are used to hard code digital inputs. Hard coding of static inputs results in optimized resource usage and is the preferred method of providing a constant input state.

Required Software: PSoC Creator v2.0 and above

• Voltage references and supplies
• Multiple options
• Bandgap principle to achieve timer, temperature, and voltage stability

General Description

This description applies to PSoC 3 and PSoC 5 devices. The Voltage Reference (Vref) component provides one of several voltage reference outputs. The 1.024 V and 0.256 V outputs are temperature compensated using the bandgap principle to achieve excellent stability.

Required Software: PSoC Creator v2.0 and above

• Selects 1 of up to 16 inputs
• Selection is static
• Configurable number of inputs

General Description

Virtual mux components are similar to conventional muxes in that they connect a selected input to an output. For a conventional mux, the input selection can be dynamically controlled by a control signal. For a virtual mux, the input selection is determined by an expression that evaluates to a constant when used within a design. The purpose of the virtual mux is to pick one input at build time.

There are two separate virtual mux components: one analog and one digital.

Required Software: PSoC Creator v2.0 and above

• Clock enable support
• Addition of synchronization on a clock when needed

General Description

The UDBClkEn component supports precise control over clocking behavior.

Required Software: PSoC Creator v2.0 and above

• Selectable conversion gain
• Selectable corner frequency
• Compensated for capacitive input sources
• Adjustable power settings
• Selectable input reference voltage

General Description

The Trans-Impedance Amplifier (TIA) component provides an opamp-based current to voltage conversion amplifier with resistive gain and user-selected bandwidth. It is derived from the SC/CT block. 

Required Software: PSoC Creator v2.0 and above

• Synchronizes 1 to 32 input signals

General Description

The Sync component resynchronizes a set of input signals to the rising edge of the clock signal.

Required Software: PSoC Creator v2.0 and above

Features Works with most adjustable DC-DC converters or regulators including LDOs, switchers and modules Supports up to 24 DC-DC converters 8 to 10-bit resolution PWM pseudo-DAC outputs Supports real-time, closed-loop active trimming when used in conjunction with the Power Monitor component Built-in support for margining	Symbol Diagram
General Description The Trim and Margin component provides a simple way to adjust and control the output voltage of up to 24 DC-DC converters to meet system power supply requirements.

Required Software: PSoC Creator v2.0 and above

• Programmable flicker-free dimming resolution from 2 to 32 bit
• Two pulse density outputs
• Programmable output signal density
• Serial output bit stream
• Continuous run mode
• User-configurable sequence start value
• Standard or custom polynomials provided for all sequence lengths
• Kill input disables pulse density outputs and forces them low
• Enable input provides synchronized operation with other components
• Reset input allows restart at sequence start value for synchronization with other components
• Terminal Count Output for 8-, 16-, 24-, and 32-bit sequence lengths.

General Description

The Precision Illumination Signal Modulation (PrISM) component uses a linear feedback shift register (LFSR) to generate a pseudo random sequence. The sequence outputs a pseudo random bit stream, as well as up to two user-adjustable pseudo random pulse densities. The pulse densities may range from 0 to 100 percent.

Required Software: PSoC Creator v2.0 and above

• Up to 8-bit Control Register

General Description

The Control Register allows the firmware to output digital signals.

Required Software: PSoC Creator v2.0 and above

• 2 to 64 bits PRS sequence length
• Time Division Multiplexing mode
• Serial output bit stream
• Continuous or single-step run modes
• Standard or custom polynomial
• Standard or custom seed value
• Enable input provides synchronized operation with other components
• Computed pseudo random number can be read directly from the Linear Feedback Shift Register (LFSR)

General Description

The Pseudo Random Sequence (PRS) component uses an LFSR to generate a pseudo random sequence, which outputs a pseudo random bit stream. The LFSR is of the Galois form (sometimes known as the modular form) and uses the provided maximal code length, or period. The PRS component runs continuously after starting as long as the Enable Input is held high. The PRS number generator can be started with any valid seed value other than 0.

Required Software: PSoC Creator v2.0 and above

• Adjustable counter size: 8, 16, or 32 bits
• Counter resolution of 1x, 2x, or 4x the frequency of the A and B inputs, for more accurate determination of position or speed
• Optional index input to determine absolute position
• Optional glitch filtering to reduce the impact of system-generated noise on the inputs

General Description

The Quadrature Decoder (QuadDec) Component gives you the ability to count transitions on a pair of digital signals. The signals are typically provided by a speed/position feedback system mounted on a motor or trackball.

The signals, typically called A and B, are positioned 90 degrees out of phase, which results in a Gray code output. A Gray code is a sequence where only one bit changes on each count. This is essential to avoid glitches. It also allows detection of direction and relative position. A third optional signal, named Index, is used as a reference to establish an absolute position once per rotation.

Required Software: PSoC Creator v2.0 and above

• 9-bit address mode with hardware address detection
• Baud rates from 110 to 921600 bps or arbitrary up to 4 Mbps
• RX and TX buffers = 4 to 65535
• Detection of Framing, Parity, and Overrun errors
• Full Duplex, Half Duplex, TX only, and RX only optimized hardware
• Two out of three voting per bit
• Break signal generation and detection
• 8x or 16x oversampling

General Description

The UART provides asynchronous communications commonly referred to as RS232 or RS485. The UART component can be configured for Full Duplex, Half Duplex, RX only, or TX only versions. All versions provide the same basic functionality. They differ only in the amount of resources used.

Required Software: PSoC Creator v2.0 and above

• 3- to 16-bit data width
• 4 SPI modes
• Bit Rate up to 5 Mbps

General Description

The SPI Slave provides an industry-standard, 4-wire slave SPI interface. It can also provide a 3-wire (bidirectional) SPI interface. Both interfaces support all four SPI operating modes, allowing communication with any SPI master device. In addition to the standard 8-bit word length, the SPI Slave supports a configurable 3- to 16-bit word length for communicating with nonstandard SPI word lengths.

Required Software: PSoC Creator v2.0 and above

Features

• 3- to 16-bit data width
• Four SPI operating modes
• Bit Rate up to 18 Mbps

General Description

The SPI Master component provides an industry-standard, 4-wire master SPI interface. It can also provide a 3-wire (bidirectional) SPI interface. Both interfaces support all four SPI operating modes, allowing communication with any SPI slave device. In addition to the standard 8-bit word length, the SPI Master supports a configurable 3- to 16-bit word length for communicating with nonstandard SPI word lengths.     

Required Software: PSoC Creator v2.0 and above

PSoC Creator SPI Master Component video

• Adjustable shift register size: 2 to 32 bits
• Simultaneous shift in and shift out
• Right shift or left shift
• Reset input forces shift register to all 0s
• Shift register value readable by CPU or DMA
• Shift register value writable by CPU or DMA 

The Shift Register (ShiftReg) component provides synchronous shifting of data into and out of a parallel register. The parallel register can be read or written to by the CPU or DMA. The Shift Register component provides universal functionality similar to standard 74xxx series logic shift registers including: 74164, 74165, 74166, 74194, 74299, 74595 and 74597. In most applications the Shift Register component will be used in conjunction with other components and logic to create higher level application-specific functionality, such as a counter to count the number of bits shifted.   

Required Software: PSoC Creator v2.0 and above

• Up to 8-bit Status Register
• Interrupt support

General Description

The Status Register allows the firmware to read digital signals.

Required Software: PSoC Creator v2.0 and above

Features

• Master only
• 8 to 32 data bits per sample
• 16-, 32-, 48-, or 64-bit word select period
• Data rate up to 96 kHz with 64-bit word select period: 6.144 MHz
• Tx and Rx FIFO interrupts
• DMA support
• Independent left and right channel FIFOs or interleaved stereo FIFOs
• Independent enable of Rx and Tx

General Description

The Integrated Inter-IC Sound Bus (I2S) is a serial bus interface standard used for connecting digital audio devices together. The specification is from Philips® Semiconductor (I2S bus specification; February 1986, revised June 5, 1996).

PSoC Creator I2S Component Video

Required Software: PSoC Creator v2.0 and above

Features

• Defines hardware-triggered interrupts
• Provides a software method to pend interrupt

General Description

The Interrupt component defines hardware triggered interrupts. It is an integral part of the Interrupt Design-Wide Resource system (see PSoC Creator Help, Design-Wide Resources section).

There are three types of system interrupt waveforms that can be processed by the interrupt controller:

• Level – IRQ source is sticky and remains active until firmware clears the source of the request with an action (for example clear on read). Most fixed-function peripherals have level-sensitive interrupts, including the UDB FIFOs and status registers.
• Pulse – Ideally, a pulse IRQ is a single bus clock, which logs a pending action and ensures that the ISR action is only executed once. No firmware action to the peripheral is required.
• Edge – An arbitrary synchronous waveform is the input to an edge-detect circuit and the positive edge of that waveform becomes a synchronous one-cycle pulse (Pulse mode).

Required Software: PSoC Creator v2.0 and above

• Fixed-function (FF) implementation for PSoC 3 and PSoC 5 devices
• 8-, 16-, 24-, or 32-bit timer
• Optional capture input
• Enable, trigger, and reset inputs, for synchronizing with other components
• Continuous or one shot run modes

Symbol Diagram

General Description

The Timer component provides a method to measure intervals. It can implement a basic timer function and offers advanced features such as capture with capture counter and interrupt/DMA generation.

Required Software: PSoC Creator v2.0 and above

• 8- or 16-bit resolution
• Multiple pulse width output modes
• Configurable trigger
• Configurable capture
• Configurable hardware/software enable
• Configurable dead band
• Multiple configurable kill modes
• Customized configuration tool
• Fixed-function (FF) implementation for PSoC 3 and PSoC 5 devices

General Description

The PWM component provides compare outputs to generate single or continuous timing and control signals in hardware. The PWM is designed to provide an easy method of generating complex real-time events accurately with minimal CPU intervention. PWM features may be combined with other analog and digital components to create custom peripherals.

Required Software: PSoC Creator v2.0 and above

Features
 

• Buffer with Output Enable signal
• Feedback signal

General Description

The Tri-State Buffer (Bufoe) component is a non-inverting buffer with an active high output enable signal. When the output enable signal is true, the buffer functions as a standard buffer. When the output enable signal is false, the buffer turns off.

Required Software: PSoC Creator v2.0 and above

• Marks where analog features are not connected

General Description

The Analog No Connect component provides a mechanism to designate which analog connections in the schematic are intended to be left unconnected. This allows PSoC Creator to correctly determine if there are any unconnected analog components in the design that you should be made aware of.

Required Software: PSoC Creator v2.0 and above

• Wakes up devices from low-power modes: Alternate Active and Sleep
• Contains configurable option for issuing interrupt
• Generates periodic interrupts while the device is in Active mode
• Supports twelve discrete intervals: 2, 4, 8, 16, 32, 64, 128, 256, 512, 1024, 2048, and 4096 ms
   

The Sleep Timer component can be used to wake the device from Alternate Active and Sleep modes at a configurable interval. It can also be configured to issue an interrupt at a configurable interval. For PSoC 5 architectures, an interrupt is required for the CPU to wake up.

For PSoC 5, the supported intervals are restricted to: 4, 8, 16, 32, 64, 128 or 256 ms. Refer to the CyPmSleep() function description in the System Reference Guide for details about this restriction. The PSoC 5LP device supports the full set of intervals.

Required Software: PSoC Creator v2.0 and above

• Single-ended or differential inputs
• Mux or switch mode
• From 1 to 32 inputs
• Hardware controlled
• Bi-directional (passive)

General Description

The Analog Hardware Multiplexer (AMuxHw) component is used to provide hardware switchable connections from GPIOs to analog resource blocks (ARBs).

When to use an AMuxHw

The AMuxHw component should be used when a signal needs to be switched in hardware. Currently, only the GPIOs can be multiplexed with this multiplexer. Since the AMuxHw component is bidirectional, it can also be used as de-multiplexer.

Required Software: PSoC Creator v2.0 and above

• The library provides documentation for annotation components.
   

General Description

The Annotation Component library provides a way for you to mix external and internal components on the same schematic. This makes it possible to improve documentation and better understand the internal schematic and entire design. The components in this library cover the most common components that are most likely to be placed on the periphery of a PSoC device. These components consist of resistors, capacitors, transistors, inductors, switches, and others. The library is not intended to supply every possible part, but should support a wide range of designs. You can easily create your own part or parts library if your design includes a custom or unique component.

Required Software: PSoC Creator v2.0 and above

• Asynchronous reset or preset
• Synchronous reset, preset, or both
• Configurable width for array of D Flip Flops

General Description

The D Flip Flop stores a digital value.

Required Software: PSoC Creator v2.0 and above

• Gain steps from -1 to -49
• High input impedance
• Adjustable power settings

General Description

The Inverting Programmable Gain Amplifier (PGA_Inv) component implements an opamp-based inverting amplifier with user-programmable gain. It is derived from the switched capacitor/continuous time (SC/CT) block.

The inverting gain can be between -1.0 (0 dB) and -49.0 (+33.8 dB). The gain can be selected using the configuration window or changed at run time using the provided API. The maximum bandwidth is limited by the gain-bandwidth of the opamp and is reduced as the gain is increased. The input of the PGA_Inv operates from rail to rail, but the maximum input swing (difference between Vin and Vref) is limited to V_DDA/Gain. The output of the PGA_Inv is class A, and is rail to rail for sufficiently high load resistance.

Required Software: PSoC Creator v2.0 and above

Features

• Selectable resolutions, 8 to 20 bits (device dependent)
• Eleven input ranges for each resolution
• Sample rate 10 sps to 384 ksps
• Operational modes:
  • Single sample
  • Multi-sample
  • Continuous mode
  • Multi-sample (Turbo)
• High input impedance input buffer
  • Selectable input buffer gain (1, 2, 4, 8) or input buffer bypass
• Multiple internal or external reference options
• Automatic power configuration
• Up to four run-time ADC configurations

General Description

The Delta Sigma Analog to Digital Converter (ADC_DelSig) provides a low power, low noise front end for precision measurement applications. The ADC_DelSig is usable in a wide range of applications depending on resolution, sample rate and operating mode. It is capable 16-bit audio, high speed low resolution for communications processing, and high precision 20-bit low speed conversions for sensors such as strain gauges, thermocouples and other high precision sensors. When processing audio information, the ADC_DelSig is used in a continuous operation mode. When used for scanning multiple sensors, the ADC_DelSig is used in one of the multi-sample modes. When used for single point high resolution measurements, the ADC_DelSig is used in single sample mode.    

Required Software: PSoC Creator v2.0 and above

• 2 to 768 pixels or symbols
• 1/3, 1/4 and 1/5 bias supported
• 10 to 150 Hz refresh rate
• Integrated bias generation between 2.0 V and 5.2 V with up to 128 digitally controlled bias levels for dynamic contrast control
• Supports both type A (standard) and type B (low power) waveforms
• Pixel state of the display may be inverted for negative image
• 256 bytes of display memory (frame buffer)
• User-defined pixel or symbol map with optional 7-, 14-, or 16-segment character; 5x7 or 5x8 dot matrix; and bar graph calculation routines.
• Supports PSoC 3 ES3 silicon revisions and above.

General Description

The Segment LCD (LCD_Seg) component can directly drive a variety of LCD glass at different voltage levels with multiplex ratios up to 16x. This component provides an easy method of configuring the PSoC device to drive your custom or standard glass. 

Required Software: PSoC Creator v2.0 and above

Features
 

• CAN2.0A and CAN2.0B protocol implementation, ISO 11898-1 compliant
• Programmable bit rate up to 1 Mbps at 8 MHz (BUS_CLK)
• Two-wire or three-wire interface to external transceiver (Tx, Rx, and Enable)
• Extended hardware message filter that covers Data Byte 1 and Data Byte 2 fields
• Programmable transmit priority: Round Robin and Fixed
• CAN component fully supports PSoC 5LP device, but does not support PSoC 5

General Description

The Controller Area Network (CAN) controller implements the CAN2.0A and CAN2.0B specifications as defined in the Bosch specification and conforms to the ISO-11898-1 standard.

Required Software: PSoC Creator v2.0 and above

• Conforms to IEC-60958, AES/EBU, AES3 standards for Linear PCM Audio Transmission
• Sample rate support for clock/128 (up to 192 kHz)
• Configurable audio sample length (8/16/24)
• Channel status bits generator for consumer applications
• DMA support
• Independent left and right channel FIFOs or interleaved stereo FIFOs

General Description

The SPDIF_Tx component provides a simple way to add digital audio output to any design. It formats incoming audio data and metadata to create the S/PDIF bit stream appropriate for optical or coaxial digital audio. The component supports interleaved and separated audio.

Required Software: PSoC Creator v2.0 and above

• Easy user configuration of filters running on the Digital Filter Block (DFB) available in some PSoC 3, PSoC 5 and PSoC5 LP devices.
• Supports two separate filter channels, each one constructed as a cascade of up to four separately designed stages.
• Multiple FIR and IIR (Biquad) filter methods (including user coefficient entry) give great flexibility
• Final coefficient values can be extracted for further analysis

General Description

The customizer for the Filter component allows you to configure digital filters on one or two data streams passed to the Digital Filter Block (DFB), using DMA, interrupts, or polling to manage data flow. The DFB’s 128 data and coefficient locations are shared as needed between the two filter channels. The customizer reports (but does not set) the minimum bus clock frequency required to execute the filtering within the user-declared sample interval.

This component supports a huge number of use cases. If you encounter something unusual when using it, report it (with a good description of what you did to cause it) to psoc_creator_fb@cypress.com so Cypress can investigate. 

Required Software: PSoC Creator v2.0 and above

• Support for user-defined combinations of button, slider, touch pad, and proximity capacitive sensors.
• Automatic SmartSense™ tuning or manual tuning with integrated PC GUI.
• High immunity to AC power line noise, EMC noise, and power supply voltage changes.
• Optional two scan channels (parallel synchronized), which increases sensor scan rate.
• Shield electrode support for reliable operation in the presence of water film or droplets.
• Guided sensor and terminal assignments using the CapSense customizer.

General Description

Capacitive Sensing, using a Delta-Sigma Modulator (CapSense CSD) component, is a versatile and efficient way to measure capacitance in applications such as touch sense buttons, sliders, touchpad, and proximity detection.

Required Software: PSoC Creator v2.0 and above

• Accuracy of /-5° C
• Range -40° C to 140° C (0xFFD8 to 0x008C)
• Blocking and non-blocking API
• Does not support PSoC 5 silicon

General Description

The Die Temperature (DieTemp) component provides an API to acquire the temperature of the die. The System Performance Controller (SPC) is used to get the die temperature. The API includes blocking and nonblocking calls.

Required Software: PSoC Creator v2.0 and above

• 1 to 64 bits
• Time Division Multiplexing mode
• Requires clock and data for serial bit stream input
• Serial data in, parallel result
• Standard [CRC-1 (parity bit), CRC-4 (ITU-T G.704), CRC-5-USB, etc.] or custom polynomial
• Standard or custom seed value
• Enable input provides synchronized operation with other components

General Description

The default use of the Cyclic Redundancy Check (CRC) component is to compute the CRC from a serial bit stream of any length. The input data is sampled on the rising edge of the data clock. The CRC value is reset to 0 before starting or can optionally be seeded with an initial value. On completion of the bitstream, the computed CRC value may be read out.

Required Software: PSoC Creator v2.0 and above

• USB Full Speed device interface driver
• Support for interrupt, control, bulk, and isochronous transfer types
• Runtime support for descriptor set selection
• Optional USB string descriptors
• Optional USB HID class support
• Optional Bootloader support
• Optional Audio class support
• Optional MIDI devices support
• Optional CDC class support

General Description

The USBFS component provides a USB full-speed Chapter 9 compliant device framework. It provides a low-level driver for the control endpoint that decodes and dispatches requests from the USB host. Additionally, this component provides a USBFS customizer to make it easy to construct your descriptor.   

Required Software: PSoC Creator v2.0 and above

PSoC Creator USB FS Component Video

• Single or differential connections
• Adjustable between 1 and 64 connections for single AMux, 1 and 32 connections for Differential AMux
• Software controlled
• Connections may be pins or internal sources
• No simultaneous connections
• Bidirectional (passive)

General Description

The analog multiplexer sequencer (AMuxSeq) component is used to connect one analog signal at a time to a different common analog signal, by breaking and making connections in hookup-order sequence. The AMuxSeq is primarily used for time division multiplexing.

Required Software: PSoC Creator v2.0 and above

• Fixed-function (FF) implementation for PSoC 3 and PSoC 5 devices
• 8-, 16-, 24-, or 32-bit counter
• Up, down, or up-and-down configurations
• Optional compare output
• Optional capture input
• Enable and reset inputs, for synchronizing with other components
• Continuous or one shot run modes

General Description

The Counter component provides a method to count events. It can implement a basic counter function and offers advanced features such as capture, compare output, and count direction control. 

Required Software: PSoC Creator v2.0 and above

Features

• Quickly defines new clocks
• Refers to system or design-wide clocks
• Configures the clock frequency tolerance

General Description

The Clock component provides two key features: it provides allows you to create local clocks, and it allows you to connect designs to system and design-wide clocks. All clocks are shown in the Design-Wide Resources (DWR) Clock Editor.

Required Software: PSoC Creator v2.0 and above

• Rapid setup of all pin parameters and drive modes
• Allows PSoC Creator to automatically place and route signals
• Allows interaction with one or more pins simultaneously

General Description

The Pins component is the preferred way for hardware resources to connect to a physical portpin. It provides access to external signals through an appropriately configured physical IO pin. It also allows electrical characteristics to be associated with one or more pins; these characteristics are then used by PSoC Creator to automatically place and route the signals within the component.

Required Software: PSoC Creator v2.0 and above

Features

• Implements the industry standard Hitachi HD44780 LCD display driver chip protocol
• Requires only seven I/O pins on one I/O port
• Contains built-in character editor to create user-defined custom characters
• Supports Horizontal and vertical bar graphs

General Description

The Character LCD component contains a set of library routines that enable simple use of one, two, or four-line LCD modules that follow the Hitachi 44780 standard 4-bit interface. The component provides APIs to implement horizontal and vertical bar graphs, or you can create and display your own custom characters.

Required Software: PSoC Creator v2.0 and above

• Single or differential connections
• Adjustable between 1 and 64 connections for single AMux, 1 and 32 connections for Differential AMux.
• Software controlled
• Connections may be pins or internal sources
• Multiple simultaneous connections
• Bi-directional (passive)

General Description

The analog multiplexer (AMux) component can be used to connect none, one, or more analog signals to a different common analog signal. The ability to connect more than one analog signal at a time provides cross-bar switch support, which is an extension beyond traditional mux functionality.

Required Software: PSoC Creator v2.0 and above

• Separate Bootloader and Bootloadable components
• Configurable set of supported commands
• Flexible component configuration

General Description

The bootloader system manages the process of updating the device flash memory with new application code and/or data. To make the process work we use these components:

• Bootloader project - project with Bootloader and Communication components
• Bootloadable project - project with a Bootloadable component, which creates the code

Required Software: PSoC Creator v2.0 and above

Features

• Produces a selectable output voltage that is higher than the input voltage
• Input voltage range between 0.5 V and 3.6 V
• Boosted output voltage range between 1.8 V and 5.25 V
• Source up to 75 mA depending on the selected input and output voltage parameter values
• Two modes of operation: Active and Standby for PSoC 3 or Sleep for PSoC 5LP
• Boost Converter component is not supported on PSoC 5

General Description

The Boost Converter (BoostConv) component allows you to configure and control the PSoC boost converter hardware block. The boost converter enables input voltages that are lower than the desired system voltage to be boosted to the desired system voltage level. The converter uses an external inductor to convert the input voltage to the desired output voltage.

Required Software: PSoC Creator v2.0 and above

Features

• Supports PSoC 5 and PSoC 5LP devices
• 12-bit resolution at up to 1 msps maximum
• Four power modes
• Selectable resolution and sample rate
• Single-ended or differential input

General Description

The ADC Successive Approximation Register (ADC_SAR) component provides medium-speed (maximum 1-msps sampling), medium-resolution (12 bits maximum), analog-to-digital conversion.

Required Software: PSoC Creator v2.0 and above

• Low input offset
• User controlled offset calibration
• Multiple speed modes
• Low-power mode
• Output routable to digital logic blocks or pins
• Selectable output polarity
• Configurable operation mode during Sleep

General Description

The Comparator (Comp) component provides a hardware solution to compare two analog input voltages. The output can be sampled in software or digitally routed to another component. Three speed levels are provided to allow you to optimize for speed or power consumption. A reference or external voltage can be connected to either input.

You can also invert the output of the comparator using the Polarity parameter.   

Required Software: PSoC Creator v2.0 and above

• 24 channels
• Eight priority levels
• 128 Transaction Descriptors (TDs)
• 8-, 16-, and 32-bit data transfers
• Configurable source and destination addresses
• Support for endian compatibility
• Can generate an interrupt when data transfer is complete
• DMA Wizard to assist with application development

General Description

The DMA component allows data transfers to and from memory, components, and registers. The controller supports 8-, 16-, and 32-bit wide data transfers, and can be configured to transfer data between a source and destination that have different endianess. TDs can be chained together for complex operations.

Required Software: PSoC Creator v2.0 and above

• Voltage output ranges: 1.020-V and 4.080-V full scale
• Software or clock driven output strobe
• Data source can be CPU, DMA, or Digital components

General Description

The VDAC8 component is an 8-bit voltage output Digital to Analog Converter (DAC). The output range can be from 0 to 1.020 V (4 mV/bit) or from 0 to 4.08 V (16 mV/bit). The VDAC8 can be controlled by hardware, software, or a combination of both hardware and software.

Required Software: PSoC Creator v2.0 and above

Features

• Full LIN 2.1 or 2.0 Slave Node implementation
• Supports compliance with SAE J2602-1 specification
• Automatic baud rate synchronization
• Fully implements a Diagnostic Class I Slave Node
• Full transport layer support
• Automatic detection of bus inactivity
• Full error detection
• Automatic configuration services handling
• Customizer for fast and easy configuration
• Import of *.ncf/*.ldf files and *.ncf file export
• Editor for *.ncf/*.ldf files with syntax checking

General Description

The LIN Slave component implements a LIN 2.1 slave node on PSoC 3 and PSoC 5 devices. Options for LIN 2.0 or SAE J2602-1 compliance are also available. This component consists of the hardware blocks necessary to communicate on the LIN bus, and an API to allow the application code to easily interact with the LIN bus communication. The component provides an API that conforms to the API specified by the LIN 2.1 Specification.

Required Software: PSoC Creator v2.0 and above

• 1 to 61 pixels or symbols
• 10- to 150-Hz refresh rate
• User-defined pixel or symbol map with optional 7-segment, 14-segment, 16-segment and bar graph calculation routines
• Direct drive static (one common) LCDs

General Description

The Static Segment LCD (LCD_SegStatic) component can directly drive 3.3-V and 5.0-V LCD glass. This component provides an easy method of configuring the PSoC device for your custom or standard glass.

Each LCD pixel/symbol may be either on or off. The Static Segment LCD component also provides advanced support to simplify the following types of display structures within the glass:

• 7-Segment numeral
• 14-Segment alphanumeric
• 16-Segment alphanumeric
• 1- to 255-element bar graphs

Required Software: PSoC Creator v2.0 and above

• Single-ended mixer
• Continuous-time up mixing:
  • Input frequencies up to 500 kHz
  • Sample clock up to 1 MHz
• Discrete-time, sample-and-hold down mixing:
  • Input frequencies up to 14 MHz
  • Sample clock up to 4 MHz
• Adjustable power settings
• Selectable reference voltage

General Description

The Mixer component provides a single-ended modulator. The Mixer component can be used for frequency conversion of an input signal using a fixed Local Oscillator (LO) signal as the sampling clock. The manipulations of signal frequencies that a mixer performs can be used to move signals between frequency bands or to encode and decode signals. A mixer can be used to convert signal power at one frequency into power at another frequency to make signal processing easier, typically shifting higher frequencies to baseband.

Required Software: PSoC Creator v2.0 and above

Features

• Follower or Opamp configuration
• Unity gain bandwidth > 3.0 MHz
• Input offset voltage 2.0 mV max
• Rail-to-rail inputs and output
• Output direct low resistance connection to pin
• 25 mA output current
• Programmable power and bandwidth
• Internal connection for follower (saves pin)

General Description

The Opamp component provides a low-voltage, low-power operational amplifier and may be internally connected as a voltage follower. The inputs and output may be connected to internal routing nodes, directly to pins, or a combination of internal and external signals. The Opamp is suitable for interfacing with high-impedance sensors, buffering the output of voltage DACs, driving up to 25 mA; and building active filters in any standard topology.   

Required Software: PSoC Creator v2.0 and above

• Three ranges 2040 μA, 255 μA, and 31.875 μA
• Current sink or source selectable
• Software or clock driven output strobe
• Data source may be CPU, DMA, or Digital components

General Description

The IDAC8 component is an 8-bit current output DAC (Digital to Analog Converter). The output can source or sink current in three ranges. The IDAC8 can be controlled by hardware, software, or by a combination of both hardware and software.

Required Software: PSoC Creator v2.0 and above

• Multiple Alarm Options
• Multiple Overflow Options
• Daylight Saving Time (DST) Option

General Description

The Real-Time Clock (RTC) component provides accurate time and date information for the system. The time and date are updated every second based on a one pulse per second interrupt from a 32.768-kHz crystal. Clock accuracy is based on the crystal provided and is typically 20 ppm.   

Required Software: PSoC Creator v2.0 and above

Features

• Gain steps from 1 to 50
• High input impedance
• Selectable input reference
• Adjustable power settings

General Description

The PGA implements an opamp-based, non-inverting amplifier with user-programmable gain. This amplifier has high input impedance, wide bandwidth and selectable input voltage reference. It is derived from the switched capacitor/continuous time (SC/CT) block.

The gain can be between 1 (0 dB) and 50 (+34 dB). The gain can be selected using the configuration window or changed at run time using the provided API. The maximum bandwidth is limited by the gain-bandwidth product of the opamp and is reduced as the gain is increased. The input of the PGA operates from rail to rail, but the maximum input swing (difference between Vin and Vref) is limited to V_DDA/Gain. The output of the PGA is class A, and is rail to rail for sufficiently high load resistance.

Required Software: PSoC Creator v2.0 and above

• 512 B to 2 KB EEPROM memory
• 1,000,000 cycles, 20-year retention
• Read/Write 1 byte at a time
• Program 16 bytes (a row) at a time

General Description

The EEPROM component provides a set of APIs to erase and write data to nonvolatile EEPROM memory. The term write implies that it will erase and then program in one operation.

An EEPROM memory in PSoC devices is organized in arrays. PSoC 3 and PSoC 5 devices offer an EEPROM array of size 512 bytes, 1 KB or 2 KB depending on the device. This array is divided into rows of size 16 bytes each. The API set of the EEPROM component supports write operations at the byte and row levels and erase operation at the sector level. A sector in EEPROM has 64 rows.

Required Software: PSoC Creator v2.0 and above

• Industry standard NXP® I2C bus interface
• Emulates common I2C EEPROM interface
• Only two pins (SDA and SCL) required to interface to I2C bus
• Standard data rates of 50/100/400/1000 kbps
• High level APIs require minimal user programming
• Supports one or two address decoding with independent memory buffers
• Memory buffers provide configurable Read/Write and Read Only regions

General Description

The EZI2C Slave component implements an I2C register-based slave device. It is compatible with I2C Standard-mode, Fast-mode, and Fast-mode Plus devices as defined in the NXP I2C-bus specification.The master initiates all communication on the I2C bus and supplies the clock for all slave devices. The EZI2C Slave supports standard data rates up to 1000 kbps and is compatible with multiple devices on the same bus.
 

Required Software: PSoC Creator v2.0 and above

• Enable input allows d input to be selectively captured
• Configurable width for array of D Flip Flops with a single enable

General Description

The D Flip Flop w/Enable selectively captures a digital value.  Use the D Flip Flop w/ Enable to implement sequential logic.

Required Software:PSoC Creator v2.2 and above

• Represents a digital value clearly on a schematic
• Display in hexadecimal or decimal
• Configurable width up to 32 bits

The Digital Constant provides a convenient way to represent digital values in designs.  Use whenever a constant digital value is needed in a design including bit-masks and magnitude comparisons.

Required Software:PSoC Creator v2.2 and above

• Clocked for safe use in synchronous circuits
• Configurable width for array of SR Flip Flops

General Description

The SR Flip Flop stores a digital value that can be set or reset.  Use to implement sequential logic.

Required Software: PSoC Creator v2.2 and above

• T input toggles Q values
• Configurable width for array of Toggle Flip Flops with a single enable

General Description

The Toggle Flip Flop captures a digital value that can be toggled.  Use to implement sequential logic.

Required Software: PSoC Creator v2.2 and above

• 1 to 32 bit Configurable Digital Comparator
• Six selectable comparison operators

General Description

The Digital Comparator component provides a selectable-width, selectable-type comparator implemented in PLD macrocells.  Use when the digital values of two signals need to be compared.

Required Software: PSoC Creator v2.2 and above

• Detects Rising Edge, Falling Edge or Either Edge

General Description

The Edge Detector component samples the connected signal and produces a pluse when the selected edge occurs.  Use when a circuit needs to respond to a state change on a signal.

Required Software: PSoC Creator v2.2 and above

• Divides a clock or arbitrary signal by a specified value
• Enable and Reset inputs to control and align divided output

General Description

The Frequency Divider component produces an output that is the clock input divided by the specified value.  Use as a simple clock divider for UDB components or to divide the frequency of another signal.

Required Software: PSoC Creator v2.2 and above

• Supports up to four TMP05 or TMP06 digital temperature sensors connected in daisy chain mode only
• Continuous and one-shot modes of operation
• Supports frequencies from 100 to 500 kHZ
• Supports temperature range from 0 to 70 Celsius degrees

General Description

The TMP05 Temp Sensor Interface component is a simple, easy to use component capable of interfacing with Analog Device’s TMP05/06 digital temperature sensors in daisy chain mode only. You can configure the component and monitor the temperature readings in one of two ways:

• The continuous monitoring option allows you to record temperatures in a continuous fashion, at a sample rate dictated by the temperature sensor(s)
• One-shot mode triggers the temperature measurement at a rate you can control control.

The first mode is intended for use in an environment where temperature variations are abrupt and need to be monitored frequently. The second option should be used when temperature measurements only need to be sampled once in a while or in applications where minimizing power consumption is important.
 

Required Software: PSoC Creator v2.2 and above