Features

• Device Operating Voltage Options:
  • MoBL Clock M200 Family: 1.8V
• Selectable clock output voltages for both MoBL Clock M200 and M500:
  • 1.5V, 1.8V, 2.5V, 3.0V, or 3.3V
• Fully integrated ultra low power phase-locked loops (PLLs)
• Input reference clock frequency range: 1–48 MHz
• Output clock frequency range: 3–50 MHz
• Three I2C™ programmable output clocks
• Programmable output drive strengths
• For more, see pdf
   

General Description

2 Configurable PLLs

The MoBL® Clock M200/M500 Family of products are two-PLL Clock Generator ICs designed for cell phone, portable, or consumer electronics applications. It can be used to generate two independent output frequencies ranging from 3 to 50MHz from a single input reference clock.

Features

• Low jitter crystal oscillator (XO)
• Less than 1 ps typical root mean square (RMS) phase jitter
• Differential low-voltage positive emitter coupled logic (LVPECL) output
• Output frequency from 50 MHz to 690 MHz
• Frequency margining through I²C bus
• Factory-configured or field-programmable
• Integrated phase-locked loop (PLL)
• Pb-free package: 5.0 × 3.2 mm leadless chip carrier (LCC)
• Supply voltage: 3.3 V or 2.5 V
• Commercial and industrial temperature ranges
   

Functional Description

The CY2XF24 is a high-performance and high-frequency XO. It uses a Cypress-proprietary low-noise PLL to synthesize the frequency from an integrated crystal. The output frequency can be changed using the I2C bus serial interface, allowing easy frequency margin testing in applications.

Features

• Low Jitter Crystal Oscillator (XO)
• Less than 1 ps Typical RMS Phase Jitter
• Differential LVDS Output
• Output Frequency from 50 MHz to 690 MHz
• Two Frequency Margining Control Pins (FS0, FS1)
• Factory Configured or Field Programmable
• Integrated Phase-Locked Loop (PLL)
• Supply Voltage: 3.3V or 2.5V
• Pb-Free Package: 5.0 x 3.2 mm LCC
• Commercial and Industrial Temperature Ranges
   

Functional Description

The CY2XF33 is a high performance and high frequency Crystal Oscillator (XO). It uses a Cypress proprietary low noise PLL to synthesize the frequency from an integrated crystal. The output frequency can be changed through two select pins, allowing easy frequency margin testing in applications.

• One differential (LVPECL, LVDS, HCSL, or CML) input pair distributed to two LVPECL output pairs
• Translates any single-ended input signal to 3.3 V LVPECL levels with resistor bias on INx# input
• 20-ps maximum output-to-output skew
• 480-ps maximum propagation delay
• 0.15-ps maximum additive RMS phase jitter at 156.25 MHz (12-kHz to 20-MHz offset)
• Up to 1.5-GHz operation
• 8-pin SOIC or 8-pin TSSOP package
• 2.5-V or 3.3-V operating voltage
• Commercial and industrial operating temperature range
   

Functional Description

The CY2DP1502 is an ultra-low noise, low-skew, low-propagation delay 1:2 LVPECL fanout buffer targeted to meet the requirements of high-speed clock distribution applications. The device has a fully differential internal architecture that is optimized to achieve low additive jitter and low skew at operating frequencies of up to 1.5 GHz.    

The CY36800 InstaClock Universal Programmable Clock Generator Programming Kit contains the programming board with a USB cable, and 3 samples each of the CY22800 and CY22801 devices. You can order more samples of either CY22800 or CY22801 Online. The latest programming software is available to download from www.cypress.com/instaclock.

When using the CY22800 and InstaClock software, users can select from a list of over 100 different predefined configurations of commonly used frequencies in today's designs.  The CY22801 enables users to generate custom clock configurations that are not supported by the CY22800.  The CyberClocks software tool allows users to specify the XIN/CLKIN frequency, crystal load capacitance, and output frequencies for the CY22801.

Both the CY22800 and CY22801 devices are programmed through the same programming board included in this kit.  The selected configuration is then downloaded via USB to the programmer in a matter of moments.  Production quantities are easily supported by Cypress' distribution partners.  Simply provide your local distributor with the JEDEC code generated by the software.

Note: This is a programming kit only. This kit is not designed and intended to be used for device evaluation or testing purposes.

For more information, click here.

InstaClock™ CY36800 Kit Contents:

• 3 Samples of CY22800
• 3 Samples of CY22801
• 1 Programmer board with USB connector and socket onboard
• 1 USB Cable

Software Title	Description	Link
InstaClock Software	Jedec files pre-configured and Programmer software for CY22800
CyberClocks Software	Jedec file Creator and Programmer software for CY22801

Features

• Low-voltage operation VDD = 3.3V
• 1:8 fanout
• Operation to 350 MHz
• Single input configurable for LVDS, LVPECL, or LVTTL
• 8 pair of LVPECL outputs
• Drives a 50 ohm load
• Low input capacitance
• Low output skew
• Low propagation delay (tpd = 4 ns, typical)
• Commercial and Industrial temperature ranges
• 38-Pin TSSOP Package
• For more, see pdf
   

Description

The Cypress CY2DP818 fanout buffer features a single LVDS or a single ended LVTTL compatible input and eight LVPECL output pairs.

Designed for data-communications clock management applications, the large fanout from a single input reduces loading on the input clock.

The CY2DP818 is ideal for both level translations from single ended to LVPECL and/or for the distribution of LVPECL based clock signals.

The Cypress CY2DP818 has configurable input functions. The input is user configurable via the InConfig pin for single ended or differential input.

Features

• Low jitter crystal oscillator (XO)
• Less than 1 ps typical root mean square (RMS) phase jitter
• Low-voltage differential signaling (LVDS) output
• Output frequency from 50 MHz to 690 MHz
• Factory-configured or field-programmable
• Integrated phase-locked loop (PLL)
• Output enable (OE) or power-down (PD#) function
• Supply voltage: 3.3 V or 2.5 V
• Pb-free package: 5.0 x 3.2 mm leadless chip carrier (LCC)
• Commercial and industrial temperature ranges
   

Functional Description

The CY2X013 is a high-performance and high-frequency XO. The device uses a Cypress proprietary low-noise PLL to synthesize the frequency from an integrated crystal.

The CY2X013 is available as a factory-configured device or as a field-programmable device. Factory-configured devices are configured for general use or they can be customer-specific.

Features

• Low jitter crystal oscillator (XO)
• Less than 1 ps typical root mean square (RMS) phase jitter
• Differential low-voltage positive emitter coupled logic (LVPECL) output
• Output frequency from 50 MHz to 690 MHz
• Factory-configured or field-programmable
• Integrated phase-locked loop (PLL)
• Output enable or power-down function
• Supply voltage: 3.3 V or 2.5 V
• Pb-free package: 5.0 x 3.2 mm leadless chip carrier (LCC)
• Commercial and industrial temperature ranges

Functional Description

The CY2X014 is a high-performance and high-frequency XO. The device uses a Cypress proprietary low-noise PLL to synthesize the frequency from an embedded crystal.

The CY2X014 is available as a factory-configured device or as a field-programmable device. Factory-configured devices are configured for general use or they can be customer specific.

Features

• 10 MHz to 100/133 MHz operating range, compatible with CPU and PCI bus frequencies
• Zero input-output propagation delay
• 60-ps typical cycle-to-cycle jitter (high drive)
• Multiple low skew outputs
  • 85 ps typical output-to-output skew
  • One input drives five outputs (CY2305)
  • One input drives nine outputs, grouped as 4 4 1 (CY2309)
• Compatible with Pentium-based systems
• Test Mode to bypass phase-locked loop (PLL) (CY2309)
• Packages:
  • 8-pin, 150-mil SOIC package (CY2305)
  • 16-pin 150-mil SOIC or 4.4-mm TSSOP (CY2309)
• 3.3-V operation
• Commercial and industrial temperature ranges
   

Functional Description

The CY2309 is a low-cost 3.3-V zero delay buffer designed to distribute high speed clocks and is available in a 16-pin SOIC or TSSOP package. The CY2305 is an 8-pin version of the CY2309. It accepts one reference input, and drives out five low skew clocks. The -1H versions of each device operate at up to 100-/133 MHz frequencies, and have higher drive than the -1 devices. All parts have on-chip PLLs which lock to an input clock on the REF pin. The PLL feedback is on-chip and is obtained from the CLKOUT pad.

Features

• 2.5V or 3.3V operation
• 200-MHz clock support
• LVPECL or LVCMOS/LVTTL clock input
• LVCMOS-/LVTTL-compatible inputs
• 12 clock outputs: drive up to 24 clock lines
• Synchronous Output Enable
• Output three-state control
• 150 ps typical output-to-output skew
• Pin compatible with MPC948, MPC948L, MPC9448
• Available in Commercial and Industrial temp. range
• 32-pin TQFP package
   

Description

The CY29948 is a low-voltage 200-MHz clock distribution buffer with the capability to select either a differential LVPECL or a LVCMOS/LVTTL compatible input clock. The two clock sources can be used to provide for a test clock as well as the primary system clock. All other control inputs are LVCMOS/LVTTL compatible.

Features

• 12–100 MHz (CY7B9930V), or 24–200 MHz (CY7B9940V) input/output operation
• Matched pair output skew < 200 ps
• Zero input-to-output delay
• 10 LVTTL 50% duty-cycle outputs capable of driving 50ω terminated lines
• Commercial temperature range with eight outputs at 200 MHz
• Industrial temperature range with eight outputs at 200 MHz
• 3.3V LVTTL/LV differential (LVPECL), fault-tolerant and hot insertable reference inputs
• Multiply ratios of (1–6, 8, 10, 12)
• Operation up to 12x input frequency
• For more, see pdf

Functional Description

The CY7B9930V and CY7B9940V High-Speed Multifrequency PLL Clock Buffers offer user-selectable control over system clock functions. This multiple output clock driver provides the system integrator with functions necessary to optimize the timing of high performance computer or communication systems.

Features

• 10 MHz to 100–133 MHz operating range
• Zero input and output propagation delay
• Multiple low skew outputs
• One input drives five outputs (CY2305C)
• One input drives nine outputs, grouped as 4 4 1 (CY2309C)
• 50 ps typical cycle-to-cycle jitter (15 pF, 66 MHz)
• Test mode to bypass phase locked loop (PLL) (CY2309C) only
• Available in space saving 16-pin 150 Mil small outline integrated circuit (SOIC) or 4.4 mm thin shrunk small outline package (TSSOP) packages (CY2309C), and 8-pin, 150 Mil SOIC package (CY2305C)
• 3.3 V operation
• Commercial, industrial and automotive-A flows available

Functional Description

The CY2305C and CY2309C are die replacement parts for CY2305 and CY2309.

The CY2309C is a low-cost 3.3 V zero delay buffer designed to distribute high speed clocks and is available in a 16-pin SOIC or TSSOP package. The CY2305C is an 8-pin version of the CY2309C. It accepts one reference input and drives out five low skew clocks. The -1H versions of each device operate up to 100–133 MHz frequencies and have higher drive than the -1 devices. All parts have on-chip phase locked loops (PLLs) which lock to an input clock on the REF pin. The PLL feedback is on-chip and is obtained from the CLKOUT pad.

Features

• Small Footprint, 8-Pin QFN 1.7 mm x 1.7 mm x 0.6 mm Package
• Low Power and Low Jitter Operation
• Multiple Operating Voltages:
  • CY22M1S: 2.5 V, 3.0 V, or 3.3 V
  • CY22M1L: 1.8 V
• Programmable Single Output Clock Generator Frequency Range:
  • 1 to 80 MHz
• Crystal or External Reference Clock Input Frequency Range:
  • Fundamental Tuned Crystal: 8 to 48 MHz
• For more, see pdf
   

Functional Description

The MoBL® UniClock CY22M1 is a programmable, high accuracy, PLL-based clock generator device designed for low power, space constrained applications. The low jitter and accurate outputs makes this device suitable for handsets, portable media players, personal navigation devices, digital cameras, digital camcorders, and other portable applications.

Features

• Low jitter crystal oscillator (XO)
• Less than 1 ps typical root mean square (RMS) phase jitter
• Low-voltage differential signaling (LVDS) output
• Output frequency from 50 MHz to 690 MHz
• Frequency margining through I2C bus
• Factory-configured or field-programmable
• Integrated phase-locked loop (PLL)
• Pb-free package: 5.0 × 3.2 mm leadless chip carrier (LCC)
• Supply voltage: 3.3 V or 2.5 V
• Commercial and industrial temperature ranges
   

Functional Description

The CY2XF23 is a high-performance and high-frequency XO. It uses a Cypress proprietary low-noise PLL to synthesize the frequency from an integrated crystal. The output frequency can be changed using the I2C bus serial interface, allowing easy frequency margin testing in applications.

• Small Footprint, 8-Pin QFN 1.7 x 1.7 x 0.6 mm3 Package
• Low Power and Low Jitter Operation
• Multiple Operating Voltages:
  • CY22U1S: 2.5V, 3.0V, or 3.3V
  • CY22U1L: 1.8V
• Programmable Single Output Clock Generator Frequency Range:
  • 1 to 200 MHz
• Crystal or External Reference Clock Input Frequency Range
• For more, see pdf

Functional Description
 

Three PLL General Purpose EPROM Programmable Clock Generator

Features

• Three integrated phase locked loops (PLLs)
• Erasable programmable read only memory (EPROM) programmability
• Factory programmable (CY2292) or field programmable (CY2292F) device options
• Low-skew, low-jitter, high accuracy outputs
• Power management options (shutdown, OE, suspend)
• Frequency select option
• Smooth slewing on CPUCLK
• Configurable 3.3 V or 5 V operation
• 16-pin small-outline integrated circuit (SOIC) package (CY2292F also in TSSOP)

Operation

The CY2292 is a third-generation family of clock generators. The CY2292 is upwardly compatible with the industry standard ICD2023 and ICD2028 and continues their tradition by providing a high level of customizable features to meet the diverse clock generation needs of modern motherboards and other synchronous systems.

Features

• Three integrated phase-locked loops
• EPROM programmability
• Factory-programmable (CY2291) or field-programmable (CY2291F) device options
• Low-skew, low-jitter, high-accuracy outputs
• Power-management options (Shutdown, OE, Suspend)
• Frequency select option
• Smooth slewing on CPUCLK
• Configurable 3.3 V or 5 V operation
• 20-pin SOIC Package

Functional Description

The CY2291 is a third-generation family of clock generators. The CY2291 is upwardly compatible with the industry standard ICD2023 and ICD2028 and continues their tradition by providing a high level of customizable features to meet the diverse clock synchoronous systems.

All parts provide a highly configurable set of close for PC motherboard applications. Each of four configurable clock outputs (CLKA-CLKD) can be assigned 1 of 30 frequencies in any combination. Multiple outputs configured for the same or related[3] frequencies have low (<500 ps) skew, in effect providing on-chip buffering for heavily loaded signals.

Features

• Select one of two low-voltage differential signal (LVDS) input pairs to distribute to 10 LVDS output pairs
• 40-ps maximum output-to-output skew
• 600-ps maximum propagation delay
• 0.11-ps maximum additive RMS phase jitter at 156.25 MHz (12-kHz to 20-MHz offset)
• Up to 1.5-GHz operation
• Asynchronous output enable function
• 32-pin thin quad flat pack (TQFP) package
• 2.5-V or 3.3-V operating voltage [1]
• Commercial and industrial operating temperature range

Functional Description

The CY2DL15110 is an ultra-low noise, low skew, low propagation delay 1:10 LVDS fanout buffer targeted to meet the requirements of high speed clock distribution applications. The CY2DL15110 can select between two separate LVDS input clock pairs using the IN_SEL pin. The output enable function allows the outputs to be asynchronously driven to a high-impedance state. The device has a fully differential internal architecture that is optimized to achieve low additive jitter and low skew at operating frequencies of up to 1.5 GHz.

Related Documents:

Application Note: Layout Recommendations for the CY22050 and CY22150 Devices - AN1110

The CY23FP12 is a field programmable zero delay buffer. It is a high performance clock distribution device that can be customized for a wide range of applications. The CY23FP12, which integrates the functionalities of complete clock distribution solutions, takes advantage of Cypress' proprietary non-volatile memory technology to provide a fully programmable device. For prototypes, programmers are used else Cypress distributors take responsibility of programming in large volumes. 

• Jitter peak-peak (TYPICAL) = 35 ps
• LVPECL output
• Default Select option
• Serially-configurable multiply ratios
• Output edge-rate control
• 16-pin TSSOP
• High frequency
• 3.3V operation
• For more, see pdf
   

Features

• Integrated phase-locked loop (PLL)
• Field-Programmable
• Input frequency range:
• • Crystal: 8 MHz to 30 MHz
  • CLKIN: 1 MHz to 133 MHz
• Low-voltage complementary metal oxide semiconductor (LVCMOS) output frequency:
  • 1MHz to 200 MHz (commercial grade)
  • 1MHz to 166.6 MHz (industrial grade)
• For more, see pdf

General Description

The CY22801 is a flash-programmable clock generator that supports various applications in consumer and communications markets. The device uses the Cypress-proprietary PLL along with Spread Spectrum and VCXO technology to make it one of the most versatile clock synthesizers in the market. The device uses a Cypress-proprietary PLL to drive up to three configurable outputs in an 8-pin SOIC.

• Independent PWM control of up to eight LEDs
• PWM duty cycle granularity configurable to either 5 or 10% steps
• Configurable PWM frequency
• 0.4% CPU usage for 60 Hz PMW with 5% duty cycle granularity
• Maximum LED current is 25 mA
• Maximum total current load on the device is 120 mA (60 mA/side) as limited by device specifications
• In quasi closed loop current control mode, each LED requires two GPIO pins, one current limiting, and one current sensing resistor
• In explicit PWM duty cycle mode only one GPIO pin and a current limiting resistor are required
• Wizard for quick and easy LEDs configuration

Functional Description

The SmartLED User Module implements a “soft” PWM drive that provides the LED brightness/current control for up to eight independent LEDs. Configurable PWM duty cycle enables you to implement visual effects such as LED breathing.

Features

• Internal DCXO for continuous glitch-free operation
• Zero input-output propagation delay
• 100 ps typical output cycle-to-cycle jitter
• 110 ps typical output-output skew
• 1 MHz to 200 MHz reference input
• Supports industry standard input crystals
• 200 MHz (commercial), 166 MHz (industrial) outputs
• 5V-tolerant inputs
• Phase-locked loop (PLL) bypass mode
• For more, see pdf
   

Functional Description

The CY23FS08 is a FailSafe™ Zero Delay Buffer with two reference clock inputs and eight phase-aligned outputs. The device provides an optimum solution for applications where continuous operation is required in the event of a primary clock failure.

Features

• Output frequency range: 16.67 MHz to 200 MHz
• Input frequency range: 16.67 MHz to 200 MHz
• 2.5V or 3.3V operation
• Split 2.5V and 3.3V outputs
• ±2% maximum output duty cycle variation
• 11 clock outputs: drive up to 22 clock lines
• LVCMOS reference clock input
• 125 ps maximum output-output skew
• PLL bypass mode
• For more, see pdf
   

Description

The CY29352 is a low voltage high performance 200 MHz PLL based zero delay buffer designed for high speed clock distribution applications.      More...

Features

• Wide Operating Output (SSCLK) Frequency Range
  • 3 to 200 MHz
• Programmable Spread Spectrum with Nominal 31.5 kHz modulation Frequency
• Center Spread: ±0.25% to ±2.5%
• Down Spread: –0.5% to –5.0%
• Input Frequency Range
  • External crystal: 8 to 30 MHz fundamental crystals
  • External reference: 8 to 166 MHz clock
• Integrated Phase-Locked Loop (PLL)
• For more, see pdf
   

Description

The CY25200 is a programmable clock generator with spread spectrum capability. Spread spectrum modulates the output clock frequency over a small range, spreading the energy and reducing the energy peak. This is a powerful technique to reduce EMI in a variety of applications.

Features

• Fully Field-Programmable
  • Input and output dividers
  • Inverting/noninverting outputs
  • Phase-locked loop (PLL) or fanout buffer configu­ration
• 10-MHz to 200-MHz Operating Range
• Split 2.5V or 3.3V Outputs
• Two LVCMOS Reference Inputs
• Twelve Low Skew Outputs
  • 35 ps typical output-to-output skew (same frequency)
• For more, see pdf
   

Functional Description

Features

• One input to four output buffer/driver
• General-purpose or PCI-X clock buffer
• Buffers all frequencies from DC to 140 MHz
• Output-to-output skew less than 100 ps
• Space-saving 8-pin TSSOP package
• 3.3V operation
• 60 ps typical output-output skew
   

Functional Description

The CY2304NZ is a low-cost buffer designed to distribute high-speed clocks for PCI-X and other applications. The device operates at 3.3V and outputs can run up to 140 MHz.

Features

• 2.5V or 3.3V operation
• 200-MHz clock support
• LVCMOS-/LVTTL-compatible inputs
• 9-clock outputs: drive up to 18-clock lines
• Synchronous Output Enable
• Output three-state control
• 250 ps max. output-to-output skew
• Pin compatible with MPC947, MPC9447
• Available in Industrial and Commercial temp. range
• 32-pin TQFP package
   

Description

The CY29947 is a low-voltage 200-MHz clock distribution buffer with the capability to select one of two LVCMOS/LVTTL compatible clock inputs. The two clock sources can be used to provide for a test clock as well as the primary system clock. All other control inputs are LVCMOS/LVTTL compatible. The 9 outputs are LVCMOS or LVTTL compatible and can drive 50-ohm series or parallel terminated transmission lines.For series terminated transmission lines, each output can drive one or two traces giving the device an effective fanout of 1:18. The outputs can also be three-stated via the three-state input TS#. Low output-to-output skews make the CY29947 an ideal clock distribution buffer for nested clock trees in the most demanding of synchronous systems.

The CY29947 also provides a synchronous output enable input for enabling or disabling the output clocks. Since this input is internally synchronized to the input clock, potential output glitching or runt pulse generation is eliminated.

Features

• 2.5 V or 3.3 V operation
• 200-MHz clock support
• Two LVCMOS-/LVTTL-compatible inputs
• Ten clock outputs: drive up to 20 clock lines
• 1× or 1/2× configurable outputs
• Output three-state control
• 250-ps max output-to-output skew
• Pin-compatible with MPC946, MPC9446
• Available in commercial and industrial temperature range
• 32-pin TQFP package
   

Description

The CY29946 is a low-voltage 200-MHz clock distribution buffer with the capability to select one of two LVCMOS/LVTTL compatible input clocks. These clock sources can be used to provide for test clocks as well as the primary system clocks. All other control inputs are LVCMOS/LVTTL compatible. The 10 outputs are LVCMOS or LVTTL compatible and can drive 50Ω series or parallel terminated transmission lines. For series terminated transmission lines, each output can drive one or two traces giving the device an effective fanout of 1:20.

Features

• Output frequency up to 125 MHz
• 12 Clock outputs: frequency configurable
• 350 ps max. output-to-output skew
• Configurable output disable
• Two reference clock inputs for dynamic toggling
• Oscillator or crystal reference input
• Spread-spectrum-compatible
• Glitch-free output clocks transitioning
• 3.3V power supply
• Pin-compatible with MPC972
• Industrial temperature range: -40°C to +85°C
• 52-pin TQFP package
   

Description

The CY29972 has an integrated PLL that provides low skew and low jitter clock outputs for high-performance microprocessors. Three independent banks of four outputs and an independent PLL feedback output (FB_OUT) provide exceptional flexibility for possible output configurations. The PLL is ensured stable operation given that the VCO is configured to run between 200 MHz and 480 MHz. This allows a wide range of output frequencies up to125 MHz.

The phase detector compares the input reference clock to the external feedback input. For normal operation, the external feedback input (FB_IN) is connected to the feedback output (FB_OUT). The internal VCO is running at multiples of the input reference clock set by FB_SEL(0:2) and VCO_SEL select inputs (refer to Frequency Table). The VCO frequency is then divided to provide the required output frequencies. These dividers are set by SELA(0,1), SELB(0,1), SELC(0,1) select inputs (see Table 2 below). For situations were the VCO needs to run at relatively low frequencies and hence might not be stable, assert VCO_SEL low to divide the VCO frequency by 2. This will maintain the desired output relationships but will provide an enhanced PLL lock range.

Features

• Output Frequency up to 125 MHz
• 12 Clock Outputs: Frequency Configurable
• 350 ps max. Output to Output Skew
• Configurable Output Disable
• Two Reference Clock Inputs for Dynamic Toggling
• Oscillator or PECL Reference Input
• Spread Spectrum Compatible
• Glitch-free Output Clocks Transitioning
• 3.3V Power Supply
• Pin Compatible with MPC973
• Industrial Temperature Range: - 40°C to 85°C
• 52-Pin TQFP Package
   

Description

The CY29973 has an integrated PLL that provides low-skew and low-jitter clock outputs for high-performance microprocessors. Three independent banks of four outputs and an independent PLL feedback output, FB_OUT, provide exceptional flexibility for possible output configurations. The PLL is ensured stable operation given that the VCO is configured to run between 200 MHz to 480 MHz. This allows a wide range of output frequencies up to125 MHz.

• 2.5V or 3.3V operation
• 200-MHz clock support
• LVPECL or LVCMOS/LVTTL clock input
• LVCMOS/LVTTL compatible outputs
• 15 clock outputs: drive up to 30 clock lines
• 1X and 1/2X configurable outputs
• Output three-state control
• 350 ps maximum output-to-output skew
• Pin compatible with MPC949, MPC9449
• Available in Commercial and Industrial temperature range
• 52-pin TQFP package
   

Description

The CY29949 is a low voltage 200 MHz clock distribution buffer with the capability to select either a differential LVPECL or LVCMOS/LVTTL compatible input clocks. These clock sources are used to provide for test clocks and primary system clocks.      More...

Features

• 3-Multiplier configuration (1x, 2x, 4x ref)
• 10 MHz to 166.67 MHz operating range (reference input from 10 MHz to 41.67 MHz)
• Phase alignment
• 80 ps typical period jitter
• Output enable pin
• 3.3 V operation
• 5 V tolerant input
• 8-pin 150-mil small-outline integrated circuit (SOIC) package
• Commercial temperature range
   

Functional Description

The CY2303 is a 3 output 3.3 V phase-aligned system clock designed to distribute high-speed clocks in PC, workstation, datacom, telecom, and other high-performance applications.

The part allows user to obtain 1x, 2x, and 4x REFIN output frequencies on respective output pins.

Features

• 4-multiplier configuration
• Single PLL architecture
• Phase alignment
• Low jitter, high accuracy outputs
• Output enable pin
• 3.3 V operation
• 5 V tolerant input
• Internal loop filter
• 8-pin 150-mil small-outline integrated circuit (SOIC) package
• Commercial temperature
   

Functional Description

The CY2300 is a 4 output 3.3 V phase-aligned system clock designed to distribute high-speed clocks in PC, workstation, datacom, telecom, and other high-performance applications.

The part allows the user to obtain 1/2x, 1x, 1x and 2x REFIN output frequencies on respective output pins.

Features

• Spread Aware™—designed to work with SSFTG reference signals
• 90ps typical jitter OUT2
• 200ps typical jitter OUT1
• 65ps typical output-to-output skew
• 90ps typical propagation delay
• Voltage range: 3.3V±5%, or 5V±10%
• Output frequency range: 20MHz-133MHz
• Two outputs
• Configuration options allow various multiplication of the reference frequency.
• Available in 8-pin SOIC package
   

Overview

The CY23S02 is a two-output zero delay buffer and frequency multiplier. It provides an external feedback path allowing maximum flexibility when implementing the Zero Delay feature. This is explained further in the sections of this data sheet titled “How to Implement Zero Delay,” and “Inserting Other Devices in Feedback Path.”

Features

• 90 ps Typical Jitter OUT2
• 200 ps Typical Jitter OUT1
• 65 ps Typical Output-to-output Skew
• 90ps Typical Propagation Delay
• Voltage range: 3.3V±5%, or 5V±10%
• Output Frequency Range: 5 MHz to 133 MHz
• Two Outputs
• Configuration options allow various multiplications of the reference frequency.
• Available in 8-pin SOIC Package
   

Overview

The CY2302 is a two-output zero delay buffer and frequency multiplier. It provides an external feedback path allowing maximum flexibility when implementing the Zero Delay feature. This is explained further in the sections of this datasheet titled “How to Implement Zero Delay,” and “Inserting Other Devices in Feedback Path.”

The CY2302 is a pin-compatible upgrade of the Cypress W42C70-01. The CY2302 addresses some application dependent problems experienced by users of the older device.

Features

• Zero input-output propagation delay, adjustable by capacitive load on FBK input
• Multiple configurations
• Multiple low skew outputs
• Two banks of four outputs, three-stateable by two select inputs
• 10 MHz to 133 MHz operating range
• 75 ps typical cycle-to-cycle jitter (15 pF, 66 MHz)
• Space saving 16-pin 150 mil SOIC package or 16-pin TSSOP
• 3.3 V operation
• Industrial temperature available
   

Functional Description

The CY2308 is a 3.3 V Zero Delay Buffer designed to distribute high speed clocks in PC, workstation, datacom, telecom, and other high performance applications.

The part has an on-chip PLL that locks to an input clock presented on the REF pin. The PLL feedback is driven from external FBK pin, so user has flexibility to choose any one of the outputs as feedback input and connect it to FBK pin. The input-to-output skew is less than 250 ps and output-to-output skew is less than 200 ps.

• 25 MHz to 100 MHz Operating Frequency Range
• 9 different Spread Select options
• Accepts Clock and Crystal Inputs
• Low Power Dissipation:
  • 56 mW at Fin = 25 MHz
  • 89 mW at Fin = 65 MHz
  • 139 mW at Fin = 100 MHz
• Frequency Spread Disable Function
• Center Spread Modulation
• For more, see pdf
   

Features

• Three output frequencies plus reference out
• Programmable output frequencies through two-wire serial interface
• Output frequencies from 4.9152 to 148.5 MHz
• Uses an external 27 MHz crystal or 27 MHz input clock
• Optional analog VCXO
• Programmable output drive strength to minimize EMI
• The equivalent without a serial port is the CY22388/89/91
• 16-pin TSSOP package
• 3.3 V operation with 2.5 V output buffer option

General Description

The CY24488 generates up to three independent clock frequencies, and a buffered copy of the reference crystal frequency, from a single crystal or reference input. Five clock output pins are available, which allows some frequencies to be driven on two or more output pins. Outputs can also be individually enabled or disabled. When a CLK output is individually disabled, it drives low.

Features

• Crystal Oscillator with Spread Spectrum Clock (SSXO)
• No Spread Spectrum (XO) Option
• Wide operating output clock frequency range of 10 to166 MHz
• Programmable spread spectrum with nominal 31.5 kHz modulation frequency
• Center spread: ±0.25% to ±2.0%
• Down spread: –0.5% to –4.0%
• No spread: ± 0.0%
• Integrated phase-locked loop (PLL)
• 85 ps typical cycle-to-cycle jitter with SSCLK = 133 MHz
• For more, see pdf

Functional Description

The CY25701 is a Spread Spectrum Crystal Oscillator (SSXO) IC used to reduce the EMI found in today’s high speed digital electronic systems.

The device uses a Cypress proprietary PLL and Spread Spectrum Clock (SSC) technology to synthesize and modulate the frequency of the embedded input crystal. By frequency modulating the clock, the measured EMI at the fundamental and harmonic frequencies are greatly reduced.

Features

• Meets Rambus(R) Extended Data Rate (XDR(TM)) clocking requirements
• 25 ps typical cycle-to-cycle jitter
  • 135 dBc/Hz typical phase noise at 20 MHz offset
• 100 or 133 MHz differential clock input
• 300-800 MHz high speed clock support
• Quad (open drain) differential output drivers
• Supports frequency multipliers: 3, 4, 5, 6, 8, 9/2, 15/2, and 15/4
• Spread Aware(TM)
• 2.5V operation
• 28-pin TSSOP package

Functional Description

The device ID (ID0 and ID1) is a part of the SMBus device 8-bit address. The least significant bit of the address designates a write or read operation.      More...

Features

• Integrated phase locked loop (PLL)
• Low jitter, high accuracy outputs
• VCXO with analog adjust
• 3.3 V operation

Benefits

• Highest performance PLL tailored for multimedia applications
• Meets critical timing requirements in complex system designs
• Application compatibility for a wide variety of designs

• Integrated Phase-Locked Loop (PLL)
• Low Jitter, High Accuracy Outputs
• VCXO with Analog Adjust
• 3.3V Operation
• Compatible with MK3727 (–1, –4)
• Application compatibility for a wide variety of Designs
• Enables Design compatibility
• Lower Drive Strength settings (CY241V08A–04)
• For more, see pdf

Features

• Integrated phase-locked loop (PLL)
• Low jitter, high-accuracy outputs
• 3.3V operation
• 25-MHz input frequency
• 66.66-MHz or 33.33-MHz selectable output frequency (orig, -3,-11,-31)
• 33.33-MHz or 25-MHz selectable output frequency (-2,-21)

Benefits

• High-performance PLL tailored for Spread Spectrum application
• Meets critical timing requirements in complex system designs
• Enables application compatibility
• Works with commonly available crystal or driven reference
• Downspread Spread Spectrum with 30-kHz nominal modulation frequency

Features

• All output pair skew <100 ps typical (250 ps maximum)
• 3.75 MHz to 80 MHz output operation
• User selectable output functions
  • Selectable skew to 18 ns
  • Inverted and non-inverted
  • Operation at 1⁄2 and 1⁄4 input frequency
  • Operation at 2x and 4x input frequency (input as low as 3.75 MHz)
• Zero input to output delay
• 50% duty cycle outputs
• Outputs drive 50Ω terminated lines
• Low operating current
• 32-pin PLCC/LCC package
• Jitter <200 ps peak-to-peak (< 25 ps RMS)

Functional Description

The CY7B991 and CY7B992 Programmable Skew Clock Buffers (PSCB) offer user selectable control over system clock functions. These multiple output clock drivers provide the system integrator with functions necessary to optimize the timing of high performance computer systems. Each of the eight individual drivers, arranged in four pairs of user controllable outputs, can drive terminated transmission lines with impedances as low as 50Ω. They can deliver minimal and specified output skews and full swing logic levels (CY7B991 TTL or CY7B992 CMOS).

Features

• Fully Integrated Phase-Locked Loop (PLL)
• FailSafe™ Output
• 8 kHz Reference Clock
• PLL Driven by a Crystal Oscillator that is Phase Aligned with External Reference
• Selectable Standard Communication Output Frequencies
• Low Jitter, High Accuracy Outputs
• 3.3V Operation
• 16-Pin TSSOP Package
• Commercial and Industrial Temperature Ranges

Functional Description

CY26049 is a FailSafe frequency synthesizer with a reference clock input and three clock outputs. The device provides an optimum solution for applications which require continuous operation in case of primary clock failure. The continuous, glitch-free operation is achieved by using a DCXO which serves as a primary clock source.

Features

• Integrated phase-locked loop (PLL)
• Low jitter, high accuracy outputs
• 3.3V operation
• 8-pin SOIC package

Benefits

• High performance PLL tailored for mini disc applications.
• Meets critical timing requirements in complex system designs.
• Enables application compatibility.
• Industry standard package saves on board space.

• 50 to 166 MHz Operating Frequency Range
• Wide Range of Spread Selections: 9
• Accepts Clock and Crystal Inputs
• Low Power Dissipation
  • 70 mW-Typ at 66 MHz
• Frequency Spread Disable Function
• Center Spread Modulation
• Low Cycle-to-cycle Jitter
• 8-pin SOIC Package
   

General Description

CY25561 is a spread spectrum clock generator (SSCG) IC used to reduce electromagnetic Interference (EMI) found in today's high speed digital electronic systems.

CY25561 uses a Cypress proprietary Phase Locked Loop (PLL) and Spread Spectrum Clock (SSC) technology to synthesize and frequency modulate the input frequency of the reference clock. By doing this, the measured EMI at the fundamental and harmonic frequencies of clock (SSCLK) is reduced. 

Features

• Device operating voltage options:
  • MoBL® Clock M3000 family: 1.8 V
  • MoBL Clock M6000 family: 2.5 V, 3.0 V, or 3.3 V
• Selectable clock output voltages for both MoBL clock M3000 and M6000:
  • 1.5 V, 1.8 V, 2.5 V, 3.0 V, or 3.3 V
• Fully integrated ultra-low power phase-locked loops (PLLs)
• Input reference clock frequency range:
  • External crystal: 8 to 48 MHz
  • External reference: 1- to 48-MHz clock
• For more, see pdf
   

General Description

Three Configurable PLLs

The MoBL® Clock M3000/M6000 family of products are three-PLL clock generator ICs designed for cell phone, portable, or consumer electronics applications. It can be used to generate three independent output frequencies ranging from 3 MHz to 50 MHz from a single input reference clock.

Features

• Crystal oscillator with CMOS output
• Output frequency from 8 MHz to 200 MHz
• Two frequency margining control pins (FS0, FS1)
• Output enable or power-down function
• Factory configured or field programmable
• Integrated phase-locked loop (PLL)
• Supply voltage: 3.3 V or 2.5 V
• Pb-free package: 5.0 × 3.2 mm LCC
• Commercial and industrial temperature ranges
   

Functional Description

The CY2XF32 is a high performance and high frequency crystal oscillator (XO). It uses a Cypress proprietary low noise PLL to synthesize the frequency from an integrated crystal. The output frequency can be changed via two select pins, allowing easy frequency margin testing in applications.

The CY2XF32 is available as a factory configured device or as a field programmable device.

Features

• Low Jitter Crystal Oscillator (XO)
• Less than 1 ps Typical RMS Phase Jitter
• Differential LVPECL Output
• Output Frequency from 50 MHz to 690 MHz
• Two Frequency Margining Control Pins (FS0, FS1)
• Factory Configured or Field Programmable
• Integrated Phase-Locked Loop (PLL)
• Supply Voltage: 3.3V or 2.5V
• Pb-Free Package: 5.0 x 3.2 mm LCC
• Commercial and Industrial Temperature Ranges
   

Functional Description

The CY2XF34 is a high performance and high frequency Crystal Oscillator (XO). It uses a Cypress proprietary low noise PLL to synthesize the frequency from an integrated crystal. The output frequency can be changed through two select pins, allowing easy frequency margin testing in applications.

• One LVPECL Output Pair
• Selectable Frequency Multiplication: x2.5 or x5
• External Crystal Frequency: 25.0 MHz
• Output Frequency: 62.5 MHz or 125 MHz
• Low RMS Phase Jitter at 125 MHz, using 25 MHz Crystal (1.875 MHz to 20 MHz): 0.4 ps (Typical)
• Phase Noise at 125 MHz:
  

  Offset	Noise Power
  1 kHz	–117 dBc/Hz
  10 kHz	–126 dBc/Hz
  100 kHz	–131 dBc/Hz
  1 MHz	–131 dBc/Hz

• Pb-free 8-Pin TSSOP Package
• Supply Voltage: 3.3V or 2.5V
• Commercial and Industrial Temperature Ranges

Functional Description

Features

• Device Operating Voltage Options:
  • MoBL Clock M300 Family: 1.8V
  • MoBL Clock M600 Family: 2.5V, 3.0V, or 3.3V
• Selectable clock output voltages for both MoBL Clock M300 and M600:
  • 1.5V, 1.8V, 2.5V, 3.0V, or 3.3V
• Fully integrated ultra low power phase-locked loops (PLLs)
• Input reference clock frequency range: 1–48 MHz
• Output clock frequency range: 3–50 MHz
• Three I2C™ programmable output clocks
• For more, see pdf
   

General Description

3 Configurable PLLs

The MoBL® Clock M300/M600 Family of products are three-PLL Clock Generator ICs designed for cell phone, portable, or consumer electronics applications. It can be used to generate three independent output frequencies ranging from 3 to 50MHz from a single input reference clock.

Features

• Device Operating Voltage Options:
  • MoBL Clock M4000 Family: 1.8V
  • MoBL Clock M8000 Family: 2.5V, 3.0V, or 3.3V
• Selectable clock output voltages for both MoBL Clock M4000 and M8000:
  • 1.5V, 1.8V, 2.5V, 3.0V, or 3.3V
• Fully integrated ultra low power phase-locked loops (PLLs)
• Input reference clock frequency range:
  • External crystal: 8 to 48 MHz
  • External reference: 1 to 48 MHz clock
• For more, see pdf
   

General Description

4 Configurable PLLs

The MoBL® Clock M4000/M8000 Family of products are four-PLL Clock Generator ICs designed for cell phone, portable, or consumer electronics applications. It can be used to generate four independent output frequencies ranging from 3 to 50MHz from a single input reference clock.

Features

• Select one of two low-voltage positive emitter-coupled logic (LVPECL) input pairs to distribute to four LVPECL output pairs
• 30 ps maximum output-to-output skew
• 480-ps maximum propagation delay
• 0.15-ps maximum additive RMS phase jitter at 156.25 MHz (12-kHz to 20-MHz offset)
• Up to 1.5-GHz operation
• Synchronous clock enable function
• 20-pin thin shrunk small outline package (TSSOP)
• 2.5-V or 3.3-V operating voltage[1]
• Commercial and industrial operating temperature range

Functional Description

The CY2DP1504 is an ultra-low noise, low-skew, low-propagation delay 1:4 LVPECL fanout buffer targeted to meet the requirements of high-speed clock distribution applications. The CY2DP1504 can select between two separate LVPECL input clock pairs using the IN_SEL pin. The synchronous clock enable function ensures glitch-free output transitions during enable and disable periods. The device has a fully differential internal architecture that is optimized to achieve low additive jitter and low skew at operating frequencies of up to 1.5 GHz.

Features

• Select one of two low-voltage positive emitter-coupled logic (LVPECL) input pairs to distribute to 10 LVPECL output pairs
• 40-ps maximum output-to-output skew
• 600-ps maximum propagation delay
• 0.11-ps maximum additive RMS phase jitter at 156.25 MHz (12-kHz to 20-MHz offset)
• Up to 1.5-GHz operation
• 32-pin thin quad flat pack (TQFP) package
• 2.5-V or 3.3-V operating voltage
• Commercial and industrial operating temperature range

Functional Description

The CY2DP1510 is an ultra-low noise, low skew, low-propagation delay 1:10 LVPECL fanout buffer targeted to meet the requirements of high-speed clock distribution applications. The CY2DP1510 can select between two separate LVPECL input clock pairs using the IN_SEL pin. The device has a fully differential internal architecture that is optimized to achieve low additive jitter and low skew at operating frequencies of up to 1.5 GHz.

• High-frequency VCXO with LVPECL output
• Any output frequency from 50 MHz to 690 MHz
• Available either factory configured or field programmable
• Integrated phase-locked loop (PLL)
• 1 ps typical RMS Phase Jitter
• Output Enable or Power-down function
• Supply voltage: 3.3 V or 2.5 V
• Pb-free package: 5.0 × 3.2 mm LCC
• Commercial and industrial temperature ranges
• For more, see pdf

Functional Description

The CY2V014 is a high-performance high-frequency voltage-controlled crystal oscillator (VCXO).

The device uses a Cypress proprietary low-noise PLL to synthesize the frequency from an embedded crystal.

The output frequency is user adjustable by means of an analogcontrol voltage applied to the VIN pin.

Features

• 10 MHz to 220 MHz maximum operating range
• Zero input-output propagation delay, adjustable by loading on CLKOUT in
• Multiple low-skew outputs
  • 45 ps typical output-output skew-
  • One input drives nine outputs, grouped as 4 4 1
• 25 ps typical cycle-to-cycle jitter
• 15 ps typical period jitter
• Standard and High drive strength options
• Available in space-saving 16-pin 150-mil SOIC or 4.4-mm TSSOP packages
• 3.3V or 2.5V operation
• Industrial temperature available

Functional Description

The CY23EP09 is a 2.5V or 3.3V zero delay buffer designed to distribute high-speed clocks and is available in a 16-pin SOIC or TSSOP package. The -1H version operates up to 220 (200) MHz frequencies at 3.3V (2.5V), and has higher drive than the -1 devices. All parts have on-chip PLLs that lock to an input clock on the REF pin. The PLL feedback is on-chip and is obtained from the CLKOUT pad.

Features

• One LVPECL Output Pair
• Output Frequency: 312.5 MHz
• External Crystal Frequency: 25 MHz
• Low RMS Phase Jitter at 312.5 MHz, using 25 MHz crystal (1.875 MHz to 20 MHz): 0.3 ps (typical)
• Pb-Free 8-Pin TSSOP Package
• Supply Voltage: 3.3V or 2.5V
• Commercial and Industrial Temperature Ranges

Functional Description

The CY2XP311 is a PLL (Phase Locked Loop) based high performance clock generator. It is optimized to generate 10 Gb Ethernet, SONET, and other high performance clock frequencies. It also produces an output frequency that is 12.5 times the crystal frequency. It uses Cypress’s low noise VCO technology to achieve 0.3 ps typical RMS phase jitter, which meets both 10 Gb Ethernet and SONET jitter requirements. The CY2XP311 has a crystal oscillator interface input and one LVPECL output pair.

Features

• 25 MHz Crystal or Clock Input
• Four Differential 100 MHz PCI-Express Clocks
• Supports HCSL or LVDS Compatible Output Levels
• One Single-ended 25 MHz Output
• Spread Spectrum Capability on all 100 MHz PCI-Express Clock Outputs
• SMBus Interface with Read Back Capability
• 32-pin QFN Package
• Operating Voltage 3.3V
• Commercial and Industrial Operating Temperature Range

Functional Description

CY24292 is a clock generator device intended for PCI-Express applications. The device includes: four 100 MHz differential clocks with HCSL or LVDS compatible outputs for PCI-Express, and one single-ended 25 MHz output.

Features

• Spread Spectrum, VCXO, and Frequency Select
• Input frequency range:
  • Crystal: 8–30 MHz
  • CLKIN: 0.5–100 MHz
• Output frequency:
  • Commercial: 1–200 MHz
  • Industrial: 1–166 MHz
• Integrated phase-locked loop
• Low jitter, high accuracy outputs
• 3.3V operation
• 8-pin SOIC package

The CY22800 is a multi-function clock generator that supports various applications in consumer and communications markets. The device uses the Cypress proprietary PLL along with Spread Spectrum and VCXO technology to make it one of the most versatile clock synthesizers in the marketplace.

Features

• Fully integrated phase-locked loops (PLLs)
• QFN package
• 40% smaller than 20-pin TSSOP
• 22% smaller than 16-pin TSSOP
• Selectable Output Frequency
• Programmable Output Frequencies
• Output Frequency Range of 5-166 MHz
• Input Frequency Range
• Crystal: 10-30 MHz
• For more, see pdf

General Description

The CY22388 family of devices has an Analog VCXO (Voltage Controlled Crystal Oscillator), 4 PLLs, up to 8 clock outputs and frequency selection capabilities. The frequency selects do not modify any PLL frequency. Instead they allow the user to choose between up to 8 different output divider selections depending on the clock and package configuration. This is illustrated in the following Frequency Selection tables and Functional Block Diagram. 

Features

• Internal digital controlled crystal oscillator (DCXO) for continuous glitch-free operation
• Zero input-output propagation delay
• Low-jitter (35 ps max RMS) outputs
• Low output-to-output skew (200 ps max)
• 4.17 MHz to 166.7 MHz reference input
• Supports industry standard input crystals
• 166.7 MHz outputs
• 5V-tolerant inputs
• Phase-locked loop (PLL) bypass mode
• Dual reference inputs
• For more, see pdf

Functional Description

The CY23FS04-3 is a FailSafe™ zero delay buffer with two reference clock inputs and four phase-aligned outputs. The device provides an optimum solution for applications where continuous operation is required in the event of a primary clock failure. The continuous, glitch-free operation is achieved by using a DCXO, which serves as a redundant clock source in the event of a reference clock failure by maintaining the last frequency and phase information of the reference clock.

Features

• Maximized EMI suppression using Cypress’s Spread Spectrum technology
• Reduces measured EMI by as much as 10 dB
• Four skew-controlled copies of CPU output
• Four skew-controlled copies of SDRAM output
• One copy of 14.31818-MHz Reference output
• One copy of 48-MHz USB clock (not spread)
• Selectable SSFTG modulation width
• Available in 28-pin SSOP (209 mil)

Spread Spectrum Generator

The device generates a clock that is frequency modulated in order to increase the bandwidth that it occupies. By increasing the bandwidth of the fundamental and its harmonics, the amplitudes of the radiated electromagnetic emissions are reduced.

Features

• Integrated phase-locked loop (PLL)
• Commercial and industrial operation
• Flash programmable
• Field programmable
• Two-wire I2C interface
• Low skew, low jitter, high accuracy outputs
• 3.3 V operation with 2.5 V output option
• 16-pin TSSOP
• For more, see pdf

Frequency Calculation and Register Definitions

The CY22150 is an extremely flexible clock generator with four basic variables that are used to determine the final output frequency. They are the input reference frequency (REF), the internally calculated P and Q dividers, and the post divider, which can be a fixed or calculated value.

 Two Outputs PCI-Express Clock Generator

Features

• 25 MHz Crystal or Clock Input
• Two sets of Differential PCI-Express Clocks
• Pin Selectable Output Frequencies
• Supports HCSL or LVDS Compatible Output Levels
• Spread Spectrum Capability on all Output Clocks with Pin Selectable Spread Range
• 16-pin TSSOP Package
• Operating Voltage 3.3V
• Commercial and Industrial Operating Temperature Range

Functional Description

CY24293 is a two output PCI-Express clock generator device intended for networking applications. The device takes 25 MHz crystal or clock input and provides two pairs of differential outputs at 25 MHz, 100 MHz, 125 MHz, or 200 MHz for HCSL signaling standard.

Features

• Integrated phase-locked loop (PLL)
• Commercial and Industrial operation
• Flash-programmable
• Field-programmable
• Low-skew, low-jitter, high-accuracy outputs
• 3.3 V operation with 2.5 V output option
• 16-pin TSSOP package (CY22050)
• 16-pin TSSOP package with NiPdAu lead finish (CY220501)
• For more, see pdf

Functional Description

The CY22050 is programmable clock generator for use in networking, telecommunication, datacom, and other general-purpose applications. The CY22050 offers up to six configurable outputs in a 16-pin TSSOP, running off a 3.3 V power supply. The on-chip reference oscillator is designed to run off an 8–30-MHz crystal, or a 1–133-MHz external clock signal.

Features

• Three Integrated Phase-locked Loops
• Ultra Wide Divide Counters (8-bit Q, 11-bit P, and 7-bit Post Divide)
• Improved Linear Crystal Load Capacitors
• Flash Programmability
• Field Programmable
• Low-jitter, High-accuracy Outputs
• Power Management Options (Shutdown, OE, Suspend)
• Configurable Crystal Drive Strength
• Frequency Select through three External LVTTL Inputs
• 3.3V Operation
• 16-pin TSSOP Packages
• CyClocksRT™ Support

Operation

The CY22392 is an upgrade to the existing CY2292. The new device has a wider frequency range, greater flexibility, improved performance, and incorporates many features that reduce PLL sensitivity to external system issues.

The device has three PLLs which, when combined with the reference, enable up to four independent frequencies to be output on up to six pins. These three PLLs are completely programmable.

Features

• Supports clock requirements for printers
• 48-MHz spread spectrum clock output
• 48-MHz reference clock output
• Two selectable spread percentages: –1% and –3%
• Integrated loop filter
• 48-MHz crystal or external clock input
• 3.3-V supply operation (2.5-V functional)
• 8-pin small outline integrated circuit (SOIC) package

Functional Description

The CY27020 clock generator provides a low EMI clock output for printers. It features spread spectrum technology, a modulation technique designed specifically for reducing EMI at the fundamental frequency and its harmonics.

Features

• Three integrated phase-locked loops
• Ultra-wide divide counters (eight-bit Q, eleven-bit P, and seven-bit post divide)
• Improved linear crystal load capacitors
• Flash programmability
• Field programmability
• Low-jitter, high-accuracy outputs
• Power-management options (Shutdown, OE, Suspend)
• Configurable crystal drive strength
• Frequency select option through external LVTTL Input
• For more, see pdf

Operation

The CY22381 is an upgrade to the existing CY2081. The new device has a wider frequency range, greater flexibility, improved performance, and incorporates many features that reduce PLL sensitivity to external system issues.

The device has three PLLs that allow each output to operate at an independent frequencies. These three PLLs are completely programmable.

The CY223811 is the CY22381 with NiPdAu lead finish.