PSoC Programmer 3.18 offers the user a simple GUI that connects to programming hardware to program and configure PSoC, Clock, and configurable fixed function devices. Also provided with PSoC Programmer is the Bridge Control Panel, which can be used to debug, graph and log I2C serial communications using various supported Cypress Software. PSoC Programmer also provides a hardware layer for customers to design custom applications or use existing code examples for testing hardware and Firmware designs.

PSoC Programmer 3.18 release shall support both PSoC Creator and PSoC Designer in a single installation.

PSoC Programmer 3.18 is a minor release. For additional information regarding the installation and the new features please see the release notes in the downloads table below.

PSoC Programmer:

PSoC Programmer is a flexible, integrated programming application for programming PSoC devices. PSoC Programmer can be used with PSoC Designer and PSoC Creator to program any design onto a PSoC device. PSoC Programmer supports all PSoC 1, PSoC 3 and PSoC 5LP devices.

Supported PC Operating Systems:

PSoC Programmer currently supports the following windows operating systems:

• Windows XP (32/64 bit)
• Windows Vista (32/64 bit)
• Windows 7 (32/64 bit)

PSoC Programmer does not support installations on Windows 8 machines. We will be adding Windows 8 support by August of 2013.

COM Hardware Layer Supported Languages:

PSoC Programmer provides the user a hardware layer with API’s to design specific applications utilizing the programmers and bridge devices. The PSoC Programmer hardware layer is fully detailed in the COM guide documentation as well as example code across the following languages: C#, C, Perl, and Python.

PSoC Programmer Secondary Software

PSoC Programmer includes additional software beyond just PSoC Programmer. For more information on that additional software please: Click Here

Third Party IDE and Programming Support

PSoC Programmer delivers a number of files and utilities that enable 3^rd party programming and debugging support for PSoC device families. In the downloads table below we include the 3^rd party user guide which will assists the user in configuring and enabling the support in the IDEs or programming utilities. The files and applications can be found in the root installation directory for each programmer installation.

Archived Software:

PSoC Programmer software is archived at the following page: Click Here

Additional Programming Links:
Prototype Programming Hardware:

PSoC Programmer is part of a suite of programming options and programming content available to PSoC users. For customers who are looking for more information on general programming options and information please navigate to the web page linked below. On the General Programming web page we discuss all of the available programming options for customers including Software, Schematics, Programming Specifications, and 3rd party mass programming.

www.cypress.com/go/programming

All PDF documents require at least a PDF reader installed prior to opening.

There are generally two types of PLC systems: high-bandwidth (video, audio, and so on) and low-bandwidth (command and control). This application note describes how to implement a low-bandwidth, half-duplex PLC solution with the PSoC 5LP family of devices.

The following table indicates the PSoC devices, PSoC Creator versions, compilers, and development kits that will work with this application note project:

1. Click on AN84741 - PSoC® 5 to PSoC 5LP Migration Guide to learn differences between PSoC 5 and PSoC 5LP.
2. For PSoC 5 project and related document, please download file AN76458_Archive.zip.

Projects associated with this application note can be downloaded from the 'Related Files' section below. For your convenience, we have provided projects that are compatible with the two most recent versions of PSoC Creator:

• AN76458.zip is used with PSoC 5LP and PSoC Creator 2.1 SP1
• AN76458_Archive.zip is used with PSoC 5 and PSoC Creator 2.1/2.1 SP1.

The project’s default settings may not be compatible with your device or kit, and you may need to change your project settings. For more information, see:

This document is a technical reference manual for all PSoCs with a base part number of CY8C2xxxx, except for the CY8C25122 and CY8C26xxx PSoC devices. It also applies to CY7C64215, CY7C603xx,CY8CNP1xx, and CYWUSB6953.

The ICE-Cube also serves as a single-site device programmer via an ISSP (In-System Serial Programming) Cable and MiniEval board included in the kit. The MiniEval board is a programming and evaluation board which connects to the ICE-Cube via an ISSP Cable and allows programming of DIP devices. There are also other Programming boards available for programming other packages. The MiniEval also includes LEDs and a POT for simple evaluation and demonstration.

PSoC 1 Debugger Includes:

• PSoC Designer Software CD-ROM
• ICE-Cube In-Circuit Emulator
• ICE Flex-Pod for CY8C29xxx Family
• Backward compatibility Cat-5 Adapter
• ISSP Cable
• Mini-Eval Programming Board in One
• USB 2.0 Cable and Blue Cat-5 Cable
• 110 ~ 240V Power Supply, Euro-Plug Adapter
• 2 CY8C29466-24PXI 28-PDIP Chip Samples

Supports following 8 bit PSoC1 (Programmable System-On Chip) families, including automotive, except CY8C25/26xxx devices.

PSoC 1 Getting Started Debugging - Part 1 - The Hardware

PSoC 1 Getting Started Debugging - Part 2 - The PSoC Designer

Software Title	Description	Link
PSoC Designer	This kit requires PSoC Designer for development
PSoC Programmer	This kit requires PSoC Programmer for programming

Related Resources:

PSoC Designer 5.0 SP6 will continue to be available for System Level Design users, and it will co-exist with future PSoC Designer 5.1 releases. However, we are not recommending System Level Design for production designs.

We suggest users to use the latest version of PSoC Designer located here:

www.cypress.com/go/psocdesigner

PSoC Designer 5.0 SP6 supports Internet Explorer 6 through 8, but does not support Internet Explorer 8 Beta or Internet Explorer 9 due to compatibility issues.

To Install PSoC Designer 5.0 SP6 users must first have PSoC Programmer installed first. For the latest release of PSoC Programmer please, Click Here

PSoC Designer 5.0 PS6 was tested using Beta version of Windows 7. PSoC Designer 5.0 SP6 is not supported for Windows 7 systems.

To Install:

Shut Down any currently running instances of PSoC Designer.

If an earlier service pack of PSoC Designer 5.0 is currently installed, uninstall it. To do this please navigate to Start>Control Panel>Add or Remove Programs.

• Install latest PSoC Programmer.
• Install PSoC Designer 5.0 SP6 by running the installed in the downloads table below.”

Note to HI-TECH Compiler Users:

There are new devices in this release. To compile projects containing these devices with the HI-TECH compiler, you must manually update the psoc.ini file. The HI-TECH psoc.ini file is found in the HI-TECH installation folder. The default location of the psoc.ini is here:

C:\Program Files\HI-TECH Software\HCPSOC\PRO\9.61\dat\psoc.ini

The default location of the replacement psoc.ini file that adds support for the new devices is here:

C:\Program Files\Cypress\Common\CypressSemiBuildMgr\tools\psoc.ini

PSoC Programmer: The latest version of PSoC Programmer must be installed along with PSoC Designer. For the latest release please navigate to the PSoC Programmer web page: Click Here

PSoC Designer: User Guides - Click Here

PSoC Designer Archive - Click Here

 
Features:

• User friendly PLC Control Panel Application available on kit CD
• CY8CPLC20-OCD – 100-pin TQFP on-chip debug (OCD) device that allows quick design and debug of a PLC application. The CY8CPLC20 100-pin TQFP is available for debug purposed only. For production quantities, CY8CPLC20 is available in 28-pin SSOP and 48-pin QFN packages.
• Chip power supply derived from 90V to 264V AC
• User configurable general purpose LEDs
• General purpose 8-bit DIP switch
• On board surge protection and isolation circuit
• RJ45 connector to use ICE debugger
• RS232 COM port for communication
• Header to attach LCD card
• I2C header for communicating to external device
• ISSP header for programming the CY8CPLC20

 
Kit Contents:

• CY3274 Quick Start Guide
• CY3274 PLC HV Development Board
• CDs containing:
  • Packet Test Software – PLC Control Panel Application
  • CY8CPLC20 Data Sheet
  • Development Board User Guide
  • Application Note – Using CY8CPLC20 in Powerline Communication (PLC) Applications
  • CY3274 Board Schematics
  • CY3274 Board Gerbers
  • PSoC Designer™
  • PSoC Programmer
• AC Power Cable
• MiniProg1 to Program CY8CPLC20
• 25 Jumper Wires
• LCD Module
• USB-I2C Bridge
• Retractable USB Cable
• Five CY8CPLC20-28PVXI Device Samples

Software Title	Description	Link
PSoC Designer	This kit requires PSoC Designer for development
PSoC Programmer	This kit requires PSoC Programmer for programming
Powerline Communcation	PLC Contol Panel Application

Cypress’ Powerline Communication (PLC) devices (CY8CPLC10, CY8CPLC20 and CY8CLED16P01) provide a secure and reliable solution that integrates a Powerline PHY modem and Powerline optimized network protocol with CSMA into single device. These devices work with an external Powerline coupling circuit and power supply, which may need to be designed to meet certain compliance standards and specifications. This application note describes the design of these circuits and provides an overview of the commonly encountered compliance specifications along with guidelines on selection of critical components necessary to meet these specifications. 

In this video it is shown, how Cypress's Powerline Communication solution can be used to control LED lighting.

• 6-bit resolution with 32X oversampling to 14-bit resolution with 256X oversampling
• Data in unsigned or signed 2’s complement formats
• Maximum sample rates of 65,500 sps at 6 bit resolution, 7812 sps at 14-bit resolution
• Sinc² filter fully implemented in hardware reduces CPU overhead and anti-alias requirements
• 1st-Order or 2nd-Order modulator, user selectable
• Input range defined by internal and external reference options
• Optional synchronized PWM Output

The DelSig is an integrating converter, requiring from 32 to 256 integration cycles to generate a single output sample. Changing multiplexed inputs, invalidates the first two samples following the change.

• The 8-bit general purpose counter uses one PSoC block
• Source clock rates up to 48 MHz
• Automatic reload of period on terminal count
• Programmable pulse width
• Input enables/disables continuous counter operation
• Interrupt option on compare output or terminal count
   

The 8-Bit Counter User Module provides a down counter with a programmable period and pulse width. The clock and enable signals can be selected from any system time base or external source. Once started, the counter operates continuously and reloads its internal value from the period register upon reaching terminal count. During each clock cycle, the counter compares the current count to the value stored in the compare register. Each clock cycle, the Counter tests the count against the value of the compare register for either a “less than" or “less than or equal to" condition. The comparator output provides a logic level that may be routed to pins and to other user modules. Most PSoC device families also permit the terminal count output to be routed in the same manner.

Features

• Powerline Communication Solution
• Powerful Harvard Architecture Processor
• Programmable System Resources (PSoC® Blocks)
• Flexible On-Chip Memory
• Programmable Pin Configurations
• Additional System Resources
• Complete Development Tools
• For more, see pdf
   

PLC Functional Overview

The CY8CPLC20 is an integrated Powerline Communication (PLC) chip with the Powerline Modem PHY and Network Protocol Stack running on the same device. Apart from the PLC core, the CY8CPLC20 also offers Cypress's revolutionary PSoC technology that enables system designers to integrate multiple functions on the same chip.

Features

• Integrated Powerline Modem PHY
• 2400 bps Frequency Shift Keying Modulation
• Powerline Optimized Network Protocol
• Integrates Data Link, Transport, and Network Layers
• Supports Bidirectional Half-Duplex Communication
• 8-bit CRC Error Detection to Minimize Data Loss
• I2C enabled Powerline Application Layer
• Supports I2C Frequencies of 50, 100, and 400 kHz
• Reference Designs for 110V to 240V AC, 12V to 24V AC/DC Powerlines
• Reference Designs Comply with CENELEC EN50065-1:2001 and FCC Part 15
   

Functional Overview

The CY8CPLC10 is an integrated Powerline Communication chip with the Powerline Modem PHY and Powerline Network Protocol Stack. This chip provides robust communication between different nodes on a Powerline.

• One PLC20Q Pod
• One Flex cable
• Two 48QFN Feet

 
Features:

• User friendly PLC Control Panel Application available on the kit CD
• Chip power supply derived from 110V to 240V AC
• On-chip powerline bridge application layer, powerline network protocol layer, and physical layer FSK modem
• LED status indicators for Power, Powerline Transmit and Receive, and Band in Use.
• Five-position DIP switches
  • Three DIP switches for manual powerline node logical address selection
  • One DIP switch to configure I2C slave address
  • One DIP switch to select between external crystal and oscillator
• On board surge protection and isolation circuit
• Integrated Powerline Modem PHY
   

Kit Contents:

• CY3272 Quick Start Guide
• One CY3272 PLC HV Evaluation Board
• CD containing:
  • Packet Test Software – PLC Control Panel Application
  • CY8CPLC10 Data Sheet
  • CY3272 Evaluation Board User Guide
  • Application Note – Using CY8CPLC10 in Powerline Communication (PLC) Applications
  • CY3272 Board Schematics
  • CY3272 Board Gerbers
• AC Power Cable
• USB-I2C Bridge
• Ribbon Cable for I2C communication, External Reset, and Powering External Board
• Retractable USB Cable
• Five CY8CPLC10-28PVXI Device Samples

Software Title	Description	Link
PSoC Designer	This kit requires PSoC Designer for development
PSoC Programmer	This kit requires PSoC Programmer for programming
Powerline Communcation	PLC Contol Panel Application

Kit content:

• One PLC20 Pod
• One Flex cable
• Two 28SSOP Feet
• One 28 Pin Mask

• Chip power supply derived from 12V to 24V AC/DC
• On-chip powerline bridge application layer, powerline network protocol layer, and physical layer FSK modem
• LED status indicators for Power, Powerline Transmit and Receive, and Band in Use
• Five-position DIP switches
  • Three DIP switches for node logical address selection
  • One DIP switch to configure node I2C addressing mode
  • One DIP switch to select between the external crystal and oscillator
• Integrated Powerline Modem PHY
   

Kit Contents:

• CY3273 Quick Start Guide
• CY3273 PLC LV Evaluation Board
• CD containing:
  • CY8CPLC10 Data Sheet
  • Packet Test Software – PLC Control Panel Application
  • CY3273 Evaluation Board User Guide
  • Application Note – Using CY8CPLC10 in Powerline Communication (PLC) Applications
  • CY3273 Board Schematics
  • CY3273 Board Gerbers
• 12V Power Supply
• Cable to Create LV Daisy Chain
• USB-I2C Bridge
• Five Wire Ribbon Cable for I2C communication, External Reset, and Powering External Board
• Retractable USB Cable
• Five CY8CPLC10-28PVXI Device Samples

Software Title	Description	Link
PSoC Designer	This kit requires PSoC Designer for development
PSoC Programmer	This kit requires PSoC Programmer for programming
Powerline Communcation	PLC Contol Panel Application

The CY3277 kit is obsolete as of June 22, 2011. If you are looking for a low voltage (12V – 24V AC/DC) Powerline Communication kit please see: CY3273 kit here: www.cypress.com/go/CY3273 and CY3275 kit here: www.cypress.com/go/CY3275

Please contact Cypress customer support if you have any questions. Call 1-800-541-4736 and select 8 or email us at customercare@cypress.com

The CY3276 kit is obsolete as of June 22, 2011. If you are looking for a high voltage (110V – 240V AC) Powerline Communication kit please see: CY3272 kit here: www.cypress.com/go/CY3272 and CY3274 kit here: www.cypress.com/go/CY3274

Please contact Cypress customer support if you have any questions. Call 1-800-541-4736 and select 8 or email us at customercare@cypress.com

•       Is any other Cypress software running that has connected to the USBI2C bridge? The USBI2C Bridge can only be connected to using one program at a time. Examples of other software that uses the bridge are PSoC Programmer and Bridge Control Panel. Close all the open Cypress programs and restart the PLC Control Panel.
•       Is the USBI2C bridge connect to the PC and does it appear in the USB-I2C bridges section of the Control Panel as shown below. If it does not appear please uninstall and reinstall the latest build of PSoC Programmer and restart the PLC Control Panel application. A green LED should power on the USBI2C bridge once it is successfully connected to the PC.

• Is the bridge connected to the I2C header of the board? For the CY3272, the I2C header is J5. For the CY3273, the I2C header is J8. For the CY3274 and CY3275, the I2C header is J15. A picture showing the correct connection is shown below for the CY3273 kit. It is similar for all the other kits.

• Is the correct I2C bridge selected? If you have two bridges connected to the PC as shown below, choose the one that is connected to the board you are trying to connect to. Use the Blink GRN LED button to blink the led on the USBI2C bridge that is currently selected.

• Is the correct I2C slave address selected? For the CY3272/3, the I2C address can be configured by the I2C DIP (S1) switch on the board. When this switch is in the off position, the I2C address is 0x01 and when it is on, the I2C address is 0x7A. For the CY3274/5, the USB-I2C bridge can only connect to FSK Modem + Network Modem + I2C Bridge option of the PLT User Module. The I2C slave address is a configurable property of the User Module. The user module property value is in decimal form, while the Control Panel GUI I2C address is in hexadecimal form. For example if the user module I2C Slave Address property is set to 15, the Control Panel should connect to the PLC Address “0f” by selecting the “Other” option.
• If the “USBI2C options” is set to “+5V PWR”, make sure a jumper is placed on the USBI2C bridge at the J1 position and make sure there is no jumper on the PWR jumper header of the PLC board. When the connect button is clicked, a red LED on the USBI2C bridge should turn on. If it is set to “EXT. PWR” place a jumper on the PWR jumper header of the PLC board. The red LED on the USBI2C bridge should begin to blink.

          Note that the USBI2C bridge can connect with any I2C Clock Rate.

• If the connection is successful, the GUI should display a PLC #0 Connected in the status bar as shown in the picture below.

The available values can be found in the CY8CPLC10 data sheet or the PLT User Module datasheet in PSoC Designer. If you are using PSoC Designer, the value can be configured using the PLT User Module property Noise Level Threshold. Note that this property is only available for the “FSK Modem” and “FSK Modem + Network Stack” selection. The “FSK Modem + Network Stack + I2C Bridge” selection and the CY8CPLC10 device require an external host to change this value by writing to the Threshold Noise register.

The BIU can also be disabled completely by setting the Disable BIU bit in the PLC Mode register [Offset 0x05].

Figure3. CY3275 jumper layout

Figure4. CY3274 jumper layout

When there are multiple independent networks sharing the same Powerline grid, it is important to bind the nodes (e.g. slave host only processes messages from the master’s source address, or the nodes use a unique key in the payload or the additional byte in the extended address to define the network).

1. Isolation Transformer for the Coupling Circuit (T1).
2. Power Transformer EE-16 for the Power Supply (T2).
3. 24mH Common Mode Choke for the Power Supply (T3).

The datasheets for T1, T2 and T3 are also attached with this KB.

The following transformer options were tested:                                                                   

1. Renco EE16 Flyback Transformer SS40213 (T2).
2. Pulse Engineering PE-65812 (T1)
3. Myrra 74714 (T1)
4. VAC 5024-X044 (T1)

Note that changing the transformer will require the PLC design to be recertified for compliance. Please open a support case asking for the transformer test report if you would like more information on the tests that were conducted and the results.

Also, before the packet starts being transmitted, a constant frequency tone is transmitted for the duration set by Modem_TXDelay, which is located in the  Modem_Config register (0x31). For 1200bps, the minimum delay required is 19ms. For 600bps, the minimum delay required is 25ms. For 1800bps and 2400bps, the delay can be any value.

Lastly, it takes ~15ms to process the packet.

Therefore, the maximum amount of time allowed between calls to PLT_Poll() is:

t_{PLT_Poll}      < 500ms - processing time – transmit delay - (acknowledgment packet length * t_BYTE)

The following maximum durations are for the longest packets (22 bytes) at each of the baud rates:

2400bps : t_{PLT_Poll} < 500ms – 15ms – 7ms – (22 * 5ms) = 368ms

1800bps : t_{PLT_Poll} < 500ms – 15ms – 7ms – (22 * 6.7ms) = 330ms

1200bps : t_{PLT_Poll} < 500ms – 15ms – 19ms – (22 * 10ms) = 246ms

600bps   : t_{PLT_Poll} < 500ms – 15ms – 25ms – (22 * 20ms) = 20ms

Note that if using an external host (e.g. Cypress Powerline Control Panel GUI), the durations may need to be shorter (<50ms in the case of the GUI) because the host may expect a status update sooner.

1)   External 32.768 kHz Crystal only: This clocking option requires an external 32.768 kHz crystal that connects to pins P1[0] and P1[1]. Additionally, there should be a 22pF capacitor between P1[0] and VDD and a second 22pF capacitor between P1[1] and VDD. Lastly, a 0.1 uF bypass capacitor should be placed between P1[3] (XTAL_Stability) and GND.
In PSoC Designer, the following settings should be made:

a.    32K_Select = “External”

b.    PLL_Mode = Ext_Lock

c.     SysClk Source = “Internal”

d.    P1[0] Select = “XtalOut” and Drive = “StdCPU”

e.    P1[1] Select = “XtalIn” and Drive = “StdCPU”

For more details, refer to application note AN2027 “Using the PSoC Microcontroller External Crystal Oscillator”. Also, as a reference, the CY3274 High Voltage Powerline Communication Development Kit has the external crystal circuitry.

2)   External 32.768 kHz crystal and 24 MHz clock oscillator: This clocking option requires an external 32.768 kHz crystal that connects to pins P1[0] and P1[1]. Additionally, there should be a 22pF capacitor between P1[0] and VDD and a second 22pF capacitor between P1[1] and VDD. Lastly, a 0.1 uF bypass capacitor should be placed between P1[3] (XTAL_Stability) and GND.
Also, this clocking option requires an external 24 MHz clock oscillator connected to pin P1[4]. Additionally, the oscillator will need to be powered by VCC and should have appropriate decoupling. It should be placed as closed to the pin as possible to reduce EMI.
In PSoC Designer, the following settings should be made (note that the external clock oscillator will not be selected until run-time. This is to set up the device so that the switch can be made at run-time):

a.    32K_Select = “External”

b.    PLL_Mode = “Disable”

c.     SysClk Source = “Internal”

d.    P1[0] Select = “XtalOut” and Drive = “StdCPU”

e.    P1[1] Select = “XtalIn” and Drive = “StdCPU”

f.     P1[4] Select = “ExtSysClk” and Drive = “High Z”

At run-time, the following code should be inserted at the beginning of main.c to switch the SysClk source to the external 24 MHz clock oscillator from the IMO:

        int i;

for (i=0; i<254; i++)

{

M8C_ClearWDT;

}

OSC_CR2 |= (OSC_CR2_EXTCLKEN | OSC_CR2_IMODIS | OSC_CR2_SYSCLKX2DIS);

As a reference, the CY3274 High Voltage Powerline Communication Development Kit has the external clock oscillator and external crystal circuitry.

1)   Properties Window: In the chip view, the parameters can be modified individually in the properties window. This is the traditional way of statically setting the parameter values prior to run-time. However, when there are many parameters (e.g. when “FSK Modem + Network” user module option is selected), this is the slowest method of setting the parameters.

2)   PLC Config Wizard: Right-click on the PLT_1 user module instance and select “PLC Config Wizard”. This will open the wizard, which allows the user to quickly set all of     the parameters prior to run-time. However, this method cannot be used for changing the parameters at run-time.

3)   PLT_Memory_Array variable: In the application code, the parameters can be set by writing to the PLT_Memory_Array variable. The constants for the address offset and bit names are listed in plt.h.  The bit mapping and description of each of the parameters in the PLT_Memory_Array can be found in the data sheet. This method has the advantage of being able to modify the parameters at run-time. Note: For the “FSK Modem Only” user module option, only register offsets 0x30 through 0x34 and 0x6A through 0x72 are available.

To control multiple PLC nodes, open multiple instances of the Control Panel GUI. Every instance of the Control Panel GUI will show all the USB – I2C bridges connected to the PC. Selecting a different bridge in every instance of the Control Panel GUI will enable the user to control multiple PLC nodes from the same PC.

With the Control Panel GUI, users can easily evaluate the features provided by Cypress’s Powerline Communication solution, configure the FSK Modem, transmit and receive data packets between multiple PLC nodes.

Before transmitting an I2C message, the host can check the TX_LED pin to see if there is an ongoing PLC transmission. There is a short time (<1 ms) that the TX LED is off and the I2C interrupts are disabled, but this will at least reduce the likelihood of temporarily stalling the I2C bus.

Additionally, the host can monitor the PLC device's HOST_IRQ pin to check if there is a status update instead of continuosly polling via I2C.

1. Go to www.cypress.com.  On the top right, you will see a “Keyword / Part Number” search box (adjacent to “Contact Us.”) 

2. Select the “Part Number” tab above this text box.

3. Type the exact part number, for example CY8C29466-12PVXE.

4. The part number will be listed in the search results page.

5. Click on the part number link (1st column starting from the left). This will open a new web page.

Moisture Sensitivity Level (MSL) can be found by clicking the “Quality & Pb-free Data” link on the top, or by just scrolling down to the Quality & Pb-free Data” section about half way down the page.

All other Quality information for this part number (e.g., RoHS compliance, Lead/Ball Finish, Qualification Reports, IPC reports) can also be found on this web page. 

In case of any questions, or if the information is not available for a particular part number, please create a support case at www.cypress.com/support

If you do not know the Cypress part number: 

1. Go to www.cypress.com.  Browse the different products (“Products” tab on the top navigation menu) by family.

2. Once you choose the relevant product family (e.g., “Clocks and Buffers->Clock Distribution,” “Memory->FIFOs”), scroll down the particular page to get to the “Parametric Product Selector.”

3. Use this tool to find the part number by function/feature, and click on the part number you are interested in. This will lead you directly to step # 5 above.

1. Install the PLC Control Panel onto your PC. The latest version of the Control Panel can be downloaded from http://www.cypress.com/?rID=38135.
2. Install and run PSoC Programmer from the Kit CD or download the latest version from http://www.cypress.com/?rID=38050
3. Set the device family to CY8C-PLC-LED16P, programming mode to reset and enable Auto Detection. Plug the MiniProg provided with the kit into your PC.
4. The firmware for the CY8CPLC20 Kits (CY3274, CY3275) can be found in Control Panel installation folder. The default location for this is C:\Program Files\Cypress\PLC Control Panel\. The firmware for the PLC20 Kits is PLC20_FW_5.8.hex. Load the correct file for your kits from PSoC Programmer.
5. Make sure the device is powered and then program the board. Make sure the MiniProg is attached onto header J21 on the board.
6. After the programming is complete and successful, remove the MiniProg and reset the board.
7. You can now use Section 1.3 of the PLC Control Panel User Guide to connect and use the board with the GUI.

Additionally, to increase the receiver impedance of the system, the RC filter input to the receiver can be changed to an RLC filter that is tuned to 132kHz. This is shown in the attached schematics for R52, C4, C5, and the addition of L5.

The schematics labeled “CY3273 RevStarStar Modified” have the potential improvements. The changes are circled in blue in both schematics.

Additional settings that may provide a slight improvement in performance are lowering the Baud Rate from 2400bps and increasing the Transmit Delay from 7ms. If testing with 1200bps (Modem_BPS_MASK = 0b01), the Transmit Delay must be set to >=12ms (TX_Delay != 0x00). If testing with 600bps (Modem_BPS_MASK = 0b00), the Transmit Delay must be set to >=18ms (TX_Delay = 0b10 or 0b11).

The FSK Bandwidth (Deviation) should be set to 130.4kHz - 133.3kHz (Modem_FSK_BW_MASK = '1').

If using the CY8CPLC20, setting the CPU frequency to 24MHz (Sysclk/1) will give the best performance.

If using the CY8CPLC10 device, refer to the CY8CPLC10 data sheet for more details on setting these parameters. If using the CY8CPLC20 device, refer to the Powerline Transceiver (PLT) User Module data sheet for more details on setting these parameters.

Cypress’s Powerline Communication (PLC) solution enables the implementation of robust and reliable communication over AC and DC Powerlines. With Cypress’s PLC solution, you do not need new wires to transmit command and control data — you can reuse the existing infrastructure. Cypress’s PLC family of devices (CY8CPLC10, CY8CPLC20, and CY8CLED16P01) combines revolutionary PSOC® technology with reliable Powerline Communication to allow integration of multiple system functions in a single device, thereby reducing BOM costs and providing a smarter way to implement command and control. FCC- and CENELEC-compliant boards and complete network protocol implementation from Cypress accelerate time-to-market.

See the attached Hirose20PinDescription.jpg file for the pin description of this connector.

The schematic of CY3250 flex cable can be viewed at this link:- http://www.cypress.com/?docID=2975

These connections can also be verified by checking the continuity between pin nos. 4,5,8,9,12,13,16,17 as all of them are grounded. 

This problem may be because of slow internet connection.

The workaround is to use ISO file of the Designer, it can be downloaded by clicking on "PSoC Designer" under "Software" from our website.

After downloading the ISO file, burn it on a CD and this CD can be used for installing Designer without the need of internet connection.

Click the download links below for a high-resolution images of the PLC solution, block diagrams and other images.