The video describes the case of using a DMA to buffer ADC data. Buffering of 20 bit ADC data is taken as an example and discussed. The video also gives a preview of the project implementing the 20 bit data buffering and explains the DMA configuration in code.

The following table indicates the PSoC devices, PSoC Creator versions, compilers, and development kits that will work with this application note project:

*Refer to Migrating CY8CKIT-001 DVK project to CY8CKIT 030/ 050. 

Notes:

1. Click on AN84741 - PSoC® 5 to PSoC 5LP Migration Guide to learn differences between PSoC 5 and PSoC 5LP.
2. Click on AN77835 - PSoC® 3 to PSoC 5LP Migration Guide to learn differences between PSoC 3 and PSoC 5LP.
3. For PSoC 5 project and related document, please download file AN61102_Archive.zip.

Projects associated with this application note can be downloaded from the ‘Related Files’ section below. For your convenience, we have provided projects that are compatible with the two most recent versions of PSoC Creator:

• AN61102.zip is used with PSoC Creator 2.1 SP1
• AN61102_Archive.zip is used with PSoC Creator 2.1/2.0

The project’s default settings may not be compatible with your device or kit, and you may need to change your project settings. For more information, see:

With PSoC Creator, you can:

• Create and share user-defined, custom peripherals using hierarchical schematic design and Verilog entry
• Automatically place and route selected components and integrate simple glue logic normally residing in discrete muxes or 22V10s
• Trade-off hardware and software design considerations allowing you to focus on what matters: getting to market fast

PSoC Creator also allows you to tap into an entire tools ecosystem with integrated compiler tool chains, RTOS solutions and top production programmers to support PSoC 3, PSoC 5 and PSoC 5LP.
 

New Features in Creator 2.2

• Project Datasheet Generation
• Component Distribution (Import/Export)
• Rename Annotation Components to External / Off-Chip
• New DWR Parameter – “Variable Vdda”
• Binding Error Symbols
• Peripheral Register Debug in IDEs
• MISRA Support for Automotive Applications
• Datapath Editor Enhancements

Additional Information and Documentation

Further details on this release are available in the Release Notes. Additionally, a Migration Guide is also available to aid in the process of porting designs into the latest PSoC Creator toolset.

System Configuration

The following minimum configuration is required for installation of the PSoC Creator 2.2 application. See the release notes for details on performance expectations in resource constrained systems.

• Windows Operating System
  • Windows XP SP2 or SP3
  • Windows Vista (32- and 64-bit supported) and SP1
  • Windows 7 (32- and 64-bit supported) and SP1
  • MacOS v10 with Parallels Desktop v6 running Windows XP SP3
• 1 GHz CPU
• 512 MB RAM (minimum), 1 GB RAM (preferred)
• 2 GB of hard disk space
• USB 2.0
• 1024x768 screen resolution  

PSoC Creator Training

Need help downloading/installing? Call 1-800-541-4736 and select 8.

The TMP05 Digital Temperature Sensor Interface Component is a building block for thermal management applications. It enables designers using PSoC 3 to quickly and easily interface with Analog Devices’ TMP05 or TMP06 digital temperature sensors through a simple, serial 2-wire digital interface. The sensors can be daisy-chained together, minimizing I/O requirements on the controller. For more details on the specific functions of the TMP05 Digital Temperature Sensor Interface Component, refer to the component datasheet.

Notes:

1. Click on AN84741 - PSoC® 5 to PSoC 5LP Migration Guide to learn differences between PSoC 5 and PSoC 5LP.
2. For PSoC 5 project and related document, please download file AN65977_Archive.zip.

Projects associated with this application note can be downloaded from the 'Related Files' section below. For your convenience, we have provided projects that are compatible with the two most recent versions of PSoC Creator:

• AN65977.zip is used with PSoC Creator 2.1 SP1
• AN65977_Archive.zip is used with PSoC Creator 2.1/2.0

The project’s default settings may not be compatible with your device or kit, and you may need to change your project settings. For more information, see:

The document AN66477 - PSoC® 3 and PSoC 5 Temperature Measurement with Thermistor is currently being reviewed and updated to support the new Thermistor Component available in PSoC Creator 2.1. The updated application note is expected by 11/30/2012. The below abstract describes what this application note covers. If you have an immediate need for this document, please click here to create a technical support case requesting this material. 

Please note that the Thermistor Component is now provided in PSoC Creator 2.1. Please access the Thermistor Component Datasheet for features and configuration details. 

AN66477 Abstract:

AN66477 explains how to measure temperature with a thermistor using PSoC® 3 or PSoC 5LP®. This application note describes the PSoC Creator™ Thermistor Calculator Component, which simplifies the math-intensive resistance-to-temperature conversion. In addition, we discuss a PSoC Creator thermistor measurement project.

1. Click on AN84741 - PSoC® 5 to PSoC 5LP Migration Guide to learn differences between PSoC 5 and PSoC 5LP.
2. Click on AN77835 - PSoC® 3 to PSoC 5LP Migration Guide to learn differences between PSoC 3 and PSoC 5LP.

• 8-, 16-, 24-bit address bus width
• 8-, 16-bit data bus width
• Supports external synchronous memory
• Supports external asynchronous memory
• Supports custom interface for memory
• Supports a range of speeds of external memories (from 5 to 200 ns)
• Supports external memory power-down, sleep, and wakeup modes

General Description

The EMIF component enables access by the CPU or DMA to memory ICs external to the PSoC 3/5LP. It facilitates setup of the EMIF hardware, as well as UDBs and GPIOs as required. The EMIF can control synchronous and asynchronous memories without the need to configure any UDBs in synchronous and asynchronous modes. In UDB mode, UDBs must be configured to generate external memory control signals.

1. Click on AN84741 - PSoC® 5 to PSoC 5LP Migration Guide to learn differences between PSoC 5 and PSoC 5LP.

In addition, this application note walks you through an example project for PSoC 5LP. Through this project example, PSoC Creator is introduced. The first part of the project guides you on how to blink an LED like a typical MCU. In the second part you develop a "breathing" LED using the Programmable-System-On-Chip concept.

An additional bonus project is included with this application note that takes a design example a little farther than simply blinking LEDs. The bonus project uses some of the mixed signal functionality of PSoC 5LP to create an ambient light/dark detector using one of the LEDs on the CY8CKIT-050 demonstration board. 

The following table indicates the PSoC devices, PSoC Creator versions, compilers, and development kits that will work with this application note project:

*Refer to Migrating CY8CKIT-001 DVK project to CY8CKIT 030/050.

1. Click on AN84741 - PSoC® 5 to PSoC 5LP Migration Guide to learn differences between PSoC 5 and PSoC 5LP.
2. For PSoC 5 project and related document, please download file AN77759_Archive.zip.
3. Click on AN77835, PSoC 3 to PSoC 5LP Migration Guide. to learn differences between PSoC 3 and PSoC 5LP

Projects associated with this application note can be downloaded from the 'Related Files' section below. For your convenience, we have provided projects that are compatible with the two most recent versions of PSoC Creator:

• AN77759.zip is used with PSoC Creator 2.1 SP1
• AN77759_Archive.zip is used with PSoC Creator 2.1/2.0

The project’s default settings may not be compatible with your device or kit, and you may need to change your project settings. For more information, see:

Architecture:

PSoC 3/PSoC 5/PSoC 5LP has total of 24 UDBs. Each UDB mainly consists of: 8 macrocells, PLA (which can implement 16 Product terms), 1 datapath cell, 1 Control cell and 1 Status cell.

Altera MAXV 570ZM device has a total of 570 Logic elements. Each logic element consists of: One 4-input LUT and One register (D flip-flop).

Lattice MACHXO2 256HC device has a total of 128 slices. Each slice consists of: Two 4-input LUTs and Two registers (D flip-flop).

Xilinx XC2C384 consists of 24 Function blocks. Each function block consists of 16 Macrocells and a PLA (which can implement 56 Pterms).

Conclusion:

Data from the above table shows that the PSoC 3/PSoC 5/PSoC 5LP UDB utilization is comparable to:

Mid to higher end CPLDs from Altera MAXV series

Mid to higher end CPLDs from Xilinx Cool runner series

Lower end to mid range FPGAs from Lattice’s MACHXO2 series

The following table indicates the PSoC devices, PSoC Creator versions, compilers, and development kits that will work with this application note project:

Refer to Migrating CY8CKIT-001 DVK project to CY8CKIT 030/ 050.

Kit Upgrade: Now it’s time to make the upgrade to PSoC® 5LP Processor Module and take advantage of all that PSoC has to offer.

These upgrades are FREE to our valued customers. Log on to http://www.cypress.com/go/psockitupgrade to know more details. Cypress appreciates your business and continued loyalty.

Kit Contents:

• PSoC Development Board 
• PSoC 1 CY8C28 Family Processor Module
• PSoC 3 CY8C38 Family Processor Module
• PSoC 5 CY8C58LP Family Processor Module
• MiniProg3 Program/Debug Device
• Program/Debug Ribbon Cable
• USB Cable
• 12V AC Power Adapter
• Quick Start Guide
• Kit CDs, which includes: PSoC Creator™, PSoC Designer™, PSoC Programmer, Projects, and Documentation

For PSoC training, please visit http://www.cypress.com/go/training.

Software Title	Description	Link
PSoC Creator	This kit requires PSoC Creator for development
PSoC Designer	This kit requires PSoC Designer for development
PSoC Programmer	This kit requires PSoC Programmer for programming

Introduction

PSoC® 3 and PSoC 5LP have a powerful clocking system. This system offers the flexibility and performance to suit the needs of most embedded applications. It is comprised of clock sources and a clock distribution network. The clock sources available are the internal main oscillator (IMO), external crystal oscillators (ECO) and internal low-speed oscillator (ILO). This application note describes the IMO and ILO as well a method to improve their accuracy through run-time calibration.

The following table indicates the PSoC devices, PSoC Creator versions, compilers, and development kits that will work with this application note project:

Notes:

1. Click on AN84741 - PSoC® 5 to PSoC 5LP Migration Guide to learn differences between PSoC 5 and PSoC 5LP.
2. Click on AN77835 - PSoC® 3 to PSoC 5LP Migration Guide to learn differences between PSoC 3 and PSoC 5LP.
3. For PSoC 5 project and related document, please download file AN80248_Archive.zip.

Projects associated with this application note can be downloaded from the 'Related Files' section below. For your convenience, we have provided projects that are compatible with the two most recent versions of PSoC Creator:

• AN80248.zip is used with PSoC Creator 2.1 SP1
• AN80248_Archive.zip is used with PSoC Creator 2.1/2.0

The project’s default settings may not be compatible with your device or kit, and you may need to change your project settings. For more information, see:

Introduction

The DMA controller (DMAC) in PSoC 3 and PSoC 5LP can transfer data from a source to a destination with no CPU intervention. This allows the CPU to handle other tasks while the DMA does data transfers, thereby achieving a „multiprocessing‟ environment.

The PSoC DMA Controller (DMAC) is highly flexible – it can seamlessly transfer data between memory and on chip peripherals including ADCs, DACs, Filter, USB, UART, and SPI. There are 24 independent DMA channels.

 The following video gives the user a brief description of how to use the DMA on PSoC3 and the different parameters related to it:

The following table indicates the PSoC devices, PSoC Creator versions, compilers, and development kits that will work with this application note project:

 *Refer to Migrating CY8CKIT-001 DVK project to CY8CKIT 030/ 050. 

1. Click on AN84741 - PSoC® 5 to PSoC 5LP Migration Guide to learn differences between PSoC 5 and PSoC 5LP.
2. For PSoC 5 project and related document, please download file AN52705_Archive.zip.

Projects associated with this application note can be downloaded from the ‘Related Files’ section below. For your convenience, we have provided projects that are compatible with the two most recent versions of PSoC Creator:

• AN52705.zip is used with PSoC Creator 2.1 SP1
• AN52705_Archive.zip is used with PSoC Creator 2.1/2.0

The project’s default settings may not be compatible with your device or kit, and you may need to change your project settings. For more information, see:

This processor module must be used in conjunction with the PSoC Development Kit (CY8CKIT-001) to create designs utilizing on-board DVK resources or compatible expansion boards. This kit provides you with an additional processor module to use with different projects.

Kit Contents:

• PSoC® CY8C58LP Family Processor Module
• Kit CD, which includes: PSoC Creator™, PSoC Programmer, and Documentation

For PSoC training, please visit  http://www.cypress.com/go/training .

Software Title	Description	Link
PSoC Creator	This kit requires PSoC Creator for development
PSoC Programmer	This kit requires PSoC Programmer for programming

Note: The installation file will install the sample projects onto your system

• Eliminates unwanted “glitch” pulses on digital input lines
• Programmable filtering length and bypass option
  
   

General Description

Glitch filtering is the process of removing unwanted pulses from a digital input signal that is usually high or low. Glitches frequently occur on lines carrying signals from sources such as RF receivers. Electrical or in some cases even mechanical interference can trigger an unwanted glitch pulse from the receiver.

This design outputs a ‘1’ only when the current and previous N samples are ‘1’, and a ‘0’ only when the current and previous N samples are ‘0’. Otherwise the output is unchanged from its current value.

For more details on glitch filtering please see application note AN60024.

Required Software: PSoC Creator 2.1 Component Pack 4 and above.

• USB Clock for Full-Speed operation – 48 MHz (+0.25% tolerance).
• UART with 8x oversampling, voting enabled, the tolerance for tclock: ±3.9%
• UART with 16x oversampling, voting enabled, he tolerance for tclock: ±4.6%
• The accuracy of CAN CLK_BUS must be at least 1.58% for 125 Kbps and slower bit rates

  For bit rates faster than 125 Kbps, the accuracy of CAN CLK_BUS must be 0.5% or better.

Therefore, the project that uses IMO as clock source with USB/UART/CAN does not work in PSoC Creator 2.0 or later version. You must use an external crystal-base for clocking the device when using USB, CAN, and UART communication. For USB communication, you must use a 24-Mhz external crystal.

Refer to AN54439 - PSoC® 3 and PSoC 5 External Crystal Oscillators for more details on how to configure hardware and firmware for PSoC 3 or PSoC 5 using the integrated oscillator subsystems and external resonators.

To get introduced to basics of PSoC 3 and PSoC 5LP Bootloader please refer  AN73854 - PSoC® 3 and PSoC 5LP - Introduction to Bootloaders. If you intend to learn how to develop I2C Bootloader for PSoC 3 and PSoC 5LP,  AN60317 - PSoC® 3/PSoC 5LP I2C Bootloader  should get you going. 

Since the projects involve the use of USB component, in case of PSoC 5LP it is mandatory to use an external 24 MHz crystal.

The Bootloader GUI provided with this App Note has been tested to work on full-fledged Windows operating system only.
The GUI is not tested and not guaranteed to work on Virtual machines.
 

*Refer to Migrating CY8CKIT-001 DVK project to CY8CKIT 030/ 050. 

Notes:

1. Click on AN84741 - PSoC® 5 to PSoC 5LP Migration Guide to learn differences between PSoC 5 and PSoC 5LP.
2. Click on AN77835 - PSoC® 3 to PSoC 5LP Migration Guide to learn differences between PSoC 3 and PSoC 5LP.
3. For PSoC 5 project and related document, please download file AN73503_Archive.zip.

Projects associated with this application note can be downloaded from the ‘Related Files’ section below. For your convenience, we have provided projects that are compatible with the two most recent versions of PSoC Creator:

• AN73503.zip is used with PSoC Creator 2.1 SP1
• AN73503_Archive.zip is used with PSoC Creator 2.1/2.0

The project’s default settings may not be compatible with your device or kit, and you may need to change your project settings. For more information, see:

• Asynchronous reset or preset
• Synchronous reset, preset, or both
• Configurable width for array of D Flip Flops

General Description

The D Flip Flop stores a digital value.

Required Software: PSoC Creator v1.0 Beta 5 and above

Features

• Produces a selectable output voltage that is higher than the input voltage
• Input voltage range between 0.5 V and 3.6 V
• Boosted output voltage range between 1.8 V and 5.25 V
• Source up to 75 mA depending on the selected input and output voltage parameter values
• Two modes of operation: Active and Standby for PSoC 3 or Sleep for PSoC 5LP
• Boost Converter component is not supported on PSoC 5

General Description

The Boost Converter (BoostConv) component allows you to configure and control the PSoC boost converter hardware block. The boost converter enables input voltages that are lower than the desired system voltage to be boosted to the desired system voltage level. The converter uses an external inductor to convert the input voltage to the desired output voltage.

Required Software: PSoC Creator v1.0 Beta 5 and above

• Gain steps from -1 to -49
• High input impedance
• Adjustable power settings

General Description

The Inverting Programmable Gain Amplifier (PGA_Inv) component implements an opamp-based inverting amplifier with user-programmable gain. It is derived from the switched capacitor/continuous time (SC/CT) block.

The inverting gain can be between -1.0 (0 dB) and -49.0 (+33.8 dB). The gain can be selected using the configuration window or changed at run time using the provided API. The maximum bandwidth is limited by the gain-bandwidth of the opamp and is reduced as the gain is increased. The input of the PGA_Inv operates from rail to rail, but the maximum input swing (difference between Vin and Vref) is limited to V_DDA/Gain. The output of the PGA_Inv is class A, and is rail to rail for sufficiently high load resistance.

Required Software: PSoC Creator v1.0 Beta 5 and above

• Interfaces to up to 32 DC-DC power converters
• Measures power converter output voltages and load currents using a DelSig-ADC
• Monitors the health of the power converters generating warnings and faults based on user-defined thresholds
• Support for measuring other auxiliary voltages in the system
• Support 3.3V and 5V chip power supply

General Description

Power Converter Voltage Measurements:

For power converter voltage measurements, the ADC can be configured into single-ended mode (0-4.096 V range or 0-2.048 V range). The ADC can also be configurable into differential mode (±2.048 V range) to support remote sensing of voltages where the remote ground reference is returned to PSoC over a PCB trace. In cases where the analog voltage to be monitored equals or exceeds Vdda or the ADC range, external resistor dividers are recommended to scale the monitored voltages down to an appropriate range.

Power Converter Current Measurements:

For power converter load current measurements, the ADC can be configured into differential mode (+/- 64 mV or +/- 128 mV range) to support voltage measurement across a high-side series shunt resistor on the outputs of the power converters. Firmware APIs convert the measured differential voltage into the equivalent current based on the external resistor component value used. The ADC can also be configured into single-ended mode (0-4.096V range or 0-2.048 V range) to support connection to external current sense amplifiers (CSAs) that convert the differential voltage drop across the shunt resistor into a single ended voltage or to support power converters or hot-swap controllers that integrate similar functionality.

Required Software: PSoC Creator 2.0 Component Pack 3 and above

PSoC Creator Power Monitor Component Video
 

• Programmable flicker-free dimming resolution from 2 to 32 bit
• Two pulse density outputs
• Programmable output signal density
• Serial output bit stream
• Continuous run mode
• User-configurable sequence start value
• Standard or custom polynomials provided for all sequence lengths
• Kill input disables pulse density outputs and forces them low
• Enable input provides synchronized operation with other components
• Reset input allows restart at sequence start value for synchronization with other components
• Terminal Count Output for 8-, 16-, 24-, and 32-bit sequence lengths.

General Description

The Precision Illumination Signal Modulation (PrISM) component uses a linear feedback shift register (LFSR) to generate a pseudo random sequence. The sequence outputs a pseudo random bit stream, as well as up to two user-adjustable pseudo random pulse densities. The pulse densities may range from 0 to 100 percent.

Required Software: PSoC Creator v1.0 Beta 5 and above

• 2 to 768 pixels or symbols
• 1/3, 1/4 and 1/5 bias supported
• 10 to 150 Hz refresh rate
• Integrated bias generation between 2.0 V and 5.2 V with up to 128 digitally controlled bias levels for dynamic contrast control
• Supports both type A (standard) and type B (low power) waveforms
• Pixel state of the display may be inverted for negative image
• 256 bytes of display memory (frame buffer)
• User-defined pixel or symbol map with optional 7-, 14-, or 16-segment character; 5x7 or 5x8 dot matrix; and bar graph calculation routines.
• Supports PSoC 3 ES3 silicon revisions and above.

General Description

The Segment LCD (LCD_Seg) component can directly drive a variety of LCD glass at different voltage levels with multiplex ratios up to 16x. This component provides an easy method of configuring the PSoC device to drive your custom or standard glass. 

Required Software: PSoC Creator v1.0 Beta 5 and above

• SMBus Slave mode
• PMBus Slave mode
• SMBALERT# pin support
• 25 ms Timeout
• Fixed Function (FF) and UDB implementations
• Configurable SM/PM Bus commands
   

General Description

The System Management Bus (SMBus) and Power Management Bus (PMBus) Slave component provides a simple way to add an I2C physical layer interface to a PSoC 3 or PSoC 5 design with either SMBus or PMBus protocol running on top of it.

The SMBus is a two-wire interface with various System Management chips that can communicate with the system host. It uses I2C as a physical layer. The SMBus Slave component implements most of the SMBus Slave device specifications and provides options for configuring the slave device parameters. The slave device can communicate with the SMBus Master using the provided APIs.

The PMBus protocol is a specific implementation of the more generic SMBus protocol. With the PMBus, the component presents all the possible PMBus commands and allows you to select which commands are relevant to your application.

Required Software: PSoC Creator 2.1 Component Pack 4 and above.
 

• Conforms to IEC-60958, AES/EBU, AES3 standards for Linear PCM Audio Transmission
• Sample rate support for clock/128 (up to 192 kHz)
• Configurable audio sample length (8/16/24)
• Channel status bits generator for consumer applications
• DMA support
• Independent left and right channel FIFOs or interleaved stereo FIFOs

General Description

The SPDIF_Tx component provides a simple way to add digital audio output to any design. It formats incoming audio data and metadata to create the S/PDIF bit stream appropriate for optical or coaxial digital audio. The component supports interleaved and separated audio.

Required Software: PSoC Creator v1.0 Beta 5 and above

Features

• 3- to 16-bit data width
• Four SPI operating modes
• Bit Rate up to 18 Mbps

General Description

The SPI Master component provides an industry-standard, 4-wire master SPI interface. It can also provide a 3-wire (bidirectional) SPI interface. Both interfaces support all four SPI operating modes, allowing communication with any SPI slave device. In addition to the standard 8-bit word length, the SPI Master supports a configurable 3- to 16-bit word length for communicating with nonstandard SPI word lengths.     

Required Software: PSoC Creator v1.0 Beta 5 and above 

PSoC Creator SPI Master Component video

• Calculation accuracy 0.01 °C for -200 °C to 850 °C temperature range
• Provides simple API function for resistance to temperature conversion
• Displays Error Vs Temperature graph

General Description

The Resistance Temperature Detector (RTD) Calculator component generates a polynomial approximation for calculating the RTD Temperature in terms of RTD resistance for a PT100, PT500 or PT1000 RTD. Calculation error budget is user-selectable, and determines the order of the polynomial that will be used for the calculation (from 1 to 5). A lower calculation error budget will result in a more computation intensive calculation. For example, a fifth order polynomial will give a more accurate temperature calculation than lower order polynomials, but will take more time for execution. After maximum and minimum temperatures and error budget are selected, the component generates the maximum temperature error, and an error vs. temperature graph for all temperatures in the range, along with an estimate of the number of CPU cycles necessary for calculation using the selected polynomial. Selecting the lowest error budget will choose the highest degree polynomial. For the whole RTD temperature range, -200 °C to 850 °C, the component can provide a maximum error of <0.01 °C using a fifth order polynomial.

Required Software: PSoC Creator 2.1 Component Pack 4 and above
 

• Single or differential connections
• Adjustable between 1 and 64 connections for single AMux, 1 and 32 connections for Differential AMux.
• Software controlled
• Connections may be pins or internal sources
• Multiple simultaneous connections
• Bi-directional (passive)

General Description

The analog multiplexer (AMux) component can be used to connect none, one, or more analog signals to a different common analog signal. The ability to connect more than one analog signal at a time provides cross-bar switch support, which is an extension beyond traditional mux functionality.

Required Software: PSoC Creator v1.0 Beta 5 and above

• Single or differential connections
• Adjustable between 1 and 64 connections for single AMux, 1 and 32 connections for Differential AMux
• Software controlled
• Connections may be pins or internal sources
• No simultaneous connections
• Bidirectional (passive)

General Description

The analog multiplexer sequencer (AMuxSeq) component is used to connect one analog signal at a time to a different common analog signal, by breaking and making connections in hookuporder sequence. The AMuxSeq is primarily used for time division multiplexing.

Required Software: PSoC Creator v1.0 Beta 5 and above

Features

• Supports PSoC 5 and PSoC 5LP devices
• 12-bit resolution at up to 1 msps maximum
• Four power modes
• Selectable resolution and sample rate
• Single-ended or differential input

General Description

The ADC Successive Approximation Register (ADC_SAR) component provides medium-speed (maximum 1-msps sampling), medium-resolution (12 bits maximum), analog-to-digital conversion.

Required Software: PSoC Creator v1.0 Beta 5 and above

• Provides an editor to enter the assembler instructions to configure the DFB block and an assembler that converts the assembly instructions to instruction words.
• Supports simulation of the assembly instructions.
• Supports a code optimization option that provides a mechanism to incorporate up to 128 very large instruction words inside the DFB Code RAM.
• Provides hardware signals such as DMA requests, DSI inputs and outputs, and interrupt lines.
• Supports semaphores to interact with the system software and the option to tie the semaphores to hardware signals.

General Description

The digital filter block (DFB) in PSoC 3 and PSoC 5 can be used as mini DSP processor and allows you to configure the DFB using assembly instructions. The component assembles the instructions entered in the editor and generates the corresponding hex code words, which can be loaded into the DFB. It also includes a simulator, which helps the user to simulate and debug the assembly instructions.

The DFB consists of a programmable 24*24 multiplier/accumulator (MAC), an arithmetic logic unit (ALU), shifter, and various program and data memory to store instructions and data. The DFB runs on the bus clock, and can interface with both CPU and DMA. It can be used to offload the CPU and can speed up arithmetic calculations that involve intensive multiply accumulate operations. Typical operations you can use the DFB component to implement include: vector operations, matrix operations, filtering operations, and signal processing.

• Easy user configuration of filters running on the Digital Filter Block (DFB) available in some PSoC 3, PSoC 5 and PSoC5 LP devices.
• Supports two separate filter channels, each one constructed as a cascade of up to four separately designed stages.
• Multiple FIR and IIR (Biquad) filter methods (including user coefficient entry) give great flexibility
• Final coefficient values can be extracted for further analysis

General Description

The customizer for the Filter component allows you to configure digital filters on one or two data streams passed to the Digital Filter Block (DFB), using DMA, interrupts, or polling to manage data flow. The DFB’s 128 data and coefficient locations are shared as needed between the two filter channels. The customizer reports (but does not set) the minimum bus clock frequency required to execute the filtering within the user-declared sample interval.

This component supports a huge number of use cases. If you encounter something unusual when using it, report it (with a good description of what you did to cause it) to psoc_creator_fb@cypress.com so Cypress can investigate. 

Required Software: PSoC Creator v1.0 Beta 5 and above

• Accuracy of /-5° C
• Range -40° C to 140° C (0xFFD8 to 0x008C)
• Blocking and non-blocking API
• Does not support PSoC 5 silicon

General Description

The Die Temperature (DieTemp) component provides an API to acquire the temperature of the die. The System Performance Controller (SPC) is used to get the die temperature. The API includes blocking and nonblocking calls.

Required Software: PSoC Creator v1.0 Beta 5 and above

Features

• Industry-standard NXP® I2C bus interface
• Supports Slave, Master, Multi-Master and Multi-Master-Slave operation
• Requires only two pins (SDA and SCL) to interface to I2C bus
• Supports standard data rates of 100/400/1000 kbps
• High level APIs require minimal user programming

General Description

The I2C component supports I2C slave, master, and multi-master configurations. The I2C bus is an industry-standard, two-wire hardware interface developed by Philips. The master initiates all communication on the I2C bus and supplies the clock for all slave devices.

The I2C component supports standard clock speeds up to 1000 kbps. It is compatible with I2C Standard-mode, Fast-mode, and Fast-mode Plus devices as defined in the NXP I2C-bus specification. The I2C component is compatible with other third-party slave and master devices.

Note: This version of the component datasheet covers both the fixed hardware I2C block and the UDB version.

Features

• Master only
• 8 to 32 data bits per sample
• 16-, 32-, 48-, or 64-bit word select period
• Data rate up to 96 kHz with 64-bit word select period: 6.144 MHz
• Tx and Rx FIFO interrupts
• DMA support
• Independent left and right channel FIFOs or interleaved stereo FIFOs
• Independent enable of Rx and Tx

General Description

The Integrated Inter-IC Sound Bus (I2S) is a serial bus interface standard used for connecting digital audio devices together. The specification is from Philips® Semiconductor (I2S bus specification; February 1986, revised June 5, 1996).

PSoC Creator I2S Component Video

Required Software: PSoC Creator v1.0 Beta 5 and above

• USB Full Speed device interface driver
• Support for interrupt, control, bulk, and isochronous transfer types
• Runtime support for descriptor set selection
• Optional USB string descriptors
• Optional USB HID class support
• Optional Bootloader support
• Optional Audio class support
• Optional MIDI devices support
• Optional CDC class support

General Description

The USBFS component provides a USB full-speed Chapter 9 compliant device framework. It provides a low-level driver for the control endpoint that decodes and dispatches requests from the USB host. Additionally, this component provides a USBFS customizer to make it easy to construct your descriptor.   

Required Software: PSoC Creator v1.0 Beta 5 and above

PSoC Creator USB FS Component Video

• 2 to 64 bits PRS sequence length
• Time Division Multiplexing mode
• Serial output bit stream
• Continuous or single-step run modes
• Standard or custom polynomial
• Standard or custom seed value
• Enable input provides synchronized operation with other components
• Computed pseudo random number can be read directly from the Linear Feedback Shift Register (LFSR)

General Description

The Pseudo Random Sequence (PRS) component uses an LFSR to generate a pseudo random sequence, which outputs a pseudo random bit stream. The LFSR is of the Galois form (sometimes known as the modular form) and uses the provided maximal code length, or period. The PRS component runs continuously after starting as long as the Enable Input is held high. The PRS number generator can be started with any valid seed value other than 0.

Required Software: PSoC Creator v1.0 Beta 5 and above

• 8- or 16-bit resolution
• Multiple pulse width output modes
• Configurable trigger
• Configurable capture
• Configurable hardware/software enable
• Configurable dead band
• Multiple configurable kill modes
• Customized configuration tool

General Description

The PWM component provides compare outputs to generate single or continuous timing and control signals in hardware. The PWM is designed to provide an easy method of generating complex real-time events accurately with minimal CPU intervention. PWM features may be combined with other analog and digital components to create custom peripherals.

Required Software: PSoC Creator v1.0 Beta 5 and above

• Available for PSoC 5 devices only (For PSoC 3 and PSoC 5LP devices, use the Segment LCD version 3.10 component)
• 2 to 768 pixels or symbols
• 1/3, 1/4, and 1/5 bias supported
• 10- to 150-Hz refresh rate
• Integrated bias generation between 2.0 V and 5.2 V with up to 128 digitally controlled bias levels for dynamic contrast control
• Supports both type A (standard) and type B (low power) waveforms
• Pixel state of the display may be inverted for negative image
• 256 bytes of display memory (frame buffer)
• User-defined pixel or symbol map with optional 7-, 14-, or 16-segment character; 5x7 or 5x8 dot matrix; and bar graph calculation routines

General Description

The Segment Display (Seg_Display) component can directly drive 3.3-V and 5.0-V LCD glass at multiplex ratios up to 16x. This component provides an easy method of configuring the PSoC device to drive your custom or standard glass.

• Component Creation Process Overview
• Conventions
• References
• Revision History

• Low input offset
• User controlled offset calibration
• Multiple speed modes
• Low-power mode
• Output routable to digital logic blocks or pins
• Selectable output polarity
• Configurable operation mode during Sleep

General Description

The Comparator (Comp) component provides a hardware solution to compare two analog input voltages. The output can be sampled in software or digitally routed to another component. Three speed levels are provided to allow you to optimize for speed or power consumption. A reference or external voltage can be connected to either input.

You can also invert the output of the comparator using the Polarity parameter.   

Required Software: PSoC Creator v1.0 Beta 5 and above

• Fixed function (FF) and universal digital block (UDB) implementations
• 8-, 16-, 24-, or 32-bit counter
• Up, down, or up-and-down configurations
• Optional compare output
• Optional capture input
• Enable and reset inputs, for synchronizing with other components
• Continuous or one shot run modes

General Description

The Counter component provides a method to count events. It can implement a basic counter function and offers advanced features such as capture, compare output, and count direction control. 

Required Software: PSoC Creator v1.0 Beta 5 and above

• 1 to 64 bits
• Time Division Multiplexing mode
• Requires clock and data for serial bit stream input
• Serial data in, parallel result
• Standard [CRC-1 (parity bit), CRC-4 (ITU-T G.704), CRC-5-USB, etc.] or custom polynomial
• Standard or custom seed value
• Enable input provides synchronized operation with other components

General Description

The default use of the Cyclic Redundancy Check (CRC) component is to compute the CRC from a serial bit stream of any length. The input data is sampled on the rising edge of the data clock. The CRC value is reset to 0 before starting or can optionally be seeded with an initial value. On completion of the bitstream, the computed CRC value may be read out.

Required Software: PSoC Creator v1.0 Beta 5 and above

Features

• Quickly defines new clocks
• Refers to system or design-wide clocks
• Configures the clock frequency tolerance

General Description

The Clock component provides two key features: it provides allows you to create local clocks, and it allows you to connect designs to system and design-wide clocks. All clocks are shown in the Design-Wide Resources (DWR) Clock Editor.

Required Software: PSoC Creator v1.0 Beta 5 and above

• 24 channels
• Eight priority levels
• 128 Transaction Descriptors (TDs)
• 8-, 16-, and 32-bit data transfers
• Configurable source and destination addresses
• Support for endian compatibility
• Can generate an interrupt when data transfer is complete
• DMA Wizard to assist with application development

General Description

The DMA component allows data transfers to and from memory, components, and registers. The controller supports 8-, 16-, and 32-bit wide data transfers, and can be configured to transfer data between a source and destination that have different endianess. TDs can be chained together for complex operations.

Required Software: PSoC Creator v1.0 Beta 5 and above

Features

• Defines hardware-triggered interrupts
• Provides a software method to pend interrupt

General Description

The Interrupt component defines hardware triggered interrupts. It is an integral part of the Interrupt Design-Wide Resource system (see PSoC Creator Help, Design-Wide Resources section).

There are three types of system interrupt waveforms that can be processed by the interrupt controller:

• Level – IRQ source is sticky and remains active until firmware clears the source of the request with an action (for example clear on read). Most fixed-function peripherals have level-sensitive interrupts, including the UDB FIFOs and status registers.
• Pulse – Ideally, a pulse IRQ is a single bus clock, which logs a pending action and ensures that the ISR action is only executed once. No firmware action to the peripheral is required.
• Edge – An arbitrary synchronous waveform is the input to an edge-detect circuit and the positive edge of that waveform becomes a synchronous one-cycle pulse (Pulse mode).

Required Software: PSoC Creator v1.0 Beta 5 and above

• Rapid setup of all pin parameters and drive modes
• Allows PSoC Creator to automatically place and route signals
• Allows interaction with 1 or more pins simultaneously

General Description

The Pins component is the preferred way for hardware resources to connect to a physical portpin. It provides access to external signals through an appropriately configured physical IO pin. It also allows electrical characteristics to be associated with one or more pins; these characteristics are then used by PSoC Creator to automatically place and route the signals within the component.

Required Software: PSoC Creator v1.0 Beta 5 and above

PSoC® 3 and PSoC 5LP (hereafter referred to as PSoC) are more than just microcontrollers. With PSoC you can integrate the functions of a microcontroller, complex programmable logic device (CPLD) and high-performance analog with unmatched flexibility. This saves cost, board space, power and development time.

This application note introduces the PLDs in the PSoC Universal Digital Block (UDB), and then teaches how to use them by creating PSoC Creator components. It is an effective first step in porting complex programmable logic device (CPLD) functionality to PSoC. After reading this application note, you should be familiar with PSoC PLDs, and be able to create your own custom Verilog-based components using PSoC Creator™.

* Refer to Migrating CY8CKIT-001 DVK project to CY8CKIT 030/ 050.

Notes:

1. Click on AN84741 - PSoC® 5 to PSoC 5LP Migration Guide to learn differences between PSoC 5 and PSoC 5LP.
2. For PSoC 5 project and related document, please download file AN82250_Archive.zip.

Projects associated with this application note can be downloaded from the 'Related Files' section below. For your convenience, we have provided projects that are compatible with the two most recent versions of PSoC Creator:

• AN82250.zip is used with PSoC Creator 2.1 SP1
• AN82250_Archive.zip is used with PSoC Creator 2.1/2.0

The project’s default settings may not be compatible with your device or kit, and you may need to change your project settings. For more information, see:

• 9-bit address mode with hardware address detection
• Baud rates from 110 to 921600 bps or arbitrary up to 4 Mbps
• RX and TX buffers = 4 to 65535
• Detection of Framing, Parity, and Overrun errors
• Full Duplex, Half Duplex, TX only, and RX only optimized hardware
• Two out of three voting per bit
• Break signal generation and detection
• 8x or 16x oversampling

General Description

The UART provides asynchronous communications commonly referred to as RS232 or RS485. The UART component can be configured for Full Duplex, Half Duplex, RX only, or TX only versions. All versions provide the same basic functionality. They differ only in the amount of resources used.

Required Software: PSoC Creator v1.0 Beta 5 and above

• Voltage output ranges: 1.020-V and 4.080-V full scale
• Software or clock driven output strobe
• Data source can be CPU, DMA, or Digital components

General Description

The VDAC8 component is an 8-bit voltage output Digital to Analog Converter (DAC). The output range can be from 0 to 1.020 V (4 mV/bit) or from 0 to 4.08 V (16 mV/bit). The VDAC8 can be controlled by hardware, software, or a combination of both hardware and software.

Required Software: PSoC Creator v1.0 Beta 5 and above

• Support for up to 16 PWM controlled, 4-wire brushless DC fans
• Individual or banked PWM outputs with tachometer inputs
• Supports 25 kHz, 50 kHz or user-specified PWM frequencies
• Supports fan speeds up to 25,000 RPM
• Supports 4-pole and 6-pole motors
• Supports fan stall / rotor lock detection on all fans
• Supports firmware controlled or hardware controlled fan speed regulation
• Customizable alert pin for fan fault reporting

General Description

The Fan Controller component enables designers to quickly and easily develop fan controller solutions using PSoC. The component is a system-level solution that encapsulates all necessary hardware blocks including PWMs, tachometer input capture timer, control registers, status registers and a DMA controller reducing development time and effort.

The component is customizable through a graphical user interface enabling designers to enter fan electromechanical parameters such as duty cycle-to-RPM mapping and physical fan bank organization. Performance parameters including PWM frequency and resolution as well as open or closed loop control methodology can be configured through the same user interface. Once the system parameters are entered, the component delivers the most optimal implementation saving resources within PSoC to enable integration of other thermal management and system management functionality. Easy-to-use APIs are provided to enable firmware developers to get up and running quickly.

Required Software: PSoC Creator 2.0 Component Pack 3 and above

PSoC Creator Fan Controller Component Video

Features

• Full LIN 2.1 or 2.0 Slave Node implementation
• Supports compliance with SAE J2602-1 specification
• Automatic baud rate synchronization
• Fully implements a Diagnostic Class I Slave Node
• Full transport layer support
• Automatic detection of bus inactivity
• Full error detection
• Automatic configuration services handling
• Customizer for fast and easy configuration
• Import of *.ncf/*.ldf files and *.ncf file export
• Editor for *.ncf/*.ldf files with syntax checking

General Description

The LIN Slave component implements a LIN 2.1 slave node on PSoC 3 and PSoC 5 devices. Options for LIN 2.0 or SAE J2602-1 compliance are also available. This component consists of the hardware blocks necessary to communicate on the LIN bus, and an API to allow the application code to easily interact with the LIN bus communication. The component provides an API that conforms to the API specified by the LIN 2.1 Specification.

Required Software: PSoC Creator v1.0 Beta 5 and above

• CAN2.0 A/B protocol implementation, ISO 11898-1 compliant
• Programmable bit rate up to 1 Mbps @ 8 MHz (BUS_CLK)
• Two or three wire interface to external transceiver (Tx, Rx, and Tx Enable)
• Driver provided and supported by Vector

General Description

The Vector CANbedded environment consists of a number of adaptive source code components that cover the basic communication and diagnostic requirements in automotive applications.

The Vector CANbedded software suite is customer specific and its operation will vary according to application and OEM. This component for the Vector CANbedded suite is written to generically support the CANbedded structure regardless of the flavor of the particular OEM application. 

• 3- to 16-bit data width
• 4 SPI modes
• Bit Rate up to 5 Mbps

General Description

The SPI Slave provides an industry-standard, 4-wire slave SPI interface. It can also provide a 3-wire (bidirectional) SPI interface. Both interfaces support all four SPI operating modes, allowing communication with any SPI master device. In addition to the standard 8-bit word length, the SPI Slave supports a configurable 3- to 16-bit word length for communicating with nonstandard SPI word lengths.

Required Software: PSoC Creator v1.0 Beta 5 and above

• 1 to 61 pixels or symbols
• 10- to 150-Hz refresh rate
• User-defined pixel or symbol map with optional 7-segment, 14-segment, 16-segment and bar graph calculation routines
• Direct drive static (one common) LCDs

General Description

The Static Segment LCD (LCD_SegStatic) component can directly drive 3.3-V and 5.0-V LCD glass. This component provides an easy method of configuring the PSoC device for your custom or standard glass.

Each LCD pixel/symbol may be either on or off. The Static Segment LCD component also provides advanced support to simplify the following types of display structures within the glass:

• 7-Segment numeral
• 14-Segment alphanumeric
• 16-Segment alphanumeric
• 1- to 255-element bar graphs

Required Software: PSoC Creator v1.0 Beta 5 and above

• Adaptable for majority of negative temperature coefficient (NTC) thermistors
• Look-Up-Table (LUT) or equation implementation methods
• Selectable reference resistor, based on thermistor value
• Selectable temperature range
• Selectable calculation resolution for LUT method

General Description

The Thermistor Calculator component calculates the temperature based on a provided voltage measured from a thermistor. The component is adaptable to most NTC thermistors. It calculates the Steinhart-Hart equation coefficients based on the temperature range and corresponding user-provided reference resistances. The component provides API functions that use the generated coefficients to return the temperature value based on measured voltage values.

This component doesn't use an ADC or AMUX inside and thus requires those components to be placed separately in your projects.

Required Software: PSoC Creator 2.1 Component Pack 4 and above.
 

• Supports B, E, J, K, N, R, S, and T Type Thermocouples
• Provides functions for thermo-emf to temperature and temperature to voltage conversions
• Displays Calculation Error Vs. Temperature graph

General Description

In thermocouple temperature measurement, the thermocouple temperature is calculated based on the measured thermo-emf voltage. The voltage to temperature conversion is characterized by the National Institute of Standards and Technology (NIST), and NIST provides tables and polynomial coefficients for thermo-emf to temperature conversion. The NIST tables and polynomial coefficients can be found in the following link:

http://srdata.nist.gov/its90/download/download.html

Thermocouple temperature measurement also involves measuring the thermocouple reference junction temperature and converting it into a voltage. The Thermocouple Calculator component simplifies the thermocouple temperature measurement process by providing APIs for thermo-emf to temperature conversion and vice versa for all thermocouple types mentioned above, using polynomials generated at compile time. The thermocouple component evaluates the polynomial in an efficient way to reduce computation time.

Required Software: PSoC Creator 2.1 Component Pack 4 and above.

• Fixed-function (FF) and universal digital block (UDB) implementations
• 8-, 16-, 24-, or 32-bit timer
• Optional capture input
• Enable, trigger, and reset inputs, for synchronizing with other components
• Continuous or one shot run modes

Symbol Diagram

General Description

The Timer component provides a method to measure intervals. It can implement a basic timer function and offers advanced features such as capture with capture counter and interrupt/DMA generation.

Required Software: PSoC Creator v1.0 Beta 5 and above

*Refer to Migrating CY8CKIT-001 DVK project to CY8CKIT 030/ 050.

1. Click on AN84741 - PSoC® 5 to PSoC 5LP Migration Guide to learn differences between PSoC 5 and PSoC 5LP.
2. Click on AN77835 - PSoC® 3 to PSoC 5LP Migration Guide to learn differences between PSoC 3 and PSoC 5LP.
3. For PSoC 5 project and related document, please download file AN77900_Archive.zip.

Projects associated with this application note can be downloaded from the 'Related Files' section below. For your convenience, we have provided projects that are compatible with the two most recent versions of PSoC Creator:

• AN77900.zip is used with PSoC Creator 2.1 SP1
• AN77900_Archive.zip is used with PSoC Creator 2.1/2.0

The project’s default settings may not be compatible with your device or kit, and you may need to change your project settings. For more information, see:

• Single-ended mixer
• Continuous-time up mixing:
  • Input frequencies up to 500 kHz
  • Sample clock up to 1 MHz
• Discrete-time, sample-and-hold down mixing:
  • Input frequencies up to 14 MHz
  • Sample clock up to 4 MHz
• Adjustable power settings
• Selectable reference voltage

General Description

The Mixer component provides a single-ended modulator. The Mixer component can be used for frequency conversion of an input signal using a fixed Local Oscillator (LO) signal as the sampling clock. The manipulations of signal frequencies that a mixer performs can be used to move signals between frequency bands or to encode and decode signals. A mixer can be used to convert signal power at one frequency into power at another frequency to make signal processing easier, typically shifting higher frequencies to baseband.

Required Software: PSoC Creator v1.0 Beta 5 and above

• Two operating modes: Sample and Hold, Track and Hold
• Four power mode settings

General Description

The Sample/Track and Hold component provides a way to sample a continuously varying analog signal and to hold or freeze its value for a finite period of time. It supports both Track and Hold and Sample and Hold functions, which can be selected in the customizer.

Features

• Follower or Opamp configuration
• Unity gain bandwidth > 3.0 MHz
• Input offset voltage 2.0 mV max
• Rail-to-rail inputs and output
• Output direct low resistance connection to pin
• 25 mA output current
• Programmable power and bandwidth
• Internal connection for follower (saves pin)

General Description

The Opamp component provides a low-voltage, low-power operational amplifier and may be internally connected as a voltage follower. The inputs and output may be connected to internal routing nodes, directly to pins, or a combination of internal and external signals. The Opamp is suitable for interfacing with high-impedance sensors, buffering the output of voltage DACs, driving up to 25 mA; and building active filters in any standard topology.   

Required Software: PSoC Creator v1.0 Beta 5 and above 

• Three ranges 2040 μA, 255 μA, and 31.875 μA
• Current sink or source selectable
• Software or clock driven output strobe
• Data source may be CPU, DMA, or Digital components

General Description

The IDAC8 component is an 8-bit current output DAC (Digital to Analog Converter). The output can source or sink current in three ranges. The IDAC8 can be controlled by hardware, software, or by a combination of both hardware and software.

Required Software: PSoC Creator v1.0 Beta 5 and above

• Wakes up devices from low-power modes: Alternate Active and Sleep
• Contains configurable option for issuing interrupt
• Generates periodic interrupts while the device is in Active mode
• Supports twelve discrete intervals: 2, 4, 8, 16, 32, 64, 128, 256, 512, 1024, 2048, and 4096 ms
   

The Sleep Timer component can be used to wake the device from Alternate Active and Sleep modes at a configurable interval. It can also be configured to issue an interrupt at a configurable interval. For PSoC 5 architectures, an interrupt is required for the CPU to wake up.

For PSoC 5, the supported intervals are restricted to: 4, 8, 16, 32, 64, 128 or 256 ms. Refer to the CyPmSleep() function description in the System Reference Guide for details about this restriction. The PSoC 5LP device supports the full set of intervals.

Required Software: PSoC Creator v1.0 Beta 5 and above

• Multiple Alarm Options
• Multiple Overflow Options
• Daylight Saving Time (DST) Option

General Description

The Real-Time Clock (RTC) component provides accurate time and date information for the system. The time and date are updated every second based on a one pulse per second interrupt from a 32.768-kHz crystal. Clock accuracy is based on the crystal provided and is typically 20 ppm.   

Required Software: PSoC Creator v1.0 Beta 5 and above

• Monitor up to 32 voltage inputs
• User-defined over and under voltage limits
• Simply outputs a good/bad status result

General Description

The Voltage Fault Detector component provides a simple way to monitor up to 32 voltage inputs against user-defined over and under voltage limits without using the ADC and without having to write any firmware. The component simply outputs a good/bad status result (“power good” or pgood[x]) for each voltage being monitored.

The component operates entirely in hardware without any intervention from PSoC’s CPU core resulting in known, fixed fault detection latency.

Note: This component supports PSoC 3 and PSoC 5LP devices only.

• Supports sequencing and monitoring of up to 32 power converter rails
• Supports power converter circuits with logic-level enable inputs and logic-level power good (pgood) status outputs
• Autonomous (standalone) or host driven operation
• Sequence order, timing and inter-rail dependencies can be configured through an intuitive, easy-to-use graphical configuration GUI

General Description

The Voltage Sequencer component provides a simple way to define power-up and power-down sequencing of up to 32 power converters to meet user-defined system requirements. Once the sequencing requirements have been entered into the easy-to-use graphical configuration GUI, the component will automatically take care of the sequencing implementation without requiring any firmware development by the user.

Features

• Gain steps from 1 to 50
• High input impedance
• Selectable input reference
• Adjustable power settings

General Description

The PGA implements an opamp-based, non-inverting amplifier with user-programmable gain. This amplifier has high input impedance, wide bandwidth and selectable input voltage reference. It is derived from the switched capacitor/continuous time (SC/CT) block.

The gain can be between 1 (0 dB) and 50 (+34 dB). The gain can be selected using the configuration window or changed at run time using the provided API. The maximum bandwidth is limited by the gain-bandwidth product of the opamp and is reduced as the gain is increased. The input of the PGA operates from rail to rail, but the maximum input swing (difference between Vin and Vref) is limited to V_DDA/Gain. The output of the PGA is class A, and is rail to rail for sufficiently high load resistance.

Required Software: PSoC Creator v1.0 Beta 5 and above

• 512 B to 2 KB EEPROM memory
• 1,000,000 cycles, 20-year retention
• Read/Write 1 byte at a time
• Program 16 bytes (a row) at a time

General Description

The EEPROM component provides a set of APIs to erase and write data to nonvolatile EEPROM memory. The term write implies that it will erase and then program in one operation.

An EEPROM memory in PSoC devices is organized in arrays. PSoC 3 and PSoC 5 devices offer an EEPROM array of size 512 bytes, 1 KB or 2 KB depending on the device. This array is divided into rows of size 16 bytes each. The API set of the EEPROM component supports write operations at the byte and row levels and erase operation at the sector level. A sector in EEPROM has 64 rows.

Required Software: PSoC Creator v1.0 Beta 5 and above

• Up to four Secure Digital (SD) cards in SPI mode
• FAT12/16 or FAT32 format
• Optional integration with an Operating System (OS)
• Optional Long File Name (LFN) handling

General Description

The emFile component provides an interface to SD cards formatted with a FAT file system. The SD card specification includes multiple hardware interface options for communication with an SD card. This component uses the SPI interface method for communication. Up to four independent SPI interfaces can be used for communication with one SD card each. Both FAT12/16 and FAT32 file system formats are supported. This component provides the physical interface to the SD card and works with the emFile library licensed from SEGGER Microcontroller to provide a library of functions to manipulate a FAT file system.

Required Software

Firmware Installation:  The firmware files for this component are not distributed with PSoC Creator and can be downloaded below. Please refer to the component datasheet for installation instructions.

IMPORTANT NOTICE REGARDING LONG FILE NAMES:  If you configure the software to support long file names on FAT file systems, you should review the information at http://www.microsoft.com/about/legal/en/us/IntellectualProperty/IPLicensing/Programs/FATFileSystem.aspx to determine whether a license from Microsoft is required. Cypress and its suppliers grant no license under Microsoft's intellectual property rights and assume no liability for any use of the software without obtaining any license that may be required.

PSoC^® Creator^™ emFile Component Video

• Industry standard NXP® I2C bus interface
• Emulates common I2C EEPROM interface
• Only two pins (SDA and SCL) required to interface to I2C bus
• Standard data rates of 50/100/400/1000 kbps
• High level APIs require minimal user programming
• Supports one or two address decoding with independent memory buffers
• Memory buffers provide configurable Read/Write and Read Only regions

General Description

The EZI2C Slave component implements an I2C register-based slave device. It is compatible with I2C Standard-mode, Fast-mode, and Fast-mode Plus devices as defined in the NXP I2C-bus specification.The master initiates all communication on the I2C bus and supplies the clock for all slave devices. The EZI2C Slave supports standard data rates up to 1000 kbps and is compatible with multiple devices on the same bus.
 

Required Software: PSoC Creator v1.0 Beta 5 and above 

• Up to 8-bit Status Register
• Interrupt support

General Description

The Status Register allows the firmware to read digital signals.

Required Software: PSoC Creator v1.0 Beta 5 and above

• Support for user-defined combinations of button, slider, touch pad, and proximity capacitive sensors.
• Automatic SmartSense™ tuning or manual tuning with integrated PC GUI.
• High immunity to AC power line noise, EMC noise, and power supply voltage changes.
• Optional two scan channels (parallel synchronized), which increases sensor scan rate.
• Shield electrode support for reliable operation in the presence of water film or droplets.
• Guided sensor and terminal assignments using the CapSense customizer.

General Description

Capacitive Sensing, using a Delta-Sigma Modulator (CapSense CSD) component, is a versatile and efficient way to measure capacitance in applications such as touch sense buttons, sliders, touchpad, and proximity detection.

Required Software: PSoC Creator v1.0 Beta 5 and above

Features
 

• CAN2.0A and CAN2.0B protocol implementation, ISO 11898-1 compliant
• Programmable bit rate up to 1 Mbps at 8 MHz (BUS_CLK)
• Two-wire or three-wire interface to external transceiver (Tx, Rx, and Enable)
• Extended hardware message filter that covers Data Byte 1 and Data Byte 2 fields
• Programmable transmit priority: Round Robin and Fixed
• CAN component fully supports PSoC 5LP device, but does not support PSoC 5

General Description

The Controller Area Network (CAN) controller implements the CAN2.0A and CAN2.0B specifications as defined in the Bosch specification and conforms to the ISO-11898-1 standard.

Required Software: PSoC Creator v1.0 Beta 5 and above

PSoC Programmer 3.17 offers the user a simple GUI that connects to programming hardware to program and configure PSoC, Clock, and configurable fixed function devices. Also provided with PSoC Programmer is the Bridge Control Panel, which can be used to debug, graph and log I2C serial communications using various supported Cypress Software. PSoC Programmer also provides a hardware layer for customers to design custom applications or use existing code examples for testing hardware and Firmware designs.

PSoC Programmer 3.17 release shall support both PSoC Creator and PSoC Designer in a single installation.

PSoC Programmer 3.17 is a minor release. For additional information regarding the installation and the new features please see the release notes in the downloads table below.

PSoC Programmer:

PSoC Programmer is a flexible, integrated programming application for programming PSoC devices. PSoC Programmer can be used with PSoC Designer and PSoC Creator to program any design onto a PSoC device. PSoC Programmer supports all PSoC 1, 3, and 5 devices.

COM Hardware Layer Supported Languages:

PSoC Programmer provides the user a hardware layer with API’s to design specific applications utilizing the programmers and bridge devices. The PSoC Programmer hardware layer is fully detailed in the COM guide documentation as well as example code across the following languages: C#, C, Perl, and Python.

PSoC Programmer Secondary Software

PSoC Programmer includes additional software beyond just PSoC Programmer. For more information on that additional software please: Click Here

Third Party IDE and Programming Support

PSoC Programmer delivers a number of files and utilities that enable 3^rd party programming and debugging support for PSoC device families. In the downloads table below we include the 3^rd party user guide which will assists the user in configuring and enabling the support in the IDEs or programming utilities. The files and applications can be found in the root installation directory for each programmer installation.

Archived Software:

PSoC Programmer software is archived at the following page: Click Here

Additional Programming Links:
Prototype Programming Hardware:

PSoC Programmer is part of a suite of programming options and programming content available to PSoC users. For customers who are looking for more information on general programming options and information please navigate to the web page linked below. On the General Programming web page we discuss all of the available programming options for customers including Software, Schematics, Programming Specifications, and 3rd party mass programming.

www.cypress.com/go/programming

All PDF documents require at least a PDF reader installed prior to opening.

The PSoC 3 device supports eight hardware program address breakpoints and one data address watch point.

PSoC 5 and PSoC 5LP support six hardware program address breakpoints and four data address watch points.

However, PSoC Creator reserves one breakpoint to use it to perform operations such as step, jump, and run-to-cursor. After all the hardware breakpoints are exhausted, PSoC Creator automatically uses software breakpoints for all future breakpoints, which is implemented on the host PC side.

A breakpoint is used to cause the debugger to halt the next time its location is reached. If you set a hardware breakpoint, a red dot appears in the left margin of the source/disassembly corresponding to the line in which the breakpoint is assigned. If the number of hardware breakpoints has been exhausted, and if you attempt to add another, the debugger displays an information message to announce that the maximum number of breakpoints has been reached. You will be prompted to place a software breakpoint instead. Software breakpoint is indicated by a green dot in the left margin of the source/disassembly corresponding to the line in which the breakpoint is assigned.

A watchpoint is used to set a breakpoint on a place in data memory as opposed to the standard breakpoint, which is used for program memory. Instead of setting the breakpoint on a line of code, you set it on a variable in the code. This watchpoint is hit each time the address that the variable is located at is read, written, or accessed based on your selection for Break on.

Documentation

The following application notes guide you through the process of component development:

1. AN82250 - PSoC® 3 and PSoC 5LP Implementing Programmable Logic Designs with Verilog
2. AN82156 - PSoC® 3 and PSoC 5LP - Designing PSoC Creator™ Components With UDB Datapaths

The Component Author Guide included with PSoC Creator provides instructions and information on how to create components for PSoC Creator. To open the component guide from PSoC Creator, select Help > Documentation > Component Author Guide.
To download from the website, browse to: PSoC Creator Component Author Guide

The Component Development Kit installed with PSoC Creator includes additional documents. To open from your desktop, select
Start > All Programs > Cypress > PSoC Creator > Component Development Kit.
 

The Component Development kit contains the following:
 

• Component Author Guide: Provides instructions and information on how to create components for PSoC Creator.
• Customizer API Reference Guide: Provides API reference information for PSoC Creator Extensions code.
• Datapath Configuration Tool: Used to edit datapath instance configurations in a Verilog implementation of a PSoC component.
• Tuner API Reference Guide: Provides API reference information for PSoC Creator Tuner code.
• Warp Verilog Reference Guide: The Warp synthesis tool is a Verilog compiler used by PSoC Creator to design with PSoC devices.
   

Training
 

Cypress also has a series of instructional videos for component development.
 

Basic Component Trainings

PSoC Creator 110: Schematic Components
PSoC Creator 111: Component Parameters
PSoC Creator 112: Introduction to Component API Generation
PSoC Creator 113: PLD Based Verilog Components
 

Advanced Component Trainings

PSoC Creator 210: Intro to Datapath Components
PSoC Creator 211: Datapath Computation
PSoC Creator 212: Datapath FIFOs
PSoC Creator 213: Multi-Byte Datapath Components
PSoC Creator 214: Datapath API Generation

Introduction

Have you maxed out your CPU bandwidth? PSoC 3 and PSoC 5LP UDBs can lighten the load on your CPU by creating intelligent custom peripherals. The datapaths in those UDBs can be used to create sophisticated multiprocessor-based designs.

Many PSoC customers have experience writing HDL code for CPLDs or FPGAs. PSoC 3 and PSoC 5LP support Verilog for PLDs. However, PSoC 3 and PSoC 5LP PLDs are smaller than full-fledged CPLDs or FPGAs, and many designs are too large for PSoC 3 and PSoC 5LP. PSoC’s unique datapath modules remove this obstacle by integrating one or more small 8-bit processors into PLD-based designs.

1. Click on AN84741 - PSoC® 5 to PSoC 5LP Migration Guide to learn differences between PSoC 5 and PSoC 5LP.
2. Click on AN77835 - PSoC® 3 to PSoC 5LP Migration Guide to learn differences between PSoC 3 and PSoC 5LP.
3. For PSoC 5 project and related document, please download file AN82156_Archive.zip.

Projects associated with this application note can be downloaded from the 'Related Files' section below. For your convenience, we have provided projects that are compatible with the two most recent versions of PSoC Creator:

• AN82156.zip is used with PSoC Creator 2.1 SP1
• AN82156_Archive.zip is used with PSoC Creator 2.1/2.0

The project’s default settings may not be compatible with your device or kit, and you may need to change your project settings. For more information, see:

The following table provides the list of devices, the supported Creator version, Development kit and Compiler for this application note project:

*Refer to Migrating CY8CKIT-001 DVK project to CY8CKIT 030/ 050.

1. Click on AN84741 - PSoC® 5 to PSoC 5LP Migration Guide to learn differences between PSoC 5 and PSoC 5LP.
2. Click on AN77835 - PSoC® 3 to PSoC 5LP Migration Guide to learn differences between PSoC 3 and PSoC 5LP.
3. For PSoC 5 project and related document, please download file AN58726_Archive.zip.

Projects associated with this application note can be downloaded from the ‘Related Files’ section below. For your convenience, we have provided projects that are compatible with the two most recent versions of PSoC Creator:

• AN58726.zip is used with PSoC Creator 2.1 SP1
• AN58726_Archive.zip is used with PSoC Creator 2.1/2.0

The project’s default settings may not be compatible with your device or kit, and you may need to change your project settings. For more information, see:

• Eliminates unwanted oscillations on digital input lines
   

General Description

Mechanical switches and relays tend to make and break connections for a finite time before settling down to a stable state. Within this settling time, the digital circuit can see multiple transitions as the switch contacts bounce between make or break conditions.

The Debouncer component takes an input signal from a bouncing contact and generates a clean output for digital circuits. The component will not pass the signal to the output until the predetermined period of time when the switch bouncing settles down. In this way, the circuit will respond to only one pulse generation performed by the pressing or releasing of the switch and not several state transitions caused by contact bouncing.

For more details on switch debouncing please see application note AN60024.

Required Software: PSoC Creator 2.1 Component Pack 4 and above.

Below are some of videos demonstrating  how to impliment bulk transfers and vendor commands which are discussed in this application note.

The following table indicates the PSoC devices, PSoC Creator versions, compilers, and development kits that will work with this application note project:

*Refer to Migrating CY8CKIT-001 DVK project to CY8CKIT 030/ 050. 

Notes:

1. Click on AN84741 - PSoC® 5 to PSoC 5LP Migration Guide to learn differences between PSoC 5 and PSoC 5LP.
2. For PSoC 5 project and related document, please download file AN56377_Archive.zip.

Projects associated with this application note can be downloaded from the ‘Related Files’ section below. For your convenience, we have provided projects that are compatible with the two most recent versions of PSoC Creator:

• AN56377.zip is used with PSoC Creator 2.1 SP1
• AN56377_Archive.zip is used with PSoC Creator 2.1/2.0

The project’s default settings may not be compatible with your device or kit, and you may need to change your project settings. For more information, see:
Information on application note projects compatible with PSoC Creator 1.0 SP2
PSoC® 3 and PSoC 5 AN/CE project file naming convention and usage

If, instead of PSoC 5, you want to migrate from a PSoC 3 design to PSoC 5LP, see AN77835, PSoC 3 to PSoC 5LP Migration Guide.

The PSoC 5 and PSoC 5LP devices are designed for easy migration from PSoC 5 to PSoC 5LP. Although there are some differences such as additional features in PSoC 5LP, the programmable analog, programmable digital, programmable routing, pin functions, and other features are quite similar. Furthermore, the PSoC Creator IDE handles a lot of the migration issues for you, automatically. Often, migrating a PSoC Creator design is as simple as specifying a new part and then rebuilding the project.

There are generally two types of PLC systems: high-bandwidth (video, audio, and so on) and low-bandwidth (command and control). This application note describes how to implement a low-bandwidth, half-duplex PLC solution with the PSoC 5LP family of devices.

The following table indicates the PSoC devices, PSoC Creator versions, compilers, and development kits that will work with this application note project:

1. Click on AN84741 - PSoC® 5 to PSoC 5LP Migration Guide to learn differences between PSoC 5 and PSoC 5LP.
2. For PSoC 5 project and related document, please download file AN76458_Archive.zip.

Projects associated with this application note can be downloaded from the 'Related Files' section below. For your convenience, we have provided projects that are compatible with the two most recent versions of PSoC Creator:

• AN76458.zip is used with PSoC 5LP and PSoC Creator 2.1 SP1
• AN76458_Archive.zip is used with PSoC 5 and PSoC Creator 2.1/2.1 SP1.

The project’s default settings may not be compatible with your device or kit, and you may need to change your project settings. For more information, see: