Cypress.com: Documentation http://www.cypress.com/?app=search&searchType=advanced&id%3D2232 PSoC<sup>®</sup> USB Mass Storage Class Support – KBA93269 http://www.cypress.com/?rID=97863 Answer: All PSoC devices that are USB capable can support the USB MSC and conform to it as a slave device. At the moment, Cypress® does not provide any working examples nor does PSoC Designer™ or PSoC Creator™ support it natively. However, it is possible to implement the MSC yourself. This functionality can be implemented by making modifications to the descriptor table in the USBFS_descr.c file. To gain an understanding of what the mass storage descriptors should look like, refer to Universal Serial Bus Mass Storage Class: Bulk-Only Transport, a document provided by the USB Implementers Forum (USB-IF).

Additionally, Use of User-Defined Descriptors in a Full Speed USB Component – KBA91688 will provide instructions on how to use user-defined descriptors.

Once the proper descriptors are implemented, the PSoC device will enumerate as a mass storage device. At that point, the bulk endpoints can be used to transfer data upstream and downstream. If you are using a PSoC 3 or PSoC 5LP device, the emFile Component could be used in conjunction with the USBFS Component, configured for mass storage, as a way to provide expanded storage capabilities.

Note that Microsoft® Windows® 2000/XP and beyond are released with built in MSC drivers. No additional drivers need to be provided by the end user. For additional information on understanding USB descriptors and bulk endpoints, refer to the following application notes or contact Cypress Technical Support.

AN57294 – USB 101: An Introduction to Universal Serial Bus 2.0

AN56377 – PSoC® 3 and PSoC 5LP USB Transfer Types

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Wed, 23 Jul 2014 04:50:37 -0600
PSoC<sup>®</sup> 3 and PSoC 5LP Boost Inductor Current Rating - KBA80957 http://www.cypress.com/?rID=39945 Answer: The DC current rating of the inductor should be greater than or equal to 700mA. The inductor peak current can go up to a maximum of 700 mA during start-up. So, if you use an inductor with a lesser current rating, the boost converter may not start properly.

During startup or transient operation (when the output voltage changes), the load capacitor acts like a short circuit and will draw as much current as the converter can deliver. There are current limiting provisions inside the boost converter that prevent the current from growing unbounded. The effective current limit is under 700mA. So, if you use an underrated inductor the boost converter may not start properly. The reason is that the inductor becomes saturated and ceases to behave as an inductor, dissipating energy in it and hence, not transferring the energy effectively.

The boost converter can give a maximum load current of 75mA. Even if the load is small, the inductor must be capable of delivering peak currents. This is because transient loads will pull the output below the narrow regulation window provided by minimum PWM signals, requiring occasional full current (maximum duty cycle) pulses to restore the voltage to target value.

Thus the inductor always needs to be rated for full current.

Note: The maximum ratio of the output voltage to the input voltage of the boost can be 4.

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Wed, 23 Jul 2014 04:32:31 -0600
PSoC 3 Device Programming http://www.cypress.com/?rID=40740 Wed, 23 Jul 2014 00:50:05 -0600 Voltage Fault Detector (VFD) http://www.cypress.com/?rID=69014 Features
  • Monitor up to 32 voltage inputs
  • User-defined over and under voltage limits
  • Simply outputs a good/bad status result
Symbol Diagram

General Description

The Voltage Fault Detector component provides a simple way to monitor up to 32 voltage inputs against user-defined over and under voltage limits without using the ADC and without having to write any firmware. The component simply outputs a good/bad status result (“power good” or pgood[x]) for each voltage being monitored.

The component operates entirely in hardware without any intervention from PSoC’s CPU core resulting in known, fixed fault detection latency.

Note: This component supports PSoC 3 and PSoC 5LP devices only.

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Tue, 22 Jul 2014 11:51:19 -0600
UDB Clock Enable (UDBClkEn) http://www.cypress.com/?rID=48865 Features

  • Clock enable support
  • Addition of synchronization on a clock when needed
Symbol Diagram

General Description

The UDBClkEn component supports precise control over clocking behavior.

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Tue, 22 Jul 2014 11:39:06 -0600
Full Speed USB (USBFS) http://www.cypress.com/?rID=48924 Features
  • USB Full Speed device interface driver
  • Support for interrupt, control, bulk, and isochronous transfer types
  • Runtime support for descriptor set selection
  • Optional USB string descriptors
  • Optional USB HID class support
  • Optional Bootloader support
  • Optional Audio class support
  • Optional MIDI devices support
  • Optional CDC class support
Symbol Diagram

General Description

The USBFS component provides a USB full-speed Chapter 9 compliant device framework. It provides a low-level driver for the control endpoint that decodes and dispatches requests from the USB host. Additionally, this component provides a USBFS customizer to make it easy to construct your descriptor.   

 

PSoC Creator USB FS Component Video

use for camtasia screencasts

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Mon, 21 Jul 2014 18:58:22 -0600
Sample/Track and Hold Component (Sample_Hold) http://www.cypress.com/?rID=56758 Features Symbol Diagram
  • Two operating modes: Sample and Hold, Track and Hold
  • Four power mode settings

General Description

The Sample/Track and Hold component provides a way to sample a continuously varying analog signal and to hold or freeze its value for a finite period of time. It supports both Track and Hold and Sample and Hold functions, which can be selected in the customizer.

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Mon, 21 Jul 2014 18:54:06 -0600
Real-Time Clock (RTC) http://www.cypress.com/?rID=48907 Features

  • Multiple Alarm Options
  • Multiple Overflow Options
  • Daylight Savings Time (DST) Option
Symbol Diagram

General Description

The Real-Time Clock (RTC) component provides accurate time and date information for the system. The time and date are updated every second based on a one pulse per second interrupt from a 32.768-kHz crystal. Clock accuracy is based on the crystal provided and is typically 20 ppm.   

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Mon, 21 Jul 2014 18:49:21 -0600
Design Reuse - It is Time for New IP Creation Tools http://www.cypress.com/?rID=43833 For many years design reuse has been touted as an essential part of completing projects on-time and on-budget. This idea is not new and the expression “don’t reinvent the wheel” is used in high-tech environments the world over for very good reasons. However, design reuse is typically approached either from a solely hardware (microprocessor cores, reusable IP peripherals, hardware acceleration, and so on) or software (RTOS, protocol stacks, run-time libraries and so on) perspective, but rarely both. Why is that and how can it change?  To read more, click the download link below or visit: SOCcentral.

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Mon, 21 Jul 2014 06:59:45 -0600
PSoC 3 Architecture http://www.cypress.com/?rID=40738 Sun, 20 Jul 2014 12:27:05 -0600 PSoC 3 Known Problems and Solutions http://www.cypress.com/?rID=40741 Mon, 14 Jul 2014 02:48:02 -0600 AN61102 - PSoC<sup>®</sup> 3 and PSoC 5LP - ADC Data Buffering Using DMA http://www.cypress.com/?rID=44335 AN61102 describes how to configure the direct memory access (DMA) to buffer the analog-to-digital converter (ADC) data. It discusses how to overcome some of the limitations of the DMA when buffering the ADC data.

The DMA controller in PSoC® 3 and PSoC 5LP is used to handle data transfer without CPU intervention. This is useful in applications that require ADC data buffering and allows the CPU to do simultaneous tasks.

The video describes the case of using a DMA to buffer ADC data. Buffering of 20 bit ADC data is taken as an example and discussed. The video also gives a preview of the project implementing the 20 bit data buffering and explains the DMA configuration in code.

 

 

The following table indicates the PSoC devices, PSoC Creator versions, compilers, and development kits that will work with this application note project:


Project
Device
PSoC Creator
Version
Development Kit
CY8CKIT-xxx
Compiler
Architecture
Silicon
Revision
V3.0 SP1
V2.1 SP1
/2.1
001
DVK
030/050
DVK
003/014
FTK
Keil
GCC
RVDS
MDK

AN61102.zip

Prod
YES
NO
YES
YES*
NO
YES
N/A
N/A
N/A
Prod
YES
NO
YES
YES*
NO
N/A
YES
YES
YES
AN61102_Archive.zip
ES3, Prod
NO
YES
YES
YES*
NO
YES
N/A
N/A
N/A
ES1, Prod
NO
YES
YES
YES*
NO
N/A
YES
YES
YES

*Refer to Migrating CY8CKIT-001 DVK project to CY8CKIT 030/ 050

Notes:

  1. Click on AN77835 - PSoC® 3 to PSoC 5LP Migration Guide to learn differences between PSoC 3 and PSoC 5LP.
  2. For PSoC 5 project and related document, please download file AN61102_Archive.zip.

Projects associated with this application note can be downloaded from the ‘Related Files’ section below. For your convenience, we have provided projects that are compatible with the two most recent versions of PSoC Creator:

  • AN61102.zip is used with PSoC Creator 3.0 SP1
  • AN61102_Archive.zip is used with PSoC Creator 2.1 SP1/2.1

The project’s default settings may not be compatible with your device or kit, and you may need to change your project settings. For more information, see:

PSoC® 3, PSoC 4 and PSoC 5LP AN Project File Naming Convention and Use
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Fri, 11 Jul 2014 03:56:20 -0600
Universal Asynchronous Receiver Transmitter (UART) http://www.cypress.com/?rID=48892 Features

  • 9-bit address mode with hardware address detection
  • Baud rates from 110 to 921600 bps or arbitrary up to 4 Mbps
  • RX and TX buffers = 4 to 65535
  • Detection of Framing, Parity, and Overrun errors
  • Full Duplex, Half Duplex, TX only, and RX only optimized hardware
  • Two out of three voting per bit
  • Break signal generation and detection
  • 8x or 16x oversampling
Symbol Diagram

General Description

The UART provides asynchronous communications commonly referred to as RS232 or RS485. The UART component can be configured for Full Duplex, Half Duplex, RX only, or TX only versions. All versions provide the same basic functionality. They differ only in the amount of resources used.

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Wed, 09 Jul 2014 19:18:33 -0600
Timer http://www.cypress.com/?rID=48870 Features

  • Fixed-function (FF) implementation for PSoC 3 and PSoC 5 devices
  • 8-, 16-, 24-, or 32-bit timer
  • Optional capture input
  • Enable, trigger, and reset inputs, for synchronizing with other components
  • Continuous or one shot run modes
Symbol Diagram

General Description

The Timer component provides a method to measure intervals. It can implement a basic timer function and offers advanced features such as capture with capture counter and interrupt/DMA generation.

 
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Wed, 09 Jul 2014 18:54:15 -0600
Thermocouple Calculator http://www.cypress.com/?rID=69779 Features
  • Supports B, E, J, K, N, R, S, and T Type Thermocouples
  • Provides functions for thermo-emf to temperature and temperature to voltage conversions
  • Displays Calculation Error Vs. Temperature graph
Symbol Diagram

General Description

In thermocouple temperature measurement, the thermocouple temperature is calculated based on the measured thermo-emf voltage. The voltage to temperature conversion is characterized by the National Institute of Standards and Technology (NIST), and NIST provides tables and polynomial coefficients for thermo-emf to temperature conversion. The NIST tables and polynomial coefficients can be found in the following link:

http://srdata.nist.gov/its90/download/download.html

Thermocouple temperature measurement also involves measuring the thermocouple reference junction temperature and converting it into a voltage. The Thermocouple Calculator component simplifies the thermocouple temperature measurement process by providing APIs for thermo-emf to temperature conversion and vice versa for all thermocouple types mentioned above, using polynomials generated at compile time. The thermocouple component evaluates the polynomial in an efficient way to reduce computation time.

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Wed, 09 Jul 2014 18:50:31 -0600
Thermistor Calculator http://www.cypress.com/?rID=69783 Features
  • Adaptable for majority of negative temperature coefficient (NTC) thermistors
  • Look-Up-Table (LUT) or equation implementation methods
  • Selectable reference resistor, based on thermistor value
  • Selectable temperature range
  • Selectable calculation resolution for LUT method
Symbol Diagram

General Description

The Thermistor Calculator component calculates the temperature based on a provided voltage measured from a thermistor. The component is adaptable to most NTC thermistors. It calculates the Steinhart-Hart equation coefficients based on the temperature range and corresponding user-provided reference resistances. The component provides API functions that use the generated coefficients to return the temperature value based on measured voltage values.

This component doesn't use an ADC or AMUX inside and thus requires those components to be placed separately in your projects.

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Wed, 09 Jul 2014 18:45:47 -0600
Terminal Reserve http://www.cypress.com/?rID=56767 Features

  • Prevents an analog router from using an analog block terminal routing resource
  • Allows safe firmware access to an analog block terminal routing resource
Symbol Diagram

General Description

The Terminal Reserve component reserves the analog routing resource connected to a component, such as the analog wire connected to a comparator or pin. This is an advanced feature that is not needed for most designs, and should be used with caution.

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Wed, 09 Jul 2014 18:41:16 -0600
Digital Filter Block (DFB) Assembler http://www.cypress.com/?rID=60720 Features Symbol Diagram
  • Provides an editor to enter the assembler instructions to configure the DFB block and an assembler that converts the assembly instructions to instruction words.
  • Supports simulation of the assembly instructions.
  • Supports a code optimization option that provides a mechanism to incorporate up to 128 very large instruction words inside the DFB Code RAM.
  • Provides hardware signals such as DMA requests, DSI inputs and outputs, and interrupt lines.
  • Supports semaphores to interact with the system software and the option to tie the semaphores to hardware signals.

General Description

The digital filter block (DFB) in PSoC 3 and PSoC 5LP can be used as mini DSP processor and allows you to configure the DFB using assembly instructions. The component assembles the instructions entered in the editor and generates the corresponding hex code words, which can be loaded into the DFB. It also includes a simulator, which helps the user to simulate and debug the assembly instructions.

The DFB consists of a programmable 24*24 multiplier/accumulator (MAC), an arithmetic logic unit (ALU), shifter, and various program and data memory to store instructions and data. The DFB runs on the bus clock, and can interface with both CPU and DMA. It can be used to offload the CPU and can speed up arithmetic calculations that involve intensive multiply accumulate operations. Typical operations you can use the DFB component to implement include: vector operations, matrix operations, filtering operations, and signal processing.

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Wed, 09 Jul 2014 18:36:32 -0600
Sync http://www.cypress.com/?rID=48925 Features

  • Synchronizes 1 to 32 input signals
Symbol Diagram

General Description

The Sync component resynchronizes a set of input signals to the rising edge of the clock signal.

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Wed, 09 Jul 2014 18:32:15 -0600
Status Register http://www.cypress.com/?rID=46453 Features

  • Up to 8-bit Status Register
  • Interrupt support
Symbol Diagram

General Description

The Status Register allows the firmware to read digital signals.

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Wed, 09 Jul 2014 18:23:42 -0600
Sleep Timer http://www.cypress.com/?rID=48912 Features

  • Wakes up devices from low-power modes: Alternate Active and Sleep
  • Contains configurable option for issuing interrupt
  • Generates periodic interrupts while the device is in Active mode
  • Supports twelve discrete intervals: 2, 4, 8, 16, 32, 64, 128, 256, 512, 1024, 2048, and 4096 ms
     
Symbol Diagram
General Description

The Sleep Timer component can be used to wake the device from Alternate Active and Sleep modes at a configurable interval. It can also be configured to issue an interrupt at a configurable interval. For PSoC 5 architectures, an interrupt is required for the CPU to wake up.

For PSoC 5, the supported intervals are restricted to: 4, 8, 16, 32, 64, 128 or 256 ms. Refer to the CyPmSleep() function description in the System Reference Guide for details about this restriction. The PSoC 5LP device supports the full set of intervals.

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Wed, 09 Jul 2014 18:10:07 -0600
Shift Register (ShiftReg) http://www.cypress.com/?rID=48887 Features

  • Adjustable shift register size: 2 to 32 bits
  • Simultaneous shift in and shift out
  • Right shift or left shift
  • Reset input forces shift register to all 0s
  • Shift register value readable by CPU or DMA
  • Shift register value writable by CPU or DMA 

 

Symbol Diagram
General Description

The Shift Register (ShiftReg) component provides synchronous shifting of data into and out of a parallel register. The parallel register can be read or written to by the CPU or DMA. The Shift Register component provides universal functionality similar to standard 74xxx series logic shift registers including: 74164, 74165, 74166, 74194, 74299, 74595 and 74597. In most applications the Shift Register component will be used in conjunction with other components and logic to create higher-level application-specific functionality, such as a counter to count the number of bits shifted.

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Wed, 09 Jul 2014 18:00:15 -0600
Software Transmit UART (SW_Tx_UART) http://www.cypress.com/?rID=82360 Features Symbol Diagram
  • Baud rates from 9,600 up to 115,200 bps
  • High baud rate accuracy
  • Low Flash/ROM resource usage

General Description

The Software Transmit UART (SW_Tx_UART) component is an 8-bit RS-232 data-format compliant serial transmitter.


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Wed, 09 Jul 2014 17:24:17 -0600
Serial Peripheral Interface (SPI) Slave http://www.cypress.com/?rID=48908 Features

  • 3- to 16-bit data width
  • 4 SPI modes
  • Bit Rate up to 5 Mbps
Symbol Diagram

General Description

The SPI Slave provides an industry-standard, 4-wire slave SPI interface. It can also provide a 3-wire (bidirectional) SPI interface. Both interfaces support all four SPI operating modes, allowing communication with any SPI master device. In addition to the standard 8-bit word length, the SPI Slave supports a configurable 3- to 16-bit word length for communicating with nonstandard SPI word lengths.

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Wed, 09 Jul 2014 17:17:56 -0600
Serial Peripheral Interface (SPI) Master http://www.cypress.com/?rID=48906

Features

  • 3- to 16-bit data width
  • Four SPI operating modes
  • Bit Rate up to 18 Mbps
Symbol Diagram

General Description

The SPI Master component provides an industry-standard, 4-wire master SPI interface. It can also provide a 3-wire (bidirectional) SPI interface. Both interfaces support all four SPI operating modes, allowing communication with any SPI slave device. In addition to the standard 8-bit word length, the SPI Master supports a configurable 3- to 16-bit word length for communicating with nonstandard SPI word lengths.     


PSoC Creator SPI Master Component video

use for camtasia screencasts

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Wed, 09 Jul 2014 17:13:11 -0600
SMBus and PMBus Slave http://www.cypress.com/?rID=69782 Features
  • SMBus Slave mode
  • PMBus Slave mode
  • SMBALERT# pin support
  • 25 ms Timeout
  • Fixed Function (FF) and UDB implementations
  • Configurable SM/PM Bus commands
     
Symbol Diagram

General Description

The System Management Bus (SMBus) and Power Management Bus (PMBus) Slave component provides a simple way to add an I2C physical layer interface to a PSoC 3 or PSoC 5LP design with either SMBus or PMBus protocol running on top of it.

The SMBus is a two-wire interface with various System Management chips that can communicate with the system host. It uses I2C as a physical layer. The SMBus Slave component implements most of the SMBus Slave device specifications and provides options for configuring the slave device parameters. The slave device can communicate with the SMBus Master using the provided APIs.

The PMBus protocol is a specific implementation of the more generic SMBus protocol. With the PMBus, the component presents all the possible PMBus commands and allows you to select which commands are relevant to your application.

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Wed, 09 Jul 2014 16:43:07 -0600
Stay Awake http://www.cypress.com/?rID=51208 Features

  • Use routes which remain active during sleep
Symbol Diagram

General Description

To protect against unintended shorts, the SC/CT and SAR blocks disconnect their terminals when the block goes to sleep. This will also disconnect any routes (static or dynamic) which use the block terminal as a via, or use the block terminal for track jumping.

We allow the user to identify those routes which must stay awake during device sleep using the Stay Awake component, which has a single connection and no parameters. The net to which the stay_awake component is attached will be routed without using the SC/CT or SAR block terminals.

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Wed, 09 Jul 2014 16:39:14 -0600
Trans-Impedance Amplifier (TIA) http://www.cypress.com/?rID=48921 Features

  • Selectable conversion gain
  • Selectable corner frequency
  • Compensation for capacitive input sources
  • Adjustable power settings
  • Selectable input reference voltage
Symbol Diagram

General Description

The Trans-Impedance Amplifier (TIA) component provides an opamp-based current-to-voltage conversion amplifier with resistive gain and user-selected bandwidth. It is derived from the SC/CT block. 

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Wed, 09 Jul 2014 16:32:52 -0600
Switched-Capacitor / Continuous-Time Comparator (SCCT_COMP) http://www.cypress.com/?rID=82358 Features Symbol Diagram
  • Selectable input reference voltage
  • Output routable to digital logic blocks or pins
  • Selectable output polarity

General Description

The SC/CT Comparator (SCCT_Comp) component provides a hardware solution to compare two analog input voltages. The implementation uses a mode of the Switched Capacitor / Continuous Time (SC/CT) analog block to implement the comparator. The output can be digitally routed to another component. A reference or external voltage can be connected to either input. You can also invert the output of the comparator using the Polarity parameter.


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Wed, 09 Jul 2014 16:29:34 -0600
Resistive Touch http://www.cypress.com/?rID=58690 Features

  • Supports 4-wire resistive touchscreen interface
  • Supports the Delta Sigma Converter for both the PSoC 3 and PSoC 5 devices
  • Supports the ADC Successive Approximation Register for PSoC 5 devices
    Symbol Diagram
General Description

This resistive touchscreen component is used to interface with a 4-wire resistive touch screen. The component provides a method to integrate and configure the resistive touch elements of a touchscreen with the emWin Graphics library. It integrates hardware-dependent functions that are called by the touchscreen driver supplied with emWin when polling the touch panel.

PSoC® Creator emWin and Resistive Touch Components Video
use for camtasia screencasts

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Wed, 09 Jul 2014 16:00:30 -0600
Resistance Temperature Detector Calculator (RTD) http://www.cypress.com/?rID=69784 Features
  • Calculation accuracy 0.01 °C for -200 °C to 850 °C temperature range
  • Provides simple API function for resistance to temperature conversion
  • Displays Error Vs Temperature graph
Symbol Diagram

General Description

The Resistance Temperature Detector (RTD) Calculator component generates a polynomial approximation for calculating the RTD Temperature in terms of RTD resistance for a PT100, PT500 or PT1000 RTD. Calculation error budget is user-selectable, and determines the order of the polynomial that will be used for the calculation (from 1 to 5). A lower calculation error budget will result in a more computation intensive calculation. For example, a fifth order polynomial will give a more accurate temperature calculation than lower order polynomials, but will take more time for execution. After maximum and minimum temperatures and error budget are selected, the component generates the maximum temperature error, and an error vs. temperature graph for all temperatures in the range, along with an estimate of the number of CPU cycles necessary for calculation using the selected polynomial. Selecting the lowest error budget will choose the highest degree polynomial. For the whole RTD temperature range, -200 °C to 850 °C, the component can provide a maximum error of <0.01 °C using a fifth order polynomial.

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Wed, 09 Jul 2014 15:54:01 -0600
Quadrature Decoder (QuadDec) http://www.cypress.com/?rID=46480 Features

  • Adjustable counter size: 8, 16, or 32 bits
  • Counter resolution of 1x, 2x, or 4x the frequency of the A and B inputs, for more accurate determination of position or speed
  • Optional index input to determine absolute position
  • Optional glitch filtering to reduce the impact of system-generated noise on the inputs
Symbol Diagram

General Description

The Quadrature Decoder (QuadDec) Component gives you the ability to count transitions on a pair of digital signals. The signals are typically provided by a speed/position feedback system mounted on a motor or trackball.

The signals, typically called A and B, are positioned 90 degrees out of phase, which results in a Gray code output. A Gray code is a sequence where only one bit changes on each count. This is essential to avoid glitches. It also allows detection of direction and relative position. A third optional signal, named Index, is used as a reference to establish an absolute position once per rotation.

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Wed, 09 Jul 2014 15:48:34 -0600
Precision Illumination Signal Modulation (PrISM) http://www.cypress.com/?rID=48890 Features

  • Programmable flicker-free dimming resolution from 2 to 32 bit
  • Two pulse density outputs
  • Programmable output signal density
  • Serial output bit stream
  • Continuous run mode
  • User-configurable sequence start value
  • Standard or custom polynomials provided for all sequence lengths
  • Kill input disables pulse density outputs and forces them low
  • Enable input provides synchronized operation with other components
  • Reset input allows restart at sequence start value for synchronization with other components
  • Terminal Count Output for 8-, 16-, 24-, and 32-bit sequence lengths.
Symbol Diagram

General Description

The Precision Illumination Signal Modulation (PrISM) component uses a linear feedback shift register (LFSR) to generate a pseudo random sequence. The sequence outputs a pseudo random bit stream, as well as up to two user-adjustable pseudo random pulse densities. The pulse densities may range from 0 to 100 percent.

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Wed, 09 Jul 2014 15:40:06 -0600
Pins http://www.cypress.com/?rID=48513 Features

  • Rapid setup of all pin parameters and drive modes
  • Allows PSoC Creator to automatically place and route signals
  • Allows interaction with one or more pins simultaneously
Symbol Diagram

General Description

The Pins component allows hardware resources to connect to a physical port-pin. It provides access to external signals through an appropriately configured physical IO pin. It also allows electrical characteristics (e.g., Drive Mode) to be chosen for one or more pins; these characteristics are then used by PSoC Creator to automatically place and route the signals within the component.

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Wed, 09 Jul 2014 12:35:57 -0600
S/PDIF Transmitter (SPDIF_Tx) http://www.cypress.com/?rID=56750 Features
Symbol Diagram
  • Conforms to IEC-60958, AES/EBU, AES3 standards for Linear PCM Audio Transmission
  • Sample rate support for clock/128 (up to 192 kHz)
  • Configurable audio sample length (8/16/24)
  • Channel status bits generator for consumer applications
  • DMA support
  • Independent left and right channel FIFOs or interleaved stereo FIFOs

General Description

The SPDIF_Tx component provides a simple way to add digital audio output to any design. It formats incoming audio data and metadata to create the S/PDIF bit stream appropriate for optical or coaxial digital audio. The component supports interleaved and separated audio.

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Wed, 09 Jul 2014 12:31:54 -0600
Pulse Width Modulator (PWM) http://www.cypress.com/?rID=48869 Features

  • 8- or 16-bit resolution
  • Multiple pulse width output modes
  • Configurable trigger
  • Configurable capture
  • Configurable hardware/software enable
  • Configurable dead band
  • Multiple configurable kill modes
  • Customized configuration tool
  • Fixed-function (FF) implementation for PSoC 3 and PSoC 5 devices
Symbol Diagram

General Description

The PWM component provides compare outputs to generate single or continuous timing and control signals in hardware. The PWM provides an easy method of generating complex real-time events accurately with minimal CPU intervention. PWM features may be combined with other analog and digital components to create custom peripherals.

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Wed, 09 Jul 2014 12:25:41 -0600
Component Locking Feature Using the Analog Device Editor in PSoC<sup>®</sup> Creator™ – KBA85474 http://www.cypress.com/?rID=97356 Answer: There are two methods by which this can be achieved.

Method 1: Use the placement force directives under the Directives tab of the .cydwr file of the project.

Example: Forcing a SAR ADC component on Top Design to a particular location in the fitter (i.e., a way of telling the routing tool which of the available two fixed function SAR ADCs to select for this component). The following design schematic has two SAR ADCs: ADC1 and ADC2, which should be locked down to SAR0 and SAR1 respectively.

Figure 1. Design Schematic

Design Schematic

Figure 2. The .cydwr Settings under the Directives Tab

Directives Tab

Method 2: Use the lock down and relocate feature of the Analog Device Editor. This is limited to locking down only analog components, signals, and nets.

For the same example and Top Design as the above method, do the following.

  1. Go to the Analog tab under the .cydwr file of the project.
  2. For relocating the current selection of component using the fitter tool: Right-click the component, select Relocate, and make the appropriate selection.
  3. For locking the existing selection of a component: Right-click a particular SAR ADC position—say, SAR0—and click Lock to F(SAR,0).
  4. The display table on the right side also has a description of the components, muxes, pins, and nets. Locking can also be done by checking the corresponding Locked check box. The locked components have a small lock symbol at the top of the component.

Figures 3–5 depict the procedure explained here.

Figure 3. Relocating an Existing Selection of the Component

Relocating

Figure 4. Lock-Down Feature in the Analog Device Editor

Lock-Down

Figure 5. The Lock Symbol at the Top Left of SAR0

Lock Symbol

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Wed, 09 Jul 2014 04:00:35 -0600
Endian Format in a PSoC<sup>®</sup> 3/4/5LP Device Versus a Compiler – KBA91560 http://www.cypress.com/?rID=97351 Answer:

CPU Access:

The Keil Compiler provides macros (defined in cymem.a51) to access registers that internally control byte swapping. These macros must be used to access 8-, 16-, and 32-bit registers in PSoC 3 devices.

Macros for accessing registers mapped in the first 64K of XDATA space:

  • CY_GET_REG8(addr)
  • CY_SET_REG8(addr, value)
  • CY_GET_REG16(addr)
  • CY_SET_REG16(addr, value)
  • CY_GET_REG24(addr)
  • CY_SET_REG24(addr, value)
  • CY_GET_REG32(addr)
  • CY_SET_REG32(addr, value)

Macros for accessing registers mapped above the first 64K of XDATA space:

  • CY_GET_XTND_REG8(addr)
  • CY_SET_XTND_REG8(addr, value)
  • CY_GET_XTND_REG16(addr)
  • CY_SET_XTND_REG16(addr, value)
  • CY_GET_XTND_REG24(addr)
  • CY_SET_XTND_REG24(addr, value)
  • CY_GET_XTND_REG32(addr)
  • CY_SET_XTND_REG32(addr, value)

DMA Access:

When the source and destination data is organized in different endianness, the DMA transaction descriptor can be programmed to have the bytes endian swapped while in transit.

The SWAP_EN bit of the PHUB.TDMEM[0..127].ORIG_TD0 register specifies whether an endian swap should occur. If SWAP_EN is ‘1’ then an endian swap will occur. The size of the swap is determined by the SWAP_SIZE bit of the PHUB.TDMEM[0..127].ORIG_TD0 register.

  • If SWAP_SIZE = 0 then the swap size is two bytes, meaning that every two bytes are endian swapped during the DMA transfer.
    The code snippet of the TD configuration API to enable byte swapping for 2bytes data is given below.

    CyDmaTdSetConfiguration(myTd, 2, myTd, TD_TERMOUT0_EN | TD_SWAP_EN);

  • If SWAP_SIZE = 1 then the swap size is four bytes, meaning that every four bytes are endian swapped during the DMA transfer.
    The code snippet of the TD configuration API to enable byte swapping for 4bytes data is given below.

    CyDmaTdSetConfiguration(myTd, 4, myTd, TD_TERMOUT0_EN | TD_SWAP_EN | TD_SWAP_SIZE4);

PSoC 4/5LP:

PSoC 4/5LP designs use a GCC or MDK compiler that is based on little endian, unlike the PSoC 3 Keil Compiler. Therefore, DMA byte swapping must be disabled when the code is ported to a PSoC 5LP device. The same is not applicable for PSoC 4 because there is no DMA support for PSoC 4.

Refer to the DMA component datasheet, PSoC 3 Technical Reference Manual, and PSoC 5LP Technical Reference Manual for more details on DMA operation and usage.

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Wed, 09 Jul 2014 01:39:08 -0600
Scanning Comparator (ScanComp) http://www.cypress.com/?rID=86075

Features

  • Scan up to 64 single ended or differential channels automatically
    Note The number of input and output channels will be limited by
    the hardware available in the device being used.
  • Up to 64 outputs routable to digital logic blocks or pins
  • Multiple comparison modes

Symbol Diagram

General Description

The Scanning Comparator (ScanComp) component provides a hardware solution to compare up to 64 pairs of analog input voltages signals using just one hardware comparator. The sampled comparator outputs can be enabled for connection in digital hardware. A reference or external voltage can be connected to each input.

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Tue, 08 Jul 2014 17:54:32 -0600
Trim and Margin http://www.cypress.com/?rID=71587  

Features
  • Works with most adjustable DC-DC converters or regulators including LDOs, switchers and modules
  • Supports up to 24 DC-DC converters
  • 8 to 10-bit resolution PWM pseudo-DAC outputs
  • Supports real-time, closed-loop active trimming when used in conjunction with the Power Monitor component
  • Built-in support for margining
Symbol Diagram

General Description

The Trim and Margin component provides a simple way to adjust and control the output voltage of up to 24 DC-DC converters to meet system power supply requirements.

Users of this component simply enter the power converter nominal output voltages, voltage trimming range, margin high and margin low settings into the intuitive, easy-to-use graphical configuration GUI and the component takes care of the rest. The component will also assist the user to select appropriate external passive component values based on performance requirements.

The provided firmware APIs enable users to manually trim the power converter output voltages to any desired level within the operational limits of the power converter. Real-time active trimming or margining is supported via as a continuously running background task with an update frequency controlled by the user. 

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Tue, 08 Jul 2014 16:37:41 -0600
Dithered Voltage Digital to Analog Converter (DVDAC) http://www.cypress.com/?rID=86073

Features

  • Two voltage ranges, 1 and 4 volts
  • Adjustable 9, 10, 11, or 12 bit resolution
  • Dithered using DMA for zero CPU overhead
  • Uses a single DAC block

Symbol Diagram

General Description

The Dithered Voltage Digital to Analog Converter (DVDAC) component has a selectable resolution between 9 and 12 bits. Dithering is used to increase the resolution of its underlying 8-bit VDAC8. Only a small output capacitor is required to suppress the noise generated by dithering.

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Tue, 08 Jul 2014 16:26:14 -0600
8-Bit Voltage Digital to Analog Converter (VDAC8) http://www.cypress.com/?rID=49054 Features

  • Voltage output ranges: 1.020-V and 4.080-V full scale
  • Software or clock driven output strobe
  • Data source can be CPU, DMA, or Digital components
Symbol Diagram

General Description

The VDAC8 component is an 8-bit voltage output Digital to Analog Converter (DAC). The output range can be from 0 to 1.020 V (4 mV/bit) or from 0 to 4.08 V (16 mV/bit). The VDAC8 can be controlled by hardware, software, or a combination of both hardware and software.

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Tue, 08 Jul 2014 13:50:15 -0600
LED Segment and Matrix Driver http://www.cypress.com/?rID=82355 Features Symbol Diagram
  • Up to 8 RGB 7-segment digits, or 24 monochrome 7-segment digits
  • Up to 8 14-segment or 16-segment displays
  • Up to 192 LEDs in an 8x8 tri-color matrix
  • Active high or active low commons
  • Active high or active low segments
  • Driver is multiplexed requiring no CPU overhead or interrupts
  • Functions for numeric and string display using 7-, 14-, and 16-segment displays
  • Independent brightness level for each common


General Description

The LED Segment and Matrix Driver component is a multiplexed LED driver that can handle up to 24 segment signals and 8 common signals. It can be used to drive 24 7-segment LEDs, eight 14/16-segment LEDs, eight RGB 7-segment LEDs, or a tri-color matrix of up to 192 LEDs in an 8x8 pattern. APIs are provided to convert alpha-numeric values to their segment codes, and the brightness of each of the commons can be controlled by the user. This component is supported for PSoC 3 and PSoC 5LP.

Multiplexing the LEDs is an efficient way to save GPIO pins, however the commons must be multiplexed at a steady rate. To address this latter issue, the component uses PSoC’s DMA and UDBs to multiplex the LEDs without CPU overhead. This eliminates cases of non-periodic updating as the multiplexing is handled solely using hardware. The CPU is thus used only when updating the display information and to change the brightness settings.

When displaying the 7/14/16 segment digits, these digits do not have to be grouped as a single numerical display. An 8 digit display could be divided up into one 2-digit and two 3-digit displays. When operating in the LED matrix mode, the individual displays do not have to be arranged in a matrix, but instead can be various single or grouped LEDs. The component also supports displaying combined digits with annunciators.


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Tue, 08 Jul 2014 12:08:05 -0600
Inter-IC Sound Bus (I2S) http://www.cypress.com/?rID=46464

Features

  • Master only
  • 8 to 32 data bits per sample
  • 16-, 32-, 48-, or 64-bit word select period
  • Data rate up to 96 kHz with 64-bit word select period: 6.144 MHz
  • Tx and Rx FIFO interrupts
  • DMA support
  • Independent left and right channel FIFOs or interleaved stereo FIFOs
  • Independent enable of Rx and Tx
Symbol Diagram

General Description

The Integrated Inter-IC Sound Bus (I2S) is a serial bus interface standard used for connecting digital audio devices together. The specification is from Philips® Semiconductor (I2S bus specification; February 1986, revised June 5, 1996).

The I2S component operates in master mode only. It also operates in two directions, as a transmitter (Tx) and a receiver (Rx). The data for Tx and Rx are independent byte streams. The  byte streams are packed with the most significant byte first and the most significant bit in bit 7 of  the first word. The number of bytes used for each sample (a sample for the left or right channel)  is the minimum number of bytes to hold a sample.


PSoC Creator I2S Component Video

 

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Tue, 08 Jul 2014 11:47:48 -0600
Direct Memory Access (DMA) http://www.cypress.com/?rID=46450 Features

  • 24 channels
  • Eight priority levels
  • 128 Transaction Descriptors (TDs)
  • 8-, 16-, and 32-bit data transfers
  • Configurable source and destination addresses
  • Support for endian compatibility
  • Can generate an interrupt when data transfer is complete
  • DMA Wizard to assist with application development
Symbol Diagram

General Description

The DMA component allows data transfers to and from memory, components, and registers. The controller supports 8-, 16-, and 32-bit wide data transfers, and can be configured to transfer data between a source and destination that have different endianess. TDs can be chained together for complex operations.

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Mon, 07 Jul 2014 23:57:46 -0600
TMP05 Temp Sensor Interface http://www.cypress.com/?rID=73669 Features

  • Supports up to four TMP05 or TMP06 digital temperature sensors connected in daisy chain mode only
  • Continuous and one-shot modes of operation
  • Supports frequencies from 100 to 500 kHZ
  • Supports temperature range from 0 to 70 Celsius degrees
Symbol Diagram

General Description

The TMP05 Temp Sensor Interface component is a simple, easy to use component capable of interfacing with Analog Device’s TMP05/06 digital temperature sensors in daisy chain mode only. You can configure the component and monitor the temperature readings in one of two ways:

  • The continuous monitoring option allows you to record temperatures in a continuous fashion, at a sample rate dictated by the temperature sensor(s)
  • One-shot mode triggers the temperature measurement at a rate you can control control.

The first mode is intended for use in an environment where temperature variations are abrupt and need to be monitored frequently. The second option should be used when temperature measurements only need to be sampled once in a while or in applications where minimizing power consumption is important.
 

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Mon, 07 Jul 2014 19:01:34 -0600
Power Monitor http://www.cypress.com/?rID=63922 Features

  • Interfaces to up to 32 DC-DC power converters
  • Measures power converter output voltages and load currents using a DelSig-ADC
  • Monitors the health of the power converters generating warnings and faults based on user-defined thresholds
  • Support for measuring other auxiliary voltages in the system
  • Support 3.3V and 5V chip power supply
Symbol Diagram


General Description

Power Converter Voltage Measurements:

For power converter voltage measurements, the ADC can be configured into single-ended mode (0-4.096 V range or 0-2.048 V range). The ADC can also be configurable into differential mode (±2.048 V range) to support remote sensing of voltages where the remote ground reference is returned to PSoC over a PCB trace. In cases where the analog voltage to be monitored equals or exceeds Vdda or the ADC range, external resistor dividers are recommended to scale the monitored voltages down to an appropriate range.

Power Converter Current Measurements:

For power converter load current measurements, the ADC can be configured into differential mode (+/- 64 mV or +/- 128 mV range) to support voltage measurement across a high-side series shunt resistor on the outputs of the power converters. Firmware APIs convert the measured differential voltage into the equivalent current based on the external resistor component value used. The ADC can also be configured into single-ended mode (matching the selected voltage measurement range) to support connection to external current sense amplifiers (CSAs) that convert the differential voltage drop across the shunt resistor into a single ended voltage or to support power converters or hot-swap controllers that integrate similar functionality.

PSoC Creator Power Monitor Component Video  

use for camtasia screencasts

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Mon, 07 Jul 2014 18:50:13 -0600
Pseudo Random Sequence (PRS) http://www.cypress.com/?rID=46478 Features

  • 2 to 64 bits PRS sequence length
  • Time Division Multiplexing mode
  • Serial output bit stream
  • Continuous or single-step run modes
  • Standard or custom polynomial
  • Standard or custom seed value
  • Enable input provides synchronized operation with other components
  • Computed pseudo random number can be read directly from the Linear Feedback Shift Register (LFSR)
Symbol Diagram

General Description

The Pseudo Random Sequence (PRS) component uses an LFSR to generate a pseudo random sequence, which outputs a pseudo random bit stream. The LFSR is of the Galois form (sometimes known as the modular form) and uses the provided maximal code length, or period. The PRS component runs continuously after starting as long as the Enable Input is held high. The PRS number generator can be started with any valid seed value other than 0.

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Mon, 07 Jul 2014 18:29:58 -0600
Programmable Gain Amplifier (PGA) http://www.cypress.com/?rID=48849

Features

  • Gain steps from 1 to 50
  • High input impedance
  • Selectable input reference
  • Adjustable power settings
Symbol Diagram

General Description

The PGA implements an opamp-based, non-inverting amplifier with user-programmable gain. This amplifier has high input impedance, wide bandwidth and selectable input voltage reference. It is derived from the switched capacitor/continuous time (SC/CT) block.

The gain can be between 1 (0 dB) and 50 (+34 dB). The gain can be selected using the configuration window or changed at run time using the provided API. The maximum bandwidth is limited by the gain-bandwidth product of the opamp and is reduced as the gain is increased. The input of the PGA operates from rail to rail, but the maximum input swing (difference between Vin and Vref) is limited to VDDA/Gain. The output of the PGA is class A, and is rail to rail for sufficiently high load resistance.

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Mon, 07 Jul 2014 18:22:44 -0600
Inverting Programmable Gain Amplifier (PGA_Inv) http://www.cypress.com/?rID=48923 Features

  • Gain steps from -1 to -49
  • High input impedance
  • Adjustable power settings
Symbol Diagram

General Description

The Inverting Programmable Gain Amplifier (PGA_Inv) component implements an opamp-based inverting amplifier with user-programmable gain. It is derived from the switched capacitor/continuous time (SC/CT) block.

The inverting gain can be between -1.0 (0 dB) and -49.0 (+33.8 dB). The gain can be selected using the configuration window or changed at run time using the provided API. The maximum bandwidth is limited by the gain-bandwidth of the opamp and is reduced as the gain is increased. The input of the PGA_Inv operates from rail to rail, but the maximum input swing (difference between Vin and Vref) is limited to VDDA/Gain. The output of the PGA_Inv is class A, and is rail to rail for sufficiently high load resistance.

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Mon, 07 Jul 2014 18:15:03 -0600
Operational Amplifier (Opamp) http://www.cypress.com/?rID=48919

Features

  • Follower or Opamp configuration
  • Unity gain bandwidth > 3.0 MHz
  • Input offset voltage 2.0 mV max
  • Rail-to-rail inputs and output
  • Output direct low resistance connection to pin
  • 25 mA output current
  • Programmable power and bandwidth
  • Internal connection for follower (saves pin)
Symbol Diagram

General Description

The Opamp component provides a low-voltage, low-power operational amplifier and may be internally connected as a voltage follower. The inputs and output may be connected to internal routing nodes, directly to pins, or a combination of internal and external signals. The Opamp is suitable for interfacing with high-impedance sensors, buffering the output of voltage DACs, driving up to 25 mA; and building active filters in any standard topology.   

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Mon, 07 Jul 2014 18:04:28 -0600
Net Tie http://www.cypress.com/?rID=69003 Features

  • Connects two analog routes
  • Connects a constrained analog route with an unconstrained analog route
  • Connects two analog routes with different routing resource constraints
Symbol Diagram

General Description

The Net Tie component connects two analog routes to each other. Each of the routes may have a different analog resource constraint.
 

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Mon, 07 Jul 2014 17:52:03 -0600
Net Join http://www.cypress.com/?rID=56746 Features

  • Connects two analog routes
  • Connects a constrained analog route with an unconstrained analog route
  • Connects two analog routes with different routing resource constraints
Symbol Diagram

General Description

The Net Join component connects two analog routes to each other. Each of the routes may have a different analog resource constraint.

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Mon, 07 Jul 2014 17:48:26 -0600
Mixer http://www.cypress.com/?rID=48920 Features
Symbol Diagram
  • Single-ended mixer
  • Continuous-time up mixing:
    • Input frequencies up to 500 kHz
    • Sample clock up to 1 MHz
  • Discrete-time, sample-and-hold down mixing:
    • Input frequencies up to 14 MHz
    • Sample clock up to 4 MHz
  • Adjustable power settings
  • Selectable reference voltage

General Description

The Mixer component provides a single-ended modulator. The Mixer component can be used for frequency conversion of an input signal using a fixed Local Oscillator (LO) signal as the sampling clock. The manipulations of signal frequencies that a mixer performs can be used to move signals between frequency bands or to encode and decode signals. A mixer can be used to convert signal power at one frequency into power at another frequency to make signal processing easier, typically shifting higher frequencies to baseband.

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Mon, 07 Jul 2014 17:43:18 -0600
Lookup Table (LUT) http://www.cypress.com/?rID=46472 Features

  • 1 to 5 Inputs
  • 1 to 8 Outputs
  • Configuration Tool
  • Optionally Registered Outputs
Symbol Diagram

General Description

You can set up the Lookup Table (LUT) component to perform any logic function with up to five inputs and eight outputs. This is done by generating logic equations that are realized in the UDB PLDs. Optionally, the outputs can be registered. These registers are implemented in PLD macrocells. All macrocell flip-flops are initialized to a 0 value at power up and after any reset of the device.

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Mon, 07 Jul 2014 17:40:17 -0600
LIN Slave http://www.cypress.com/?rID=56718

Features

Symbol Diagram
  • Full LIN 2.1 or 2.0 Slave Node implementation
  • Supports compliance with SAE J2602-1 specification
  • Automatic baud rate synchronization
  • Fully implements a Diagnostic Class I Slave Node
  • Full transport layer support
  • Automatic detection of bus inactivity
  • Full error detection
  • Automatic configuration services handling
  • Customizer for fast and easy configuration
  • Import of *.ncf/*.ldf files and *.ncf file export
  • Editor for *.ncf/*.ldf files with syntax checking


General Description

The LIN Slave component implements a LIN 2.1 slave node on PSoC 3 and PSoC 5LP devices. Options for LIN 2.0 or SAE J2602-1 compliance are also available. This component consists of the hardware blocks necessary to communicate on the LIN bus, and an API to allow the application code to easily interact with the LIN bus communication. The component provides an API that conforms to the API specified by the LIN 2.1 Specification.

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Mon, 07 Jul 2014 17:35:44 -0600
Segment LCD (SegLCD) http://www.cypress.com/?rID=48918 Features

  • 2 to 768 pixels or symbols
  • 1/3, 1/4 and 1/5 bias supported
  • 10- to 150-Hz refresh rate
  • Integrated bias generation between 2.0 V and 5.2 V with up to 128 digitally controlled bias levels for dynamic contrast control
  • Supports both type A (standard) and type B (low power) waveforms
  • Pixel state of the display may be inverted for negative image
  • 256 bytes of display memory (frame buffer)
  • User-defined pixel or symbol map with optional 7-, 14-, or 16-segment character; 5x7 or 5x8 dot matrix; and bar graph calculation routines.
Symbol Diagram


General Description

The Segment LCD (LCD_Seg) component can directly drive a variety of LCD glass at different voltage levels with multiplex ratios up to 16x. This component provides an easy method of configuring the PSoC device to drive your custom or standard glass. 

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Mon, 07 Jul 2014 17:22:18 -0600
Graphic LCD Controller (GraphicLCDCtrl) http://www.cypress.com/?rID=48850 Features

  • Fully programmable screen size support up to HVGA resolution including:
    • QVGA (320x240) @ 60 Hz 16 bpp
    • WQVGA (480x272) @ 60 Hz 16 bpp
    • HVGA (480x320) @ 60 Hz 16 bpp
  • Supports virtual screen operation
  • Interfaces with SEGGER emWin graphics library
  •  Performs read and write transactions during the blanking intervals
  • Generation of continuous timing signals to the panel without CPU intervention
  • Supports up to a 23-bit address and a 16-bit data async SRAM device used as externally provided frame buffer
  • Generates a selectable interrupt pulse at the entry and exit of the horizontal and vertical blanking intervals
Symbol Diagram

General Description

The Graphic LCD Controller (GraphicLCDCtrl) component provides the interface to an LCD panel that has an LCD driver, but not an LCD controller. This type of panel does not include a frame buffer. The frame buffer must be provided externally.

This component also interfaces to an externally provided frame buffer implemented using a 16-bit wide async SRAM device.

     
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Mon, 07 Jul 2014 17:11:57 -0600
Static Segment LCD (StaticSegLCD) http://www.cypress.com/?rID=46487
 Features
 
  • 1 to 61 pixels or symbols
  • 10- to 150-Hz refresh rate
  • User-defined pixel or symbol map with optional 7-segment, 14-segment, 16-segment and bar graph calculation routines
  • Direct drive static (one common) LCDs
   Symbol Diagram


General Description

The Static Segment LCD (LCD_SegStatic) component can directly drive 3.3-V and 5.0-V LCD glass. This component provides an easy method of configuring the PSoC device for your custom or standard glass.

Each LCD pixel/symbol may be either on or off. The Static Segment LCD component also provides advanced support to simplify the following types of display structures within the glass:

  • 7-Segment numeral
  • 14-Segment alphanumeric
  • 16-Segment alphanumeric
  • 1- to 255-element bar graph
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Mon, 07 Jul 2014 16:47:44 -0600
Interrupt http://www.cypress.com/?rID=46451

Features

  • Defines hardware-triggered interrupts
  • Provides a software method to pend interrupt
Symbol Diagram

General Description

The Interrupt component defines hardware triggered interrupts. It is an integral part of the Interrupt Design-Wide Resource system (see PSoC Creator Help, Design-Wide Resources section).

There are three types of system interrupt waveforms that can be processed by the interrupt controller:

  • Level – IRQ source is sticky and remains active until firmware clears the source of the request with an action (for example clear on read). Most fixed-function peripherals have level-sensitive interrupts, including the UDB FIFOs and status registers.
  • Pulse – Ideally, a pulse IRQ is a single bus clock, which logs a pending action and ensures that the ISR action is only executed once. No firmware action to the peripheral is required.
  • Edge – An arbitrary synchronous waveform is the input to an edge-detect circuit and the positive edge of that waveform becomes a synchronous one-cycle pulse (Pulse mode).
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Mon, 07 Jul 2014 16:35:41 -0600
I2C Master/Multi-Master/Slave http://www.cypress.com/?rID=51969

Features

  • Industry-standard NXP® I2C bus interface
  • Supports Slave, Master, Multi-Master and Multi-Master-Slave operation
  • Requires only two pins (SDA and SCL) to interface to I2C bus
  • Supports standard data rates of 100/400/1000 kbps
  • High level APIs require minimal user programming
   
  Symbol Diagram


General Description

The I2C component supports I2C slave, master, and multi-master configurations. The I2C bus is an industry-standard, two-wire hardware interface developed by Philips. The master initiates all communication on the I2C bus and supplies the clock for all slave devices.

The I2C component supports standard clock speeds up to 1000 kbps. It is compatible with I2C Standard-mode, Fast-mode, and Fast-mode Plus devices as defined in the NXP I2C-bus specification. The I2C component is compatible with other third-party slave and master devices.

Note: This version of the component datasheet covers both the fixed hardware I2C block and the UDB version.

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Mon, 07 Jul 2014 16:27:30 -0600
Graphic LCD Interface (GraphicLCDIntf) http://www.cypress.com/?rID=48854 Features

  • 8 or 16 bit interface to Graphic LCD Controller
  • Compatible with many graphic controller devices
  • Interfaces with SEGGER emWin graphics library
  • Performs Read and write transaction
  • 2-255 cycles for Read Low Pulse Width
  • 1-255 cycles for Read High Pulse Width
  • Implements typical i8080 interface
Symbol Diagram
General Description

The Graphic LCD Interface (GraphicLCDIntf) component provides the interface to a graphic LCD controller and driver device. These devices are commonly integrated into an LCD panel. The interface to these devices is commonly referred to as an i8080 interface. This is a reference to the historic parallel bus interface protocol of the Intel 8080 microprocessor.    

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Mon, 07 Jul 2014 16:18:59 -0600
Glitch Filter http://www.cypress.com/?rID=69781 Features
  • Eliminates unwanted “glitch” pulses on digital input lines
  • Programmable filtering length and bypass option

     
Symbol Diagram

General Description

Glitch filtering is the process of removing unwanted pulses from a digital input signal that is usually high or low. Glitches frequently occur on lines carrying signals from sources such as RF receivers. Electrical or in some cases even mechanical interference can trigger an unwanted glitch pulse from the receiver.

This design outputs a ‘1’ only when the current and previous N samples are ‘1’, and a ‘0’ only when the current and previous N samples are ‘0’. Otherwise the output is unchanged from its current value.

For more details on glitch filtering please see application note AN60024.

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Mon, 07 Jul 2014 16:15:13 -0600
Filter http://www.cypress.com/?rID=46458 Features

  • Easy filter configuration using the Digital Filter Block (DFB) available in select PSoC 3 and PSoC 5LP devices
  • Supports two separate filter channels, each one constructed as a cascade of up to four separately designed stages.
  • Multiple FIR and IIR (Biquad) filter methods
  • Support for flexible coefficient entry
  • Final coefficient values available for further analysis
Symbol Diagram

 

General Description

The Filter component allows easy creation of single or dual channel digital filters using the DFB. The component includes a filter design feature, which greatly simplifies the design and implementation processes. It supports two streaming channels that can be streamed directly from other hardware blocks (such as the ADC) using DMA. The filtered results can likewise be transferred using DMA, interrupts, or polling methods. The DFB’s 128 data and coefficient locations are shared as needed between the two filter channels, and this information is used to guide the choice of filter implementation. It reports (but does not set) the minimum bus clock frequency required to execute the filtering within the declared sample interval. This clock can then be set in the design-wide resource manager.

The Filter component supports many use cases. If something unusual occurs when using it, please report it (with a good description). Either email psoc_creator_feedback@cypress.com or contact tech support at www.cypress.com.


PSoC® Creator Filter 2.0 Component Video

 

 
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Mon, 07 Jul 2014 16:09:20 -0600
Fan Controller http://www.cypress.com/?rID=63918 Features

  • Support for up to 16 PWM controlled, 4-wire brushless DC fans
  • Individual or banked PWM outputs with tachometer inputs
  • Supports 25 kHz, 50 kHz or user-specified PWM frequencies
  • Supports fan speeds up to 25,000 RPM
  • Supports 4-pole and 6-pole motors
  • Supports fan stall / rotor lock detection on all fans
  • Supports firmware controlled or hardware controlled fan speed regulation
  • Customizable alert pin for fan fault reporting
Symbol Diagram

General Description

The Fan Controller component enables designers to quickly and easily develop fan controller solutions using PSoC. The component is a system-level solution that encapsulates all necessary hardware blocks including PWMs, tachometer input capture timer, control registers, status registers and a DMA controller reducing development time and effort.

The component is customizable through a graphical user interface enabling designers to enter fan electromechanical parameters such as duty cycle-to-RPM mapping and physical fan bank organization. Performance parameters including PWM frequency and resolution as well as open or closed loop control methodology can be configured through the same user interface. Once the system parameters are entered, the component delivers the most optimal implementation saving resources within PSoC to enable integration of other thermal management and system management functionality. Easy-to-use APIs are provided to enable firmware developers to get up and running quickly.

 

PSoC Creator Fan Controller Component Video

use for camtasia screencasts

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Mon, 07 Jul 2014 15:42:09 -0600
Emulated EEPROM http://www.cypress.com/?rID=82352 Features Symbol Diagram
  • Provides EEPROM-like non-volatile storage
  • Supports PSoC 3, PSoC 4, and PSoC 5LP devices

General Description

The Emulated EEPROM component emulates an EEPROM device in the flash memory of a PSoC, providing simplified access to non-volatile memory.


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Mon, 07 Jul 2014 13:54:22 -0600
EZI2C Slave http://www.cypress.com/?rID=48917 Features
  • Industry standard NXP® I2C bus interface
  • Emulates common I2C EEPROM interface
  • Only two pins (SDA and SCL) required to interface to I2C bus
  • Standard data rates of 50/100/400/1000 kbps
  • High level APIs require minimal user programming
  • Supports one or two address decoding with independent memory buffers
  • Memory buffers provide configurable Read/Write and Read Only regions
Symbol Diagram

General Description

The EZI2C Slave component implements an I2C register-based slave device. It is compatible with I2C Standard-mode, Fast-mode, and Fast-mode Plus devices as defined in the NXP I2C-bus specification.The master initiates all communication on the I2C bus and supplies the clock for all slave devices. The EZI2C Slave supports standard data rates up to 1000 kbps and is compatible with multiple devices on the same bus.
 

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Mon, 07 Jul 2014 13:45:17 -0600
External Memory Interface (EMIF) http://www.cypress.com/?rID=56752 Features
Symbol Diagram
  • 8-, 16-, 24-bit address bus width
  • 8-, 16-bit data bus width
  • Supports external synchronous memory
  • Supports external asynchronous memory
  • Supports custom interface for memory
  • Supports a range of speeds of external memories (from 5 to 200 ns)
  • Supports external memory power-down, sleep, and wakeup modes

General Description

The EMIF component enables access by the CPU or DMA to memory ICs external to the PSoC 3/PSoC 5LP. It facilitates setup of the EMIF hardware, as well as UDBs and GPIOs as required. The EMIF can control synchronous and asynchronous memories without the need to configure any UDBs in synchronous and asynchronous modes. In UDB mode, UDBs must be configured to generate external memory control signals.

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Mon, 07 Jul 2014 13:39:38 -0600
EEPROM http://www.cypress.com/?rID=46455 Features Symbol Diagram
  • 512 B to 2 KB EEPROM memory
  • 1,000,000 cycles, 20-year retention
  • Read/Write 1 byte at a time
  • Program 16 bytes (a row) at a time

General Description

The EEPROM component provides a set of APIs to erase and write data to nonvolatile EEPROM memory. The term write implies that it will erase and then program in one operation.

An EEPROM memory in PSoC devices is organized in arrays. PSoC 3 and PSoC 5LP devices offer an EEPROM array of size 512 bytes, 1 KB or 2 KB depending on the device. This array is divided into rows of size 16 bytes each. The API set of the EEPROM component supports write operations at the byte and row levels and erase operation at the sector level. A sector in EEPROM has 64 rows.

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Mon, 07 Jul 2014 13:34:24 -0600
Digital Multiplexer and De-Multiplexer http://www.cypress.com/?rID=48518 Features

  • Digital Multiplexer
  • Digital De-Multiplexer
  • Up to 16 channels
Symbol Diagram

General Description

The Multiplexer component is used to select 1 of n inputs while the De-Multiplexer component is used to route 1 signal to n outputs.

The Multiplexer component implements a 2-16 input mux providing a single output, based on hardware control signals. The De-Multiplexer component implements a 2-16 output demux from a single input, based on hardware control signals. Only 1 input or output connection may be made at a time.

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Mon, 07 Jul 2014 13:28:48 -0600
PSoC® Creator™ Component Author Guide http://www.cypress.com/?rID=49025 This guide provides instructions and information that will help you create components for PSoC Creator. This guide is intended for advanced users to create sophisticated components that other users employ to interact with PSoC Creator. However, there are some basic principles in this guide that will also benefit novice users who may wish to create their own components. This chapter includes:

  • Component Creation Process Overview
  • Conventions
  • References
  • Revision History
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Mon, 07 Jul 2014 13:13:30 -0600
Tri-State Buffer (Bufoe) http://www.cypress.com/?rID=48510

Features
 

  • Buffer with Output Enable signal
  • Feedback signal
Symbol Diagram

General Description

The Tri-State Buffer (Bufoe) component is a non-inverting buffer with an active high output enable signal. When the output enable signal is true, the buffer functions as a standard buffer. When the output enable signal is false, the buffer turns off.

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Mon, 07 Jul 2014 13:05:46 -0600
PSoC® Creator™ System Reference Guide (CY_Boot Component) http://www.cypress.com/?rID=51972 This System Reference Guide describes functions supplied by the PSoC Creator cy_boot component. The cy_boot component provides the system functionality for a project to give better access to chip resources. The functions are not part of the component libraries but may be used by them.You can use the function calls to reliably perform needed chip functions.

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Mon, 07 Jul 2014 12:05:32 -0600
Analog Mux Constraint http://www.cypress.com/?rID=69001 Features
Symbol Diagram
  • Limits analog routing of an switchable mux connection to a specific routing resource
  • All terminals on the signal must connect directly to the routing resource

Note: Routing is strict. All of the devices connected to the net with the resource constraint must have a direct hardware connection to the resource. Refer to the Analog Routing Diagram in the applicable Technical Reference Manual (TRM), which is available from the Cypress website, www.cypress.com. If the resources do not have a hardware connection to the specified constraint, an error will occur.


General Description

The Analog Mux Constraint component allows you to define the route of the analog signal on the switchable mux connection to which it is connected. This is an advanced feature that is not needed for most designs, and should be used with caution.

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Mon, 07 Jul 2014 12:00:33 -0600
Analog Hardware Multiplexer (AMuxHw) http://www.cypress.com/?rID=46438 Features

  • Single-ended or differential inputs
  • Mux or switch mode
  • From 1 to 32 inputs
  • Hardware controlled
  • Bi-directional (passive)
Symbol Diagram

General Description

The Analog Hardware Multiplexer (AMuxHw) component is used to provide hardware switchable connections from GPIOs to analog resource blocks (ARBs).

When to use an AMuxHw

The AMuxHw component should be used when a signal needs to be switched in hardware. Currently, only the GPIOs can be multiplexed with this multiplexer. Since the AMuxHw component is bidirectional, it can also be used as de-multiplexer.

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Mon, 07 Jul 2014 11:51:33 -0600
Down Counter 7-bit (Count7) http://www.cypress.com/?rID=86076

Features

  • 7-bit read/write period register
  • 7-bit count register that is read/write
  • Automatic reload of the period to the count register on terminal count
  • Routed load and enable signals

Symbol Diagram

General Description

The Count7 component is a 7-bit down counter with the count value available as hardware signals. This counter is implemented using a specific configuration of a universal digital block (UDB). To implement the counter, pieces of the control and status registers are used along with counter logic that is present in the UDB specifically for this function.

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Mon, 07 Jul 2014 11:47:09 -0600
Pulse Converter http://www.cypress.com/?rID=73668 Features

  • Terminals for out_clk and sample_clk for configurability of sample rate and output pulse width
Symbol Diagram

General Description

The Pulse Converter component produces a pulse of known width when a pulse of any width is sampled on p_in.  Use to interface pulse events from a fast domain to a slow domain or when a specific pulse width must be guaranteed.

 

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Mon, 07 Jul 2014 11:43:28 -0600
AN82156 - PSoC® 3, PSoC 4, and PSoC 5LP - Designing PSoC Creator™ Components with UDB Datapaths http://www.cypress.com/?rID=69774

Introduction

PSoC 3, PSoC 4 and PSoC 5LP (hereafter referred to as "PSoC") support a wide variety of functions, called components. Many of these components are implemented using the programmable logic inside the PSoC. As a result, you can create your own components and use them in PSoC Creator projects.

Notes:

  1. Click on AN77835 - PSoC® 3 to PSoC 5LP Migration Guide to learn differences between PSoC 3 and PSoC 5LP.
  2. For PSoC 5 project and related document, please download file AN82156_Archive.zip.

Project Device PSoC Creator
Version
Development Kit
CY8CKIT-xxx
Architecture Silicon
Revision
V2.2 SP1
or higher
V2.1 SP1
/2.1
001
DVK
030/050
DVK
042 Pioneer DVK
AN82156.zip PSoC3 Prod YES NO YES YES* N/A
PSoC4 Prod YES NO YES N/A YES**
PSoC5LP Prod YES NO YES YES* N/A
AN82156_Archive.zip PSoC3 ES2, ES3, Prod NO YES YES YES* N/A
PSoC5 ES1, Prod NO YES YES YES* N/A

* Refer to Migrating CY8CKIT-001 DVK project to CY8CKIT 030/ 050.
** The project can be easily adapted to this DVK.

Projects associated with this application note can be downloaded from the 'Related Files' section below. For your convenience, we have provided projects that are compatible with the two most recent versions of PSoC Creator:

  • AN82156.zip is used with PSoC Creator 3.0 SP1 and 2.2 SP1
  • AN82156_Archive.zip is used with PSoC Creator 2.1 SP1/2.1

The project’s default settings may not be compatible with your device or kit, and you may need to change your project settings. For more information, see:

PSoC® 3, PSoC 5, and PSoC 5LP AN Project File Naming Convention and Use
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Wed, 02 Jul 2014 06:38:57 -0600
PSoC® Programmer 3.21 http://www.cypress.com/?rID=38050

PSoC Programmer 3.21 offers the user a simple GUI that connects to programming hardware to program and configure PSoC, Clock, and configurable Cypress devices. Also provided with PSoC Programmer is the Bridge Control Panel, which can be used to debug, graph and log I2C serial communications. PSoC Programmer also provides a hardware layer for customers to design custom applications or use existing code examples for testing hardware and firmware designs.

PSoC Programmer 3.21 supports both PSoC Creator and PSoC Designer in a single installation.

PSoC Programmer 3.21 is a minor release. For additional information regarding the installation and the new features please see the release notes in the downloads table below.


PSoC Programmer:

PSoC Programmer is a flexible, integrated programming application for programming PSoC devices. PSoC Programmer can be used with PSoC Designer and PSoC Creator to program any design onto a PSoC device. PSoC Programmer supports all PSoC 1, PSoC 3, PSoC 4, and PSoC 5LP devices.

Supported PC Operating Systems:

PSoC Programmer currently supports the following windows operating systems:

  • Windows XP (32/64 bit)
  • Windows Vista (32/64 bit)
  • Windows 7 (32/64 bit)
  • Windows 8 (32/64 bit) 
  • Windows 8.1 (32/64 bit)

COM Hardware Layer Supported Languages:

PSoC Programmer provides the user a hardware layer with API’s to design specific applications utilizing the programmers and bridge devices. The PSoC Programmer hardware layer is fully detailed in the COM guide documentation as well as example code across the following languages: C#, C, Perl, and Python.

PSoC Programmer Secondary Software

PSoC Programmer includes additional software beyond just PSoC Programmer. For more information on that additional software please: Click Here

Third Party IDE and Programming Support

PSoC Programmer delivers a number of files and utilities that enable 3rd party programming and debugging support for PSoC device families. In the downloads table below we include the 3rd party user guide which will assists the user in configuring and enabling the support in the IDEs or programming utilities. The files and applications can be found in the root installation directory for each programmer installation.

Archived Software:

PSoC Programmer software is archived at the following page: Click Here

Additional Programming Links:
Prototype Programming Hardware:

PSoC Programmer is part of a suite of programming options and programming content available to PSoC users. For customers who are looking for more information on general programming options and information please navigate to the web page linked below. On the General Programming web page we discuss all of the available programming options for customers including Software, Schematics, Programming Specifications, and 3rd party mass programming.

www.cypress.com/go/programming

All PDF documents require at least a PDF reader installed prior to opening.

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Fri, 27 Jun 2014 18:36:48 -0600
AN56377 - PSoC® 3 and PSoC 5LP USB Transfer Types http://www.cypress.com/?rID=39553 AN56377 describes the four USB transfer types: Interrupt, Bulk, Isochronous, and Control. It then shows how to configure PSoC® 3 and PSoC 5LP to perform each of these transfers. Code examples are also included for specific considerations, including vendor commands for custom USB functionality, and to use DMA for faster data throughput. This application note assumes advanced level knowledge of USB. For an introduction to USB, see AN57294.

Below are some of videos demonstrating  how to impliment bulk transfers and vendor commands which are discussed in this application note.

 

 

 

The following table indicates the PSoC devices, PSoC Creator versions, compilers, and development kits that will work with this application note project:


Project
Device
PSoC Creator
Version
Development Kit
CY8CKIT-xxx
Compiler
Architecture
Silicon
Revision
V2.1 SP1
or higher
V2.1 / 2.0
001
DVK
030/050
DVK
003/014
FTK
Keil
GCC
RVDS
MDK

AN56377.zip

Prod
YES
NO
YES
YES*
NO
YES
N/A
N/A
N/A
Prod
YES
NO
YES
YES*
NO
N/A
YES
YES
YES
AN56377_Archive.zip
ES2,ES3, Prod
NO
YES
YES
YES*
NO
YES
N/A
N/A
N/A
ES1, Prod
NO
YES
YES
YES*
NO
N/A
YES
YES
YES

*Refer to Migrating CY8CKIT-001 DVK project to CY8CKIT 030/ 050

Notes:

  1. For PSoC 5 project and related document, please download file AN56377_Archive.zip.

Projects associated with this application note can be downloaded from the ‘Related Files’ section below. For your convenience, we have provided projects that are compatible with the two most recent versions of PSoC Creator:

  • AN56377.zip is used with PSoC Creator 3.0 and 2.1 SP1
  • AN56377_Archive.zip is used with PSoC Creator 2.1/2.0

The project’s default settings may not be compatible with your device or kit, and you may need to change your project settings. For more information, see:
PSoC® 3, PSoC 4 and PSoC 5LP AN Project File Naming Convention and Use

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Fri, 20 Jun 2014 08:53:58 -0600
PSoC Creator : Custom Components http://www.cypress.com/?rID=40360

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Wed, 18 Jun 2014 00:31:13 -0600
Die Temperature (DieTemp) http://www.cypress.com/?rID=46454 Features

  • Accuracy of /-5° C
  • Range -40° C to 140° C (0xFFD8 to 0x008C)
  • Blocking and non-blocking API
  • Does not support PSoC 5 silicon
Symbol Diagram

General Description

The Die Temperature (DieTemp) component provides an API to acquire the temperature of the die. The System Performance Controller (SPC) is used to get the die temperature. The API includes blocking and nonblocking calls.

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Fri, 13 Jun 2014 18:02:21 -0600
Delta Sigma Analog to Digital Converter (ADC_DelSig) http://www.cypress.com/?rID=48916

Features

  • Selectable resolutions, 8 to 20 bits
  • Eleven input ranges for each resolution
  • Sample rate 8 sps to 384 ksps
  • Operational modes:
    • Single sample
    • Multi-sample
    • Continuous mode
    • Multi-sample (Turbo)
  • High input impedance input buffer
    • Selectable input buffer gain (1, 2, 4, 8) or input buffer bypass
  • Multiple internal or external reference options
  • Automatic power configuration
  • Up to four run-time ADC configurations
Symbol Diagram

General Description

The Delta Sigma Analog to Digital Converter (ADC_DelSig) provides a low-power, low-noise front end for precision measurement applications. You can use it in a wide range of applications, depending on resolution, sample rate, and operating mode. It can produce 16-bit audio; high speed and low resolution for communications processing; and high-precision 20-bit low-speed conversions for sensors such as strain gauges, thermocouples, and other high-precision sensors. When processing audio information, the ADC_DelSig is used in a continuous operation mode. When used for scanning multiple sensors, the ADC_DelSig is used in one of the multisample modes. When used for single-point high-resolution measurements, the ADC_DelSig is used in single-sample mode.

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Fri, 13 Jun 2014 17:56:33 -0600
Debouncer http://www.cypress.com/?rID=69780 Features
  • Eliminates unwanted oscillations on digital input lines
     
Symbol Diagram

General Description

Mechanical switches and relays tend to make and break connections for a finite time before settling down to a stable state. Within this settling time, the digital circuit can see multiple transitions as the switch contacts bounce between make or break conditions.

The Debouncer component takes an input signal from a bouncing contact and generates a clean output for digital circuits. The component will not pass the signal to the output until the predetermined period of time when the switch bouncing settles down. In this way, the circuit will respond to only one pulse generation performed by the pressing or releasing of the switch and not several state transitions caused by contact bouncing.

For more details on switch debouncing please see application note AN60024.

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Fri, 13 Jun 2014 17:12:10 -0600
D Flip Flop w/Enable http://www.cypress.com/?rID=73662 Features

  • Enable input allows d input to be selectively captured
  • Configurable width for array of D Flip Flops with a single enable
Symbol Diagram

General Description

The D Flip Flop w/Enable selectively captures a digital value.  Use the D Flip Flop w/ Enable to implement sequential logic.

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Thu, 12 Jun 2014 18:47:43 -0600
D Flip Flop http://www.cypress.com/?rID=48911 Features

  • Asynchronous reset or preset
  • Synchronous reset, preset, or both
  • Configurable width for array of D Flip Flops

 

Symbol Diagram

General Description

The D Flip Flop stores a digital value.

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Thu, 12 Jun 2014 18:40:22 -0600
Cyclic Redundancy Check (CRC) http://www.cypress.com/?rID=46448 Features

  • 1 to 64 bits
  • Time Division Multiplexing mode
  • Requires clock and data for serial bit stream input
  • Serial data in, parallel result
  • Standard [CRC-1 (parity bit), CRC-4 (ITU-T G.704), CRC-5-USB, etc.] or custom polynomial
  • Standard or custom seed value
  • Enable input provides synchronized operation with other components
Symbol Diagram

General Description

The default use of the Cyclic Redundancy Check (CRC) component is to compute the CRC from a serial bit stream of any length. The input data is sampled on the rising edge of the data clock. The CRC value is reset to 0 before starting or can optionally be seeded with an initial value. On completion of the bitstream, the computed CRC value may be read out.

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Thu, 12 Jun 2014 18:33:41 -0600
Counter http://www.cypress.com/?rID=48909 Features

  • Fixed-function (FF) implementation for PSoC 3 and
    PSoC 5LP devices
  • 8-, 16-, 24-, or 32-bit counter
  • Up, down, or up-and-down configurations
  • Optional compare output
  • Optional capture input
  • Enable and reset inputs, for synchronizing with other components
  • Continuous or one shot run modes
Symbol Diagram

General Description

The Counter component provides a method to count events. It can implement a basic counter function and offers advanced features such as capture, compare output, and count direction control. 


 
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Thu, 12 Jun 2014 18:28:03 -0600
Controller Area Network (CAN) http://www.cypress.com/?rID=46443

Features
 

  • CAN2.0A and CAN2.0B protocol implementation, ISO 11898-1 compliant
  • Programmable bit rate up to 1 Mbps at 8 MHz (BUS_CLK)
  • Two-wire or three-wire interface to external transceiver (Tx, Rx, and Enable)
  • Extended hardware message filter that covers Data Byte 1 and Data Byte 2 fields
  • Programmable transmit priority: Round Robin and Fixed
  • CAN component fully supports PSoC 5LP device, but does not support PSoC 5

 

Symbol Diagram

General Description

The Controller Area Network (CAN) controller implements the CAN2.0A and CAN2.0B specifications as defined in the Bosch specification and conforms to the ISO-11898-1 standard.

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Thu, 12 Jun 2014 18:19:14 -0600
Control Register http://www.cypress.com/?rID=46452 Features

  • Up to 8-bit Control Register
Symbol Diagram

General Description

The Control Register allows the firmware to output digital signals.

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Thu, 12 Jun 2014 18:12:48 -0600
Comparator (Comp) http://www.cypress.com/?rID=48915 Features
  • Low input offset
  • User controlled offset calibration
  • Multiple speed modes
  • Low-power mode
  • Output routable to digital logic blocks or pins
  • Selectable output polarity
  • Configurable operation mode during Sleep
Symbol Diagram

General Description

The Comparator (Comp) component provides a hardware solution to compare two analog input voltages. The output can be sampled in software or digitally routed to another component. Three speed levels are provided to allow you to optimize for speed or power consumption. A reference or external voltage can be connected to either input.

You can also invert the output of the comparator using the Polarity parameter.   

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Thu, 12 Jun 2014 18:01:46 -0600
Clock http://www.cypress.com/?rID=46449

Features

  • Quickly defines new clocks
  • Refers to system or design-wide clocks
  • Configures the clock frequency tolerance
Symbol Diagram

General Description

The Clock component provides two key features: it allows you to create local clocks, and it allows you to connect to system and design-wide clocks. All clocks are shown in the Design-Wide Resources (DWR) Clock Editor.

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Wed, 11 Jun 2014 18:42:21 -0600
AN58304 - PSoC® 3 and PSoC 5LP – Pin Selection for Analog Designs http://www.cypress.com/?rID=39974 AN58304 provides an overview of the analog routing matrix in PSoC® 3 and PSoC 5LP. This matrix is used to interconnect analog blocks and GPIO pins. A good understanding of the analog routing and pin connections can help the designer make selections to achieve the best possible analog performance. Topics such as LCD and CapSense routing are not covered in this application note.

Notes:

  1. Click on AN77835 - PSoC® 3 to PSoC 5LP Migration Guide to learn differences between PSoC 3 and PSoC 5LP.
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Wed, 11 Jun 2014 04:22:46 -0600
Character LCD with an I2C Interface (I2C LCD) http://www.cypress.com/?rID=78824 Features Symbol Diagram
  • Communicate on a 2-wire I2C bus
  • The API is compatible with the current character LCD component
  • A single component may drive one or more LCDs on the same I2C bus
  • The I2C LCD can coexist on an existing I2C bus if the PSoC is the I2C master
  • Support for the NXP PCF2119x command format

General Description

The I2C LCD component drives an I2C interfaced 2 line by 16 character LCD. The I2C LCD component is a wrapper around an I2C Master component and makes use of an existing I2C Master component. If a project does not already have an I2C Master component, one is required in order to operate. When one of the API functions is called, that function calls one or more of the I2C Master functions in order to communicate with the LCD.

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Mon, 09 Jun 2014 19:08:31 -0600
Capacitive Sensing (CapSense® CSD) http://www.cypress.com/?rID=48884 Features
                   Symbol Diagram
  • Support for user-defined combinations of button, slider, touchpad, and proximity capacitive sensors.
  • Automatic SmartSense™ tuning or manual tuning with integrated PC GUI.
  • High immunity to AC power line noise, EMC noise, and power supply voltage changes.
  • Optional two scan channels (parallel synchronized), which increases sensor scan rate.
  • Shield electrode support for reliable operation in the presence of water film or droplets.
  • Guided sensor and terminal assignments using the CapSense customizer.

General Description

Capacitive Sensing, using a Delta-Sigma Modulator (CapSense CSD) component, is a versatile and efficient way to measure capacitance in applications such as touch sense buttons, sliders, touchpad, and proximity detection.

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Mon, 09 Jun 2014 19:01:33 -0600
Boost Converter (BoostConv) http://www.cypress.com/?rID=46442

Features

  • Produces a selectable output voltage that is higher than the input voltage
  • Input voltage range between 0.5 V and 3.6 V
  • Boosted output voltage range between 1.8 V and 5.25 V
  • Source up to 75 mA depending on the selected input and output voltage parameter values
  • Two modes of operation: Active and Standby for PSoC 3 or Sleep for PSoC 5LP
Symbol Diagram

General Description

The Boost Converter (BoostConv) component allows you to configure and control the PSoC boost converter hardware block. The boost converter enables input voltages that are lower than the desired system voltage to be boosted to the desired system voltage level. The converter uses an external inductor to convert the input voltage to the desired output voltage.

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Mon, 09 Jun 2014 18:55:43 -0600
Basic Counter http://www.cypress.com/?rID=73660 Features

  • 2 to 32 bit Counter
  • Direct access to count value
  • Enable and reset inputs for easily customizable counter circuit
Symbol Diagram

General Description

The Basic Counter component provides a selectable-width up-counter, implemented in PLD macrocells.  Use the Basic Counter when the bussed counter value needs to be routed, or when small, basic counter functionality is all that is needed.  In a Mux Sequencer, connect the cnt output to the input of a mux to easily sequence signals.  In a Small Counter, count level events on the en input without consuming any datapath resources.  In a Small Timer, measure the number of clocks between events without consuming any datapath resources.

 

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Mon, 09 Jun 2014 18:43:24 -0600
Annotation Library http://www.cypress.com/?rID=56759 Features

  • The library provides documentation for annotation components.
     

General Description

The Annotation Component library provides a way for you to mix external and internal components on the same schematic. This makes it possible to improve documentation and better understand the internal schematic and entire design. The components in this library cover the most common components that are most likely to be placed on the periphery of a PSoC device. These components consist of resistors, capacitors, transistors, inductors, switches, and others. The library is not intended to supply every possible part, but should support a wide range of designs. You can easily create your own part or parts library if your design includes a custom or unique component.

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Mon, 09 Jun 2014 18:40:43 -0600
Analog Resource Reserve (Cy_Analog_Reserve) http://www.cypress.com/?rID=56744  

Features

  • Prevents an analog router from using a global analog routing resource
  • Allows safe firmware access to a global analog routing resource
Symbol Diagram

General Description

The Analog Resource Reserve component reserves a global analog routing resource so that the resource can be safely used by firmware-based manual analog routing. This is an advanced feature that is not needed for most designs, and should be used with caution.

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Mon, 09 Jun 2014 18:37:40 -0600
Analog Resource Constraint (Cy_Analog_Constraint) http://www.cypress.com/?rID=56747 Features
Symbol Diagram
  • Limits analog routing of a signal to a specific routing resource
  • All terminals on the signal must connect directly to the routing resource

Note: Routing is strict. All of the devices connected to the net with the resource constraint must have a direct hardware connection to the resource. Refer to the Analog Routing Diagram in the applicable Technical Reference Manual (TRM), which is available from the Cypress website, www.cypress.com. If the resources do not have a hardware connection to the specified constraint, an error will occur.

General Description

The Analog Resource Constraint component allows you to define the route of the analog signal to which it is connected. This is an advanced feature that is not needed for most designs, and should be used with caution. 

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Mon, 09 Jun 2014 18:27:54 -0600