Cypress.com: Documentation http://www.cypress.com/?app=search&searchType=advanced&id%3D2232 Working of the PSoC<sup>®</sup> 3/5LP RTC Without a Power Supply and Across Resets – KBA93082 http://www.cypress.com/?rID=51941 Answer: The PSoC 3/5LP RTC block requires a constant power supply. There is no internal capacitor to hold some charge for keeping the RTC running for some time without a power supply. The RTC can run in sleep mode and alternate active mode. In this case, one pulse-per-second (OPPS) has to be the wake-up resource to update real-time for the clock. The RTC cannot run in hibernate mode.

Once PSoC 3/5LP is reset, the RTC block will also get reset and it will start from the beginning.

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Thu, 30 Oct 2014 06:36:47 -0600
PSoC 3 Architecture http://www.cypress.com/?rID=40738 Tue, 28 Oct 2014 17:45:32 -0600 AN73054 - PSoC® 3 and PSoC 5LP Programming Using an External Microcontroller (HSSP) http://www.cypress.com/?rID=57435 PSoC 3 / PSoC 5LP device programming refers to programming of the nonvolatile memory in PSoC 3 / PSoC 5LP using an external host programmer. The host can be the MiniProg3 Programmer supplied by Cypress; a third-party programmer; or a custom-made programmer, such as an on-board microcontroller.


Project
Device
PSoC Creator
Version
Development Kit
CY8CKIT-xxx
Compiler
Architecture
Silicon
Revision
 V2.1 SP1
or higher
V2.1/2.0
001
DVK
030/050
DVK
003/014
FTK
Keil
GCC
RVDS
MDK

AN73054.zip

Prod
YES
NO
YES
YES*
NO
N/A
YES
YES
YES
AN73054_Archive.zip
ES3, Prod
NO
YES
YES
YES*
NO
YES
N/A
N/A
N/A
ES1, Prod
NO
YES
YES
YES*
NO
N/A
YES
YES
YES

*Refer to Migrating CY8CKIT-001 DVK project to CY8CKIT 030/ 050.

Notes:
  1. Click on AN84741 - PSoC® 5 to PSoC 5LP Migration Guide to learn differences between PSoC 5 and PSoC 5LP.
  2. For PSoC 5 project and related document, please download file AN73054_Archive.zip.

Projects associated with this application note can be downloaded from the 'Related Files' section below. For your convenience, we have provided projects that are compatible with the two most recent versions of PSoC Creator:

  • AN73054.zip is used with PSoC Creator 2.1 SP1
  • AN73054_Archive.zip is used with PSoC Creator 2.1/2.0

The project’s default settings may not be compatible with your device or kit, and you may need to change your project settings. For more information, see:

PSoC® 3, PSoC 5, and PSoC 5LP AN Project File Naming Convention and Use
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Tue, 28 Oct 2014 05:09:43 -0600
QTP 100401: 68-LEAD SAW QFN (QUAD FLAT NO-LEAD) - 8 X 8 X 1.0MM NIPDAU, MSL3, 260C REFLOW CML-RA http://www.cypress.com/?rID=58391 Mon, 27 Oct 2014 03:00:18 -0600 PSoC 3 Device Programming http://www.cypress.com/?rID=40740 Fri, 24 Oct 2014 01:03:16 -0600 Attaching a MiniProg3 to a Running PSoC<sup>®</sup> 3 Causes a Reset – KBA83516 http://www.cypress.com/?rID=101836 Answer: Attaching the MiniProg3 to a running target device may create a voltage sag or dip on the RESET line. This toggles the XRES line for the target device, causing the device to reset. To work around this issue, please use one of the following methods:

  • Connect the cable to the board. Click the Attach to running target button in PSoC Creator™, and then connect the cable to the MiniProg3.
  • Before clicking the Attach to running target button, make the XRES selection in PSoC Creator equal to ‘1’. This enables the high-speed level translator and power-on VTARG on the MiniProg3. This precharges the cable from the MiniProg3 and prevents any cable capacitance from resetting the target device. Once the selections have been made, connect the MiniProg3 to the target.
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Wed, 22 Oct 2014 02:09:37 -0600
PSoC 3/4/5 Code Examples http://www.cypress.com/?rID=101641 The following Code Examples are integrated with PSoC Creator. To access these code examples, follow the path File -> Example Projects.

Title Part# Description
ADC_DifferentialMode PSoC 3, PSoC 5, PSoC 5LP The ADC Differential project contains an example for the use of the ADC_DelSig component in differential mode. The input analog voltage fed to the ADC input terminal is converted to the corresponding digital value and this is displayed on the LCD module.
ADC_Differential_Preamplifier PSoC 4 (PSoC 4100, PSoC 4200) This code example demonstrates how to sample four different channels with Sequencing ADC, use Opamps to form a Differential preamplifier, and send results to HyperTerminal (PC) using UART.
ADC_DMA_VDAC PSoC 3, PSoC 5, PSoC 5LP This code example shows the usage of DMA with ADC and VDAC components. The ADC is configured in default single ended mode. The ADC EOC signal is connected to DRQ input of DMA. On each rising edge of EOC signal, ADC output is transferred to VDAC input register. VDAC converts this digital value to analog signal which can be measured using a multimeter.
ADC_SAR_PrISM PSoC 5LP This datasheet code example demonstrates operation of the ADC_SAR (ADC Successive Approximation Register) and PrISM (Precision Illumination -Signal Modulation) components with the PSoC Creator Software. The ADC_SAR measurements are transferred using ISR and DMA to the PrISM and Character LCD components.
ADC_SAR_Seq_DieTemp_PSoC4 PSoC 4 (PSoC 4100, PSoC 4200) This project demonstrates two channel measurements by the PSoC 4 sequencing SAR ADC, transferring results to the LCD and PWM using an ISR.
ADC_SAR_Seq_Example PSoC 5LP This datasheet code example demonstrates the operation of the PSoC 5LP ADC SAR Sequencer.
ADC_SingleEndedMode PSoC 3, PSoC 5, PSoC 5LP The ADC Single Ended mode code example demonstrates use of the ADC_DelSig component in single ended mode. The input analog voltage fed to the ADC input terminal is converted to the corresponding digital value and this is displayed on the LCD module.
BasicDesign PSoC 3, PSoC 5LP The BasicDesign project contains an example for use with the PSoC Creator Help tutorials: "Basic Design" and "Debugging a Design." This project and tutorials provide more details about working with a design, including pins, clocks, and interrupts. They also provide a simple example that can be used with the debugger.
BoostExample PSoC 3, PSoC 5LP This datasheet code example demonstrates operation of the BoostConv (Boost Converter) -component with the PSoC Creator Software. code example demonstrates the usage of the Boost Converter component as a power source for a PSoC chip.
Bootloadable_PSoC4_Example PSoC 4 This code example demonstrates the basic operation of the Bootloader and Bootloadable components. This is the bootloadable application project. Refer to the Bootloader_PSoC4_code example for the bootloader application.
Bootloader_PSoC4_Example PSoC 4 This code example demonstrates the basic operation of the Bootloader and Bootloadable components. This is the bootloader application project. Refer to the Bootloadable_PSoC4_code example for the bootloadable application.
CANExampleControl PSoC 3, PSoC 5LP The CANExampleControl code example demonstrates use of the CAN Component. CAN Configuration, transmitting and receiving Full messages, and handling Tx and Rx errors are demonstrated. For additional information on use of the CAN component also refer to the CANExampleRemote project.
CANExampleRemote PSoC 3, PSoC The CANExampleRemote code example demonstrates use of the CAN Component.CAN Configuration, transmitting and receiving Full messages, handling Tx and Rx error is demonstrated. This is only one part of code example, for getting entire example you should also find CANExampleControl project.
CapSense_CSD_Design PSoC 3, PSoC 5, PSoC 5LP This CapSense_CSD_Design code example demonstrates operation of the CapSense CSD component with the PSoC Creator Software and DVK hardware. The component is configured with 2 buttons and linear slider. Visual feedback of a Button/Slider touch can be observed via LEDs/LCD.
CapSense_CSD_P4_Design PSoC 4 This CapSense_CSD_P4_Design code example demonstrates operation of the CapSense CSD component with the PSoC Creator Software and PSoC 4 Pioneer Kit (CY8CKIT-042) or PSoC 4 S0 Kit (CY8CKIT-040) hardware. The component is configured with a linear slider. Visual feedback of a Slider touch can be observed via LEDs.
CapSense_CSD_P4_Example_WithTuner PSoC 4 (PSoC 4100, PSoC 4200) This CapSense_CSD_P4 Tuner Design code example demonstrates operation of the CapSense CSD component with the PSoC Creator software, CapSense Tuner software and PSoC 4 Pioneer Kit hardware (CY8CKIT-042). The component is configured with a linear slider. The CapSense Tuner software is used for displaying scanning results. Visual feedback of a Slider touch can be observed via LEDs.
CapSense_CSD_WithTuner PSoC 3, PSoC 5, PSoC 5LP This CapSense_CSD Tuner Design code example demonstrates operation of the CapSense CSD (Capacitive Sensing using a Delta-Sigma Modulator) component with the PSoC Creator Software and CapSense Tuner software. The component is configured with 2 buttons and linear slider. The CapSense Tuner software is used for displaying scanning results.
CapSense_LowPower PSoC 4 (PSoC 4000) For PSoC 4000 devices only, this code example demonstrates a low power CapSense system. Any battery driven equipment requires very low system power consumption, while maintaining the required performance. The PSoC 4000 family supports a capacitive touch sensing known as CapSense® and two device low power modes: Sleep and Deep-Sleep. These low power modes enable PSoC 4 to achieve the required performance while operating at very low system power consumption.
CapSense_Proximity_Design PSoC 4 (PSoC 4000) For PSoC 4000 devices only, this project demonstrates a CapSense based proximity sensing design to control brightness of a LED. It will help user learn how to design a proximity sensor in their design using a PSoC 4 (4000 family) device and see how an approaching hand controls the intensity of a LED. It will employ the CapSense auto tuning ability, SmartSense®, to tune the proximity sensor of any wire/trace length. The project will also help user understand and design a simple Sleep-scan routine using the proximity sensor where the device will enter a periodic scan mode at a configurable rate and sleep once the sensor scan is complete to save power.
CharLCD_CustomFont PSoC 3, PSoC 5, PSoC 5LP, PSoC 4 (PSoC 4100, PSoC 4200) This code example demonstrates the use of available custom font with the LCD component. It displays "CYPRESS" in custom font on 2 X 16 LCD available with CY8CKIT-001 kit.
CharLCD_HBar PSoC 3, PSoC 5, PSoC 5LP, PSoC 4 (PSoC 4100, PSoC 4200) The CharLCD Hbar design project contains an example for the use of the CharLCD component. A series of horizontal bar graphs are drawn, left to right. Bars move towards the right, becoming shorter and shorter.
ComparatorExample PSoC 3, PSoC 5LP This code example demonstrates use of the Comparator components.
Comparator_PSoC4_Example PSoC 4 (PSoC 4100, PSoC 4200) This code example demonstrates the PSoC 4 Comparator in Non-Inverting mode.
Count7_Example PSoC 3, PSoC 4 (PSoC 4200), PSoC 5LP This code example demonstrates functionality of the Count7 component.
Counter PSoC 3, PSoC 5, PSoC 5LP This project contains an example for the use of the Counter, ISR and clock components. A clock is connected to Count input of Counter via a Sync block. On each rising edge of this clock signal, the Counter will be decremented by one count. The Counter is configured to trigger interrupt on terminal count event. This simple example reads the Counter Period, Count and Compare values and displays them on the LCD module.
CRCExample PSoC 3, PSoC 4 (PSoC 4200), PSoC 5, PSoC 5LP This datasheet code example demonstrates operation of the CRC (Cyclic Redundancy Check) component with the PSoC Creator Software. The CRC-16 polynomial, 16 bit resolution and single cycle configuration is demonstrated.
CSD_Comp_AMUX PSoC 4 (PSoC 4000) This code example demonstrates how the comparator's input can be multiplexed using the Amux component.
DebouncerExample PSoC 3, PSoC 4 (PSoC 4200), PSoC 5LP This code example shows how to do switch debouncing in hardware using the PSoC Creator Debouncer component.
DelSig_16Channel PSoC 3, PSoC 5LP This code example demonstrates a convenient way to implement a multi-channel ADC completely in PSoC hardware
DelSig_I2CM PSoC 3, PSoC 5, PSoC 5LP This Starter Design provides an 8-channel multiplexed Delta Sigma ADC with sequencing logic. The analog inputs to the ADC are converted to digital sequentially and then made available through an I2C Master interface. This design additionally makes use of the LCD character display to provide a debugging output interface.
DelSig_I2CM_Test PSoC 3, PSoC 5, PSoC 5LP This is the test project for the 8-ch DelSig ADC and I2C master code example
DelSig_I2CS PSoC 3, PSoC 5, PSoC 5LP This Starter Design provides an 8-channel multiplexed Delta Sigma ADC with sequencing logic. The analog inputs to the ADC are converted to digital sequentially and then made available through an I2C Slave interface. This design additionally makes use of the LCD character display to provide a debugging output interface.
DelSig_I2CS_Test PSoC 3, PSoC 5, PSoC 5LP This is the test project for the 8-ch DelSig ADC and I2C Slave Example
DelSig_SPIM PSoC 3, PSoC 5, PSoC 5LP This Starter Design provides an 8-channel multiplexed Delta Sigma ADC with sequencing logic. The analog inputs to the ADC are converted to digital sequentially and then made available through a SPI Master interface. This design additionally makes use of the LCD character display to provide a debugging output interface.
DelSig_SPIM_Test PSoC 3, PSoC 5, PSoC 5LP This is the test project for the 8-ch DelSig ADC and SPI Master Example
DFBExample PSoC 3, PSoC 5, PSoC 5LP This code example demonstrates the use of the Digital Filter Block (DFB) Assembler component for matrix multiplication by a scalar. It also demonstrates the DFB interaction with DMA.
DieTemp_BasicTest PSoC 3, PSoC 5LP The DieTemp basic design project contains an example for the use of Die Temp. This simple example uses a Character LCD to display the current Die Temperature value.
DigitalUtilityExample PSoC 3, PSoC 5, PSoC 5LP This project contains an example of the use of some of the Digital Utility components. Using an Edge Detector and a Basic Counter, falling edge events on a pin are counted and driven to a Status Register. Using a Digital Comparator and a Digital Constant, the Basic Counter is reset whenever the count value reaches 100.
DVDAC_Example PSoC 3, PSoC 5LP This code example demonstrates the basic functionality of the DVDAC component. The Delta Sigma ADC component is used to measure the output voltage.
EEPROM_Design PSoC 3, PSoC 5, PSoC 5LP The EEPROM basic design project contains an example for the use of the EEPROM component. This simple example uses a Character LCD to display data written to EEPROM memory.
emFile_Example PSoC 3, PSoC 5, PSoC 5LP This code example demonstrates emFile component operation
EMIFExample PSoC 3, PSoC 5LP This data sheet code example demonstrates operation of the EMIF (External Memory Interface) component with the PSoC Creator Software. The Asynchronous External Memory Type, 24 bits Address Width, 8 bits Data Width, 30 ns External Memory Speed configuration is demonstrated.
Em_EEPROM_Example PSoC 3, PSoC 4 (PSoC 4100, PSoC 4200), PSoC 5LP The code example demonstrates the basic functionality of the Emulated EEPROM component.
Ezi2cDesign PSoC 3, PSoC 5, PSoC 5LP This datasheet code example demonstrates operation of the EZI2C (EZ I2C Slave) and I2C (Inter-Integrated Circuit Master/Multi-Master/Slave) components communication. The EZI2C component is configured as one slave device with the 8 bit sub-address size and 100 kbps data rate.
Fan_Control_Auto_FW_with_Alert PSoC 4 (PSoC 4200) This data sheet code example demonstrates operation of the Fan Controller component in Automatic (Firmware) mode with the PSoC Creator Software.
Filter_ADC_VDAC PSoC 3, PSoC 5, PSoC 5LP The Filter_ADC_VDAC contains an example for the use of the Filter component. FIR Low pass filter with Blackman window is used to filter the 8-bit ADC output. The filtered output is converted into an unsigned value, then fed via an ISR to VDAC to convert it to analog signal.
Filter_ADC_VDAC_poll PSoC 3, PSoC 5, PSoC 5LP The Filter_ADC_VDAC_poll contain a polling example for the Filter component. FIR Low pass filter with Blackman window is used to filter the 8-bit ADC output. The filtered output is converted into an unsigned value, then fed via an ISR to VDAC to convert it to analog signal.
FW_Fan_Control PSoC 3, PSoC 4 (PSoC 4200), PSoC 5LP This project demonstrates the Fan Controller component configured for firmware based Fan Control enabling designers to customize the control algorithm.
GlitchFilterExample PSoC 3, PSoC 4 (PSoC 4200), PSoC 5LP This code example shows how to do glitch filtering in hardware using the PSoC Creator GlitchFilter component.
HelloWorld_Blinky PSoC 3, PSoC 5, PSoC 5LP This project provides an introduction into the process of creating a design in PSoC Creator. It accomplishes the simple tasks of printing "Hello World" on an LCD, and blinking an LED using a PWM component.
Hibernate_and_Stop_PowerModes PSoC 4 (PSoC 4100, PSoC 4200) This code example demonstrates how to enter and wake up from hibernate and stop low power modes, and how to retain SRAM variables in hibernate mode.
Hibernate_PSoC4_Example PSoC 4 (PSoC 4100, PSoC 4200) This System Reference Guide code example demonstrates operation of the Power Manager API with the PSoC Creator Software. The Hibernate low power mode entry and wake up on external event are implemented.
HW_Fan_Control_with_Alert PSoC 3, PSoC 5LP This project demonstrates the Fan Controller component configured for hardware (UDB) based Fan Control. This method completely frees-up the CPU for other system tasks. This example also demonstrates how to handle FanController exceptions such as fan stall/rotor lock etc. through the use of the alert pin and CPU interrupts.
I2C_LCD_Example PSoC 3, PSoC 5, PSoC 5LP This code example demonstartes functionality of I2C LCD component.
I2C_LCD_Example_PSoC4 PSoC 4 (PSoC 4100, PSoC 4200) This code example demonstartes functionality of I2C LCD component.
IDAC8_Example PSoC 3, PSoC 5, PSoC 5LP The IDAC8_Example design project contains an example to demonstrate the use of IDAC8 component. This simple example sets the IDAC range to 255µA and the current value to 100µA. The output can be verified using a Multimeter.
IDAC8_PSoC4_Example PSoC 4 (PSoC 4100, PSoC 4200) This code example demonstartes basic functionality of PSoC4 IDAC8.
ILO_Trim_1kHz PSoC 3, PSoC 5LP This code example demonstrates 1kHz ILO trimming for PSoC3 and PSoC5LP.
ILO_Trim_Compensate PSoC 4 (PSoC 4100, PSoC 4200) This code example demonstrates the compensation operation of the ILO Trim component for PSoC 4.
InterIcSound PSoC 3, PSoC 5, PSoC 5LP This datasheet code example demonstrates operation of the I2S (Inter-IC Sound Bus) component with the PSoC Creator Software. The operation of I2S, configuring a DMA transfer and displaying results on LCD screen are described and implemented.
LED_Driver_7Segment PSoC 3, PSoC 5LP This code example demonstrates driving an external 8 digit 7-segment display
LIN_Slave_Example PSoC 3, PSoC 5, PSoC 5LP This datasheet code example demonstrates the LIN Slave component operation: signal interaction APIs, Transport Layer and Configuration services usage.
LPComparator_PSoC4_Example PSoC 4 (PSoC 4100, PSoC 4200) This is code example demonstrates the PSoC 4 LP Comparator.
LUT_ExampleProject PSoC 3, PSoC 4 (PSoC 4200), PSoC 5, PSoC 5LP The LUT Example design project contains an example for the use of the LUT component. This simple example sets the input and output to 2. Output is verified using a Character LCD.
MDIO_Advanced_Example PSoC 3, PSoC 5LP This code example demonstrates the advanced mode of the MDIO Interface component by letting the hardware process the frames, and concurrently prints the derived information on the LCD.
MDIO_Basic_Example PSoC 3, PSoC 5LP This code example demonstrates the basic mode of the MDIO Interface component by processing the received frame in firmware, and then prints the derived information on the LCD
Mixer_SampleProject PSoC 3, PSoC 5, PSoC 5LP The Mixer_SampleProject contains an example for the use of the Mixer component. The mixer type used is Up mixer or Multiply mixer which multiplies the input signal frequency with the local oscillator frequency. The resultant output waveform can be viewed using an oscilloscope.
Multiplexed_Comparator PSoC 4 (PSoC 4200) This code example demonstrates how to monitor multiple input signals using multiplexed analog comparator without any CPU intervention.
OpAmp_Example PSoC 3, PSoC 5, PSoC 5LP This code example contains an example for the use of the OpAmp component in Non-inverting Mode.
Opamp_Dynamic_Gain_Switching PSoC 4 (PSoC 4200) This code example demonstrates how to multiplex three different channels with ADC using Analog Mux and send results to HyperTerminal (PC) using UART. The ADC input and gain can be changed on the fly by pressing a switch.
OpAmp_PSoC4_Example PSoC 4 (PSoC 4100, PSoC 4200) This is code example demonstrates the functionality of the PSoC 4 OpAmp.
PGA_ExampleProject PSoC 3, PSoC 5, PSoC 5LP This design project contains an example for the use of the PGA component. This simple example sets the PGA gain to 1 and outputs a Voltage set in the firmware to a fixed pin. This voltage can be verified using a Multimeter.
PGA_Inv_ExampleProject PSoC 3, PSoC 5, PSoC 5LP This design project contains an example for the use of the PGA_Inv component. This simple example sets the PGA_Inv gain to 1 and outputs a Voltage set in the firmware to a fixed pin. This voltage can be verified using a Multimeter.
PMBusExample PSoC 3, PSoC 5LP This code example demonstrates usage of the PMBus Slave component in a simulated Power Supervision application.
PMBusThermExample PSoC 4 (PSoC 4100, PSoC 4200) This code example demonstrates usage of the PMBus Slave component in a simulated Thermal Management application.
PowerManagement_Hibernate PSoC 3, PSoC 5LP This System Reference Guide code example demonstrates operation of the Power Manager API with the PSoC Creator Software. The Hibernate low power mode entry and wake up on external event are implemented.
PowerMonitorExample PSoC 3, PSoC 5, PSoC 5LP This project demonstrates the PowerMonitor component configured for using with 035-Power Management EBK development kit.
PrISM_Led PSoC 3, PSoC 4 (PSoC 4200), PSoC 5, PSoC 5LP This datasheet code example demonstrates operation of the PrISM component with the PSoC Creator Software. The LED blinking is demonstrated.
PRSExample PSoC 3, PSoC 4 (PSoC 4200), PSoC 5, PSoC 5LP This datasheet code example demonstrates operation of the PRS (Pseudo Random Sequence) component with the PSoC Creator Software. The clocked and API Single Step run modes, 16 bit resolution and single cycles implementation configuration is demonstrated.
PulseConvertExample PSoC 3, PSoC 5, PSoC 5LP This project contains an example of the use of the Pulse Converter component. 2 Basic Counter components, clocked slower than BUS_CLK, count the number of DMA nrq pulses. One uses the nrq output directly, so it misses pulses. The other uses a Pulse Converter component to guarantee that it does not miss pulses.
PWMExample PSoC 4 This data sheet code example demonstrates operation of the TCPWM (PWM Mode) component with the PSoC Creator Software.
PWM_BasicTest PSoC 3, PSoC 5, PSoC 5LP This code example demonstrates operation of the PWM Fixed Function component. This simple example uses a Character LCD to display the current PWM Period, Compare values and status of PWM output on the LCD module.
QDExample PSoC 3, PSoC 5, PSoC 5LP This datasheet code example demonstrates operation of the QuadDec (Quadrature Decoder) component with the PSoC Creator Software. The quadrature counts handling and index input usage is demonstrated.
QuadDecExample PSoC 4 This data sheet code example demonstrates operation of the TCPWM (Quadrature Decoder Mode) component with the PSoC Creator Software.
RtcDesign PSoC 3, PSoC 5LP This datasheet code example demonstrates operation of the RTC (Real Time Clock) component with the PSoC Creator Software. The operation with full time, data and alarm features, including Daylight Savings Time (DST) is -implemented.
RTDExample PSoC 3, PSoC 5, PSoC 5LP This data sheet code example demonstrates operation of the RTD (resistance temperature detector) calculator component with the PSoC Creator Software. The PT100 RTD type, [-50, 150] Temperature Range, minimal calculation error budget, IEC60751 Coefficients is demonstrated.
SampleHold_BasicTest PSoC 3, PSoC 5, PSoC 5LP This code example demonstrates operation of the Sample/Track and Hold component in Sample and Hold mode. This simple example uses a Character LCD to display the Sample and Hold value which is converted using an ADC.
SAR_SPIM_USB PSoC 5, PSoC 5LP This Starter Design provides two 4-channel SAR ADCs with two analog muxes to choose input channels. The channel to be read is dictated by the USB host device. The ADC then processes the input and then outputs it to a SPI Slave and to the USB host. This design will additionally make use of the LCD character display to provide a debugging output interface.
SAR_SPIM_USB_Test PSoC 5, PSoC 5LP This is the test project for the 4ch dual SAR with SPI master and USBUART code example
ScanCompCommonExample PSoC 3, PSoC 4 (PSoC 4200), PSoC 5LP This data sheet code example demonstrates operation of the Scanning Comparator (Common Mode) component with the PSoC Creator Software.
ScanCompIntRefExample PSoC 3, PSoC 5LP This data sheet code example demonstrates operation of the Scanning Comparator (Internal VDAC Per channel Mode) component with the PSoC Creator Software.
SCB_EzI2cCommSlave PSoC 4 This code example demonstrates the basic operation of the EZI2C slave (SCB mode) component. The EZI2C slave accepts packet with command from I2C master to control RGB LED color. The EZI2C slave updates its buffer with status packet in response to the accepted -command.
SCB_I2cCommMaster PSoC 4 This code example demonstrates the basic operation of the I2C master (SCB mode) component. I2C master sends packet with command to I2C slave to control RGB LED color. The packet with status is read back.
SCB_I2cCommSlave PSoC 4 This code example demonstrates the basic operation of the I2C slave (SCB mode) component. The I2C slave accepts packet with command from I2C master to control RGB LED color. The I2C slave updates its buffer with status packet in response to the accepted command.
SCB_SpiComm PSoC 4 (PSoC 4100, PSoC 4200) This datasheet code example demonstrates operation of the SCB component configured in SPI. The first instance of SCB is configued as SPI master and the second as SPI Slave mode. The SPI master communicates with slave (bit rate 1Mbps).
SCB_UartTxRxComm PSoC 4 (PSoC 4100, PSoC 4200) This datasheet code example demonstrates operation of the SCB component configured in UART Tx+Rx mode. Data typed on the HyperTerminal is sent through serial port to the DVK and displayed on the LCD.After that this data is sent back and displayed on the HyperTerminal.
SegDisplay_Example PSoC 5 This code example demonstrates the Segment Display component operation in Always Active mode. In this code example, Bar graph, 7 Segment and 14 Segment helpers handle data processing and proper pixel reflection output on the LCD's Bar graph, 7 segments or 14 Segment digits.
SegLCD_LowPowerExample PSoC 3, PSoC 5LP The SegLCD Low Power design project contains an example for the use of the Segment LCD component. This example features the Segment LCD in Low Power (ILO) mode at a 62Hz refresh rate. It displays 14 Segment helper.
SegLCD_PSoC4_Example PSoC 4 (PSoC 4100, PSoC 4200) This code example demonstrates the PSoC 4 Segment LCD.
My1stLib PSoC 3 The My1stLib project contains an example of a library project for use with the PSoC Creator Help tutorial "Library Component Project." This project and tutorial provide an introduction into the process of creating simple shifter components. Add this project to the Shifter code example Workspace and add the dependency to the Shifter to generate the correct code example.
Shifter PSoC 3 The Shifter project contains an code example for use with the PSoC Creator tutorial: "Basic Hierarchical Design." This project and tutorial demonstrate how to re-use components created in the "Library Component Project" tutorial to create a simple hierarchical design. This project requires the My1stLib project be located in the same root directory.
ShiftReg_Design PSoC 3, PSoC 5, PSoC 5LP This datasheet code example demonstrates operation of the ShiftReg (Shift Register) component with the PSoC Creator Software. The basic functionality of 8-bit and 16-bit shift register is demonstrated.
SleepTimer_Interrupt_Sleep PSoC 3, PSoC 5, PSoC 5LP This datasheet code example demonstrates operation of the Sleep Timer component with the PSoC Creator Software. The wake up from Sleep low power mode every 4 milliseconds with interrupt issuing is implemented. The Power Management API is used for proper low power mode entry.
SPDIF_Tx PSoC 3, PSoC 5, PSoC 5LP This datasheet code example demonstrates operation of the S/PDIF Transmitter (SPDIF_Tx) component with the PSoC® Creator™ Software. The operation of the SPDIF_Tx and configuring a DMA transfer for this component are described and implemented.
SPIM_Example PSoC 3, PSoC 5, PSoC 5LP This code example demonstrates the operation of the SPI(Serial Peripheral Interface) Master component with the PSoC Creator Software. The operation of the SPI Master, configuring a DMA transfer and displaying results on an LCD screen are described and implemented. This example is intended to be used with the SPIS_code example.
SPIS_Example PSoC 3, PSoC 5, PSoC 5LP This code example demonstrates operation of the SPI(Serial Peripheral Interface) Slave component with the PSoC Creator Software. The operation of the SPI Master, configuring a DMA transfer and displaying results on LCD screen are described and implemented. This example is intended to be used with the SPIM_code example
SPI_Design PSoC 3, PSoC 5, PSoC 5LP This datasheet code example demonstrates operation of the SPI (Serial Peripheral Interface) component with the PSoC Creator Software. The communication between SPI Master and SPI Slave is implemented. The SPI Mode 0 (CPOL = 0, CPHA = 0) with 8 byte Rx and Tx software buffers is configured. The bit rate is set to 1 Mbps.
StaticSegLCD_Example PSoC 3 The SegLCD Low Power design project contains an example for the use of the Static Segment LCD in Sleep mode. It shows operation of 7 Segment helper.
SW_Tx_UART_Example PSoC 3, PSoC 4 (PSoC 4100, PSoC 4200), PSoC 5LP This code example demonstrates basic functionality of Software Transmit UART component.
TCPWMExample PSoC 4 This data sheet code example demonstrates operation of the TCPWM (Unconfigured TCPWM Mode) component with the PSoC Creator Software.
ThermistorCalc_Example PSoC 3, PSoC 5, PSoC 5LP This code example demonstrates the use of the Thermistor Calculator component for temperature measurement.
ThermocoupleExample PSoC 3, PSoC 5, PSoC 5LP This data sheet code example demonstrates operation of the Thermocouple calculator component with the PSoC Creator Software. The K-type thermocouple type, 0.1 Calculation error budget is demonstrated.
TIA_Example PSoC 3, PSoC 5, PSoC 5LP This design project contains an example for the use of the TIA component.
Timer PSoC 3, PSoC 5, PSoC 5LP This design project contains an example for the use of the Timer, ISR and clock components. The 16-bit UDB timer counts down on the positive edge of each clock, and captures the count value for the rising edge of a slower clock given as input. An interrupt is triggered on every terminal count, and the number of interrupts generated is displayed on the Character LCD. In addition, this simple example reads the timer Period, Capture, and Counter values and displays them on the LCD module.
TimerExample PSoC 4 This data sheet code example demonstrates operation of the TCPWM (Timer / Counter Mode) component with the PSoC Creator Software.
TMP05IntfExample PSoC 3,PSoC 4(PSoC 4200,PSoC 5, PSoC 5LP) This data sheet code example demonstrates operation of theTMP05 Temp Sensor Interface component with the PSoC Creator Software. The continuous mode is demonstrated.
TrimMarginExample PSoC 3, PSoC 5LP This code example demonstrates the basic operation of the Trim Margin component
UART_Rx PSoC 3, PSoC 4 (PSoC 4200), PSoC 5, PSoC 5LP The UART Rx design project contains an example for the use of the UART component. This example demonstrates the UART Reception (Rx) mechanism. Data input via Hyperterminal is sent through the serial port and displayed on the LCD module.
UART_Tx PSoC 3, PSoC 4 (PSoC 4200), PSoC 5, PSoC 5LP The UART Tx design project contains an example for the use of the UART component. This example demonstrates the UART Transmission (Tx) -mechanism. Data sent via the serial port is displayed on Hyperterminal and the LCD module.
USBFS_AUDIO PSoC 3, PSoC 5LP This datasheet code example demonstrates the operation of the 8-bit, 32-kHz, mono USB Audio Device.
USBFS_Bootloadable PSoC 3, PSoC 5LP This datasheet code example demonstrates the operation of the Bootloadable component. Add this project to the USBFS_Bootloader code example Workspace and add Dependency to the USBFS_Bootloader to generate the correct code example.
USBFS_Bootloader PSoC 3, PSoC 5LP This datasheet code example demonstrates the operation of the Bootloader with USBFS as an I/O component.
USBFS_Bulk_Wraparound PSoC 3, PSoC 5LP This datasheet code example demonstrates the operation of the USBFS (Full Speed USB) component with the PSoC Creator software. It also shows the Bulk transfers implementation.
USBFS_HID PSoC 3, PSoC 5LP This datasheet code example demonstrates the operation of the USBFS (Full Speed USB) component with the PSoC Creator software. It also shows the USB mouse implementation.
USB_MIDI PSoC 3, PSoC 5LP This datasheet code example demonstrates the operation of the MIDI interface device operation.
USB_UART PSoC 3, PSoC 5LP This datasheet code example demonstrates the operation of the USBFS component as an RS-232 logical cable replacement.
VDAC8_ExampleProject PSoC 3, PSoC 5, PSoC 5LP This design project contains an example for the use of the VDAC component. This simple example sets the VDAC range to 1.020V and outputs a Voltage set in the firmware to a fixed pin. This voltage can be verified using a Multimeter.
VFD_Example PSoC 3, PSoC 5LP This datasheet code example demonstrates the operation of the Voltage Fault Detector.
VoltSeqExample PSoC 3, PSoC 5LP This code example demonstrates the basic operation of the Voltage Sequencer component.
Watchdog_CY8C401x PSoC 4 (PSoC 4000) This code example demonstrates the basic operation of the WDT: device reset and periodic interrupt generation.
Watchdog_PSoC4_Example PSoC 4 (PSoC 4100, PSoC 4200) This code example demonstrates basic functionality of PSoC4 watchdog.
WaveDAC8_Example PSoC 3, PSoC 5LP This code example demonstrates basic functionality of WaveDAC8 component.
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Tue, 21 Oct 2014 06:01:02 -0600
PSoC Creator Training http://www.cypress.com/?rID=40547 PSoC 3 and PSoC 5 Workshops:

Introduction to PSoC 3
This half day workshop will give you hands-on experience using and developing PSoC3 and PSoC5 solutions utilizing Cypress's PSoC® Creator™ Software development environment and the PSoC Development Kit (CY8CKIT-001)

Introduction to PSoC 5
This half day workshop will give you hands-on experience using and developing PSoC 5 solutions utilizing Cypress's PSoC® Creator™ Software development environment and the PSoC Development Kit (CY8CKIT-001)

PSoC 3 and PSoC 5 Intermediate Workshop
This full day workshop provides in depth training on how to use the high precision and programmable analog, programmable digital and advanced CPU subsystems in your embedded designs. This workshop builds off of the first, half-day, Introduction to PSoC 3 and PSoC 5 Workshop and provides more in depth and hands-on training for you to fully understand these features and how to use them with the PSoC Creator integrated development environment.

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PSoC Videos:

PSoC Creator: Made for Engineers
Meet Alan Hawse, Executive Vice President of Software for Cypress, and his vision for PSoC Creator.

PSoC Today! Introducing PSoC 4 Part I
Special Guest Max Kingsbury kicks off a series introducing the PSoC 4 and the Pioneer kit.

PSoC 5LP Analog Design
Jim Davis, Product Marketing Manager for PSoC, introduces you to the analog design methodology of PSoC and PSoC Creator

For more PSoC videos visit our video library at video.cypress.com

PSoC On-Demand Training:

PSoC Creator 101 Lesson 1: Introduction to PSoC Creator 101
PSoC Creator 101 Lesson 2: Introduction to PSoC
PSoC Creator 101 Lesson 3: Getting to Know PSoC Creator
PSoC Creator 101 Lesson 4: Let's Get an LED to Blink Part 1
PSoC Creator 101 Lesson 5: Let's Get an LED to Blink Part 2
PSoC Creator 101 Lesson 6: Let's Get CapSense Working
PSoC Creator 101 Lesson 7: IDE Export
PSoC Creator 101 Lesson 8: PSoC Resources

Getting Started

Using the UDB Editor

Component Creation Tutorials


Component Development Training For PSoC using PSoC Creator

PSoC Creator 110: Schematic Components
PSoC Creator 111: Component Parameters
PSoC Creator 112: Intro to Component API Generation
PSoC Creator 113: PLD Based Verilog Components
PSoC Creator 210: Intro to Datapath Components
PSoC Creator 211: Datapath Computation
PSoC Creator 212: Datapath FIFOs
PSoC Creator 213: Multi-Byte Datapath Components
PSoC Creator 214: Datapath API Generation
PSoC Creator: Custom Components
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Mon, 20 Oct 2014 02:19:49 -0600
Avoiding Regeneration of Source Files in PSoC<sup>®</sup> Creator™ – KBA83286 http://www.cypress.com/?rID=46373 Answer: Yes. If you do not want to regenerate the source code for a project, go to Project > Build Settings > Code Generation. Then set Skip Code Generation to True (Figure 1). Click Apply and OK.

Figure 1. Build Settings

build_settings

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Thu, 16 Oct 2014 05:10:32 -0600
Crystal Clock Error Routine at Startup in PSoC<sup>®</sup> 3, and PSoC 5LP - KBA85476 http://www.cypress.com/?rID=101482 Answer: To counter this situation the CPU gets stuck in the Clock Startup procedure. The ClockSetup() phase is associated with a timeout window exceeding, which results in calling the CyClockStartupError().The CPU gets stuck in an infinite while loop within this routine. The routines can be found in cyfitter_cfg.c. Figures 1 and 2 depict the same.

Figure 1. Clock Setup Routine Executed During Startup

Figure 2. Clock Startup Error Routine; by Default This Would Run into an Infinite While Loop

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Wed, 15 Oct 2014 00:52:14 -0600
8-Bit Waveform Generator (WaveDAC8) http://www.cypress.com/?rID=86070

Features

  • Supports standard and arbitrary waveform generation
  • Arbitrary waveform may be drawn manually or imported from file
  • Output may be voltage or current, sink or source
  • Voltage output can be buffered or direct from DAC
  • Hardware selection between two waveforms
  • Waveforms may be up to 4000 points
  • Predefined sine, triangle, square, and sawtooth waveforms

Symbol Diagram

General Description

The WaveDAC8 component provides a simple and fast solution for automatic periodic waveform generation. A high-level interface allows you to select a predefined waveform or a custom arbitrary waveform. Two separate waveforms can be defined then selected with an external pin to create a modulated output. The input clock can also be used to change the sample rate or modulate the output.

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Mon, 13 Oct 2014 13:45:00 -0600
Voltage Sequencer http://www.cypress.com/?rID=68786 Features

  • Supports sequencing and monitoring of up to 32 power converter rails
  • Supports power converter circuits with logic-level enable inputs and logic-level power good (pgood) status outputs
  • Autonomous (standalone) or host driven operation
  • Sequence order, timing and inter-rail dependencies can be configured through an intuitive, easy-to-use graphical configuration GUI


General Description

The Voltage Sequencer component provides a simple way to define power-up and power-down sequencing of up to 32 power converters to meet user-defined system requirements. Once the sequencing requirements have been entered into the easy-to-use graphical configuration GUI, the component will automatically take care of the sequencing implementation without requiring any firmware development by the user.

Voltage Sequencer_1
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Mon, 13 Oct 2014 13:39:40 -0600
Voltage Fault Detector (VFD) http://www.cypress.com/?rID=69014 Features
  • Monitor up to 32 voltage inputs
  • User-defined over and under voltage limits
  • Simply outputs a good/bad status result
  • Programmable glitch filter lengths
Symbol Diagram

General Description

The Voltage Fault Detector component provides a simple way to monitor up to 32 voltage inputs against user-defined over and under voltage limits without using the ADC and without having to write any firmware. The component simply outputs a good/bad status result (“power good” or pgood[x]) for each voltage being monitored.

The component operates entirely in hardware without any intervention from PSoC’s CPU core resulting in known, fixed fault detection latency.

Note: This component supports PSoC 3 and PSoC 5LP devices only.

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Mon, 13 Oct 2014 13:27:56 -0600
Vector CAN http://www.cypress.com/?rID=56768 Features
Symbol Diagram
  • CAN2.0 A/B protocol implementation, ISO 11898-1 compliant
  • Programmable bit rate up to 1 Mbps @ 8 MHz (BUS_CLK)
  • Two or three wire interface to external transceiver (Tx, Rx, and Tx Enable)
  • Driver provided and supported by Vector

General Description

The Vector CANbedded environment consists of a number of adaptive source code components that cover the basic communication and diagnostic requirements in automotive applications.

The Vector CANbedded software suite is customer specific and its operation will vary according to application and OEM. This component for the Vector CANbedded suite is written to generically support the CANbedded structure regardless of the flavor of the particular OEM application. 

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Mon, 13 Oct 2014 13:22:02 -0600
Universal Asynchronous Receiver Transmitter (UART) http://www.cypress.com/?rID=48892 Features

  • 9-bit address mode with hardware address detection
  • Baud rates from 110 to 921600 bps or arbitrary up to 4 Mbps
  • RX and TX buffers = 4 to 65535
  • Detection of Framing, Parity, and Overrun errors
  • Full Duplex, Half Duplex, TX only, and RX only optimized hardware
  • Two out of three voting per bit
  • Break signal generation and detection
  • 8x or 16x oversampling
Symbol Diagram

General Description

The UART provides asynchronous communications commonly referred to as RS232 or RS485. The UART component can be configured for Full Duplex, Half Duplex, RX only, or TX only versions. All versions provide the same basic functionality. They differ only in the amount of resources used.

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Mon, 13 Oct 2014 13:15:18 -0600
Static Segment LCD (StaticSegLCD) http://www.cypress.com/?rID=46487
 Features
 
  • 1 to 61 pixels or symbols
  • 10- to 150-Hz refresh rate
  • User-defined pixel or symbol map with optional 7-segment, 14-segment, 16-segment and bar graph calculation routines
  • Direct drive static (one common) LCDs
   Symbol Diagram


General Description

The Static Segment LCD (LCD_SegStatic) component can directly drive 3.3-V and 5.0-V LCD glass. This component provides an easy method of configuring the PSoC device for your custom or standard glass.

Each LCD pixel/symbol may be either on or off. The Static Segment LCD component also provides advanced support to simplify the following types of display structures within the glass:

  • 7-Segment numeral
  • 14-Segment alphanumeric
  • 16-Segment alphanumeric
  • 1- to 255-element bar graph
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Mon, 13 Oct 2014 13:07:06 -0600
Serial Peripheral Interface (SPI) Slave http://www.cypress.com/?rID=48908 Features

  • 3- to 16-bit data width
  • Four SPI modes
  • Bit Rate up to 5 Mbps
Symbol Diagram

General Description

The SPI Slave provides an industry-standard, 4-wire slave SPI interface. It can also provide a 3-wire (bidirectional) SPI interface. Both interfaces support all four SPI operating modes, allowing communication with any SPI master device. In addition to the standard 8-bit word length, the SPI Slave supports a configurable 3- to 16-bit word length for communicating with nonstandard SPI word lengths.

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Mon, 13 Oct 2014 13:02:10 -0600
SM Bus and PM Bus Slave http://www.cypress.com/?rID=69782 Features
  • SMBus Slave mode
  • PMBus Slave mode
  • SMBALERT# pin support
  • 25 ms Timeout
  • Fixed Function (FF) and UDB implementations
  • Configurable SM/PM Bus commands
     
Symbol Diagram

General Description

The System Management Bus (SMBus) and Power Management Bus (PMBus) Slave component provides a simple way to add an I2C physical layer interface to a PSoC 3 or PSoC 5LP design with either SMBus or PMBus protocol running on top of it.

The SMBus is a two-wire interface with various System Management chips that can communicate with the system host. It uses I2C as a physical layer. The SMBus Slave component implements most of the SMBus Slave device specifications and provides options for configuring the slave device parameters. The slave device can communicate with the SMBus Master using the provided APIs.

The PMBus protocol is a specific implementation of the more generic SMBus protocol. With the PMBus, the component presents all the possible PMBus commands and allows you to select which commands are relevant to your application.

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Mon, 13 Oct 2014 09:49:01 -0600
Segment LCD (LCD_Seg) http://www.cypress.com/?rID=48918 Features

  • 2 to 768 pixels or symbols
  • 1/3, 1/4 and 1/5 bias supported
  • 10- to 150-Hz refresh rate
  • Integrated bias generation between 2.0 V and 5.2 V with up to 128 digitally controlled bias levels for dynamic contrast control
  • Supports both type A (standard) and type B (low power) waveforms
  • Pixel state of the display may be inverted for negative image
  • 256 bytes of display memory (frame buffer)
  • User-defined pixel or symbol map with optional 7-, 14-, or 16-segment character; 5x7 or 5x8 dot matrix; and bar graph calculation routines.
Symbol Diagram


General Description

The Segment LCD (LCD_Seg) component can directly drive a variety of LCD glass at different voltage levels with multiplex ratios up to 16x. This component provides an easy method of configuring the PSoC device to drive your custom or standard glass. 

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Mon, 13 Oct 2014 09:31:14 -0600
SC/CT Comparator (SCCT_Comp) http://www.cypress.com/?rID=82358 Features Symbol Diagram
  • Output routable to digital logic blocks or pins
  • Selectable output polarity

General Description

The SC/CT Comparator (SCCT_Comp) component provides a hardware solution to compare two analog input voltages. The implementation uses a mode of the Switched Capacitor / Continuous Time (SC/CT) analog block to implement the comparator. The output can be digitally routed to another component. A reference or external voltage can be connected to either input. You can also invert the output of the comparator using the Polarity parameter.

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Mon, 13 Oct 2014 09:26:43 -0600
Resistive Touch http://www.cypress.com/?rID=58690 Features

  • Supports 4-wire resistive touchscreen interface
  • Supports the Delta Sigma Converter for both the PSoC 3 and PSoC 5 devices
  • Supports the ADC Successive Approximation Register for PSoC 5 devices
    Symbol Diagram
General Description

This resistive touchscreen component is used to interface with a 4-wire resistive touch screen. The component provides a method to integrate and configure the resistive touch elements of a touchscreen with the emWin Graphics library. It integrates hardware-dependent functions that are called by the touchscreen driver supplied with emWin when polling the touch panel.

PSoC® Creator emWin and Resistive Touch Components Video
use for camtasia screencasts

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Mon, 13 Oct 2014 09:19:50 -0600
Quadrature Decoder (QuadDec) http://www.cypress.com/?rID=46480 Features

  • Adjustable counter size: 8, 16, or 32 bits
  • Counter resolution of 1x, 2x, or 4x the frequency of the A and B inputs, for more accurate determination of position or speed
  • Optional index input to determine absolute position
  • Optional glitch filtering to reduce the impact of system-generated noise on the inputs
Symbol Diagram

General Description

The Quadrature Decoder (QuadDec) Component gives you the ability to count transitions on a pair of digital signals. The signals are typically provided by a speed/position feedback system mounted on a motor or trackball.

The signals, typically called A and B, are positioned 90 degrees out of phase, which results in a Gray code output. A Gray code is a sequence where only one bit changes on each count. This is essential to avoid glitches. It also allows detection of direction and relative position. A third optional signal, named Index, is used as a reference to establish an absolute position once per rotation.

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Mon, 13 Oct 2014 09:16:16 -0600
Power Monitor http://www.cypress.com/?rID=63922 Features

  • Interfaces to up to 32 DC-DC power converters
  • Measures power converter output voltages and load currents using a DelSig-ADC
  • Monitors the health of the power converters generating warnings and faults based on user-defined thresholds
  • Support for measuring other auxiliary voltages in the system
  • Support 3.3V and 5V chip power supply
Symbol Diagram


General Description

Power Converter Voltage Measurements:

For power converter voltage measurements, the ADC can be configured into single-ended mode (0-4.096 V range or 0-2.048 V range). The ADC can also be configurable into differential mode (±2.048 V range) to support remote sensing of voltages where the remote ground reference is returned to PSoC over a PCB trace. In cases where the analog voltage to be monitored equals or exceeds Vdda or the ADC range, external resistor dividers are recommended to scale the monitored voltages down to an appropriate range.

Power Converter Current Measurements:

For power converter load current measurements, the ADC can be configured into differential mode (+/- 64 mV or +/- 128 mV range) to support voltage measurement across a high-side series shunt resistor on the outputs of the power converters. Firmware APIs convert the measured differential voltage into the equivalent current based on the external resistor component value used. The ADC can also be configured into single-ended mode (matching the selected voltage measurement range) to support connection to external current sense amplifiers (CSAs) that convert the differential voltage drop across the shunt resistor into a single ended voltage or to support power converters or hot-swap controllers that integrate similar functionality.

PSoC Creator Power Monitor Component Video  

use for camtasia screencasts

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Mon, 13 Oct 2014 09:07:02 -0600
MDIO Interface http://www.cypress.com/?rID=76699 Features
Symbol Diagram
  • Used in conjunction with Ethernet products
  • Configurable physical address
  • Supports up to 4.4 MHz in the clock bus (mdc)
  • Compliant with IEEE 802.3 Clause 45
  • Automatically allocates memory for the register spaces that can be configured through an intuitive, easy-to-use graphical configuration GUI

General Description

The MDIO Interface component supports the Management Data Input/Output, which is a serial bus defined for the Ethernet family of IEEE 802.3 standards for the Media Independent Interface (MII). The MII connects Media Access Control (MAC) devices with Ethernet physical layer (PHY) circuits. The component is compliant with IEEE 802.3 Clause 45.

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Mon, 13 Oct 2014 08:53:50 -0600
LED Segment and Matrix Driver http://www.cypress.com/?rID=82355 Features Symbol Diagram
  • Up to 8 RGB 7-segment digits, or 24 monochrome 7-segment digits
  • Up to 8 14-segment or 16-segment displays
  • Up to 192 LEDs in an 8x8 tri-color matrix
  • Active high or active low commons
  • Active high or active low segments
  • Driver is multiplexed requiring no CPU overhead or interrupts
  • Functions for numeric and string display using 7-, 14-, and 16-segment displays
  • Independent brightness level for each common


General Description

The LED Segment and Matrix Driver component is a multiplexed LED driver that can handle up to 24 segment signals and 8 common signals. It can be used to drive 24 7-segment LEDs, eight 14/16-segment LEDs, eight RGB 7-segment LEDs, or a tri-color matrix of up to 192 LEDs in an 8x8 pattern. APIs are provided to convert alpha-numeric values to their segment codes, and the brightness of each of the commons can be independently controlled. This component is supported for PSoC 3 and PSoC 5LP.

Multiplexing the LEDs is an efficient way to save GPIO pins, however the commons must be multiplexed at a steady rate. To address this latter issue, the component uses PSoC’s DMA and UDBs to multiplex the LEDs without CPU overhead. This eliminates cases of non-periodic updating as the multiplexing is handled solely using hardware. The CPU is thus used only when updating the display information and to change the brightness settings.

When displaying the 7/14/16 segment digits, these digits do not have to be grouped as a single numerical display. An 8 digit display could be divided up into one 2-digit and two 3-digit displays for example. When operating in the LED matrix mode, the individual displays do not have to be arranged in a matrix, but instead can be various single or grouped LEDs. The component also supports displaying combined digits with annunciators.

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Mon, 13 Oct 2014 08:42:40 -0600
ILO TRIM http://www.cypress.com/?rID=78823 Features Symbol Diagram
  • Trims 1 kHz and 100 kHz ILO for PSoC 3 and PSoC 5LP
  • ILO trimming support for PSoC 3 and PSoC 5LP
  • UDB and Fixed-Function modes
  • User-specified reference clock

General Description

The ILO Trim component allows your application to determine the accuracy of the ILO. It provides a scaling function to allow the application to compensate for this inaccuracy. For PSoC 3 and PSoC 5LP devices, it can also directly improve the accuracy of the ILO by using a user-defined higher frequency, higher accuracy reference clock to count the number of ILO clock cycles. The derived information is then used to trim the ILO trim registers to incrementally approach the desired ILO frequency. The component supports both UDB and Fixed-Function implementations.

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Mon, 13 Oct 2014 08:36:28 -0600
I2C Master/Multi-Master/Slave http://www.cypress.com/?rID=51969

Features

  • Industry-standard NXP® I2C bus interface
  • Supports Slave, Master, Multi-Master and Multi-Master-Slave operation
  • Requires only two pins (SDA and SCL) to interface to I2C bus
  • Supports standard data rates of 100/400/1000 kbps
  • High level APIs require minimal user programming
   
  Symbol Diagram


General Description

The I2C component supports I2C slave, master, and multi-master configurations. The I2C bus is an industry-standard, two-wire hardware interface developed by Philips. The master initiates all communication on the I2C bus and supplies the clock for all slave devices.

The I2C component supports standard clock speeds up to 1000 kbps. It is compatible with I2C Standard-mode, Fast-mode, and Fast-mode Plus devices as defined in the NXP I2C-bus specification. The I2C component is compatible with other third-party slave and master devices.

Note: This version of the component datasheet covers both the fixed hardware I2C block and the UDB version.

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Mon, 13 Oct 2014 08:22:19 -0600
Fan Controller http://www.cypress.com/?rID=63918 Features

  • Support for up to 16 PWM-controlled, 4-wire brushless DC fans for PSoC 3/PSoC 5LP devices and up to 6 fans for PSoC 4
  • Individual or banked PWM outputs with tachometer inputs
  • Supports 25 kHz, 50 kHz or user-specified PWM frequencies
  • Supports fan speeds up to 25,000 RPM
  • Supports 4-pole and 6-pole motors
  • Supports fan stall / rotor lock detection on all fans
  • Supports firmware controlled or hardware controlled fan speed regulation for PSoC 3/PSoC 5LP
  • Supports firmware-controlled fan speed regulation for PSoC 4
  • Customizable alert pin for fan fault reporting
Symbol Diagram

General Description

The Fan Controller component enables designers to quickly and easily develop fan controller solutions using PSoC. The component is a system-level solution that encapsulates all necessary hardware blocks including PWMs, or TCPWMs for PSoC 4, tachometer input capture timer, control registers, status registers and a DMA controller (ISR for PSoC 4) reducing development time and effort.

The component is customizable through a graphical user interface enabling designers to enter fan electromechanical parameters such as duty cycle-to-RPM mapping and physical fan bank organization. Performance parameters including PWM frequency and resolution as well as open or closed loop control methodology can be configured through the same user interface. Once the system parameters are entered, the component delivers the most optimal implementation saving resources within PSoC to enable integration of other thermal management and system management functionality. Easy-to-use APIs are provided to enable firmware developers to get up and running quickly.

 

PSoC Creator Fan Controller Component Video

use for camtasia screencasts

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Mon, 13 Oct 2014 08:15:59 -0600
External Memory Interface (EMIF) http://www.cypress.com/?rID=56752 Features
Symbol Diagram
  • 8-, 16-, 24-bit address bus width
  • 8-, 16-bit data bus width
  • Supports external synchronous memory
  • Supports external asynchronous memory
  • Supports custom interface for memory
  • Supports a range of speeds of external memories (from 5 to 200 ns)
  • Supports external memory power-down, sleep, and wakeup modes

General Description

The EMIF component enables access by the CPU or DMA to memory ICs external to the PSoC 3/PSoC 5LP. It facilitates setup of the EMIF hardware, as well as UDBs and GPIOs as required. The EMIF can control synchronous and asynchronous memories without the need to configure any UDBs in synchronous and asynchronous modes. In UDB mode, UDBs must be configured to generate external memory control signals.

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Mon, 13 Oct 2014 07:44:59 -0600
File System Library (emFile) http://www.cypress.com/?rID=58694 Features Symbol Diagram
  • Up to four Secure Digital (SD) cards in SPI mode
  • FAT12/16 or FAT32 format
  • Optional integration with an Operating System (OS)
  • Optional Long File Name (LFN) handling

General Description

The emFile component provides an interface to SD cards formatted with a FAT file system. The SD card specification includes multiple hardware interface options for communication with an SD card. This component uses the SPI interface method for communication. Up to four independent SPI interfaces can be used for communication with one SD card each. Both FAT12/16 and FAT32 file system formats are supported. This component provides the physical interface to the SD card and works with the emFile library licensed from SEGGER Microcontroller to provide a library of functions to manipulate a FAT file system.

Firmware Installation:  The firmware files for this component are not distributed with PSoC Creator and can be downloaded below. Please refer to the component datasheet for installation instructions.

IMPORTANT NOTICE REGARDING LONG FILE NAMES:  If you configure the software to support long file names on FAT file systems, you should review the information at http://www.microsoft.com/about/legal/en/us/IntellectualProperty/IPLicensing/Programs/FATFileSystem.aspx to determine whether a license from Microsoft is required. Cypress and its suppliers grant no license under Microsoft's intellectual property rights and assume no liability for any use of the software without obtaining any license that may be required.

PSoC® Creator emFile Component Video

use for camtasia screencasts

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Mon, 13 Oct 2014 07:32:18 -0600
Pins http://www.cypress.com/?rID=48513 Features

  • Rapid setup of all pin parameters and drive modes
  • Allows PSoC Creator to automatically place and route signals
  • Allows interaction with one or more pins simultaneously
Symbol Diagram

General Description

The Pins component allows hardware resources to connect to a physical port-pin. It provides access to external signals through an appropriately configured physical IO pin. It also allows electrical characteristics (e.g., Drive Mode) to be chosen for one or more pins; these characteristics are then used by PSoC Creator to automatically place and route the signals within the component.

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Mon, 13 Oct 2014 07:23:27 -0600
Delta Sigma Analog to Digital Converter (ADC_DelSig) http://www.cypress.com/?rID=48916

Features

  • Selectable resolutions, 8 to 20 bits
  • Eleven input ranges for each resolution
  • Sample rate 8 sps to 384 ksps
  • Operational modes:
    • Single sample
    • Multi-sample
    • Continuous mode
    • Multi-sample (Turbo)
  • High input impedance input buffer
    • Selectable input buffer gain (1, 2, 4, 8) or input buffer bypass
  • Multiple internal or external reference options
  • Automatic power configuration
  • Up to four run-time ADC configurations
Symbol Diagram

General Description

The Delta Sigma Analog to Digital Converter (ADC_DelSig) provides a low-power, low-noise front end for precision measurement applications. You can use it in a wide range of applications, depending on resolution, sample rate, and operating mode. It can produce 16-bit audio; high speed and low resolution for communications processing; and high-precision 20-bit low-speed conversions for sensors such as strain gauges, thermocouples, and other high-precision sensors. When processing audio information, the ADC_DelSig is used in a continuous operation mode. When used for scanning multiple sensors, the ADC_DelSig is used in one of the multi-sample modes. When used for single-point high-resolution measurements, the ADC_DelSig is used in single-sample mode.

]]>
Mon, 13 Oct 2014 07:15:46 -0600
PSoC® Creator™ System Reference Guide (CY_Boot Component) http://www.cypress.com/?rID=51972 This System Reference Guide describes functions supplied by the PSoC Creator cy_boot component. The cy_boot component provides the system functionality for a project to give better access to chip resources. The functions are not part of the component libraries but may be used by them. You can use the function calls to reliably perform needed chip functions.

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Mon, 13 Oct 2014 07:14:25 -0600
Capacitive Sensing (CapSense® CSD) http://www.cypress.com/?rID=48884 Features
                   Symbol Diagram
  • Support for user-defined combinations of button, slider, touchpad, and proximity capacitive sensors.
  • Automatic SmartSense™ tuning or manual tuning with integrated PC GUI.
  • High immunity to AC power line noise, EMC noise, and power supply voltage changes.
  • Optional two scan channels (parallel synchronized), which increases sensor scan rate.
  • Shield electrode support for reliable operation in the presence of water film or droplets.
  • Guided sensor and terminal assignments using the CapSense customizer.

General Description

Capacitive Sensing, using a Delta-Sigma Modulator (CapSense CSD) component, is a versatile and efficient way to measure capacitance in applications such as touch sense buttons, sliders, touchpad, and proximity detection.

]]>
Mon, 13 Oct 2014 07:01:38 -0600
Controller Area Network (CAN) http://www.cypress.com/?rID=46443

Features
 

  • CAN2.0A and CAN2.0B protocol implementation, ISO 11898-1 compliant
  • Programmable bit rate up to 1 Mbps at 8 MHz (BUS_CLK)
  • Two-wire or three-wire interface to external transceiver (Tx, Rx, and Enable)
  • Extended hardware message filter that covers Data Byte 1 and Data Byte 2 fields
  • Programmable transmit priority: Round Robin and Fixed

 

Symbol Diagram

General Description

The Controller Area Network (CAN) controller implements the CAN2.0A and CAN2.0B specifications as defined in the Bosch specification and conforms to the ISO-11898-1 standard.

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Mon, 13 Oct 2014 06:03:27 -0600
PSoC 3 Known Problems and Solutions http://www.cypress.com/?rID=40741 Wed, 08 Oct 2014 10:12:34 -0600 External Memory Interface Support in PSoC<sup>®</sup> 3 / PSoC 5LP – KBA88199 http://www.cypress.com/?rID=38590 Answer: The EMIF supports four types of external memory: synchronous SRAM, asynchronous SRAM, cellular RAM/PSRAM, and NOR flash. The following are the main features of the EMIF:

  • The EMIF Component enables access by the CPU or DMA to memory ICs external to the PSoC® 3/5LP.
  • EMIF memory can be 8- and16-bit data bus width and 8-, 16-, and 24-bit address bus width.
  • For PSoC 3, the EMIF XDATA Data Address Map ranges from 0x800000 to 0xFFFFFF; for PSoC 5LP, the EMIF Memory Address Map ranges from 0x60000000 to 0x60FFFFFF.
  • The EMIF also supports a custom interface apart from standard asynchronous and synchronous interfaces.
  • Code cannot be executed from the EMIF in PSoC 3, while it is possible in PSoC 5LP. However, it is difficult to initialize code in external memory. In general, having code in external memory is not recommended.

There is an example project associated with the EMIF Component, which can be opened from PSoC Creator™ > File > Open > Example Project. Select EMIF in Keyword #1. This project was performed with an asynchronous SRAM on a prototype QVGA board. You can also find the necessary documentation along with this project.

]]>
Wed, 08 Oct 2014 05:40:35 -0600
AN54460 - PSoC<sup>®</sup> 3 and PSoC 5LP Interrupts http://www.cypress.com/?rID=38267

AN54460 explains the interrupt architecture in PSoC® 3 and PSoC 5LP, and its configuration in PSoC Creator™ IDE with the help of example projects. Advanced interrupt topics such as handling re-entrant functions, interrupt code optimization, interrupt latency, and debug techniques are also explained.

Important Note: From version *G and above of this application note, the PSoC 4 content in the earlier versions of this application note has been moved to the dedicated PSoC 4 application note – AN90799 - PSoC® 4 Interrupts. From version *G and above, this application note covers only PSoC 3 and PSoC 5LP devices.

Introduction

Interrupts are an important part of any embedded application. They free the CPU from having to continuously poll for the occurrence of a specific event and, instead, notify the CPU only when that event occurs. In system-on-chip (SoC) architectures such as PSoC, interrupts are frequently used to communicate the status of on-chip peripherals to the CPU.

Video

The below video provides a walkthrough of basics of PSoC 3, PSoC 5LP Interrupt architecture. It demonstrates how the PSoC Creator software supports Interrupts by using a simple example project.

 

Compatibility Matrix

The following table indicates the PSoC devices, PSoC Creator versions, compilers, and development kits that will work with this application note project:

Project Device PSoC Creator
Version
Development Kit
CY8CKIT-xxx
Architecture Silicon
Revision
V3.0 SP1 or
higher
V3.0 or
lower
001
DVK
030/050
DVK
AN54460.zip PSoC3 Prod YES NO YES YES*
PSoC5LP Prod YES NO YES YES*

* Refer to Migrating CY8CKIT-001 DVK project to CY8CKIT 030/ 050.

Projects associated with this application note can be downloaded from the ‘Related Files’ section below.

]]>
Mon, 06 Oct 2014 06:37:31 -0600
AN82250 - PSoC<sup>®</sup> 3, PSoC 4, and PSoC 5LP Implementing Programmable Logic Designs with Verilog http://www.cypress.com/?rID=69773

AN82250 describes how to implement programmable digital logic designs in the PLD portion of PSoC® 3, PSoC 4 and PSoC 5LP. It introduces the PSoC Universal Digital Blocks (UDBs) and their Programmable Logic Device (PLD) subblocks. An example project illustrates how you can use the PLDs in a design by creating Verilog-based components in PSoC Creator™.

Introduction

PSoC® 3, PSoC 4 and PSoC 5LP (hereafter referred to as PSoC) are more than just microcontrollers. With PSoC you can integrate the functions of a microcontroller, complex programmable logic device (CPLD) and high-performance analog with unmatched flexibility. This saves cost, board space, power, and development time.

Note This application note does not apply to CY8C41xx parts which do not contain UDBs.


Project Device PSoC Creator
Version
Development Kit
CY8CKIT-xxx
Architecture Silicon
Revision
V3.0 SP1
or higher
V2.1 SP1
/2.1
001
DVK
030/050
DVK
042 Pioneer DVK
AN82250.zip PSoC3 Prod YES NO YES YES* N/A
PSoC4 Prod YES NO YES N/A YES**
PSoC5LP Prod YES NO YES YES* N/A
AN82250_Archive.zip PSoC3 ES2, ES3, Prod NO YES YES YES* N/A
PSoC5 ES1, Prod NO YES YES YES* N/A

* Refer to Migrating CY8CKIT-001 DVK project to CY8CKIT 030/ 050.
** The project can be easily adapted to this DVK.

Projects associated with this application note can be downloaded from the 'Related Files' section below. For your convenience, we have provided projects that are compatible with the two most recent versions of PSoC Creator:

  • AN82250.zip is used with PSoC Creator 3.0 SP1
  • AN82250_Archive.zip is used with PSoC Creator 2.2 or PSoC Creator 2.1 SP1
]]>
Wed, 01 Oct 2014 06:58:50 -0600
AN61102 - PSoC<sup>®</sup> 3 and PSoC 5LP - ADC Data Buffering Using DMA http://www.cypress.com/?rID=44335 AN61102 describes how to configure the direct memory access (DMA) to buffer the analog-to-digital converter (ADC) data. It discusses how to overcome some of the limitations of the DMA when buffering the ADC data.

The DMA controller in PSoC® 3 and PSoC 5LP is used to handle data transfer without CPU intervention. This is useful in applications that require ADC data buffering and allows the CPU to do simultaneous tasks.

The video describes the case of using a DMA to buffer ADC data. Buffering of 20 bit ADC data is taken as an example and discussed. The video also gives a preview of the project implementing the 20 bit data buffering and explains the DMA configuration in code.

 

 

The following table indicates the PSoC devices, PSoC Creator versions, compilers, and development kits that will work with this application note project:


Project
Device
PSoC Creator
Version
Development Kit
CY8CKIT-xxx
Compiler
Architecture
Silicon
Revision
V3.0 SP1
V2.1 SP1
/2.1
001
DVK
030/050
DVK
003/014
FTK
Keil
GCC
RVDS
MDK

AN61102.zip

Prod
YES
NO
YES
YES*
NO
YES
N/A
N/A
N/A
Prod
YES
NO
YES
YES*
NO
N/A
YES
YES
YES
AN61102_Archive.zip
ES3, Prod
NO
YES
YES
YES*
NO
YES
N/A
N/A
N/A
ES1, Prod
NO
YES
YES
YES*
NO
N/A
YES
YES
YES

*Refer to Migrating CY8CKIT-001 DVK project to CY8CKIT 030/ 050

Notes:

  1. Click on AN77835 - PSoC® 3 to PSoC 5LP Migration Guide to learn differences between PSoC 3 and PSoC 5LP.
  2. For PSoC 5 project and related document, please download file AN61102_Archive.zip.

Projects associated with this application note can be downloaded from the ‘Related Files’ section below. For your convenience, we have provided projects that are compatible with the two most recent versions of PSoC Creator:

  • AN61102.zip is used with PSoC Creator 3.0 SP1
  • AN61102_Archive.zip is used with PSoC Creator 2.1 SP1/2.1

The project’s default settings may not be compatible with your device or kit, and you may need to change your project settings. For more information, see:

PSoC® 3, PSoC 4 and PSoC 5LP AN Project File Naming Convention and Use
]]>
Mon, 29 Sep 2014 04:38:38 -0600
AN73854 - PSoC<sup>®</sup> 3, PSoC 4, and PSoC 5LP Introduction to Bootloaders http://www.cypress.com/?rID=56014 AN73854 gives a brief introduction to bootloader theory and technology, and then shows how bootloaders are quickly and easily implemented in PSoC® 3, PSoC 4, and PSoC 5LP MCUs, using PSoC Creator™. Topics include bootloader system description, features, and customization.

Introduction

This application note gives an overview of bootloader fundamentals and design principles, and then shows how they are implemented for PSoC 3, PSoC 4, and PSoC 5LP in PSoC Creator projects.

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Thu, 25 Sep 2014 07:48:30 -0600
AN89611 - PSoC<sup>®</sup> 3 and PSoC 5LP – Getting Started With Chip Scale Packages (CSP) http://www.cypress.com/?rID=90919 This application note provides guidelines for using Cypress PSoC® 3 and PSoC 5LP devices in wafer-level chip scale packages (CSP). Included are instructions for using the I2C bootloader that is factory installed in these devices.

Introduction

Cypress is now offering its PSoC 3 and PSoC 5LP family of products in wafer-level chip scale packages (WLCSP, or CSP for short). These devices are designed to pack the maximum mixed-signal SoC capability per cubic millimeter. They feature package sizes as small as 4.25 × 4.98 × 0.6 mm to fit into tiny spaces on very small PCBs or flexible printed circuits (FPC). However, their small size mandates special manufacturing techniques and design considerations.

]]>
Wed, 24 Sep 2014 05:49:11 -0600
PSoC 3 CSP Bootloader http://www.cypress.com/?rID=100715 Wed, 24 Sep 2014 01:55:44 -0600 AN73503 - USB HID Bootloader for PSoC<sup>®</sup> 3 and PSoC 5LP http://www.cypress.com/?rID=57561 AN73503 describes how to implement a USB bootloader for PSoC 3 and PSoC 5LP devices by using the USB Human Interface Device (HID) class. It also shows how to build a Windows-based USB host program. A PSoC Creator project and an example host program are included.

Introduction

Bootloaders are a common part of MCU system design. A bootloader makes it possible for a product's firmware to be updated in the field. At the factory, initial programming of firmware into a product is typically done through the MCU’s Joint Test Action Group (JTAG) or Serial Wire Debugger (SWD) interface. However, these interfaces are usually not available in the field.

This is where bootloading comes in. Bootloading is a process that allows you to upgrade your system firmware over a standard communication interface such as USB or I2C. A bootloader communicates with a host to get new application code or data, and writes it into the device’s flash memory.

To get introduced to basics of PSoC 3 and PSoC 5LP Bootloader please refer  AN73854 - PSoC® 3 and PSoC 5LP - Introduction to Bootloaders. If you intend to learn how to develop I2C Bootloader for PSoC 3 and PSoC 5LP,  AN60317 - PSoC® 3/PSoC 5LP I2C Bootloader  should get you going. 

Since the projects involve the use of USB component, in case of PSoC 5LP it is mandatory to use an external 24 MHz crystal.

The Bootloader GUI provided with this App Note has been tested to work on full-fledged Windows operating system only.
The GUI is not tested and not guaranteed to work on Virtual machines.
 


Project
Device
PSoC Creator
Version
Development Kit
CY8CKIT-xxx
Compiler
Architecture
Silicon
Revision
V3.0 SP1 V2.1 SP1
/V2.1
001
DVK
030/050
DVK
003/014
FTK
Keil
GCC
RVDS
MDK

AN73503.zip

Prod
YES
NO
YES
YES*
NO
YES
N/A
N/A
N/A
Prod
YES
NO
YES
YES*
NO
N/A
YES
YES
YES
AN73503_Archive.zip
ES3, Prod
NO
YES
YES
YES*
NO
YES
N/A
N/A
N/A
ES1, Prod
NO
YES
YES
YES*
NO
N/A
YES
YES
YES

*Refer to Migrating CY8CKIT-001 DVK project to CY8CKIT 030/ 050

Notes:

  1. Click on AN77835 - PSoC® 3 to PSoC 5LP Migration Guide to learn differences between PSoC 3 and PSoC 5LP.
  2. For PSoC 5 project and related document, please download file AN73503_Archive.zip.

Projects associated with this application note can be downloaded from the ‘Related Files’ section below. For your convenience, we have provided projects that are compatible with the two most recent versions of PSoC Creator:

  • AN73503.zip is used with PSoC Creator 3.0 SP1
  • AN73503_Archive.zip is used with PSoC Creator 2.1 SP1/2.1

The project’s default settings may not be compatible with your device or kit, and you may need to change your project settings. For more information, see:

PSoC® 3, PSoC 5, and PSoC 5LP AN Project File Naming Convention and Use
]]>
Mon, 22 Sep 2014 23:32:01 -0600
AN82072 - PSoC<sup>®</sup> 3 and PSoC 5LP USB General Data Transfer with Standard HID Drivers http://www.cypress.com/?rID=70131 AN82072 discusses how to use PSoC® 3 and PSoC 5LP devices to transfer generic data across USB using native OS drivers included with Windows, Mac OS, and Linux.These drivers are part of the Human Interface Device (HID) class, which is commonly used to support devices such as mice and keyboards, but can also be used for generic data transfers.A PSoC project and a program for each operating system (with source code) demonstrating generic data transfers are included with this application note.

Notes:

  1. Click on AN77835 - PSoC® 3 to PSoC 5LP Migration Guide to learn differences between PSoC 3 and PSoC 5LP.
  2. For PSoC 5 project and related document, please download file AN82072_Archive.zip.


Project
Device
PSoC Creator
Version
Development Kit
CY8CKIT-xxx
Compiler
Architecture
Silicon
Revision
V2.1 SP1
or higher
V2.1/2.0
001
DVK
030/050
DVK
003/014
FTK
Keil
GCC
RVDS
MDK

AN82072.zip

Prod
YES
NO
YES
YES*
NO
YES
N/A
N/A
N/A
Prod
YES
NO
YES
YES*
NO
N/A
YES
YES
YES
AN82072_Archive.zip
ES3, Prod
NO
YES
YES
YES*
NO
YES
N/A
N/A
N/A
ES1, Prod
NO
YES
YES
YES*
NO
N/A
YES
YES
YES

Projects associated with this application note can be downloaded from the 'Related Files' section below. For your convenience, we have provided projects that are compatible with the two most recent versions of PSoC Creator:

  • AN82072.zip is used with PSoC Creator 2.1 SP1
  • AN82072_Archive.zip is used with PSoC Creator 2.1/2.0

The project’s default settings may not be compatible with your device or kit, and you may need to change your project settings. For more information, see:

PSoC® 3, PSoC 4 and PSoC 5LP AN Project File Naming Convention and Use
]]>
Mon, 22 Sep 2014 16:35:49 -0600
AN61290 - PSoC<sup>®</sup> 3 and PSoC 5LP Hardware Design Considerations http://www.cypress.com/?rID=43337 AN61290 reviews several topics for designing a hardware system around a PSoC® 3 or PSoC 5LP device. Subjects include power system, reset, crystal, and other pin connections, and programming and debugging interfaces. Also included are instructions on how to use the PSoC Creator™ IDE to configure the device for the hardware environment.

Introduction

PSoC® 3 and PSoC 5LP devices provide power and flexibility for analog and digital applications, beyond what traditional MCUs offer. However, this flexibility raises new considerations when designing a PSoC device into a printed circuit board (PCB).

These considerations include proper connections for device power, reset, crystal, programming, and other pins. Good board layout techniques are also important, especially for precision analog applications.

Finally, the PSoC device must be configured to work optimally in its hardware environment. The PSoC Creator™ IDE is used for this purpose.

This application note provides information on each of these topics, so that you can successfully design PSoC into a PCB and hardware environment.

]]>
Mon, 22 Sep 2014 07:55:01 -0600
PSoC<sup>®</sup> Creator™ 3.0 Service Pack 1 Components Modified Without a Version Number Change – KBA94159 http://www.cypress.com/?rID=100651 Answer: You may or may not see the results of these modifications immediately. Either way you should update to PSoC Creator 3.0 Service Pack 2, which will be released as soon as possible.

If you created a design in PSoC Creator 3.0 and then updated it to PSoC Creator 3.0 Service Pack 1, any affected components received a silent component update. This update will not be immediately obvious. In the majority of cases, the updates were limited to the underlying Clock and Pins Components. There is no impact to designs.

However, for seven components, additional underlying components were changed. Cypress will make these components obsolete in PSoC Creator 3.0 Service Pack 2 and upgrade them to new versions. The other components will receive datasheet updates to include an Errata section.

Obsolete components and components receiving a datasheet update are listed below.

Obsolete Components

The following components are obsolete and have been replaced by the applicable component version.

Table 1. New Component Version for Obsolete Components

Obsolete Component Version New Component Version
Fan Controller v3.0 Fan Controller v3.10
ILO Trim v1.0 ILO Trim v1.10
Power Monitor v1.50 Power Monitor v1.60
Resistive Touch v1.20 Resistive Touch v1.30
SPI Slave v2.40 SPI Slave v2.41
Voltage Fault Detector v2.20 Voltage Fault Detector v2.30
Voltage Sequencer v3.20 Voltage Sequencer v3.21

Components receiving a datasheet update

  • ADC_SAR v2.10
  • CapSense_CSD v3.40
  • I2C v3.30
  • ScanComp v1.0
  • SegLCD_P4 v1.0
  • StaticSegLCD v2.30
  • WaveDAC8 v2.0
  • ADC_SAR_SEQ v1.10
  • DVDAC v2.0
  • LED_Driver v1.10
  • SCCT_Comp v1.0
  • SMBusSlave v2.20
  • UART v2.30
  •  
  • ADC_SAR_SEQ_P4 v1.10
  • EMIF v1.30
  • LIN v1.30
  • SegLCD v3.40
  • SPI_Slave v2.60
  • VectorCAN v1.10
  •  
  • CAN v2.30
  • emFile v1.20
  • Mixer v2.0
  • SegLCD_P4 v1.0
  • SPI_Master v2.40
  • VoltageSequencer v3.30
  •  
]]>
Mon, 22 Sep 2014 06:09:20 -0600
PSoC<sup>®</sup> USB Mass Storage Class Support – KBA93269 http://www.cypress.com/?rID=97863 Answer: All PSoC devices that are USB capable can support the USB MSC and conform to it as a slave device. At the moment, Cypress® does not provide any working examples nor does PSoC Designer™ or PSoC Creator™ support it natively. However, it is possible to implement the MSC yourself. This functionality can be implemented by making modifications to the descriptor table in the USBFS_descr.c file. To gain an understanding of what the mass storage descriptors should look like, refer to Universal Serial Bus Mass Storage Class: Bulk-Only Transport, a document provided by the USB Implementers Forum (USB-IF).

Additionally, Use of User-Defined Descriptors in a Full Speed USB Component – KBA91688 will provide instructions on how to use user-defined descriptors.

Once the proper descriptors are implemented, the PSoC device will enumerate as a mass storage device. At that point, the bulk endpoints can be used to transfer data upstream and downstream. If you are using a PSoC 3 or PSoC 5LP device, the emFile Component could be used in conjunction with the USBFS Component, configured for mass storage, as a way to provide expanded storage capabilities.

Note that Microsoft® Windows® 2000/XP and beyond are released with built in MSC drivers. No additional drivers need to be provided by the end user. For additional information on understanding USB descriptors and bulk endpoints, refer to the following application notes or contact Cypress Technical Support.

AN57294 – USB 101: An Introduction to Universal Serial Bus 2.0

AN56377 – PSoC® 3 and PSoC 5LP USB Transfer Types

]]>
Sun, 21 Sep 2014 08:03:14 -0600
PSoC® USB Audio Class Support - KBA93271 http://www.cypress.com/?rID=98073 Answer: All PSoC 3 and PSoC 5LP devices that are USB capable support the USB Audio Class and conform to it as a slave device. Additionally, PSoC Creator™ supports the USB Audio Class by default. The potential applications for USB audio are quite large and at the moment, Cypress provides a limited number of example projects for reference. Two of the available example projects are included with PSoC Creator: USB_MIDI and USB_AUDIO. These projects can be obtained using the Find Example Project window, accessed via either the PSoC Creator Tool Bar (File > Example Project) or the PSoC Creator Start Page. Figure 1 shows the available USB audio projects that can be found using the USBFS keyword.

Figure 1. Find Example Project Window

Additionally, PSoC 4 Pioneer Kit Community Project#102 – USB Audio using the PSoC 5LP is a more advanced example project that can be found at the Element14 community forum, developed by Cypress, and is targeted towards PSoC 5LP devices. This project builds upon the basics by including information on using an I2S interface and a pulse density modulation (PDM) microphone.

These three examples should provide the fundamental framework needed to develop a broad range of audio applications using isochronous (ISO) endpoints. In conjunction with these examples, you can use information provided in the Universal Serial Bus Device Class Definition for Audio Devices, provided by the USB Implementers Forum (USB-IF), to develop additional audio applications.

Note that Microsoft® Windows® 2000/XP and beyond are released with built in Audio Class Drivers. No additional drivers need to be provided by the end user. For additional information on USB descriptors and ISO endpoints, refer to the following application notes or contact Cypress Technical Support.

AN57294 - USB 101: An Introduction to Universal Serial Bus 2.0
AN56377 - PSoC® 3 and PSoC 5LP USB Transfer Types

]]>
Sun, 21 Sep 2014 08:01:09 -0600
Placing a Function or a Variable at an Absolute Location in SRAM or in Flash of PSoC<sup>®</sup> 3, PSoC 4, and PSoC 5LP, with the Keil, GCC, and MDK Compilers – KBA84773 http://www.cypress.com/?rID=57109 .padL { padding-left:75px; font-family:Courier New; } .codcol { color:#999999; } .colred { color: #FF0000; font-family:Courier New; } .sps { padding-top:10px; padding-bottom:10px; }

Answer:

To place a variable in an absolute location of SRAM in PSoC 3 (Keil compiler), please follow these steps:

Automatic (local) and global variables can be located at absolute memory locations in your C code by using the _at_ keyword. The usage for this feature is:

type variable_name _at_ constant;

where:

memory_type is the memory type, e.g., idata or xdata. If excluded, the default memory type is used.
type is the variable type, e.g., uint8.
variable_name is the variable name.
constant is the address where the variable is to be located.

The following example places an integer variable in xdata (the default) at location 0x1000.

int myVariable _at_ 0x1000;

To place a constant in flash at any address in PSoC 3 (Keil Compiler), please follow these steps:

Local or global constant variables may be located at flash memory locations in your C code using the CYCODE or const keyword. The usage for this feature is:

CYCODE = constant_value;

or

const = constant_value

where

is the variable type
is the variable name.
is the constant value to be stored in the variable .

The following example places integer variable “myVariable” with a constant value of 1000 in Flash.

CYCODE int myVariable = 1000;

PSoC Creator also provides a convenient macro CY_NOINIT, which places a variable in the .noinit section. This section is used for variables that are not initialized.

For e.g., the following code places the variable foo in the .noinit section:

uint8 foo CY_NOINIT;

Following features are not possible with PSoC 3 Keil compiler:

  • Constant in an absolute location of Flash
  • Initializing the variable placed in an absolute location of SRAM or Flash
  • Function in an absolute location of Flash
  • Function in an absolute location of SRAM
  • Function in SRAM (any address)

Please refer to AN89610 - PSoC® 4 and PSoC 5LP ARM Cortex Code Optimization to understand how this can be done for PSoC 4 or PSoC 5LP with the GCC or MDK compiler.

]]>
Fri, 19 Sep 2014 08:51:28 -0600
AN60321 - Peak Detection with PSoC<sup>®</sup> 3 and PSoC 5LP http://www.cypress.com/?rID=41001 Several of the peak detector designs described in the application note have been encapsulated as PSoC Creator™ components for easy reuse.

The following table indicates the PSoC devices, PSoC Creator versions, compilers, and development kits that will work with this application note project:


Project
Device
PSoC Creator
Version
Development Kit
CY8CKIT-xxx
Compiler
Architecture
Silicon
Revision
V3.0 SP1
or higher
V2.1/2.0
001
DVK
030/050
DVK
003/014
FTK
Keil
GCC
RVDS
MDK

AN60321.zip

Prod
YES
NO
YES
YES*
NO
YES
N/A
N/A
N/A
Prod
YES
NO
YES
YES*
NO
N/A
YES
YES
YES
AN60321_Archive.zip
ES2, ES3, Prod
NO
YES
YES
YES*
NO
YES
N/A
N/A
N/A
ES1, Prod
NO
YES
YES
YES*
NO
N/A
YES
YES
YES

*Refer to Migrating CY8CKIT-001 DVK project to CY8CKIT 030/ 050

Notes:

  1. Click on AN77835 - PSoC® 3 to PSoC 5LP Migration Guide to learn differences between PSoC 3 and PSoC 5LP.
  2. For PSoC 5 project and related document, please download file AN60321_Archive.zip.

Projects associated with this application note can be downloaded from the ‘Related Files’ section below. For your convenience, we have provided projects that are compatible with the two most recent versions of PSoC Creator:

  • AN60321.zip is used with PSoC Creator 3.0 SP1
  • AN60321_Archive.zip is used with PSoC Creator 2.1/2.0

The project’s default settings may not be compatible with your device or kit, and you may need to change your project settings. For more information, see:

PSoC® 3, PSoC 4 and PSoC 5LP AN Project File Naming Convention and Use
]]>
Fri, 19 Sep 2014 04:38:18 -0600
AN57821 - PSoC<sup>®</sup> 3, PSoC 4, and PSoC 5LP Mixed Signal Circuit Board Layout Considerations http://www.cypress.com/?rID=39677 AN57821 introduces basic PCB layout practices to achieve 12- to 20-bit performance for the PSoC® 3, PSoC 4, and PSoC 5LP family of devices. The design practices covered in this application note are good rules to use in any mixed signal design for any accuracy.

The following video introduces the designer to shared return paths and how to avoid them when designing a circuit board.

 

Note:

  1. Click on AN77835 - PSoC® 3 to PSoC 5LP Migration Guide to learn differences between PSoC 3 and PSoC 5LP.
]]>
Fri, 19 Sep 2014 03:59:17 -0600
AN56377 - PSoC<sup>®</sup> 3 and PSoC 5LP - Introduction to Implementing USB Data Transfers http://www.cypress.com/?rID=39553 AN56377 describes the four USB transfer types: Interrupt, Bulk, Isochronous, and Control. It then shows how to configure PSoC® 3 and PSoC 5LP to perform each of these transfers. Code examples are also included for specific considerations, including vendor commands for custom USB functionality, and to use DMA for faster data throughput. This application note assumes a basic-level knowledge of USB and is intended as an initial hands-on introduction to USB on PSoC 3 and PSoC 5LP. For a general introduction to USB, see AN57294.

Below are some of videos demonstrating  how to impliment bulk transfers and vendor commands which are discussed in this application note.

 

 

 

The following table indicates the PSoC devices, PSoC Creator versions, compilers, and development kits that will work with this application note project:


Project
Device
PSoC Creator
Version
Development Kit
CY8CKIT-xxx
Compiler
Architecture
Silicon
Revision
V2.1 SP1
or higher
V2.1
/ V2.0
001
DVK
030/050
DVK
003/014
FTK
Keil
GCC
RVDS
MDK

AN56377.zip

Prod
YES
NO
YES
YES*
NO
YES
N/A
N/A
N/A
Prod
YES
NO
YES
YES*
NO
N/A
YES
YES
YES
AN56377_Archive.zip
ES2,ES3, Prod
NO
YES
YES
YES*
NO
YES
N/A
N/A
N/A
ES1, Prod
NO
YES
YES
YES*
NO
N/A
YES
YES
YES

*Refer to Migrating CY8CKIT-001 DVK project to CY8CKIT 030/ 050

Notes:

  1. For PSoC 5 project and related document, please download file AN56377_Archive.zip.

Projects associated with this application note can be downloaded from the ‘Related Files’ section below. For your convenience, we have provided projects that are compatible with the two most recent versions of PSoC Creator:

  • AN56377.zip is used with PSoC Creator 3.0 SP1 and 2.1 SP1
  • AN56377_Archive.zip is used with PSoC Creator 2.1 /2.0

The project’s default settings may not be compatible with your device or kit, and you may need to change your project settings. For more information, see:
PSoC® 3, PSoC 4 and PSoC 5LP AN Project File Naming Convention and Use

]]>
Fri, 19 Sep 2014 03:57:23 -0600
AN78175 - PSoC<sup>®</sup> 3 and PSoC 5LP - IEC 60730 Class B Safety Software Library http://www.cypress.com/?rID=61356 Library routines and examples in the example project can be directly integrated with the end user?s application. This application note also describes the API functions that are available in the Library.

The International Electrotechnical Commission (IEC) has developed safety standard IEC 60730-1 that discusses mechanical, electrical, electronic, environmental endurance, EMC, and abnormal operation for home appliances.

This application note focuses on Annex H Class B: Requirements for Electronic Controls. This portion of the standard details test and diagnostic methods to ensure safe operation of embedded control hardware and software for home appliances.  


Project
Device
PSoC Creator
Version
Development Kit
CY8CKIT-xxx
Compiler
Architecture
Silicon
Revision
V2.2 SP1
or higher
V2.1 SP1/
V2.1
001
DVK
030/050
DVK
003/014
FTK
Keil
GCC
RVDS
MDK

AN78175.zip

Prod
YES
NO
YES
YES*
NO
YES
N/A
N/A
N/A
Prod
YES
NO
YES
YES*
NO
N/A
YES
YES
YES
AN78175_Archive.zip
ES3, Prod
NO
YES
YES
YES*
NO
YES
N/A
N/A
N/A
ES1, Prod
NO
YES
YES
YES*
NO
N/A
YES
YES
YES

*Refer to Migrating CY8CKIT-001 DVK project to CY8CKIT 030/ 050

Notes:
  1. Click on AN77835 - PSoC® 3 to PSoC 5LP Migration Guide to learn differences between PSoC 3 and PSoC 5LP.
  2. For PSoC 5 project and related document, please download file AN78175_Archive.zip.

Projects associated with this application note can be downloaded from the 'Related Files' section below. For your convenience, we have provided projects that are compatible with the two most recent versions of PSoC Creator:

  • AN78175.zip is used with PSoC Creator 2.2 SP1
  • AN78175_Archive.zip is used with PSoC Creator 2.1 SP1/2.1

The project’s default settings may not be compatible with your device or kit, and you may need to change your project settings. For more information, see:

PSoC® 3, PSoC 4 and PSoC 5LP AN Project File Naming Convention and Use
]]>
Thu, 18 Sep 2014 03:57:20 -0600
AN60594 - PSoC<sup>®</sup> 3 and PSoC 5LP: Low-Frequency FSK Modulation and Demodulation http://www.cypress.com/?rID=40985 The method described in this application note uses zero CPU, everything done in PSoC hardware. This application note covers only the physical layer implementation of an FSK transmitter and receiver; higher-level encoding techniques and physical modem connections are not discussed.

The following table provides the list of devices, the supported Creator version, Development kit and Compiler for this application note project:
 


Project
Device
PSoC Creator
Version
Development Kit
CY8CKIT-xxx
Compiler
Architecture
Silicon
Revision
V3.0 CP7
or greater
V2.2 SP1
V2.1
001
DVK
030/050
DVK
003/014
FTK
Keil
GCC
RVDS
MDK

AN60594.zip

Prod
YES
NO
NO
YES
YES*
NO
YES
N/A
N/A
N/A
Prod
YES
NO
NO
YES
YES*
NO
N/A
YES
YES
YES
AN60594_Archive.zip
ES3, Prod
NO
YES
YES
YES
YES*
NO
YES
N/A
N/A
N/A
ES1, Prod
NO
YES
YES
YES
YES*
NO
N/A
YES
YES
YES

 *Refer to Migrating CY8CKIT-001 DVK project to CY8CKIT 030/ 050

Notes:
  1. For PSoC 5 project and related document, please download file AN60594_Archive.zip.

Projects associated with this application note can be downloaded from the 'Related Files' section below. For your convenience, we have provided projects that are compatible with the two most recent versions of PSoC Creator:

  • AN60594.zip is used with PSoC Creator 3.0 CP7
  • AN60594_Archive.zip is used with PSoC Creator 2.1 SP1/2.1

The project’s default settings may not be compatible with your device or kit, and you may need to change your project settings. For more information, see:

PSoC® 3, PSoC 5, and PSoC 5LP AN Project File Naming Convention and Use
]]>
Thu, 18 Sep 2014 03:12:15 -0600
AN66477 - PSoC® 3, PSoC 4, and PSoC 5LP - Temperature Measurement with a Thermistor http://www.cypress.com/?rID=49052 This application note is temporarily unavailable

The document AN66477 - PSoC® 3 and PSoC 5 Temperature Measurement with Thermistor is currently being reviewed and updated to support the new Thermistor Component available in PSoC Creator 2.1. The updated application note is expected by 11/30/2012. The below abstract describes what this application note covers. If you have an immediate need for this document, please click here to create a technical support case requesting this material.

-->

Please note that the Thermistor Component is now provided in PSoC Creator 2.1. Please access the Thermistor Component Datasheet for features and configuration details.

AN66477 Abstract:

AN66477 explains how to measure temperature with a thermistor using PSoC® 3, PSoC 4, or PSoC 5LP. This application note describes the PSoC Creator™ Thermistor Calculator Component, which simplifies the math-intensive resistance-to-temperature conversion. In addition, we discuss several PSoC Creator thermistor measurement projects.

The following table provides the list of devices, the supported Creator version, Development kit and Compiler for this application note project:


Project
Device
PSoC Creator
Version
Development Kit
CY8CKIT-xxx
Compiler
Architecture
Silicon
Revision
V2.1 SP1
or higher
 V2.1
V2.0
001
DVK
030/050
DVK
003/014
FTK
Keil
GCC
RVDS
MDK

AN66477.zip

Prod
YES
NO
NO
YES
YES*
NO
YES
N/A
N/A
N/A
Prod
YES
NO
NO
YES
YES*
NO
N/A
YES
YES
YES
AN66477_Archive.zip
ES3, Prod
NO
YES
YES
YES
YES*
NO
YES
N/A
N/A
N/A
ES1, Prod
NO
YES
YES
YES
YES*
NO
N/A
YES
YES
YES


*Refer to Migrating CY8CKIT-001 DVK project to CY8CKIT 030/ 050.

Notes:

  1. Click on AN77835 - PSoC® 3 to PSoC 5LP Migration Guide to learn differences between PSoC 3 and PSoC 5LP.
]]>
Thu, 18 Sep 2014 03:04:06 -0600
AN57294 - USB 101: An Introduction to Universal Serial Bus 2.0 http://www.cypress.com/?rID=39327 AN57294 is a foundation for understanding the USB protocol, specifically focusing on the USB 2.0 specification. It is intended for those who are new to using USB in embedded designs, and for those who need to use and understand more advanced Cypress application notes.

Introduction

USB is an interface that connects a device to a computer. With this connection, the computer sends or retrieves data from the device. USB gives developers a standard interface to use in many different types of applications. A USB device is easy to connect and use because of a systematic design process.

]]>
Tue, 16 Sep 2014 05:38:13 -0600
Trim and Margin Component Errata - KBA93070 http://www.cypress.com/?rID=100159 Answer: Yes, there is one known issue that applies to version 1.30 and earlier of the Trim and Margin Component.

Problem Statement: The Trim and Margin Component conforms to a specific model when calculating the duty cycles required to achieve desired voltage targets. That model is appropriate for the linear regulator as configured in the Cypress™ CY8CKIT-036 development kit, but is not appropriate for some other configurations or for switching power supplies. As a result, using a converter that deviates from this model can result in voltage overshoot or undershoot when margining.

Workaround: Review the power regulators in the system against the configuration expected by this Component. Should regulators in the system use a different model, contact Cypress Technical Support for assistance on adapting the Component model to the system design.

]]>
Thu, 11 Sep 2014 23:53:50 -0600
Voltage Fault Detector Component Errata - KBA93069 http://www.cypress.com/?rID=100198 Answer: Yes, there are three known issues that apply to version 2.20 and earlier of the Voltage Fault Detector Component.

Issue #1

Problem Statement: The control logic responsible for selecting input voltages and configuring the over voltage (OV) and under voltage (UV) thresholds can become out of synchronization when the Component is paused and then resumed. This applies for both the usage of the VFD_Pause() and VFD_Resume() functions as well as changing the value provided on the EN terminal of the Component.

Workaround: Once the Component is started, do not disable with the EN pin or pause with the VFD_Pause() function.

Issue #2

Problem Statement: Fault status of the Voltage Fault Detector is determined by reading a power good (PGOOD) and OV status register. The bits in the OV status register are sticky and the software APIs responsible for returning fault status incorrectly clear the sticky bits. This can cause an issue to manifest in one of two scenarios:

  • If a UV fault occurs on a rail that was preceded by an OV fault, the GetOVUVFaultStatus() function may incorrectly report an OV fault and fail to report the UV fault.
  • When using the GetOVUVFaultStatus() or GetOVFaultStatus() API, the fault data returned may contain stale fault data, indicating an OV fault for a rail that did not experience that fault condition.

Workaround: When checking the fault status using the GetOVUVFaultStatus() or GetOVFaultStatus() API, call the respective function twice and use the result returned by the second function call.

Issue #3:

Problem Statement: The General tab in the Voltage Fault Detector customizer displays a fault response time next to the Glitch Filter Length selection. The time calculated only includes the delay associated with the glitch filter and does not include the delay for the final scan that will detect the fault.

Workaround: To more accurately determine the Fault Response Time. Take the number provided in the customizer and add one additional cycle period to that value.

]]>
Thu, 11 Sep 2014 01:01:13 -0600
Terminal Reserve http://www.cypress.com/?rID=56767 Features

  • Prevents an analog router from using an analog block terminal routing resource
  • Allows safe firmware access to an analog block terminal routing resource
Symbol Diagram

General Description

The Terminal Reserve component reserves the analog routing resource connected to a component, such as the analog wire connected to a comparator or pin. This is an advanced feature that is not needed for most designs, and should be used with caution.

]]>
Mon, 08 Sep 2014 23:29:33 -0600
AN84401 - PSoC® 3 and PSoC 5LP SPI Bootloader http://www.cypress.com/?rID=78703 AN84401 describes a SPI-based bootloader for PSoC® 3 and PSoC 5LP. In this application note you will learn how to use PSoC Creator™ to quickly and easily build SPI-based bootloader and bootloadable projects. It also shows how to build a SPI-based embedded bootloader host program.

Introduction

Bootloading is a process that allows you to upgrade your system firmware over a standard communication interface such as USB, I2C, UART or SPI. A bootloader communicates with a host to get new application code or data, and writes it into the device's flash memory.

This application note describes a SPI based bootloader for PSoC 3 and PSoC 5LP. To get introduced to basics of PSoC 3 and PSoC 5LP Bootloader please refer AN73854 - PSoC® 3 and PSoC 5LP - Introduction to Bootloaders. If you intend to learn how to develop USB and I2C Bootloader for PSoC 3 and PSoC 5LP, AN73503 - USB HID Bootloader for PSoC® 3 and PSoC 5LP and AN60317 – PSoC 3 and PSoC 5LP I2C Bootloader  respectively should get you going.

The following table indicates the PSoC devices, PSoC Creator versions, compilers, and development kits that will work with this application note project:


Project
Device
PSoC Creator
Version
Development Kit
CY8CKIT-xxx
Compiler
Architecture
Silicon
Revision
V3.0 SP1
or higher
V2.1 SP1
001
DVK
030/050
DVK
003/014
FTK
Keil
GCC
RVDS
MDK

AN84401.zip

Prod
YES
NO
YES*
YES
NO
YES
N/A
N/A
N/A
Prod
YES
NO
YES*
YES
NO
N/A
YES
YES
YES

*Refer to Migrating CY8CKIT-001 DVK project to CY8CKIT 030/ 050

Projects associated with this application note can be downloaded from the 'Related Files' section below.

]]>
Wed, 03 Sep 2014 11:28:13 -0600
CY8CKIT-033A PSoC® 3 MFi (Made for iPod® | iPhone® | iPad®) Digital Audio Development Kit for Lightning™ http://www.cypress.com/?rID=67222
 

Cypress’s CY8CKIT-033A PSoC 3 MFi Digital Audio Development Kit for Lightning is the most comprehensive and proven development and reference design platform for bit-perfect consumer audio (speaker docks, FM transmitters, headphones, game controllers) and music creation (pianos/keyboards, guitars, drums, synthesizers, mixers, DJ turntables, microphones, USB audio and MIDI interfaces) accessory products that connect to Apple’s iPod, iPhone and iPad devices, like Sonoma Wire Works’ GuitarJack, TASCAM’s iM2, iM2X and iXJ2 microphones, and many others.

The kit includes license-free reference hardware and firmware that comes very close to a finished product, and is your quickest path to turn your MFi Lightning Digital Audio products from concept to production.

In addition, utilize Cypress’s EA Console iOS app to jump-start development with the External Accessory framework, enabling communication between apps and accessories attached to an Apple iOS device. Also, the CY8CKIT-033A PSoC 3 MFi Digital Audio Development Kit for Lightning works with any Core Audio or Core MIDI compatible iOS apps, like Apple’s GarageBand.

The CY8CKIT-033A PSoC 3 MFi Digital Audio Development Kit for Lightning is available only to licensees of Apple's MFi program, through Apple’s authorized MFi component distributor.

For more information on the MFi program, visit http://developer.apple.com/MFi.

Contact MFi@cypress.com to discuss your MFi Lightning Digital Audio needs.

Features
  • Made for iPod, iPhone and iPad
  • Compatible with Lightning and/or 30-pin dock connector
  • Compliant to Apple’s latest MFi Accessory Interface Specification
  • Mac/PC connectivity via USB
  • Self-powered, Apple-device-powered or USB-bus-powered
  • Best-in-class USB Audio active power consumption
  • USB audio streaming input and output, with patent-pending, bit-perfect USB audio clock synchronization and recovery scheme
  • 16-/24-bit audio, 44.1/48 (and up to 96) kHz sampling rate
  • USB MIDI input and output
  • Compatible with Core Audio and Core MIDI compliant applications
  • External Accessory framework for app ↔ accessory communication and interaction
  • CapSense buttons and slider (e.g., audio playback and MIDI controls)
  • Integrated over-current protection for iPad charging
  • Multiple bootloader options (MFi, USB, etc) for seamless firmware upgrades
  • Compatible with Android (USB MIDI, limited USB Audio)
  • Expansion header for prototyping and development purposes
  • Component/Composite video output
  • Multichannel Audio ready with multiple I2S interfaces
  • MEMS Microphone interface (PDM, I2S, Analog) ready
Kit Contents
Software Prerequisites
Software Title Description Link
PSoC Creator This kit requires PSoC Creator for development
PSoC Programmer This kit requires PSoC Programmer for programming

Apple, iPod, iPhone and iPad are trademarks of Apple Inc., registered in the U.S. and other countries. Lightning is a trademark of Apple Inc.

]]>
Sun, 31 Aug 2014 09:00:24 -0600
AN76474 - PSoC&reg; 3 Power Supervisor http://www.cypress.com/?rID=66896 AN76474 demonstrates how you can quickly implement and customize a full-featured power supervisor that supports up to 13 power supply rails with Cypress’s PSoC® 3.

Introduction

Power supervision plays a critical role in modern communications systems such as routers, switches, storage systems, servers and base stations. These systems require multiple power supply rails for their various components including ASICs, PHY devices, FPGAs, CPUs, memory modules, and peripheral I/O devices.

]]>
Fri, 22 Aug 2014 00:18:25 -0600
"mkdepend.exe Has Stopped Working" Error While Building a Project in PSoC<sup>®</sup> Creator™ – KBA93735 http://www.cypress.com/?rID=99231 Answer: The "mkdepend.exe has stopped working" error in PSoC Creator is likely caused by a compatibility issue between certain software products and the Microsoft® .NET Framework. The incompatible products include Citrix® Offline Plug-in and Citrix Virtual Memory Optimization Service. To resolve the issue, disable or remove the incompatible products and then run the following command from the Command Prompt (Administrator privileges required):

%windir%\Microsoft.NET\Framework\v2.0.50727\ngen.exe update /force

The following articles contain additional information about the problem:

Memory Optimizing Tools That Rebase DLL Load Addresses Cause .NET Applications to Crash with FatalExecutionEngineException

Citrix Virtual Memory Optimization Service can lead to .NET application corruption

]]>
Thu, 21 Aug 2014 04:53:35 -0600
Learning Embedded C – KBA93302 http://www.cypress.com/?rID=99224 Answer: There are several ways to get started with learning Embedded C programming.

Online compilers (for beginners):

For a quick on-line reference, see Wikipedia http://en.wikipedia.org/wiki/C_syntax.

Links for Books and other resources:

C Courses organized by universities:

  • Many universities, community colleges, and training organizations have live C courses; some even have C/embedded programming classes. For example, Embedded Software Bootcamp from the Barr Group.

Hands on with PSoC® Creator™:

If you want to try an embedded project, you can use one of the example projects available with PSoC Creator. Most of the PSoC Creator Components have an example project to go with them. Follow these steps to try an example project:

  1. Open PSoC Creator
  2. Click File > Example Project
  3. Select the example project from the list to get started, as shown in Figure 1.

    Figure 1. Find Example Project

]]>
Thu, 21 Aug 2014 04:22:43 -0600
IBIS - CY8C36 FAMILY http://www.cypress.com/?rID=88169 Mon, 18 Aug 2014 03:00:16 -0600 IBIS - CY8C38 FAMILY http://www.cypress.com/?rID=88170 Mon, 18 Aug 2014 03:00:16 -0600 IBIS - CY8C34 FAMILY http://www.cypress.com/?rID=88168 Mon, 18 Aug 2014 03:00:15 -0600 QTP 101208: 48-LEAD SSOP, KEG3000 M/C, NIPDAU, MSL3, 260C REFLOW CML-RA http://www.cypress.com/?rID=60326 Thu, 14 Aug 2014 03:00:14 -0600 QTP 102610: 48-Lead QFN (7x7x1.0 mm) NiPdAu, MSL3, 260°C Reflow CML-RA http://www.cypress.com/?rID=60324 Thu, 14 Aug 2014 03:00:13 -0600 AN54181 - Getting Started with PSoC<sup>®</sup> 3 http://www.cypress.com/?rID=39157 AN54181 briefly introduces you to PSoC® 3, an 8051-based programmable system-on-chip. In this application note, you will learn about the PSoC 3 architecture and how the 8051-based MCU subsystem works closely with PSoC's programmable digital and analog fabric. You will also learn how to use Cypress's powerful design tools to start your first PSoC project, utilizing PSoC 3's hardware and software programmability.

Introduction

PSoC 3 is a true programmable embedded system-onchip, integrating custom analog and digital peripheral functions, memory, and an 8051 microcontroller on a single chip.

PSoC contains a processor, but it is not an MCU. The name PSoC (Programmable-System-on-Chip) defines its true identity. AN54181 introduces the Programmable-System-on-Chip concept with specific emphasis on PSoC 3. Here, you learn about PSoC 3 and what it can do for you and your projects. It also introduces PSoC Creator™, a powerful IDE development tool for PSoC 3 and PSoC 5LP.The following video gives brief introduction for PSoC3:

 

The following video guides how to create projects using PSoC3:

 

 

The following table indicates the PSoC devices, PSoC Creator versions, compilers, and development kits that will work with this application note project:


Project
Device
PSoC Creator
Version
Development Kit
CY8CKIT-xxx
Compiler
Architecture
Silicon
Revision
V3.0 SP1
or higher
V2.1 SP1/
2.1
001
DVK
030/050
DVK
003/014
FTK
Keil
GCC
RVDS
MDK

AN54181.zip

Prod
YES
NO
YES
YES*
NO
YES
N/A
N/A
N/A
Prod
YES
NO
YES
YES*
NO
N/A
YES
YES
YES
AN54181_Archive.zip
ES3, Prod
NO
YES
YES
YES*
YES
YES
N/A
N/A
N/A

*Refer to Migrating CY8CKIT-001 DVK project to CY8CKIT 030/050

Notes:
  1. Click on AN77835 - PSoC® 3 to PSoC 5LP Migration Guide to learn differences between PSoC 3 and PSoC 5LP.
  2. For PSoC 5 project and related document, please download file AN54181_Archive.zip.

Projects associated with this application note can be downloaded from the ‘Related Files’ section below. For your convenience, we have provided projects that are compatible with the two most recent versions of PSoC Creator:

  • AN54181.zip is used with PSoC Creator 3.0 SP1
  • AN54181_Archive.zip is used with PSoC Creator 2.1 SP1/2.1.

The project’s default settings may not be compatible with your device or kit, and you may need to change your project settings. For more information, see:

PSoC® 3, PSoC 4 and PSoC 5LP AN Project File Naming Convention and Use
]]>
Wed, 13 Aug 2014 08:17:20 -0600
Pins v2.0 Pulled-Up and Pulled-Down POR Settings Show a Glitch at Power Up - KBA93531 http://www.cypress.com/?rID=98709 Answer: The glitch appears in Pins v2.0 for PSoC 3 and PSoC 5LP due to a firmware bug that switches the Power-On Reset settings for Pulled-Up and Pulled-Down modes. The Component is not affected if it is set as Don't Care or High-Z Analog. If you wish to use the Pulled-Up or Pulled-Down POR settings, then choose one of the following workaround options:

  • The preferred workaround is to downgrade to the Pins v1.90 Component in the design. This will allow you to configure the Power-On Reset state to Pulled-Up or Pulled-Down without any issues.
  • If you want to use Pins v2.0 in PSoC 3 and PSoC 5LP designs, then there are two options:
    • Leave the Power-On Reset configuration as Don't Care, which is a high-impedance state, and use external pull-up or pull-down resistors.
    • Flip the POR settings for Pulled-Up and Pulled-Down (i.e., select pull-up if you want pull-down, or vice-versa). However, if you upgrade to the Pins v2.10 Component, then you must undo this change.
]]>
Wed, 13 Aug 2014 00:23:51 -0600
AN60317 - PSoC<sup>®</sup> 3 and PSoC 5LP I<sup>2</sup>C Bootloader http://www.cypress.com/?rID=41002 Beginning with PSoC Creator 2.1, the bootloader system has been reorganized to provide more configuration options. In previous releases, the bootloader system was part of the cy_boot component (a required component that is automatically and invisibly instantiated in all designs). From PSoC Creator 2.1 onwards the bootloader component is separated from cy_boot component and is available as a separate component in component catalogue. Please refer ‘Chapter11.Bootloader Migration’ in System Reference Guide (Help>Documentation>System Reference) to know how to migrate your older versions of bootloader/bootloadable projects to PSoC Creator 2.1.

AN60317 describes how to add an I2C bootloader to a PSoC® 3 / PSoC 5LP project. It also discusses how to use the PC based bootloader host program provided with PSoC Creator. Finally the application note illustrates how to create your own embedded bootloader host. Each of these is explained with examples.

To learn about PSoC 3 and PSoC5 Bootloader implementation refer to video: PSoC3, PSoC5, PSoC Creator Bootloader Overview

The following video describes the steps to add an I2C Bootloader to PSoC3 or PSoC5 projects.

-->

AN60317 describes an I2C-based bootloader for PSoC® 3 and PSoC 5LP. In this application note you will learn how to use PSoC Creator™ to quickly and easily build an I2C-based bootloader project, and bootloadable projects. It also shows how to build an I2C-based embedded bootloader host program.

Bootloading is a process that allows you to upgrade your system firmware over a standard communication interface such as USB, I2C, UART or SPI. A bootloader communicates with a host to get new application code or data, and writes it into the device's flash memory.

This application note describes an I2C based bootloader for PSoC 3 and PSoC 5LP. To get introduced to basics of PSoC 3 and PSoC 5LP Bootloader please refer AN73854 - PSoC® 3 and PSoC 5LP - Introduction to Bootloaders. If you intend to learn how to develop USB Bootloader for PSoC 3 and PSoC 5LP, AN73503 - USB HID Bootloader for PSoC® 3 and PSoC 5LP should get you going.

The following table indicates the PSoC devices, PSoC Creator versions, compilers, and development kits that will work with this application note project:


Project
Device
PSoC Creator
Version
Development Kit
CY8CKIT-xxx
Compiler
Architecture
Silicon
Revision
V3.0 SP1
or higher
V2.2
001
DVK
030/050
DVK
003/014
FTK
Keil
GCC
RVDS
MDK

AN60317.zip

Prod
YES
NO
YES*
YES
NO
YES
N/A
N/A
N/A
Prod
YES
NO
YES*
YES
NO
N/A
YES
YES
YES
AN60317_Archive.zip
Prod
NO
YES
YES*
YES
NO
YES
N/A
N/A
N/A
Prod
NO
YES
YES*
YES
NO
N/A
YES
YES
YES

*Refer to Migrating CY8CKIT-001 DVK project to CY8CKIT 030/ 050

Notes:
  1. For PSoC 5 project and related document, please download file AN60317_Archive.zip.

Projects associated with this application note can be downloaded from the ‘Related Files’ section below. For your convenience, we have provided projects that are compatible with the two most recent versions of PSoC Creator:

  • AN60317.zip is used with PSoC Creator 3.0 SP1
  • AN60317_Archive.zip is used with PSoC Creator 2.2

The project’s default settings may not be compatible with your device or kit, and you may need to change your project settings. For more information, see:

PSoC® 3, PSoC 4 and PSoC 5LP AN Project File Naming Convention and Use
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Fri, 01 Aug 2014 06:00:34 -0600
AN68272 - PSoC<sup>®</sup> 3, PSoC 4 and PSoC 5LP UART Bootloader http://www.cypress.com/?rID=50230

AN68272 describes a UART-based bootloader for PSoC® 3, PSoC 4 and PSoC 5LP. In this application note you will learn how to use PSoC Creator™ to quickly and easily build a UART-based bootloader project, and bootloadable projects. It also shows how to build a UART-based embedded bootloader host program.

Introduction

Bootloaders are a common part of MCU system design. A bootloader makes it possible for a product's firmware to be updated in the field. At the factory, initial programming of firmware into a product is typically done through the MCU's Joint Test Action Group (JTAG) or the ARM Serial Wire Debugger (SWD) interface. However, these interfaces are usually not accessible in the field.

This is where bootloading comes in. Bootloading is a process that allows you to upgrade your system firmware over a standard communication interface such as USB, I2C, UART or SPI. A bootloader communicates with a host to get new application code or data, and writes it into the device's flash memory.

 


The following table indicates the PSoC devices, PSoC Creator versions, compilers, and development kits that will work with this application note project:

Project Device PSoC Creator
Version
Development Kit
CY8CKIT-xxx
Architecture Silicon
Revision
V3.0 SP1
or higher
V2.2 SP1 001
DVK
030/050
DVK
042 Pioneer DVK
AN68272.zip PSoC3 Prod YES NO YES YES* N/A
PSoC4 Prod YES NO YES N/A YES**
PSoC5LP Prod YES NO YES YES* N/A
AN68272_Archive.zip PSoC3 Prod NO YES YES YES* N/A
PSoC5 Prod NO YES YES YES* N/A

* Refer to Migrating CY8CKIT-001 DVK project to CY8CKIT 030/ 050.
** The project can be easily adapted to this DVK.

Notes:
  1. For PSoC 5 project and related document, please download file AN68272_Archive.zip.

Projects associated with this application note can be downloaded from the ‘Related Files’ section below. For your convenience, we have provided projects that are compatible with the two most recent versions of PSoC Creator: 

  • AN68272.zip is used with PSoC Creator 3.0 SP1
  • AN68272_Archive.zip is used with PSoC Creator 2.2 SP1

The project’s default settings may not be compatible with your device or kit, and you may need to change your project settings. For more information, see:

PSoC® 3, PSoC 4 and PSoC 5LP AN Project File Naming Convention and Use
]]>
Fri, 01 Aug 2014 04:31:50 -0600
AN82156 - PSoC® 3, PSoC 4, and PSoC 5LP - Designing PSoC Creator™ Components with UDB Datapaths http://www.cypress.com/?rID=69774

Introduction

AN82156 explains how to design PSoC Creator Components that use PSoC 3, PSoC 4, and PSoC 5LP Universal
Digital Block (UDB) datapaths. Datapath-based Components can implement common functions such as counters,
PWMs, Shifters, UARTs, SPI, etc. They can also be used to create custom digital peripherals, and to perform data
management tasks to offload the CPU. The use of the PSoC Creator UDB Editor Tool to create, view, and modify
datapath instances is described.
 

Notes:

  1. Click on AN77835 - PSoC® 3 to PSoC 5LP Migration Guide to learn differences between PSoC 3 and PSoC 5LP.
  2. For PSoC 5 project and related document, please download file AN82156_Archive.zip.

Project Device PSoC Creator
Version
Development Kit
CY8CKIT-xxx
Architecture Silicon
Revision
V3.0 SP1
or higher
V2.2 SP1
/2.1
001
DVK
030/050
DVK
042 Pioneer DVK
AN82156.zip PSoC3 Prod YES NO YES YES* N/A
PSoC4 Prod YES NO YES N/A YES**
PSoC5LP Prod YES NO YES YES* N/A
AN82156_Archive.zip PSoC3 ES2, ES3, Prod NO YES YES YES* N/A
PSoC5 ES1, Prod NO YES YES YES* N/A

* Refer to Migrating CY8CKIT-001 DVK project to CY8CKIT 030/ 050.
** The project can be easily adapted to this DVK.

Projects associated with this application note can be downloaded from the 'Related Files' section below. For your convenience, we have provided projects that are compatible with the two most recent versions of PSoC Creator:

  • AN82156.zip is used with PSoC Creator 3.0 SP1 and 2.2 SP1
  • AN82156_Archive.zip is used with PSoC Creator 2.1 SP1/2.1

The project’s default settings may not be compatible with your device or kit, and you may need to change your project settings. For more information, see:

PSoC® 3, PSoC 5, and PSoC 5LP AN Project File Naming Convention and Use
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Wed, 30 Jul 2014 16:59:43 -0600
External Library http://www.cypress.com/?rID=56759 Features

  • The library provides documentation for annotation components.
     

General Description

The External Library provides a way for you to mix external and internal components on the same schematic. This makes it possible to improve documentation and better understand the internal schematic and entire design. The components in this library cover the most common components that are most likely to be placed on the periphery of a PSoC device. These components consist of resistors, capacitors, transistors, inductors, switches, and others. The library is not intended to supply every possible part, but should support a wide range of designs. You can easily create your own part or parts library if your design includes a custom or unique component.

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Wed, 30 Jul 2014 01:24:05 -0600
AN52927 - PSoC<sup>®</sup> 3 and PSoC 5LP - Segment LCD Direct Drive http://www.cypress.com/?rID=37795 AN52927 demonstrates how easy it is to drive a segment LCD glass using the integrated LCD driver in PSoC 3 and PSoC 5LP. This application note gives a brief introduction to segment LCD drive features and provides a step-bystep procedure to design Segment LCD applications using the PSoC Creator tool.

PSoC3 device is equipped with segment LCD driver which allows segment LCD glass to be directly driven without using any external components.

Segment LCD glass interface to PSoC3

The driver supports LCDs upto 16 commons and can drive upto 768 segments. PSoC Creator tool provides Segment LCD component which simplifies the task of handling different types of segment LCD features such as 7-segment, 14-segment, 16-segment, Dot-Matrix and special symbols. This application note explains how to use Segment LCD component for a given LCD specifications.

This application note only covers segment LCD drive capability of PSoC3. Another type of LCDs- the graphic LCDs can also be interfaced to PSoC3. For details of interfacing graphic LCDs to PSoC3, click the following links-

http://www.cypress.com/?rID=48850

http://www.cypress.com/?rID=48854

 

Demo Video: PSoC3 Segment LCD Direct Drive Demo

This video explains how to create projects with Segment LCD Component of PSoC3.

 

 

The following table indicates the PSoC devices, PSoC Creator versions, compilers, and development kits that will work with this application note project:


Project
Device
PSoC Creator
Version
Development Kit
CY8CKIT-xxx
Compiler
Architecture
Silicon
Revision
V3.0 SP1
or higher
V2.1 SP1/
V2.1
001
DVK
030/050
DVK
003/014
FTK
Keil
GCC
RVDS
MDK

AN52927.zip

Prod
YES
NO
YES
YES*
NO
YES
N/A
N/A
N/A
Prod
YES
NO
YES
YES*
NO
N/A
YES
YES
YES
AN52927_Archive.zip
ES3, Prod
NO
YES
YES
YES*
NO
YES
N/A
N/A
N/A

*Refer to Migrating CY8CKIT-001 DVK project to CY8CKIT 030/ 050


Projects associated with this application note can be downloaded from the ‘Related Files’ section below. For your convenience, we have provided projects that are compatible with the two most recent versions of PSoC Creator:

  • AN52927.zip is used with PSoC Creator 3.0 SP1
  • AN52927_Archive.zip is used with PSoC Creator 2.1 SP1/2.1

The project’s default settings may not be compatible with your device or kit, and you may need to change your project settings. For more information, see:

PSoC® 3 and PSoC 5 AN/CE project file naming convention and usage
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Mon, 28 Jul 2014 05:15:14 -0600
AN52705 - PSoC® 3 and PSoC 5LP - Getting Started with DMA http://www.cypress.com/?rID=37793 AN52705 provides an introduction to direct memory access (DMA) in PSoC® 3 and PSoC 5LP. PSoC DMA can transfer data between on-chip peripherals and memory with no CPU intervention. The application note illustrates how to configure the DMA for simple data transfers, including peripheral to memory, memory to peripheral, peripheral to peripheral and memory to memory, using example projects.

Introduction

The DMA controller (DMAC) in PSoC 3 and PSoC 5LP can transfer data from a source to a destination with no CPU intervention. This allows the CPU to handle other tasks while the DMA does data transfers, thereby achieving a 'multiprocessing' environment.

The PSoC DMA Controller (DMAC) is highly flexible – it can seamlessly transfer data between memory and on chip peripherals including ADCs, DACs, Filter, USB, UART, and SPI. There are 24 independent DMA channels.

 The following table indicates the PSoC devices, PSoC Creator versions, compilers, and development kits that will work with this application note project:


Project
Device
PSoC Creator
Version
Development Kit
CY8CKIT-xxx
Compiler
Architecture
Silicon
Revision
V3.0 SP1
or higher
V2.1/2.0
001
DVK
030/050
DVK
003/014
FTK
Keil
GCC
RVDS
MDK

AN52705.zip

Prod
YES
NO
YES
YES*
NO
YES
N/A
N/A
N/A
Prod
YES
NO
YES
YES*
NO
N/A
YES
YES
YES
AN52705_Archive.zip
ES2, ES3, Prod
NO
YES
YES
YES*
NO
YES
N/A
N/A
N/A
ES1, Prod
NO
YES
YES
YES*
NO
N/A
YES
YES
YES

 *Refer to Migrating CY8CKIT-001 DVK project to CY8CKIT 030/ 050

Note:
  1. For PSoC 5 project and related document, please download file AN52705_Archive.zip.

Projects associated with this application note can be downloaded from the ‘Related Files’ section below. For your convenience, we have provided projects that are compatible with the two most recent versions of PSoC Creator:

  • AN52705.zip is used with PSoC Creator 3.0 SP1
  • AN52705_Archive.zip is used with PSoC Creator 2.1/2.0

The project’s default settings may not be compatible with your device or kit, and you may need to change your project settings. For more information, see:

PSoC® 3, PSoC 4 and PSoC 5LP AN Project File Naming Convention and Use
]]>
Mon, 28 Jul 2014 03:51:09 -0600
Toggle Flip Flop http://www.cypress.com/?rID=73664 Features

  • T input toggles Q values
  • Configurable width for array of Toggle Flip Flops with a single enable
Symbol Diagram

General Description

The Toggle Flip Flop captures a digital value that can be toggled.  Use to implement sequential logic.

 

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Thu, 24 Jul 2014 11:53:46 -0600
SR Flip Flop http://www.cypress.com/?rID=73663 Features

  • Clocked for safe use in synchronous circuits
  • Configurable width for array of SR Flip Flops
Symbol Diagram

General Description

The SR Flip Flop stores a digital value that can be set or reset.  Use to implement sequential logic.

 

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Thu, 24 Jul 2014 11:51:18 -0600
Frequency Divider http://www.cypress.com/?rID=73667 Features

  • Divides a clock or arbitrary signal by a specified value
  • Enable and Reset inputs to control and align divided output
Symbol Diagram

General Description

The Frequency Divider component produces an output that is the clock input divided by the specified value.  Use as a simple clock divider for UDB components or to divide the frequency of another signal.

 

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Thu, 24 Jul 2014 11:45:59 -0600
Edge Detector http://www.cypress.com/?rID=73666 Features

  • Detects Rising Edge, Falling Edge, or Either Edge
Symbol Diagram

General Description

The Edge Detector component samples the connected signal and produces a pluse when the selected edge occurs.  Use when a circuit needs to respond to a state change on a signal.

 

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Thu, 24 Jul 2014 11:42:54 -0600
Digital Comparator http://www.cypress.com/?rID=73665 Features

  • 1 to 32 bit Configurable Digital Comparator
  • Six selectable comparison operators
Symbol Diagram

General Description

The Digital Comparator component provides a selectable-width, selectable-type comparator implemented in PLD macrocells.  Use when the digital values of two signals need to be compared.

 

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Thu, 24 Jul 2014 11:40:16 -0600
Logic High/Logic Low http://www.cypress.com/?rID=48514 Features

  • Constant digital high or low signal
Symbol Diagram

General Description

The Logic High and Logic Low components provide constant digital values and are used to hard code digital inputs. Hard coding of static inputs results in optimized resource usage and is the preferred method of providing a constant input state.

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Thu, 24 Jul 2014 11:35:44 -0600
Digital Constant http://www.cypress.com/?rID=73661 Features

  • Represents a digital value clearly on a schematic
  • Display in hexadecimal or decimal
  • Configurable width up to 32 bits
Symbol Diagram

General Description

The Digital Constant provides a convenient way to represent digital values in designs.  Use whenever a constant digital value is needed in a design including bit-masks and magnitude comparisons.

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Thu, 24 Jul 2014 11:30:44 -0600
Component Locking Feature Using the Analog Device Editor in PSoC<sup>®</sup> Creator™ – KBA85474 http://www.cypress.com/?rID=97356 Answer: There are two methods by which this can be achieved.

Method 1: Use the placement force directives under the Directives tab of the .cydwr file of the project.

Example: Forcing a SAR ADC component on Top Design to a particular location in the fitter (i.e., a way of telling the routing tool which of the available two fixed function SAR ADCs to select for this component). The following design schematic has two SAR ADCs: ADC1 and ADC2, which should be locked down to SAR0 and SAR1 respectively.

Figure 1. Design Schematic

Design Schematic

Figure 2. The .cydwr Settings under the Directives Tab

Directives Tab

Method 2: Use the lock down and relocate feature of the Analog Device Editor. This is limited to locking down only analog components, signals, and nets.

For the same example and Top Design as the above method, do the following.

  1. Go to the Analog tab under the .cydwr file of the project.
  2. For relocating the current selection of component using the fitter tool: Right-click the component, select Relocate, and make the appropriate selection.
  3. For locking the existing selection of a component: Right-click a particular SAR ADC position—say, SAR0—and click Lock to F(SAR,0).
  4. The display table on the right side also has a description of the components, muxes, pins, and nets. Locking can also be done by checking the corresponding Locked check box. The locked components have a small lock symbol at the top of the component.

Figures 3–5 depict the procedure explained here.

Figure 3. Relocating an Existing Selection of the Component

Relocating

Figure 4. Lock-Down Feature in the Analog Device Editor

Lock-Down

Figure 5. The Lock Symbol at the Top Left of SAR0

Lock Symbol

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Thu, 24 Jul 2014 07:15:48 -0600
Digital Logic Gates http://www.cypress.com/?rID=48520 Features

  • Industry standard logic gates
  • Configurable number of inputs up to 8
  • Optional array of gates
Symbol Diagram

General Description

Logic gates provide basic boolean operations. The output of a logic gate is a boolean combinatorial function of the inputs. There are seven basic logic gates: AND, OR, Inverter (NOT), NAND, NOR, XOR, and XNOR.

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Wed, 23 Jul 2014 12:49:50 -0600
Voltage Reference (Vref) http://www.cypress.com/?rID=48512 Features

  • Voltage references and supplies
  • Multiple options
  • Bandgap principle to achieve timer, temperature, and voltage stability
Symbol Diagram

General Description

This description applies to PSoC 3 and PSoC 5LP devices. The Voltage Reference (Vref) component provides one of several voltage reference outputs. The 1.024 V and 0.256 V outputs are temperature compensated using the bandgap principle to achieve excellent stability.

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Wed, 23 Jul 2014 12:44:45 -0600
Virtual Mux http://www.cypress.com/?rID=48511 Features

  • Selects 1 of up to 16 inputs
  • Selection is static
  • Configurable number of inputs
Symbol Diagram

General Description

Virtual mux components are similar to conventional muxes in that they connect a selected input to an output. For a conventional mux, the input selection can be dynamically controlled by a control signal. For a virtual mux, the input selection is determined by an expression that evaluates to a constant when used within a design. The purpose of the virtual mux is to pick one input at build time.

There are two separate virtual mux components: one analog and one digital.

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Wed, 23 Jul 2014 12:41:07 -0600
PSoC<sup>®</sup> 3 and PSoC 5LP Boost Inductor Current Rating - KBA80957 http://www.cypress.com/?rID=39945 Answer: The DC current rating of the inductor should be greater than or equal to 700mA. The inductor peak current can go up to a maximum of 700 mA during start-up. So, if you use an inductor with a lesser current rating, the boost converter may not start properly.

During startup or transient operation (when the output voltage changes), the load capacitor acts like a short circuit and will draw as much current as the converter can deliver. There are current limiting provisions inside the boost converter that prevent the current from growing unbounded. The effective current limit is under 700mA. So, if you use an underrated inductor the boost converter may not start properly. The reason is that the inductor becomes saturated and ceases to behave as an inductor, dissipating energy in it and hence, not transferring the energy effectively.

The boost converter can give a maximum load current of 75mA. Even if the load is small, the inductor must be capable of delivering peak currents. This is because transient loads will pull the output below the narrow regulation window provided by minimum PWM signals, requiring occasional full current (maximum duty cycle) pulses to restore the voltage to target value.

Thus the inductor always needs to be rated for full current.

Note: The maximum ratio of the output voltage to the input voltage of the boost can be 4.

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Wed, 23 Jul 2014 04:32:31 -0600
UDB Clock Enable (UDBClkEn) http://www.cypress.com/?rID=48865 Features

  • Clock enable support
  • Addition of synchronization on a clock when needed
Symbol Diagram

General Description

The UDBClkEn component supports precise control over clocking behavior.

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Tue, 22 Jul 2014 11:39:06 -0600
Full Speed USB (USBFS) http://www.cypress.com/?rID=48924 Features
  • USB Full Speed device interface driver
  • Support for interrupt, control, bulk, and isochronous transfer types
  • Runtime support for descriptor set selection
  • Optional USB string descriptors
  • Optional USB HID class support
  • Optional Bootloader support
  • Optional Audio class support
  • Optional MIDI devices support
  • Optional CDC class support
Symbol Diagram

General Description

The USBFS component provides a USB full-speed Chapter 9 compliant device framework. It provides a low-level driver for the control endpoint that decodes and dispatches requests from the USB host. Additionally, this component provides a USBFS customizer to make it easy to construct your descriptor.   

 

PSoC Creator USB FS Component Video

use for camtasia screencasts

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Mon, 21 Jul 2014 18:58:22 -0600
Sample/Track and Hold Component (Sample_Hold) http://www.cypress.com/?rID=56758 Features Symbol Diagram
  • Two operating modes: Sample and Hold, Track and Hold
  • Four power mode settings

General Description

The Sample/Track and Hold component provides a way to sample a continuously varying analog signal and to hold or freeze its value for a finite period of time. It supports both Track and Hold and Sample and Hold functions, which can be selected in the customizer.

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Mon, 21 Jul 2014 18:54:06 -0600
Real-Time Clock (RTC) http://www.cypress.com/?rID=48907 Features

  • Multiple Alarm Options
  • Multiple Overflow Options
  • Daylight Savings Time (DST) Option
Symbol Diagram

General Description

The Real-Time Clock (RTC) component provides accurate time and date information for the system. The time and date are updated every second based on a one pulse per second interrupt from a 32.768-kHz crystal. Clock accuracy is based on the crystal provided and is typically 20 ppm.   

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Mon, 21 Jul 2014 18:49:21 -0600
Design Reuse - It is Time for New IP Creation Tools http://www.cypress.com/?rID=43833 For many years design reuse has been touted as an essential part of completing projects on-time and on-budget. This idea is not new and the expression “don’t reinvent the wheel” is used in high-tech environments the world over for very good reasons. However, design reuse is typically approached either from a solely hardware (microprocessor cores, reusable IP peripherals, hardware acceleration, and so on) or software (RTOS, protocol stacks, run-time libraries and so on) perspective, but rarely both. Why is that and how can it change?  To read more, click the download link below or visit: SOCcentral.

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Mon, 21 Jul 2014 06:59:45 -0600
Timer http://www.cypress.com/?rID=48870 Features

  • Fixed-function (FF) implementation for PSoC 3 and PSoC 5 devices
  • 8-, 16-, 24-, or 32-bit timer
  • Optional capture input
  • Enable, trigger, and reset inputs, for synchronizing with other components
  • Continuous or one shot run modes
Symbol Diagram

General Description

The Timer component provides a method to measure intervals. It can implement a basic timer function and offers advanced features such as capture with capture counter and interrupt/DMA generation.

 
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Wed, 09 Jul 2014 18:54:15 -0600
Thermocouple Calculator http://www.cypress.com/?rID=69779 Features
  • Supports B, E, J, K, N, R, S, and T Type Thermocouples
  • Provides functions for thermo-emf to temperature and temperature to voltage conversions
  • Displays Calculation Error Vs. Temperature graph
Symbol Diagram

General Description

In thermocouple temperature measurement, the thermocouple temperature is calculated based on the measured thermo-emf voltage. The voltage to temperature conversion is characterized by the National Institute of Standards and Technology (NIST), and NIST provides tables and polynomial coefficients for thermo-emf to temperature conversion. The NIST tables and polynomial coefficients can be found in the following link:

http://srdata.nist.gov/its90/download/download.html

Thermocouple temperature measurement also involves measuring the thermocouple reference junction temperature and converting it into a voltage. The Thermocouple Calculator component simplifies the thermocouple temperature measurement process by providing APIs for thermo-emf to temperature conversion and vice versa for all thermocouple types mentioned above, using polynomials generated at compile time. The thermocouple component evaluates the polynomial in an efficient way to reduce computation time.

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Wed, 09 Jul 2014 18:50:31 -0600
Thermistor Calculator http://www.cypress.com/?rID=69783 Features
  • Adaptable for majority of negative temperature coefficient (NTC) thermistors
  • Look-Up-Table (LUT) or equation implementation methods
  • Selectable reference resistor, based on thermistor value
  • Selectable temperature range
  • Selectable calculation resolution for LUT method
Symbol Diagram

General Description

The Thermistor Calculator component calculates the temperature based on a provided voltage measured from a thermistor. The component is adaptable to most NTC thermistors. It calculates the Steinhart-Hart equation coefficients based on the temperature range and corresponding user-provided reference resistances. The component provides API functions that use the generated coefficients to return the temperature value based on measured voltage values.

This component doesn't use an ADC or AMUX inside and thus requires those components to be placed separately in your projects.

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Wed, 09 Jul 2014 18:45:47 -0600
Digital Filter Block (DFB) Assembler http://www.cypress.com/?rID=60720 Features Symbol Diagram
  • Provides an editor to enter the assembler instructions to configure the DFB block and an assembler that converts the assembly instructions to instruction words.
  • Supports simulation of the assembly instructions.
  • Supports a code optimization option that provides a mechanism to incorporate up to 128 very large instruction words inside the DFB Code RAM.
  • Provides hardware signals such as DMA requests, DSI inputs and outputs, and interrupt lines.
  • Supports semaphores to interact with the system software and the option to tie the semaphores to hardware signals.

General Description

The digital filter block (DFB) in PSoC 3 and PSoC 5LP can be used as mini DSP processor and allows you to configure the DFB using assembly instructions. The component assembles the instructions entered in the editor and generates the corresponding hex code words, which can be loaded into the DFB. It also includes a simulator, which helps the user to simulate and debug the assembly instructions.

The DFB consists of a programmable 24*24 multiplier/accumulator (MAC), an arithmetic logic unit (ALU), shifter, and various program and data memory to store instructions and data. The DFB runs on the bus clock, and can interface with both CPU and DMA. It can be used to offload the CPU and can speed up arithmetic calculations that involve intensive multiply accumulate operations. Typical operations you can use the DFB component to implement include: vector operations, matrix operations, filtering operations, and signal processing.

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Wed, 09 Jul 2014 18:36:32 -0600
Sync http://www.cypress.com/?rID=48925 Features

  • Synchronizes 1 to 32 input signals
Symbol Diagram

General Description

The Sync component resynchronizes a set of input signals to the rising edge of the clock signal.

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Wed, 09 Jul 2014 18:32:15 -0600