Cypress.com: Documentation http://www.cypress.com/?app=search&searchType=advanced&id%3D2232 PSoC 3 Device Programming http://www.cypress.com/?rID=40740 Thu, 17 Apr 2014 12:29:04 -0600 PSoC 3 Architecture http://www.cypress.com/?rID=40738 Wed, 16 Apr 2014 14:43:17 -0600 Reading the Contents of Component Registers in PSoC<sup>®</sup> Creator™ 2.1 – KBA85475 http://www.cypress.com/?rID=94190 Answer: To access the component registers you can find the address of the register in the generated source files under the cydevice_trm.h tab and produce that address in the XData Memory 1 window, as shown in Figure 1.

Figure 1. Accessing the Component Registers in the XData Memory Space

XData Memory

However, a simpler and more straightforward method is to use the component debug window. This allows you to track the values in the various component registers during an active debug session. The procedure is depicted in Figures 2–4. First, go to Debug > Windows > Components to instantiate the component debug window during an active debug session.

Figure 2. Instantiating the Component Debug Window during an Active Debug Session

Then, select the components whose register values are to be traced.

Figure 3. Selecting Components

The key registers of the component and their corresponding values will be displayed in the component debug window.

Figure 4. Key Registers and Corresponding Values

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Wed, 16 Apr 2014 05:13:16 -0600
AN60616 - PSoC<sup>®</sup> 3 and PSoC 5LP Startup Procedure http://www.cypress.com/?rID=40991 This application note describes how to customize the startup procedure, as well as the reasons a designer might choose to change the startup procedure in different ways.

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Introduction

PSoC 3 and PSoC 5LP are incredibly powerful and complicated mixed-signal microcontrollers. Through careful configuration, they can be used to solve all kinds of technical problems. The PSoC Creator integrated design environment generates the code that will configure the parts at startup, but it requires application specific configuration details. Startup behavior can be manipulated to change the amount of time startup takes, what peripherals are configured, and much more. This application note describes the procedure of startup and also how it can be manipulated to best suit an application.

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Wed, 16 Apr 2014 00:16:24 -0600
AN60305 - Using PSoC® 3 and PSoC 5LP IDACs to build a better VDAC http://www.cypress.com/?rID=42681 It presents different approaches for using the IDACs in applications and discusses the advantages and disadvantages of the topologies presented. This application note will: help you to understand compliance voltage and why it is important; explain how to generate an “any range” or “any ground” VDAC; describe an implementation for a multiplying VDAC; give details on how to build a rail-to-rail low output impedance 9-bit VDAC from a single IDAC, an OpAmp, and a resistor; and provide information on how to build a current scaling circuit with an OpAmp and two resistors.

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Tue, 15 Apr 2014 06:59:22 -0600
USB Host in PSoC<sup>®</sup> 3 and PSoC 5LP – KBA82827 http://www.cypress.com/?rID=53702 Answer: No. The USB host side is not supported in any of the PSoC 3 or PSoC 5 families. Both of these families have only a full-speed USB device. They cannot act as USB hosts.

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Tue, 15 Apr 2014 05:37:30 -0600
Where to Find the MiniProg3 Driver File - KBA88256 http://www.cypress.com/?rID=43624 Answer: The mprog3.inf file located at “C:\Program Files\Cypress\Programmer\drivers\mprog3” is the driver file that you need to bind with Miniprog3. This inf file points to the sys file, which is required for connecting MiniProg3 to the USB.

If MiniProg3 is coming up as unconfigured in the Device Manager, then see the “First touch kit 3 / MiniProg3 unconfigured” Knowledge Base article.

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Tue, 15 Apr 2014 01:35:05 -0600
AN60631 - PSoC® 3 and PSoC 5LP Clocking Resources http://www.cypress.com/?rID=40990 This application note describes PSoC 3 and PSoC 5LP's oscillators and clock sources, phase-locked loop (PLL), and clock distribution network. However, it does not cover the details of the external crystal oscillators (ECOs). For those details, see AN54439 - PSoC® 3 and PSoC 5LP External Crystal Oscillator.

Clocks play a critical part in microcontroller operation. They are used to synchronize internal signals, ensure error free communication with other digital devices, and drive the conversion of signals to and from the analog domain. These roles make the configuration of the different clocks used inside of a microcontroller very important.

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Tue, 15 Apr 2014 01:25:18 -0600
AN56377 - PSoC® 3 and PSoC 5LP USB Transfer Types http://www.cypress.com/?rID=39553 It then shows how to configure PSoC® 3 and PSoC 5LP to perform each of these transfers. Code examples are also included for specific considerations, including vendor commands for custom USB functionality, and to use DMA for faster data throughput. This application note assumes advanced level knowledge of USB. For an introduction to USB, see AN57294.

Below are some of videos demonstrating  how to impliment bulk transfers and vendor commands which are discussed in this application note.

 

 

 

The following table indicates the PSoC devices, PSoC Creator versions, compilers, and development kits that will work with this application note project:


Project
Device
PSoC Creator
Version
Development Kit
CY8CKIT-xxx
Compiler
Architecture
Silicon
Revision
V2.1 SP1
or higher
V2.1 / 2.0
001
DVK
030/050
DVK
003/014
FTK
Keil
GCC
RVDS
MDK

AN56377.zip

Prod
YES
NO
YES
YES*
NO
YES
N/A
N/A
N/A
Prod
YES
NO
YES
YES*
NO
N/A
YES
YES
YES
AN56377_Archive.zip
ES2,ES3, Prod
NO
YES
YES
YES*
NO
YES
N/A
N/A
N/A
ES1, Prod
NO
YES
YES
YES*
NO
N/A
YES
YES
YES

*Refer to Migrating CY8CKIT-001 DVK project to CY8CKIT 030/ 050

Notes:

  1. For PSoC 5 project and related document, please download file AN56377_Archive.zip.

Projects associated with this application note can be downloaded from the ‘Related Files’ section below. For your convenience, we have provided projects that are compatible with the two most recent versions of PSoC Creator:

  • AN56377.zip is used with PSoC Creator 2.1 SP1
  • AN56377_Archive.zip is used with PSoC Creator 2.1/2.0

The project’s default settings may not be compatible with your device or kit, and you may need to change your project settings. For more information, see:
PSoC® 3, PSoC 4 and PSoC 5LP AN Project File Naming Convention and Use

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Mon, 14 Apr 2014 01:51:38 -0600
Mandatory upgrade required for PSoC® Creator™ 1.0 Service Pack 2 http://www.cypress.com/?rID=51923 PSoC® Creator™ 1.0 Service Pack 2 is a mandatory update to version 1.0 Production and Service Pack 1. Service Pack 2 is a complete superset of Service Pack 1.

All versions of PSoC3 Application Note projects and code example designed with PSoC Creator 1.0, with device silicon as ‘Production / ES3’ when opened in PSoC Creator Service Pack 2 will generate an error message. This is to enforce the user to update to v2.21 of CY_BOOT.

When a project originally designed using PSoC® Creator™ 1.0 is opened with PSoC® Creator™ 1.0 Service Pack 2 (SP2), the following screen would appear prompting the user for an upgrade. Select the “Yes” option here. This would update the CY_BOOT to v2.21.
 

 

Link for downloading PSoC® Creator™ 1.0 Service Pack 2 (SP2):  http://www.cypress.com/?rID=39551

To learn more details on error fixes and new feature set, refer to release notes

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Fri, 11 Apr 2014 04:51:35 -0600
Preloading Bytes into Flash Memory – KBA89438 http://www.cypress.com/?rID=93827 Answer: The methods of preloading bytes of data are different for PSoC® 3 and PSoC 5.

  • For PSoC 3, the prefix “code” is used to store the data in flash memory - for example:

    code uint8 array1[5] = {1,2,3,4,5};

  • For PSoC 5, the prefix “const” is used to store the data in flash memory - for example:

    const uint8 array1[5] = {1,2,3,4,5};

  • For a code to be portable from PSoC 3 to PSoC 5 and vice versa, follow this example:

    CYCODE const uint8 array1[5] = {1, 2, 3, 4, 5};

It is important to know how to load data into flash memory because you may need to use it for a look up table (LUT) or to define simple constants.

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Fri, 11 Apr 2014 00:24:13 -0600
AN60594 - PSoC<sup>®</sup> 3 and PSoC 5LP: Low-Frequency FSK Modulation and Demodulation http://www.cypress.com/?rID=40985 The method described in this application note uses zero CPU, everything done in PSoC hardware. This application note covers only the physical layer implementation of an FSK transmitter and receiver; higher-level encoding techniques and physical modem connections are not discussed.

The following table provides the list of devices, the supported Creator version, Development kit and Compiler for this application note project:
 


Project
Device
PSoC Creator
Version
Development Kit
CY8CKIT-xxx
Compiler
Architecture
Silicon
Revision
V3.0 CP7
or greater
V2.2 SP1
V2.1
001
DVK
030/050
DVK
003/014
FTK
Keil
GCC
RVDS
MDK

AN60594.zip

Prod
YES
NO
NO
YES
YES*
NO
YES
N/A
N/A
N/A
Prod
YES
NO
NO
YES
YES*
NO
N/A
YES
YES
YES
AN60594_Archive.zip
ES3, Prod
NO
YES
YES
YES
YES*
NO
YES
N/A
N/A
N/A
ES1, Prod
NO
YES
YES
YES
YES*
NO
N/A
YES
YES
YES

 *Refer to Migrating CY8CKIT-001 DVK project to CY8CKIT 030/ 050

Notes:
  1. For PSoC 5 project and related document, please download file AN60594_Archive.zip.

Projects associated with this application note can be downloaded from the 'Related Files' section below. For your convenience, we have provided projects that are compatible with the two most recent versions of PSoC Creator:

  • AN60594.zip is used with PSoC Creator 3.0 CP7
  • AN60594_Archive.zip is used with PSoC Creator 2.1 SP1/2.1

The project’s default settings may not be compatible with your device or kit, and you may need to change your project settings. For more information, see:

PSoC® 3, PSoC 5, and PSoC 5LP AN Project File Naming Convention and Use
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Tue, 08 Apr 2014 04:01:09 -0600
CY8CKIT-002 PSoC® MiniProg3 Program and Debug Kit http://www.cypress.com/?rID=38154
The Miniprog3 supports the following protocols:

  • SWD
  • JTAG
  • ISSP
  • USB-I2C

Included with the kit is a 10-pin ribbon cable for connecting to standard 10-pin JTAG header interfaces utilized for our PSoC 3, PSoC 4 and PSoC 5LP architectures while the device itself supports the 5-pin ISSP programming header for PSoC 1 architectures. The 5-pin connector also supports the USB-I2C Bridging capabilities and is a superset of the CY3240 capabilities. Please note, the CY8CKIT-002 only contains the Miniprog3 and supporting cables.


CY8CKIT-002 Kit Image


Miniprog3 *B Revision Update:

Cypress Semiconductor has completed a hardware update to the Miniprog3 to address hardware issues seen with programming, ESD, and power management. The Miniprog3 revision, either *A or *B, is indicated using sticker on the back of the programmer. The following are a list of updates made to the Miniprog3 *B programmer.

Updated Hardware to Improve Power Cycle Programming:

The Miniprog3 hardware has been updated to better improve power cycle programming for all PSoC devices. It was discovered that the Miniprog3 *A programmer revision did not correctly implement the power cycle programming methodology. Due to this issue the Miniprog3 *A programmer could not correctly support power cycle programming for PSoC 3, PSoC 4 and PSoC 5LP  devices. This specifically impacts customers who do not route out the XRES line to the programming connector or disable the optional XRES line on certain devices. The *B revision of the Miniprog3 will support power cycle programming for all PSoC 3, PSoC 4 and PSoC 5LP devices.

Over-current and Non-Polarized Connection Updates:

There are known electrical risks to the Miniprog3 *A revision that have been addressed with the *B update. To address the electrical issues the Miniprog3 *B programmer has added ESD over-current protection to the USB lines and has added electrical protection to the 5 and 10-pin connectors in case of a reverse polarity condition.

Improved Voltage Detection Capabilities:

The Miniprog3 *B programmer has been updated to improve the voltage detection capabilities. The Miniprog3 will measure the target voltage within an accuracy of 20 mV for a range of 1.8V – 5.0V.

Supported Software:

The Miniprog3 *B programmer is supported on the latest release of PSoC Programmer. To download the latest release, please navigate to the PSoC Programmer web page:

www.cypress.com/go/psocprogrammer

Additional Programming Information

The Miniprog3 programmer is part of a suite of programming options and programming content available to PSoC users. For customers who are looking for more information on general programming options and information please navigate to the web page linked below. On the General Programming web page we discuss all of the available programming options for customers including Software, Schematics, Programming Specifications, and 3rd party mass programming.

www.cypress.com/go/programming
 

The MiniProg3 programmer is not recommended for production programming. We suggest customers who need production programming support consult our 3rd party programming vendors on our General Programming page listed above or through our distribution partners: www.cypress.com/go/distributors

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Mon, 07 Apr 2014 16:35:06 -0600
CY8CKIT-001 PSoC® Development Kit http://www.cypress.com/?rID=37464 The CY8CKIT-001 PSoC® Development Kit (DVK) provides a common development platform where you can prototype and evaluate different solutions using any one of the PSoC 1, PSoC 3, or PSoC 5 architectures.

The PSoC DVK gives you a practical understanding of PSoC technology. In addition, the kit includes several example projects with step-by-step instructions to enable you to easily get started developing PSoC solutions. This kit includes PSoC 1, PSoC 3, and PSoC 5LP Family Processor Modules.

Kit Upgrade: Now it’s time to make the upgrade to PSoC® 5LP Processor Module and take advantage of all that PSoC has to offer.

Limited Time Price Reduction to $199!

Cypress is running a limited time price reduction on the CY8CKit-001 kit. Customers can use the promotion code KIT001138616289 at checkout to receive the reduced price of $199.

Cypress is running a limited time price reduction on the CY8CKit-001 kit throughout the end of 2013. Customers can use the promotion code KIT001138616289 at checkout to receive the reduced price of $199.

Simply add the Kit-001 to your cart and checkout through the Cypress online store. Just before purchasing the kit, you will be able to enter in the promotional code KIT001138616289 to reduce the kit price. The promotional code is valid for one kit per customer.

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The CY8CKIT-001 PSoC® Development Kit (DVK) provides a common development platform where you can prototype and evaluate different solutions using any one of the PSoC 1, PSoC 3, PSoC 4, or PSoC 5 architectures.

The PSoC DVK gives you a practical understanding of PSoC technology. In addition, the kit includes several example projects with step-by-step instructions to enable you to easily get started developing PSoC solutions. This kit includes PSoC 1, PSoC 3, PSoC 4 and PSoC 5LP Family Processor Modules.

 


Cypress_times_image_572010_7_1.JPG
 
 



Kit Contents:

  • PSoC Development Board
  • PSoC 1 CY8C28 Family Processor Module
  • PSoC 3 CY8C38 Family Processor Module
  • PSoC 4 CY8C42 Family Processor Module (Sold Separately)
  • PSoC 5 CY8C58LP Family Processor Module
  • MiniProg3 Program/Debug Device
  • Program/Debug Ribbon Cable
  • USB Cable
  • 12V AC Power Adapter
  • Quick Start Guide
  • Kit CDs, which includes: PSoC Creator™, PSoC Designer™, PSoC Programmer, Projects, and Documentation
     

For PSoC training, please visit http://www.cypress.com/go/training.

Software Title Description Link
PSoC Creator This kit requires PSoC Creator for development
PSoC Designer This kit requires PSoC Designer for development
PSoC Programmer This kit requires PSoC Programmer for programming
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Mon, 07 Apr 2014 16:34:05 -0600
Three-Phase PWM Generation – KBA91232 http://www.cypress.com/?rID=93027 Answer: To generate three-phase PWM signals shifted by 120 degrees, four PWM user modules are required. One PWM user module is used to generate the time interval for the other three PWMs to generate three-phase PWM signals shifted by 120 degrees. The period of the PWM that generates the time intervals for the other PWMs should be adjusted to one third of the output frequency of the other three PWMs. The PWM that generates the time intervals has to be configured for terminal count interrupt. The three PWM user modules have to be started during the first three terminal count interrupts sequentially. The three-phase PWM can be used to generate signals for three phase motors.

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Mon, 07 Apr 2014 03:57:42 -0600
Jitter Present at the PSoC 3/5LP Clock Output – KBA90382 http://www.cypress.com/?rID=93837 Answer: Consider the following schematic:

Figure 1. Clock Component Used in the Top Design

In Figure 1, the clock component is configured for 1 MHz and derived from the internal main oscillator (IMO), such as the 24-MHz IMO.
The master clock used in the design is derived from PLL_OUT. Figure 2 shows the clock configuration tree that is used in the design.

Figure 2. Clock Configuration Tree

So, in this project, Master Clock is derived from PLL_OUT, while the clock source Clock_1 is based on the IMO. The PLL is uncorrelated to the IMO-based 1-MHz clock. This asynchronicity makes it indeterminate on the PLL clock cycle that will re-sync the IMO-based divided clock. This causes jitter on the clock output.

To eliminate this jitter, do one of the following:

  1. Make the clock source of Clock_1 based on PLL_OUT.
  2. Uncheck the option “Sync with MASTER_CLK” if Clock_1 is based on the IMO as shown in Figure 3.

    Figure 3. Disable Sync With Master Clock

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Fri, 04 Apr 2014 06:10:00 -0600
QTP 120206: QTP68 QFN (8X8X1.0MM) NIPDAU, 100% CU WIRE MSL3, 260C REFLOW CML-RA http://www.cypress.com/?rID=61292 Fri, 04 Apr 2014 03:04:12 -0600 PSoC 3 Low Power with Real-Time Clock http://www.cypress.com/?rID=42739
 

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Fri, 04 Apr 2014 00:09:11 -0600
AN57294 - USB 101: An Introduction to Universal Serial Bus 2.0 http://www.cypress.com/?rID=39327 USB is an interface that connects a device to a computer. With this connection, the computer sends or retrieves data from the device. USB gives developers a standard interface to use in many different types of applications. A USB device is easy to connect and use because of a systematic design process.

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Thu, 03 Apr 2014 23:54:41 -0600
Exploring the New PSoC Platform http://www.cypress.com/?rID=40352
 

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Thu, 03 Apr 2014 08:12:42 -0600
PSoC Expansion Board Kit For iPhone & iPod Accessories Video http://www.cypress.com/?rID=41078
 

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Thu, 03 Apr 2014 08:07:13 -0600
PSoC 3/5 USB Features and Basics http://www.cypress.com/?rID=82202
 

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Thu, 03 Apr 2014 05:36:34 -0600
PSoC Today! Community Components Part I http://www.cypress.com/?rID=85055 For more information visit the Cypress Developer Community at www.cypress.com

 

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Thu, 03 Apr 2014 04:47:55 -0600
PSoC Today! Community Components Part II http://www.cypress.com/?rID=85246
 

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Thu, 03 Apr 2014 04:44:47 -0600
Introducing PSoC Creator 3.0 http://www.cypress.com/?rID=86430
 

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Thu, 03 Apr 2014 04:27:48 -0600
PSoC® 3: CY8C36 Family Data Sheet: Programmable System-on-Chip (PSoC®) http://www.cypress.com/?rID=37805 Programmable System-on-Chip (PSoC®)

General Description

With its unique array of configurable blocks, PSoC® 3 is a true system level solution providing microcontroller unit (MCU), memory, analog, and digital peripheral functions in a single chip. The CY8C36 family offers a modern method of signal acquisition, signal processing, and control with high accuracy, high bandwidth, and high flexibility. Analog capability spans the range from thermocouples (near DC voltages) to ultrasonic signals. The CY8C36 family can handle dozens of data acquisition channels and analog inputs on every general-purpose input/output (GPIO) pin. The CY8C36 family is also a high-performance configurable digital system with some part numbers including interfaces such as USB, multi-master inter-integrated circuit (I2C), and controller area network (CAN).

Features

  • Single cycle 8051 CPU core
  • Low voltage, ultra low-power
  • Versatile I/O system
  • Digital peripherals
  • Analog peripherals (1.71 V ≤ VDDA ≤ 5.5 V)
  • Programming, debug, and trace
  • Precision, programmable clocking
  • For more, see pdf
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Thu, 27 Mar 2014 08:02:14 -0600
PSoC®3: CY8C38 Family Data Sheet: Programmable System-on-Chip (PSoC®) http://www.cypress.com/?rID=35178 Programmable System-on-Chip (PSoC®)

General Description

With its unique array of configurable blocks, PSoC® 3 is a true system level solution providing microcontroller unit (MCU), memory, analog, and digital peripheral functions in a single chip. The CY8C38 family offers a modern method of signal acquisition, signal processing, and control with high accuracy, high bandwidth, and high flexibility. Analog capability spans the range from thermocouples (near DC voltages) to ultrasonic signals. The CY8C38 family can handle dozens of data acquisition channels and analog inputs on every general-purpose input/output (GPIO) pin. The CY8C38 family is also a high-performance configurable digital system with some part numbers including interfaces such as USB, multimaster inter-integrated circuit (I2C), and controller area network (CAN).
 

Features

  • Single cycle 8051 CPU
  • Low voltage, ultra low-power
  • Versatile I/O system
  • Digital peripherals
  • Analog peripherals (1.71 V ≤ VDDA ≤ 5.5 V)
  • Programming, debug, and trace
  • Precision, programmable clocking
  • For more, see pdf
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Thu, 27 Mar 2014 07:57:17 -0600
VBUS Monitoring for Self-Powered Devices – KBA86920 http://www.cypress.com/?rID=93069 Answer: For a self-powered device design, you need to make sure that the device monitors VBUS and disables or enables the pull-up on the data line accordingly. A bus-powered design does not require VBUS monitoring because it cannot drive the bus when disconnected.

For the USB Full Speed (USBFS) component, there is an option to enable VBUS monitoring in the Configure ‘USBFS’ window (Figure 1). Please select the Advanced Tab and then check Enable VBUS Monitoring.

Figure 1. Enabling VBUS Monitoring

This will add a VBUS monitor pin to the design if the Internal VBUS option is selected. When the External VBUS option is selected, the Digital Input Pin Component should be placed on the schematic and must be connected to the VBUSDET input terminal. You can then use the API USBFS_VBusPresent() to determine VBUS presence for self-powered devices. Please check the Full Speed USB (USBFS) Component Datasheet for more on this API.

Figure 2 is a sample schematic on how to connect VBUS to a GPIO pin.

Figure 2. Connecting VBUS to a GPIO Pin

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Thu, 27 Mar 2014 03:58:50 -0600
Placing an Interrupt Routine – KBA86909 http://www.cypress.com/?rID=93068 Answer: For a Component that you place in the Workspace, you can see an interrupt file associated with the Component in the Workspace Explorer once you build the project. For example, in Figure1, a Delta Sigma ADC has been placed in the Workspace. Once you build the design, you can see the file ADC_DelSig_1_INT.c. When you open this file, you can see a function named CY_ISR( ADC_DelSig_1_ISR1). Please make sure that you write the ISR code between the # START and the # END tags. To enable the global interrupts, also make sure that CyGlobalIntEnable; inside the void main() is uncommented.

Figure 1. Interrupt File Associated With ADC

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Thu, 27 Mar 2014 03:56:34 -0600
Creating a Library Project as an Object Code – KBA90606 http://www.cypress.com/?rID=93024 Answer: You can create a code in the form of an object code in PSoC Creator. The steps below show how to create a library project and then use the library project in an application project without exposing the source code of the library project.

  1. Create a library project.

    Figure 1. Create a Library Project

  2. Click the Source tab in the PSoC Creator Workspace Explorer.

    Figure 2. Source Tab in Workspace Explorer

  3. Add the cytypes.h file under Header Files. Copy this file from “\Cypress\PSoC Creator\3.0\PSoC Creator\psoc\content\CyComponentLibrary\CyComponentLibrary.cylib\cy_boot_v4_0\PSoC3\API”. Note that the path may change depending on the version of the PSoC Creator and cy_boot Component. This file is needed because many of the data types (such as uint8) are defined in this file. This file uses the macro CY_PSOC3, but this macro value is defined only when you select the device as a specific family of PSoC (PSoC 3, PSoC 5LP, etc.). Since this is a library project, you do not select a device. You assign a value to this macro manually. If you are building the library for PSoC 3, then assign the macro CY_PSOC3 a value of “1”, and the other macros CY_PSOC4 and CY_PSOC5 a value of ”0”. Comment out the line #include in the cyfitter.h file, because the fitter file is generated only in the application project (which is a normal project and not a library project).

    Figure 3. The cytypes.h File

  4. Add the source code as multiple .c files under Source Files and write the source code.

    Figure 4. Source Code

  5. Create a header file that will include all the function prototypes and extern variables for the source code.

    Figure 5. Header File

  6. Build the library project. Build it in both debug and release modes so that the library is created for both debug and release modes.

    Figure 6. Release and Debug Modes

  7. Back up the library project as development code in your choice of location. Delete all the source code. Because the library is compiled in the previous step, you can delete the source. Do not delete the header file Header01.h, which contains all the function prototypes and extern declarations. At this point, the source code exists only in the form of object code. Because this library is now in object code form, it can be used in any application project without exposing the source code.

    Figure 7. Delete the Source Code

  8. Use the library in your application project. In your application project, add dependency to the library project.

    Figure 8. Dependency to the Library

  9. Copy the header file Header01.h into the application project’s folder (for example, “ApplicationProject.cydsn”). Add the header file to the application project. This is how the application project will obtain the function prototypes and the extern declarations.

    Figure 9. Copy the Header File into the Application Project

  10. Use the library functions in the application project. Just include the Header01.h file in the file where the library code is used.

    Figure 10. Use the Library

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Thu, 27 Mar 2014 02:18:37 -0600
Serial Number String – KBA89259 http://www.cypress.com/?rID=93018 Answer: The host will use the serial number string to identify the USB device internally. The serial number string can be enabled or disabled in the String Descriptor tab of the USBFS Component.

The use of the serial number string is optional. If the serial number string option is not enabled in the PSoC® Creator™ project, the descriptor file will not have a serial string in it. In this case the OS will assign its own serial string for the device based on the port where the device is connected. Consider the case of a device without a serial number string in the descriptor. When you connect the device to one of the USB ports, the OS will assign a serial number to the device. Now, if you disconnect the device and plug it into another port, the device will enumerate again, with another serial number string. This will not happen in a device with the serial number string enabled.

For the USBFS Component, you have three different options for the serial number string. If you choose User Entered Text, the user can choose the serial number string. If you choose User Call Back, the serial number string can be provided on run time by the application on the host. If you choose Silicon Generated Serial Number, the serial number string will be assigned based on the silicon ID stored in the register. This value will be different from device to device, but it is not guaranteed to be unique. Whenever you connect a device with a different serial string, the device will enumerate again.

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Thu, 27 Mar 2014 01:44:54 -0600
Management Data Input/Output (MDIO) Host Component – KBA89252 http://www.cypress.com/?rID=93014 Answer: It should work with the switch. However, this Component has not been tested with the Marvell switch. The MDIO Host Component is not yet an official release, and is not optimized. It has been tested with our MDIO Slave Component.

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Thu, 27 Mar 2014 01:27:23 -0600
PSoC® 3: CY8C34 Family Data Sheet: Programmable System-on-Chip (PSoC®) http://www.cypress.com/?rID=37804 Programmable System-on-Chip (PSoC®)

General Description

With its unique array of configurable blocks, PSoC® 3 is a true system level solution providing microcontroller unit (MCU), memory, analog, and digital peripheral functions in a single chip. The CY8C34 family offers a modern method of signal acquisition, signal processing, and control with high accuracy, high bandwidth, and high flexibility. Analog capability spans the range from thermocouples (near DC voltages) to ultrasonic signals. The CY8C34 family can handle dozens of data acquisition channels and analog inputs on every general-purpose input/output (GPIO) pin. The CY8C34 family is also a high-performance configurable digital system with some part numbers including interfaces such as USB, multimaster inter-integrated circuit (I2C), and controller area network (CAN). In addition to communication interfaces, the CY8C34 family has an easy to configure logic array, flexible routing to all I/O pins, and a high-performance single cycle 8051 microprocessor core. You can easily create system-level designs using a rich library of prebuilt components and boolean primitives using PSoC Creator™, a hierarchical schematic design entry tool. The CY8C34 family provides unparalleled opportunities for analog and digital bill of materials integration while easily accommodating last minute design changes through simple firmware updates.

Features

  • Single cycle 8051 CPU core
  • Low voltage, ultra low-power
  • Versatile I/O system
  • Digital peripherals
  • Analog peripherals ( 1.71 V ≤ VDDA ≤ 5.5 V)
  • Programming, debug, and trace
  • Precision, programmable clocking
  • For more, see pdf
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Wed, 26 Mar 2014 02:24:19 -0600
PSoC® 3: CY8C32 Family Data Sheet: Programmable System-on-Chip (PSoC®) http://www.cypress.com/?rID=39976 Programmable System-on-Chip (PSoC®)

General Description

With its unique array of configurable blocks, PSoC® 3 is a true system level solution providing microcontroller unit (MCU), memory, analog, and digital peripheral functions in a single chip. The CY8C32 family offers a modern method of signal acquisition, signal processing, and control with high accuracy, high bandwidth, and high flexibility. Analog capability spans the range from thermocouples (near DC voltages) to ultrasonic signals. The CY8C32 family can handle dozens of data acquisition channels and analog inputs on every general-purpose input/output (GPIO) pin.

Features

  • Single cycle 8051 CPU core
  • Low voltage, ultra low-power
  • Versatile I/O system
  • Digital peripherals
  • Analog peripherals (1.71 V ≤ VDDA ≤ 5.5 V)
  • Programming, debug, and trace
  • Precision, programmable clocking
  • For more, see pdf
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Wed, 26 Mar 2014 01:50:16 -0600
Receiving the Error “fmk.M0018” When Installing/Running PSoC<sup>®</sup> Creator™ – KBA88209 http://www.cypress.com/?rID=93211 Figure 1. PSoC Creator Error “fmk.M0018”

Answer: This error occurs because the temporary files created by Creator are not available in the proper format. You have to delete
these files by following these steps:

  1. Close Creator.
  2. Go to the following path:
    • For Windows 7: “C:\Users\[User Name]\AppData\Local\Cypress Semiconductor”
    • For Windows XP: "C:\Documents and Settings\[User Name]\Local Settings\Application Data\Cypress Semiconductor"
    • Note:
    • [User Name] is the name of windows user under which you are logged in on your system.
    • Enable hidden folders to go this location (check the steps ahead).
  3. Delete the folder “PSoC Creator”.
  4. Open Creator and it should start properly.

Steps to view a hidden folder:

  1. Go to "C: drive".
  2. Press Alt + T, and then click Folder Options.
  3. Click the View tab. Under Advanced settings, click Show hidden files and folders, and then click OK.
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Tue, 25 Mar 2014 06:17:46 -0600
PSoC 3 Known Problems and Solutions http://www.cypress.com/?rID=40741 Sat, 22 Mar 2014 04:44:20 -0600 Using a 20-bit Shift Register - KBA86923 http://www.cypress.com/?rID=92993 Answer: For the API ShiftReg_WriteData, the data type is determined by the Shift Register Length parameter. When you double-click the Shift Register Component, you can see the configuration window where you set the Length (bits) field (Figure 1). This parameter determines the length of the shift register in bits. Valid values are 2 through 32 bits. Here you can set the value to 20. Now, even if you specify the argument as a 32-bit value, the API ShiftReg_WriteData will take only the lower 20 bits and do the shift operation depending on the shift direction and shift_in input. You can also directly give the argument as a 20-bit value.

Figure 1. Setting the Length (bits) Field

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Wed, 19 Mar 2014 08:02:09 -0600
Long File Name (LFN) Support with the emFile Component of PSoC® 3 - KBA86941 http://www.cypress.com/?rID=92992 Answer: The libraries stored in the “emfilezip\LinkLibrary\PSoC3\Keil_PK51” folder are all built with LFN support. There is no need to rebuild them. The compile errors are caused by the missing FS_FAT_SupportLFN() function. This function is defined only in the PSoC 5 (ARM® Cortex™-M) version of emFile. You can use the __CC_ARM pre-defined compiler define to include the FS_FAT_SupportLFN() function only for ARM targets.

This workaround will allow you to create files with LFM support:

#if __CC_ARM
FS_FAT_SupportLFN();
#endif
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Wed, 19 Mar 2014 07:46:44 -0600
Difference between Full CAN and Basic CAN Mailbox - KBA86565 http://www.cypress.com/?rID=92991 Answer:

  • A Full CAN communication can be easily set up with the help of a GUI with a very limited amount of programming involved, whereas Basic CAN requires all the parameters to be set in the firmware.
  • Full CAN uses hardware for message filtering. Basic CAN requires the CPU to be interrupted every time a message is received to determine whether it should be accepted.
  • Full CAN can be used only for receiving a single type of message per mailbox, whereas Basic CAN configuration can accept messages with a range of identifiers per mailbox.
  • The random transaction rate (RTR) feature is available only for the mailbox that is set as Full CAN. Basic CAN does not have the RTR feature enabled.
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Wed, 19 Mar 2014 07:36:14 -0600
Modifying the Full CAN Mailbox’s Identifier in the Program - KBA86567 http://www.cypress.com/?rID=92990 Answer: Yes, it is possible to change the identifier of the Full CAN mailbox dynamically in the program. The identifier can be changed by writing to the CAN Tx Msg Identifier register. This is a 32-bit register that is used to store the identifier value.

When using a standard CAN, the most significant 11 bits of the CAN Tx Msg register will contain the Identifier value. So before writing to the CAN Tx Msg Register you have to shift it by 21 bits for the standard CAN. Similarly if you are using the Extended CAN, the MSB 29 bits contain the identifier value. In this case you have to shift by three bits before writing to the register.

You can write to the aforementioned register using the following functions.

When using standard Full CAN use:

CY_SET_REG32((reg32 *)&CAN_TX[mailbox].txid, (ID << 21u));

When using Extended Full CAN use

CY_SET_REG32((reg32 *)&CAN_TX[mailbox].txid, (IDE << 3u));

Where ID – standard 11 bit Identifier; IDE – Extended 29 bit Identifier

Thus using the above function will allow you to have more than eight Full CAN mailboxes.

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Wed, 19 Mar 2014 07:26:35 -0600
Routing an External Clock to PSoC<sup>®</sup> via GPIO with PSoC Creator™ – KBA90459 http://www.cypress.com/?rID=92989 Answer:

To use an external clock source, please follow these steps:

  1. Place a digital input pin in your top design.
  2. Draw a wire from that pin and give a name to that net.
  3. In the .cydwr window, go to Clocks tab and double-click Master Clock.
  4. A window named Configure System Clocks will open. In this, check the Digital Signal and click on the Browse button.
  5. Then select the net that you gave for the pin (clock input) previously and give the frequency and tolerance value.
  6. Now you can use this clock to derive any clock source.

For further information, please refer to the application note PSoC 3 and PSoC 5LP Clocking Resources.

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Wed, 19 Mar 2014 07:14:23 -0600
Including the Cortex Microcontroller Software Interface Standard (CMSIS) Library in a PSoC<sup>®</sup> Creator™ Project – KBA90457 http://www.cypress.com/?rID=92983 Answer: Here are the steps to follow to include the CMSIS library in your project:

  1. Copy the CMSIS library into your project’s directory.
  2. In Creator’s Workspace Explorer, right-click your project and select Build Settings > Compiler > General. In Additional Include Directories, add the path of the “include” folder of the CMSIS library, as shown in Figure 1.
  3. In the same window, add ARM_MATH_CM3 to Preprocessor Definitions, as shown in Figure 1.

    Figure 1. Compiler Settings

  4. In the same window, please go to Linker > General and add Additional Libraries as m, as shown in Figure 2. Apply changes and close the window.

    Figure 2. Linker Settings

  5. In the arm_math.h file, add this line: include
  6. Right-click Source Files in Workspace Explorer, select Add > Existing Item, and add all the necessary source files that you are using.

    Now, the project will build.

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Wed, 19 Mar 2014 07:02:04 -0600
Steps to Achieve the Maximum Possible Baud Rate for the UART in PSoC® 3, PSoC 4, and PSoC 5LP - KBA90461 http://www.cypress.com/?rID=92986 Answer: To operate at the maximum baud rate (without an external clock), do the following:

  1. Enable the USB clock and configure it as IMO*2 (internal main oscillator (IMO) as 24 MHz).
  2. Now, the IMO will have only 0.25% tolerance as it is synchronized to the USB clock.
  3. Use the IMO as the clock source for the UART transmitter and receiver

For a given baud rate, the UART clock should be the oversampling rate times the baud rate (bits per second). It is possible to achieve a maximum baud rate of 6 Mbps for an oversampling rate of eight.

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Wed, 19 Mar 2014 06:54:33 -0600
Bit Addressability of GPIO Pins in PSoC® 3 - KBA88236 http://www.cypress.com/?rID=40700 Answer: Similar to 8051 code, PSoC 3 offers the flexibility to address the port pins individually. Access a specific bit using the SFR(Special Function Register) register area. The Keil compiler provides the keyword “sbit,” which is used for bit access of the SFR. Note that the sbit can be used only for the SFR registers.

For example:

To access the pin PRT1.7, define the SFR bit as follows:

sbit bit_led=SFRPRT1DR^7; // This makes the PRT1.7 bit addressable

Now, the bit can be set or cleared using the following code.

bit_led = 1; // Set the bit
bit_led = 0; // Clear the bit

There is an alternate way of doing this using the SETB command. This is an assembly command so you will need to use an inline assembly method to include it:

#pragma asm
SETB bit_led ; Set the bit
CLRB bit_led ; Clear the bit
#pragma endasm

In order to make sure that the GPIO is controlled using the SFRs, set the SFRPRTxSEL register’s bit corresponding to the pin that is being accessed to one. In the foregoing case, bit 7 of SFRPRT1SEL would be set to one in order to access PRT1.7, as shown here:

SFRPRT1SEL |= 0x80; // This makes the PRT1.7 controllable through SFRs

Refer to the Knowledge Base Article “Using Assembly Language for PSoC 3 in PSoC Creator” for the settings required to enable inline assembly.

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Wed, 19 Mar 2014 06:44:21 -0600
AN78175 - PSoC<sup>®</sup> 3 and PSoC 5LP - IEC 60730 Class B Safety Software Library http://www.cypress.com/?rID=61356 Library routines and examples in the example project can be directly integrated with the end user?s application. This application note also describes the API functions that are available in the Library.

The International Electrotechnical Commission (IEC) has developed safety standard IEC 60730-1 that discusses mechanical, electrical, electronic, environmental endurance, EMC, and abnormal operation for home appliances.

This application note focuses on Annex H Class B: Requirements for Electronic Controls. This portion of the standard details test and diagnostic methods to ensure safe operation of embedded control hardware and software for home appliances.  


Project
Device
PSoC Creator
Version
Development Kit
CY8CKIT-xxx
Compiler
Architecture
Silicon
Revision
V2.2 SP1
or higher
V2.1 SP1/
V2.1
001
DVK
030/050
DVK
003/014
FTK
Keil
GCC
RVDS
MDK

AN78175.zip

Prod
YES
NO
YES
YES*
NO
YES
N/A
N/A
N/A
Prod
YES
NO
YES
YES*
NO
N/A
YES
YES
YES
AN78175_Archive.zip
ES3, Prod
NO
YES
YES
YES*
NO
YES
N/A
N/A
N/A
ES1, Prod
NO
YES
YES
YES*
NO
N/A
YES
YES
YES

*Refer to Migrating CY8CKIT-001 DVK project to CY8CKIT 030/ 050

Notes:
  1. Click on AN77835 - PSoC® 3 to PSoC 5LP Migration Guide to learn differences between PSoC 3 and PSoC 5LP.
  2. For PSoC 5 project and related document, please download file AN78175_Archive.zip.

Projects associated with this application note can be downloaded from the 'Related Files' section below. For your convenience, we have provided projects that are compatible with the two most recent versions of PSoC Creator:

  • AN78175.zip is used with PSoC Creator 2.2 SP1
  • AN78175_Archive.zip is used with PSoC Creator 2.1 SP1/2.1

The project’s default settings may not be compatible with your device or kit, and you may need to change your project settings. For more information, see:

PSoC® 3, PSoC 4 and PSoC 5LP AN Project File Naming Convention and Use
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Tue, 18 Mar 2014 01:29:50 -0600
External Memory Interface (EMIF) Support in PSoC® 3 / PSoC 5LP - KBA88199 http://www.cypress.com/?rID=38590 Answer: The EMIF supports four types of external memory: synchronous SRAM, asynchronous SRAM, cellular RAM/PSRAM, and NOR Flash. The following are the main features of the EMIF:

  • The EMIF component enables access by the CPU or DMA to memory ICs external to the PSoC® 3/5LP.
  • EMIF memory can be 8- and16-bit data bus width and 8-, 16-, and 24-bit address bus width.
  • For PSoC 3, the EMIF XDATA Data Address Map ranges from 0x800000 to 0xFFFFFF; for PSoC 5LP, the EMIF Memory Address Map ranges from 0x60000000 to 0x61FFFFFF.
  • The EMIF also supports a custom interface apart from standard asynchronous and synchronous interfaces.
  • Code cannot be executed from the EMIF in PSoC 3, while it is possible in PSoC 5LP. However, it is difficult to initialize code in external memory. In general, having code in external memory is not recommended.

There is an example project associated with the EMIF component, which can be opened from PSoC Creator™ > File > Open > Example Project. Select EMIF in Keyword #1. This project was performed with an asynchronous SRAM on a prototype QVGA board. You can also find the necessary documentation along with this project.

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Mon, 17 Mar 2014 01:44:32 -0600
Acceptance Filter Implementation for CAN Receive Message - KBA86566 http://www.cypress.com/?rID=92894 Answer: Yes, it is possible to receive messages from a group of identifiers in one mailbox.

There are 16 mailboxes. Once a CAN message is received, it is compared with the acceptance filter of the mailboxes and the accepted message is stored in the corresponding mailbox. The acceptance filter is configured by the Acceptance Mask Register (AMR) and the Acceptance Code Register (ACR). AMR defines whether the respective incoming bit is compared to the respective bit in the ACR. If a bit in the AMR is “0”, then the corresponding bit in the ACR is compared to the corresponding bit that is received. If the bit in AMR is “1”, then the corresponding bit in ACR is not compared to the bit that is received.

A mailbox can be configured to receive messages from a group of identifiers by writing to the registers corresponding to the AMR and ACR filter of that mailbox. In PSoC® 3 implementation the AMR and ACR are 32-bit registers. In case of a standard CAN, the most significant 11 bits of the AMR and ACR register store the filter values. In case of an extended CAN, the most significant 29 bits store the filter values.

For example, if you want to receive messages with an identifier from 100h to 1FFh in mailbox 0, then AMR and ACR should be set as shown in Figure 1. The following code has to be added in the program:

/* Sets the AMR value for RX buffer 0 */
CAN_RXRegisterInit((uint32)CAN_CanIP__RX0_AMR, 0x1ffffff9);

/* Sets the ACR value for RX buffer 0 */
CAN_RXRegisterInit((uint32)CAN_CanIP__RX0_ACR, 0x20000000);

Figure 1. Setting AMR and ACR

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Mon, 17 Mar 2014 01:24:21 -0600
Application or Script to Program PSoC® - KBA88207 http://www.cypress.com/?rID=92892 Answer:

  1. Example projects in various languages (C#, C++, Perl, and Python) are available in the PSoC Programmer™ setup folder. The path for the example projects is “[Programmer installation folder]\[Version of Programmer]\Examples\Programming\”. The default path for the examples is as follows.
    1. For 32-bit operating systems, the default path is:
      “C:\Program Files\Cypress\Programmer\[Version Of Programmer]\Examples\Programming\”
    2. For 64-bit operating systems, the default path and command is:
      “C:\Program Files (x86)\Cypress\Programmer\[Version Of Programmer]\Examples\Programming\”

      Note: [Version of Programmer] is the version installed on your machine, like 3.17 or 3.18 or 3.18.1.
      The default path of the “Examples” folder for 64-bit machines and Programmer 3.18 is:
      “C:\Program Files (x86)\Cypress\Programmer\3.18\Examples\Programming\”
  2. In this folder you will find example projects for PSoC 1 or for PSoC 3, PSoC 4, or PSoC 5LP. Go to the specific folder and check for the programming language that you want to work with.
  3. For documents regarding the commands, refer to psoc_programmer_com.pdf, available at "[Programmer installation folder]\3.18.1\Documents".
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Mon, 17 Mar 2014 00:45:13 -0600
Mobile Industry Processor Interface (MIPI) Support in PSoC® 3/5LP - KBA89017 http://www.cypress.com/?rID=92891 Answer: As of now, there are no plans to support MIPI in PSoC 3/5LP.

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Mon, 17 Mar 2014 00:31:43 -0600
Renaming the TopDesign.cysch File of a PSoC® Creator™ Project - KBA89006 http://www.cypress.com/?rID=92890 Answer: No, it is not possible to rename the TopDesign.cysch file in any PSoC Creator project.

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Mon, 17 Mar 2014 00:22:35 -0600
Viewing Data in Management Data Input/Output (MDIO) Registers – KBA89251 http://www.cypress.com/?rID=92729 Answer: Check the MDIO component to determine to which REGISTER_SPACE the address belongs. Once you know this, calculate the index needed to access the register by subtracting the initial address of that REGISTER_SPACE from the address in question. Arrays are defined in the MDIO_SLAVE_REG.c file.

For example, assume you want to view the address 0x8205. If the REGISTER_SPACE_3 starts at 0x8200 and ends at 0x8206, you know that 0x8205 belongs to REGISTER_SPACE_3. The index is 0x8205 – 0x8200 = 5.

Now go to MDIO_SLAVE_REG.c and check the REGISTER_SPACE_3 array, which is:

uint16 MDIO_SLAVE_registerPage_3[MDIO_Slave_REG_PAGE_3_SIZE];

Add the MDIO_SLAVE_registerPage_3[5] in the Watch window of the debugger. Now you can see whether the content of this address is changing.

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Wed, 12 Mar 2014 07:38:07 -0600
Multiple Applications Based on CyUSB.dll Hang On Disconnection of a Device Communicating with One of Them – KBA89229 http://www.cypress.com/?rID=92722 Answer: The cause of the problem is that both of the applications call the event handler corresponding to the disconnect event. The solution is to check in the event handler which device was disconnected.

This problem occurs because both devices are attached to the CyUSB.sys driver. The driver reports a disconnect event when either one of the devices attached to it is disconnected, calling the handler for the disconnect event. So when you disconnect a device communicating with the first application, the second application still executes the event handler for a disconnect event.

You should check in the event handler in the application if the disconnected device is the one that it was communicating with. If you don’t check, the application will execute further commands as if its device is now disconnected, which will halt, or hang, the communication.

Here is an example of the device removed event handler:

void usbDevices_DeviceRemoved(object sender, EventArgs e)
{
  USBDevice dev = usbDevices[0x04B4, 0x1004]; // if MyDevice is still connected do not stop the communication.
  if (dev == null)
  {
    MyDevice = null;
    EndPoint = null;
    SetDevice();
  }
}
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Wed, 12 Mar 2014 06:47:24 -0600
Issue while Debugging a PSoC<sup>®</sup> 3/5 USB Firmware – KBA89230 http://www.cypress.com/?rID=92721 pre { padding:0px; }

Answer: This is happening due to the following issue with the ISRs: PSoC sends the descriptors using ISRs. These ISRs are not executed if the PSoC CPU is halted for debugging. Thus, when the PC sends a control request for the descriptors, they are not serviced by the PSoC CPU, which leads to failed enumeration.

To solve this problem: When using the Debug mode in PSoC, the PSoC CPU should be run freely until the device is recognized by the USB host (when the firmware exits the while(!USBFS_1_GetConfiguration()); condition).

The code snippet in the firmware will look like this:

 

void main()

{

 int i,index=0;

 /* Enable Global Interrupts */

 CyGlobalIntEnable;

 /* Start USBFS Operation with 3V operation */

 USBFS_1_Start(0u, USBFS_1_3V_OPERATION);

 /* Wait for Device to enumerate */

 while(!USBFS_1_GetConfiguration());

 /* Enumeration is done, enable OUT endpoint for receive data from Host */

 USBFS_1_EnableOutEP(OUT_EP);

...

Here, PSoC can be run step-by-step until the API USBFS_1_Start(). When this API is called it connects the pull-up resistor to the D+ data line, which makes the PC detect the device. After this API, the firmware should be executed freely with a breakpoint on the firmware statement:

USBFS_1_EnableOutEP(OUT_EP);

As this API is hit, you will see that the USB host has detected the PSoC device. Now, you can do the transactions with USBFS while debugging.

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Wed, 12 Mar 2014 06:26:10 -0600
Problem in Sending 64 bytes / Maximum Payload Size Packet in USBUART Component – KBA89052 http://www.cypress.com/?rID=92719 Answer: When you send data in maximum payload size packets, no data is seen on the serial port application because the data is stored in the application data buffer. As per the USB specification, when the packets are sent with maximum payload size, the USB host considers the transfer complete only when it receives a short-length packet (packet of length less than the maximum payload size) or zero-length packet at the end of the transfer.

Any serial port application will not display the received data until the transfer is finished, or the application’s data buffer overflows. This is what happens when you continuously send maximum packet size data to the serial port application. After the application data buffer gets full, the application displays the last received data on the terminal and stores the new data in the buffer. This leads you to think that the data is accepted when you continuously send maximum packet size data, but not accepted when you send only a few packets with data of maximum payload size.

To solve the problem: If the data to send has length that is equal to or a multiple of the maximum payload size, send a last zero-length /short length packet to end the transfer. Use the PutString() API to send a zero length packet at the end of the transfer by keeping the length argument as zero.

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Wed, 12 Mar 2014 06:01:16 -0600
High Signal on Compare Output When Period Is Changed in Firmware – KBA89231 http://www.cypress.com/?rID=92715 Answer: You will see this error if you load the period register with a value lesser than the previous period value when the count register value is greater than the new period. When Clock Mode is set to Up Counter and Reload Counter is set to On TC, the counter value is reloaded with "0" when it overflows. However, when the new period value is less than the currently running count register value (which is less than the old period value), the counter will count up to ((2^Resolution)-1) and then reload to 0—for example:

Default period = 0x09;

Counter: 0x00 0x01 0x02 0x03 0x04 0x05 0x06 (set new period = 0x05) 0x07 0x08 0x09 (here the counter should be reloaded by "0", but the counter will count up to
((2^Resolution)-1)) 0x0A 0x0B 0x0C … ((2^Resolution)-1) 0x00.

In the Up Counter mode, you should disable the counter before writing the new period value. After that, you should set the count register to "0" and enable the counter. Or you can set Clock Mode to Down Counter to avoid this situation.

Thus, instead of using the following code snippet:

Counter_WritePeriod(40); // Suppose previous value was 100

You should use this one:

Counter_WriteControlRegister(Counter_ReadControlRegister() & ~(Counter_CTRL_ENABLE)); // disable counter

Counter_WritePeriod(40); // write new value of period

Counter_WriteCounter(0); // set counter value to zero

Counter_WriteControlRegister(Counter_ReadControlRegister() | Counter_CTRL_ENABLE); // enable counter

This component issue is being worked on.

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Wed, 12 Mar 2014 05:48:34 -0600
IEC 60730 Safety Standard for Household Appliances http://www.cypress.com/?rID=91719 The International Electro-technical Commission (IEC) has developed safety standard IEC 60730 that discusses mechanical, electrical, electronic, environmental endurance, EMC, and abnormal operation for home appliances.

The IEC 60730 standard classifies appliance software into three categories:

  • Class A - Control functions that are not intended to be relied upon for the equipment's safety such as humidity controls, lighting controls, timers, and switches.
  • Class B - Control functions that are intended to prevent unsafe operation of the controlled equipment such as thermal cut-offs and door locks for laundry machines.
  • Class C - Control functions that are intended to prevent special hazards. Examples are automatic burner controls and thermal cut-outs for closed, unvented water heater systems.

Major home appliance products, such as washing machines, dishwashers, dryers, refrigerators, freezers, and cookers/stoves, tend to fall under the Class B classification. An exception is an appliance that might cause an explosion, such as a gas-fired controlled dryer that falls under Class C.

Cypress has developed safety features, including IEC 60730 Safety Library along with application notes to help manufactures meet the regulation with PSoC devices.

Application Notes:


Certification Reports:

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Wed, 12 Mar 2014 04:01:19 -0600
Eliminating Multiple Button Clicks while Programming – KBA89459 http://www.cypress.com/?rID=90635 Answer: You can choose settings for Debug Select in PSoC Creator that will control whether you are prompted with Port Acquire. PSoC Creator will ask you to click ‘Port Acquire’ every time you program in the following situations:

  1. If you have selected GPIO as the Debug Select option (see System tab in the .cydwr window)
  2. If you have checked the ‘Enable Device Protection’ option

PSoC Creator does this because you cannot access the internal Debug Access Port (DAP), but to program the chip, you need to gain access to that port. DAP allows the programmer to write the data into a buffer, whose contents will be written into the flash eventually. Refer to programming specifications available at http://www.cypress.com/?docID=44489, http://www.cypress.com/?docID=43528, and http://www.cypress.com/?docID=41080 for PSoC 3, PSoC 4 and PSoC 5LP, respectively.

Clicking the ‘Port Acquire’ button when selecting the target for programming sends a key to the chip and allows the programmer to communicate with the DAP.  In this case, you can only program the chip, not debug it. This ensures that your firmware is not available to others after final production. For programming, use PSoC Programmer™ 3.20.0, which is available at http://www.cypress.com/?rID=38050.

But if the Debug Select is set as SWD/JTAG, then you do not need to send a key to access the internal port. Therefore, you will not need to click ‘Port Acquire’ each time.

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Tue, 11 Mar 2014 05:20:11 -0600
PSoC® 3/5 USBUART: Message to HyperTerminal When a COM Port Is Opened - KBA89227 http://www.cypress.com/?rID=92672 Answer: Bind the USBUART device to the standard Communications Device Class (CDC) driver of Windows®. When you use the terminal to open a COM port on the PC, a SET_LINE_CODING command is sent from HyperTerminal.

In the firmware, you can loop to wait for a SET_LINE_CODING command. Multiple such requests can be sent from the host based on which application and driver are being used. This approach is useful when using HyperTerminal with the standard drivers.

The following code snippet implements this approach, and can be used when using the USBUART component and its generated APIs:

while(Flag)

{  
	state = USBUART_1_IsLineChanged();
	if (state & USBUART_1_LINE_CODING_CHANGED)
	{
	sprintf(&buffer, "Program starts\n\r");
	while(USBUART_1_CDCIsReady() == 0u); /* Wait till component is ready 
                                              to send more data to the PC */
	count = strlen(&buffer);
	USBUART_1_PutData(buffer, count);
	Flag = 0;
	}
}
]]>
Tue, 11 Mar 2014 02:19:09 -0600
Using a Sheet Connector in PSoC<sup>®</sup> Creator™ – KBA85341 http://www.cypress.com/?rID=46340 Answer: A sheet connector connects Components without necessarily using a wire, across multiple pages in a schematic. It can also be used to simplify the process of connecting a Component output to multiple Component inputs. You may find the sheet connector in the left pane of the TopDesign.cysch file. Refer to Figure 1.

Figure 1. Sheet Connector Icon in PSoC Creator

The following example shows you how to use a sheet connector:

There is an input pin (Pin_2) in “Page 2” of the TopDesign schematic (refer to Figure 3) and there is an AND gate in “Page1” of the TopDesign schematic (refer to Figure 2). You will connect Pin_2 from Page 2 to the AND gate’s input in Page 1.

To do so, initially place a wire on the AND gate’s input where you wish to connect Pin_2. Click the sheet connector icon as shown in Figure 1. Place this icon on the wire at the AND gate’s input as shown in Figure 2. Right-click the wire connected to the AND gate. A dialog box appears where you click Edit Name and Width. Give a particular name to the wire—say, “Input_2”. Select the width as “1”. Likewise, place a wire in Page 2 with Pin_2 and connect it to a sheet connector icon. Right-click the wire in Page 2 and give the same name as given to the sheet connector’s wire in Page 1—that is, “Input_2”—and give the width as “1”.

The above operations are equivalent to placing Pin_2 in Page 1 of the TopDesign schematic and connecting it directly to the AND gate. By following this method, you can route the input from Pin_2 to different Components placed in different pages in the TopDesign schematic file.

Figure 2. Page 1 of the TopDesign Schematic Where the AND Gate Is Placed

Figure 3. Page 2 of the TopDesign Schematic Where the Second Pin
Required for the AND Gate Is Placed

]]>
Mon, 10 Mar 2014 04:57:42 -0600
The Status of CAN Tx and Rx Lines When No CAN Transceiver IC Is Connected – KBA90988 http://www.cypress.com/?rID=92637 Answer: You will not see any traffic on the CAN Tx and Rx lines of PSoC® 3 and PSoC 5LP, if there is no external CAN transceiver IC on the board. In CAN protocol, after transmitting each bit into the bus, every node checks if the bus state is the same as the bit it transmitted. If they are the same, the node continues with the transmission of the next bit; if they are different, the node stops transmitting and starts to receive the message on the bus. So, if you do not connect the transceiver IC, the node will not see the same bit that it has transmitted on the Rx pin since there is no loop back. So it will stop transmitting.

For development purposes Cypress offers the CY8CKIT-017, which has the transceiver IC and the necessary termination resistors. Figure 1 shows the physical connections between the PSoC 3/5 DVK and 017 kit for CAN communication.

Figure 1. Connections between the PSoC 3/5 DVK and 017 Kit for CAN Communication

If you are making a custom board, you can use any of the CAN transceiver ICs, such as the TJA1050 or SN65HVD1040. Note that some transceivers have a standby (STB) pin, which keeps the device in receive mode only to save power. Do not assert this pin for normal CAN communication.

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Mon, 10 Mar 2014 02:16:37 -0600
AN66627 - PSoC® 3 and PSoC 5LP Intelligent Fan Controller http://www.cypress.com/?rID=49077 The Fan Controller Component, available in PSoC Creator™, helps manage the fans in a variety of configurations. This application note also shows how to combine fan control and temperature sensing to create a complete thermal management solution using PSoC 3 and PSoC 5LP.

The projects provided with this application note use the Fan Controller component provided as part of PSoC Creator 3.0 Component Pack 7 software. The software is available for download at http://www.cypress.com/psoccreator/.

The following table provides the list of devices, the supported Creator version, Development kit and Compiler for this application note project:


Project

Device
PSoC Creator
Version
Development Kit
CY8CKIT-xxx
Compiler
Architecture
Silicon
Revision
V3.0 CP7
or higher
V2.2
001
DVK
030/050
DVK
003/014
FTK
Keil
GCC
RVDS
MDK

AN66627.zip

Prod
YES
NO
YES
YES*
NO
YES
N/A
N/A
N/A
Prod
YES
NO
YES
YES*
NO
N/A
YES
YES
YES

* Refer to Migrating CY8CKIT-001 DVK project to CY8CKIT 030/ 050.


Projects associated with this application note can be downloaded from the 'Related Files' section below. For your convenience, we have provided projects that are compatible with the most recent version of PSoC Creator:

  • AN66627.zip is used with PSoC Creator 3.0 CP7

The project’s default settings may not be compatible with your device or kit, and you may need to change your project settings. For more information, see:

PSoC® 3, PSoC 4 and PSoC 5LP AN Project File Naming Convention and Use
]]>
Mon, 10 Mar 2014 00:40:11 -0600
PSoC Creator Training http://www.cypress.com/?rID=40547 PSoC 3 and PSoC 5 Workshops:

Introduction to PSoC 3
This half day workshop will give you hands-on experience using and developing PSoC3 and PSoC5 solutions utilizing Cypress's PSoC® Creator™ Software development environment and the PSoC Development Kit (CY8CKIT-001)

Introduction to PSoC 5
This half day workshop will give you hands-on experience using and developing PSoC 5 solutions utilizing Cypress's PSoC® Creator™ Software development environment and the PSoC Development Kit (CY8CKIT-001)

PSoC 3 and PSoC 5 Intermediate Workshop
This full day workshop provides in depth training on how to use the high precision and programmable analog, programmable digital and advanced CPU subsystems in your embedded designs. This workshop builds off of the first, half-day, Introduction to PSoC 3 and PSoC 5 Workshop and provides more in depth and hands-on training for you to fully understand these features and how to use them with the PSoC Creator integrated development environment.

-->
PSoC Videos:

PSoC Creator: Made for Engineers
Meet Alan Hawse, Executive Vice President of Software for Cypress, and his vision for PSoC Creator.

PSoC Today! Introducing PSoC 4 Part I
Special Guest Max Kingsbury kicks off a series introducing the PSoC 4 and the Pioneer kit.

PSoC 5LP Analog Design
Jim Davis, Product Marketing Manager for PSoC, introduces you to the analog design methodology of PSoC and PSoC Creator

For more PSoC videos visit our video library at video.cypress.com

PSoC On-Demand Training:

PSoC 3 and PSoC 5 101: Introduction to the Architecture and Design Flow
PSoC 3 and PSoC 5 102: Introduction to System Resources
PSoC 3 and PSoC 5 103: Introduction to Digital Peripherals
PSoC 3 and PSoC 5 104: Introduction to Analog Peripherals
PSoC 3 and PSoC 5 201: Analog Peripherals II
PSoC 3 and PSoC 5 106: CapSense Touch Sensing

Getting Started

Using the UDB Editor

Component Creation Tutorials


Component Development Training For PSoC using PSoC Creator

PSoC Creator 110: Schematic Components
PSoC Creator 111: Component Parameters
PSoC Creator 112: Intro to Component API Generation
PSoC Creator 113: PLD Based Verilog Components
PSoC Creator 210: Intro to Datapath Components
PSoC Creator 211: Datapath Computation
PSoC Creator 212: Datapath FIFOs
PSoC Creator 213: Multi-Byte Datapath Components
PSoC Creator 214: Datapath API Generation
PSoC Creator: Custom Components
]]>
Mon, 10 Mar 2014 00:38:47 -0600
PSoC Creator Software Archive http://www.cypress.com/?rID=39551 Announcing: PSoC Creator 1.0 Service Pack 2 Now Available for Download!

-->

NOTE: This version of PSoC Creator is no longer recommended for new designs. Please use the latest version of PSoC Creator which can be obtained by visiting: www.cypress.com/go/psoccreator


The Service Pack 2 release is an update to 1.0 Production. Note that the installer supports archived releases – it defaults to Production but allows you to pick any previous version by selecting a Custom installation. This release supports production designs on PSoC 3 and continues to support development on pre-production silicon revisions; PSoC 3 (ES2) and PSoC 5.

PSoC Creator 1.0 supports the PSoC 3 (CY8C3x) and PSoC 5 (CY8C5x) families. Please refer to the release notes for details.

Minimum Configuration

The following minimum configuration is required for installation of the PSoC Creator application.

      PC running Windows operating system - Windows 7, XP or Vista (32- or 64-bit)

      2GHz CPU

      2 GB memory

      1 GB of hard disk space

      USB 2.0


PSoC Creator Training
 

Need help downloading/installing? Call 1-800-541-4736 and select 8.
]]>
Mon, 10 Mar 2014 00:16:30 -0600
Multiple Slave Addresses with EZI2C – KBA88258 http://www.cypress.com/?rID=92546 Answer: Yes. You can have up to four slave addresses, two for each EZI2C component. Each EZI2C component can support a maximum of two slave addresses and uses one fixed-function I2C block in PSoC 3 and PSoC 5LP. Because there are two hardware blocks in PSoC 3 and PSoC 5LP, you can place a maximum of two EZI2C components in your project. This supports up to four slave addresses. If you need additional slave addresses for your application, you can also select an I2C slave (UDB). However, there are differences between EZI2C and I2C. Figure 1 shows an EZI2C component, and Figure 2 shows its configuration window. 

Figure 1. EZI2C Connected to the Pin

EZI2C connected to pin

Figure 2. The EZ12C Configure Window

EZI2C configure window

]]>
Fri, 07 Mar 2014 04:45:36 -0600
Operating Systems Supported by PSoC® Creator™ and PSoC Programmer™ – KBA88171 http://www.cypress.com/?rID=38522 Answer: Please refer to the tool’s release notes on the software download page for the latest information.

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Thu, 06 Mar 2014 04:06:30 -0600
AN60630 - PSoC® 3 - 8051 Code and Memory Optimization http://www.cypress.com/?rID=40986 This can result in smaller code size in flash memory, as well as faster code. The efficiency gains can be realized without writing any 8051 assembler code. Instead, keywords for the Keil 8051 C compiler are used. Several coding techniques are shown.

The following video describes how you can optimize your design and eliminate time-consuming code work in your next PSoC 3-based project.

 

 

]]>
Wed, 05 Mar 2014 00:09:12 -0600
AN61290 - PSoC® 3 and PSoC 5LP Hardware Design Considerations http://www.cypress.com/?rID=43337 Introduction

PSoC® 3 and PSoC 5LP devices provide tremendous power and flexibility for analog and digital applications, beyond what traditional MCUs offer. However, this flexibility raises new considerations when designing a PSoC device into a printed circuit board (PCB).

When designing a PCB for PSoC 3 or PSoC 5LP, considerations to keep in mind include proper connections for device power, reset, crystal, programming, and other pins. Good board layout techniques are also important, especially for precision analog applications. Finally, the PSoC 3 or PSoC 5LP device must be configured to work optimally in its hardware environment – the PSoC Creator™ IDE is used for this purpose.

This application note provides information on each of these topics, to help you to successfully design PSoC 3 or PSoC 5LP devices into a PCB and hardware environment.

]]>
Tue, 04 Mar 2014 23:57:53 -0600
AN89611 - PSoC® 3 and PSoC 5LP – Getting Started with Chip Scale Packages (CSPs) http://www.cypress.com/?rID=90919 Introduction

Cypress is now offering its PSoC 3 and PSoC 5LP family of products in wafer-level chip scale packages (WLCSPs, or CSPs for short). These devices are designed to pack the maximum mixed-signal SoC capability per cubic millimeter. They feature package sizes as small as 4.25 × 4.98 × 0.6 mm to fit into tiny spaces on very small PCBs or flexible printed circuits (FPCs). However, their small size mandates special manufacturing techniques and design considerations.

]]>
Tue, 04 Mar 2014 23:44:32 -0600
CY8CKIT-023 PSoC® MFi (Made for iPod | iPhone | iPad) Expansion Board Kit http://www.cypress.com/?rID=40218 This development kit is now obsolete. For other related made for iPod (MFi) products please see the CY8CKIT-033 for more information.


The ultimate development platform for electronic accessories that connect to iPod, iPhone and iPad

CY8CKIT-023 Kit

 

Designed for use with the CY8CKIT-001 PSoC Development Kit, CY8CKIT-030 PSoC 3 Development Kit or CY8CKIT-050 PSoC 5 Development Kit (sold separately).

Cypress’s PSoC® programmable system-on-chip architecture gives you the freedom to not only imagine revolutionary new accessories for iPod, iPhone and iPad devices, but also the capability to get those accessory products to market faster than anyone else. Utilize Cypress’s EA Console iOS app and corresponding example project that comes with the CY8CKIT-023 PSoC MFi (Made for iPod | iPhone | iPad) Expansion Board Kit to jump-start development with the External Accessory framework, enabling communication between apps and accessories attached to an Apple device. Also, explore PSoC’s configurability and flexibility when used in conjunction with other expansion boards to create accessories for a myriad of markets.

The CY8CKIT-023 PSoC MFi Expansion Board Kit is available only to licensees of Apple's MFi program, through Apple’s authorized MFi component distributor.

For more information on the MFi program, visit http://developer.apple.com/MFi.
  
Kit Contents


  • CY8CKIT-023 MFi Expansion Board
  • Quick Start Guide
     

Software Prerequisites



Software Title Description Link
PSoC Creator This kit requires PSoC Creator for development
PSoC Programmer This kit requires PSoC Programmer for programming
]]>
Tue, 04 Mar 2014 02:37:13 -0600
CY8CKIT-030 Does Not Display Voltage If the Potentiometer Is Varied – KBA90252 http://www.cypress.com/?rID=60161 Answer: CY8CKIT-030 is factory-programmed with a project called “Voltage Display.” The project measures the potentiometer voltage and displays it on the LCD. Unfortunately, some of the CY8CKIT-030 kits are factory-programmed with a different project that is used for manufacturing testing. At the time of shipping it was overlooked.

If you have received one of these kits, you will notice that the kit will not have a “Voltage Display” project when used out of the box as shown in the Quick Start Guide.

Fortunately, there is no hardware issue with the kit. Please reprogram the board with CY8CKIT-030_QuickStart.hex using PSoC® Programmer™, as shown in Figure 1. The “Voltage Display” project also is provided with the kit software, and it can be found at this location: “<Installation Path>\Cypress\PSoC 3 Development Kit\<version>\Firmware”.

Figure 1. PSoC Programmer Settings for Programming the HEX File

psoc_programmer

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Mon, 03 Mar 2014 03:46:08 -0600
Differences between CY8CKIT-030 and CY8CKIT-030A Development Kits - KBA89429 http://www.cypress.com/?rID=91900 Answer: These are the key differences between CY8CKIT-030 and CY8CKIT-030A:

  • An electrical overstress (EOS) protection circuit is in CY8CKIT-030A. EOS is the thermal damage that may occur when an electronic device is subjected to a current or voltage beyond its specification limits.
  • Extra headers and a breadboard are in CY8CKIT-030A.
  • Potentiometer is changed for better analog performance.
  • An updated CD with PSoC® Creator™ 2.2 is shipped with CY8CKIT-030A.
]]>
Tue, 18 Feb 2014 07:39:11 -0600
Using the Emulated EEPROM Component in a Bootloadable Project - KBA89149 http://www.cypress.com/?rID=91898 Answer: The Emulated EEPROM Component emulates an EEPROM device in the flash memory of PSoC, providing simplified access to nonvolatile memory. You can use this Component to update flash in the bootloadable project.

When PSoC 3, PSoC 4 or PSoC 5LP boots up, the bootloader code tests the checksum of the bootloadable code. If the checksum does not match the stored value corresponding to the original download of the bootloadable project, the bootloader does not transfer control to the bootloadable project. Because the Emulated EEPROM Component can update flash, the bootloadable project checksum may no longer match and the bootloadable project does not execute.

To work around this, you can use the following feature available in PSoC Creator™. In the project, double-click the Bootloader Component configuration window and select the check box called Fast bootloadable application validation. When this parameter is enabled, the bootloader calculates the flash checksum only once when the new bootloadable code (application code) is downloaded. Then, a nonvolatile flag is set to indicate that the checksum matches, so that the bootloader does not compute the checksum on further resets. This gives the application code the freedom to update the flash using Emulated EEPROM.

Figure 1. Bootloader Component Configuration Window

KBA89149

]]>
Tue, 18 Feb 2014 07:19:21 -0600
AN76474 - PSoC® 3 Power Supervisor http://www.cypress.com/?rID=66896 Introduction

Power supervision plays a critical role in modern communications systems such as routers, switches, storage systems, servers and base stations. These systems require multiple power supply rails for their various components including ASICs, PHY devices, FPGAs, CPUs, memory modules, and peripheral I/O devices.

]]>
Tue, 18 Feb 2014 02:50:18 -0600
Connecting the Same Pins to Two Analog Hardware Muxes - KBA89150 http://www.cypress.com/?rID=91870 Answer: You cannot connect the same analog pins to the inputs of two AMuxHws for the following reason:

The AMuxHw uses the individual switch at a pin. The following GPIO block diagram shows the digital output path and analog connectivity.

Figure 1. GPIO block diagram

GPIO block diagram

So there is only one digital signal interconnect (DSI) signal associated with one GPIO pin. This DSI signal is generated on the basis of the mux control signal, which in turn will connect a pin to the analog global or analog mux by enabling the switches. If the same pin is connected to two muxes, then two DSI signals will simultaneously try to turn on the same switches. This is not possible so Creator throws a build error. You have to connect different pins as the inputs of the two hardware muxes.

]]>
Mon, 17 Feb 2014 05:06:35 -0600
Building a PSoC® Creator™ Project from the Command Prompt – KBA88169 http://www.cypress.com/?rID=91866 Answer: Yes, you can build the project from the command prompt.

  1. Open the command prompt.
  2. Change the current directory to the folder containing the workspace file of the project. For example, type this command: cd "path of the workspace file".
  3. To build the project type this command:

    "C:\Program Files (x86)\Cypress\PSoC Creator\2.2\PSoC Creator\bin\cyprjmgr.exe" -wrk "workspace name" –build

    Note: In the above command workspace name must be replaced with the name of your workspace.
  4. This command builds the project. If you have multiple projects in the same workspace, the given command will not work. This command will be specific to Creator 2.2. If you want to build the project with other Creator versions, choose the folder accordingly in step 3.
]]>
Mon, 17 Feb 2014 03:53:34 -0600
QTP 101101: PSoC®3 Family, S8P-5RP, Fab4 http://www.cypress.com/?rID=49098 Mon, 17 Feb 2014 03:00:59 -0600 Execution Time for the FS_Write() Function in the emFile Library - KBA89381 http://www.cypress.com/?rID=91863 Answer: If the SD card is in a busy state, there will be a delay in responding to FS_Write().

The SD card in SPI mode will always respond to a command from the host, according to section 7.2.8 Error Conditions of the SD Specifications Part 1 Physical Layer Simplified Specification Version 4.10. This means that the function FS_Write() is a blocking function and it waits until it gets a response from the SD card. Hence, the execution time for the FS_Write() function will vary.

]]>
Sun, 16 Feb 2014 23:36:13 -0600
Dynamically Changing the Period Value of Timers, Counters, and PWMs in PSoC® 3/4/5LP – KBA88172 http://www.cypress.com/?rID=38641 Answer: The period value of fixed-function or universal digital block (UDB)-based Timer, Counter, and PWM Components can be changed on the fly using the WritePeriod() APIs given here. The new period value will be loaded only when the counter resets to zero.

  • Timer_WritePeriod(period);
  • PWM_WritePeriod(period);
  • Counter_WritePeriod(period);

You can also force the period value to take effect immediately by manually resetting the counter using the WriteCounter() API call given here.

  • Timer_WriteCounter(0);
  • PWM_WriteCounter(0);
  • Counter_WriteCounter(0);

Note:

  1. The change in the period of Timer/Counter/PWM made using the WritePeriod API is valid only if they are called after the Start API. Calling the Start API resets the period to the setting made in the Component Configuration window.
  2. When the new period value written into the period register is lesser than the previous value, it is recommended to call the WriteCounter(0) API immediately after that.
  3. To cause the counter count for N cycles, the period variable needs to be written as N-1.
]]>
Fri, 14 Feb 2014 05:49:11 -0600
Creating and Configuring Command Shortcut Keys in PSoC® Creator™ - KBA90934 http://www.cypress.com/?rID=91821 Answer: Shortcut key combinations make it easier to complete common tasks. For example, Ctrl + C allows you to quickly copy a selected item to the clipboard. You can configure shortcut keys in PSoC Creator to perform a specific task. A partial list of Creator’s current keyboard shortcuts can be found by searching in Creator for Keyboard Shortcuts under Help > Topics.

See Figure 1 and Figure 2 for the steps to configure shortcut keys in Creator.

Figure 1. Selecting the Customize Window

KBA90934

Figure 2. Configuring Shortcut Keys

  1. Click the Keyboard tab.
  2. Type or select the command.
  3. Select Global or the specific subsystem in which you want to use the shortcut.
  4. Type the shortcut key that you want to assign.
  5. Click Assign.
  6. Click Close.

The following are a few preconfigured shortcut keys in PSoC Creator:

  • Shift + F6 – Build the project
  • F6 – Build the workspace
  • Ctrl + Break – Cancel the build
  • F5 – Start debugging
]]>
Fri, 14 Feb 2014 04:53:29 -0600
Separate Flash Area for Storing Configuration Data in a Bootloadable Project - KBA89254 http://www.cypress.com/?rID=91815 Answer: You have to use the Manual application image placement option in the bootloadable component, and give an address that starts at "End Address of Bootloader project + Required User code area in flash" rounded off to the nearest 256 byte address. With this method, you can use the flash region between the bootloader project and the application project for storing the user data.

This user array in flash cannot be assigned an absolute address because bootloadable projects do not allow absolute address placement. You have to write to this flash location with hardcoded defines in the application project for these flash row numbers.

There are a few points to consider:

  • Your bootloader project code region should not encroach on the user area region. You have to freeze your bootloader project hex, get its code size, give a headroom of one flash row just in case, and then start the user flash area.
  • Because you are doing a backdoor write to the user flash area (which the linker has not allocated), you must protect the bootloader from being written on accidentally by protecting its flash region (W setting). You also must ensure that the application code is never updated by ensuring that the flash write functions have a check on the flash row range in the code such that the highest flash row is always below the application start address.

An example is given below.

  1. First build the bootloader project. Assume it takes 6414 bytes; 6414/256 = 26 rows. So 0x1A is the last bootloader row.
  2. Skip one row. Now the configuration data in flash can start from 0X1C. Use macros in the bootloadable project for flash rows 1C, 1D, and 1E. Write to these specific rows using the flash write API CyWriteRowData( arrayId, rowAddress, &Data) in the bootloadable project.
  3. Place the bootloadable project at 0x2000(row# 0x20) in flash using Manual application image placement.

The flash content can be read back using PSoC® Programmer™, after bootloading to verify the configuration data.

]]>
Fri, 14 Feb 2014 03:48:49 -0600
Using the Watchdog Timer to Reset PSoC® 3/5LP – KBA89152 http://www.cypress.com/?rID=91775 Answer: The WDT feature can be implemented in PSoC 3 or PSoC 5LP using the two APIs CyWdtStart and CyWdtClear. The hardware implementation of the WDT prevents any modification of the timer once it has been enabled. It also prevents the timer from being disabled once it has been enabled, which protects the WDT from changes caused by errant code.

The WDT can be used when there is a chance that a code might get stuck inside an interrupt. Please note that the WDT should be cleared using the API CyWdtClear to prevent the PSoC from getting reset. So in this case, you can write CyWdtClear inside the interrupt and if the interrupt is executed normally, the API will clear the WDT, preventing the PSoC from getting reset. On the other hand, if the code gets stuck inside the interrupt for a time greater than the watchdog period time, the PSoC will get reset.

More information about the APIs used for WDTs can be obtained from the System Reference Guide (PSoC Creator > Help > Documentation > System Reference > System Reference Guide).

For example, in a typical application you first enable the WDT.

CyWdtStart(CYWDT_1024_TICKS,CYWDT_LPMODE_NOCHANGE);

This will set the WDT for a time period of 2.048–3.072 s. Now you need to make sure that the WDT is cleared before this time. If not, the device will get reset.

So every 2.048–3.072 s, you need to call the CyWdtClear() API to clear the WDT.

]]>
Thu, 13 Feb 2014 04:39:44 -0600
AN62582 - AM Modulation and Demodulation http://www.cypress.com/?rID=44407 AM is achieved by multiplying carrier and message signals. Demodulation is achieved by sampling the AM signal at carrier frequency.

This video explains briefly how to implement amplitude modulation (AM) and demodulation using PSoC3 or PSoC 5LP controller.

 

The following table indicates the PSoC devices, PSoC Creator versions, compilers, and development kits that will work with this application note project:


Project
Device
PSoC Creator
Version
Development Kit
CY8CKIT-xxx
Compiler
Architecture
Silicon
Revision
V2.1 SP1
or higher
V2.1/2.0
001
DVK
030/050
DVK
003/014
FTK
Keil
GCC
RVDS
MDK

AN62582.zip

Prod
YES
NO
YES
YES*
NO
YES
N/A
N/A
N/A
Prod
YES
NO
YES
YES*
NO
N/A
YES
YES
YES
AN62582_Archive.zip
ES3, Prod
NO
YES
YES
YES*
NO
YES
N/A
N/A
N/A
ES1, Prod
NO
YES
YES
YES*
NO
N/A
YES
YES
YES

*Refer to Migrating CY8CKIT-001 DVK project to CY8CKIT 030/ 050

Notes:
  1. Click on AN77835 - PSoC® 3 to PSoC 5LP Migration Guide to learn differences between PSoC 3 and PSoC 5LP.
  2. For PSoC 5 project and related document, please download file AN62582_Archive.zip.

Projects associated with this application note can be downloaded from the ‘Related Files’ section below. For your convenience, we have provided projects that are compatible with the two most recent versions of PSoC Creator:

  • AN62582.zip is used with PSoC Creator 2.1 SP1
  • AN62582_Archive.zip is used with PSoC Creator 2.1/2.0

The project’s default settings may not be compatible with your device or kit, and you may need to change your project settings. For more information, see:

PSoC® 3, PSoC 4 and PSoC 5LP AN Project File Naming Convention and Use
]]>
Thu, 13 Feb 2014 04:05:42 -0600
AN84401 - PSoC® 3 and PSoC 5LP SPI Bootloader http://www.cypress.com/?rID=78703 Introduction

Bootloading is a process that allows you to upgrade your system firmware over a standard communication interface such as USB, I2C, UART or SPI. A bootloader communicates with a host to get new application code or data, and writes it into the device's flash memory.

This application note describes a SPI based bootloader for PSoC 3 and PSoC 5LP. To get introduced to basics of PSoC 3 and PSoC 5LP Bootloader please refer AN73854 - PSoC® 3 and PSoC 5LP - Introduction to Bootloaders. If you intend to learn how to develop USB and I2C Bootloader for PSoC 3 and PSoC 5LP, AN73503 - USB HID Bootloader for PSoC® 3 and PSoC 5LP and AN60317 – PSoC 3 and PSoC 5LP I2C Bootloader  respectively should get you going.

The following table indicates the PSoC devices, PSoC Creator versions, compilers, and development kits that will work with this application note project:


Project
Device
PSoC Creator
Version
Development Kit
CY8CKIT-xxx
Compiler
Architecture
Silicon
Revision
V2.2
or higher
V2.1 SP1
001
DVK
030/050
DVK
003/014
FTK
Keil
GCC
RVDS
MDK

AN84401.zip

Prod
YES
NO
YES*
YES
NO
YES
N/A
N/A
N/A
Prod
YES
NO
YES*
YES
NO
N/A
YES
YES
YES

*Refer to Migrating CY8CKIT-001 DVK project to CY8CKIT 030/ 050

Projects associated with this application note can be downloaded from the 'Related Files' section below.

]]>
Thu, 13 Feb 2014 03:57:50 -0600
AN79973 - PSoC3 and PSoC5 CapSense CSD - IEC 60730 Class B Safety Software Library http://www.cypress.com/?rID=64057 AN79973 details the self-check tests and their implementation details to match the IEC60730 standards that ensure reliable and safe operation of CapSense CSD  component in PSoC 3 and PSoC 5 devices.

The following table indicates the PSoC devices, PSoC Creator versions, compilers, and development kits that will work with this application note project:


Project
Device
PSoC Creator
Version
Development Kit
CY8CKIT-xxx
Compiler
Architecture
Silicon
Revision
V2.0
V2.1 SP1
V2.2
or higher
001
DVK
030/050
DVK
003/014
FTK
Keil
GCC
RVDS
MDK

AN79973.zip

Prod
YES
YES
YES
YES
YES
NO
YES
N/A
N/A
N/A
Prod
YES
YES
YES
YES
YES
NO
N/A
YES
YES
YES
Prod
YES
YES
YES
YES
YES
NO
N/A
YES
YES
YES

Refer to Migrating CY8CKIT-001 DVK project to CY8CKIT 030/ 050.

]]>
Thu, 13 Feb 2014 03:53:09 -0600
AN75813 - H Bridge Based Motor Drive Protection Using PSoC® 3 http://www.cypress.com/?rID=68670 Introduction:

H-Bridge driven DC motors are widely used in many automotive applications such as HVAC, power seats, wipers, and power windows. It is important to protect the motor drive system, because failure to do so may result in damaged components and, in some cases, hazardous conditions. In this application note, we discuss a novel approach to fault detection and protection where, instead of using pre-packaged motor drivers with built-in protection systems, we use basic components such as FETs and gate drivers. This method results in a larger number of available test signals and hence better determination of fault conditions. Combined with the configurability of PSoC 3 devices, this method also leads to a scalable and programmable system that can be easily shared across multiple H-Bridges.

The following table indicates the PSoC devices, PSoC Creator versions, compilers, and development kits that will work with this application note project:

Device PSoC Creator Version Supported Development Kit CY8CKIT- Supported Compiler
Architecture Silicon
Rev
V 1.0 V2.0
or higher
001
DVK
030
DVK
050
DVK
003 / 014
FTK
Keil GCC RVDS MDK
PSoC 3 ES2 No No No N/A N/A No No N/A N/A N/A
PSoC 3 ES3 / Rev A No Yes Yes Yes N/A No Yes N/A N/A N/A

The projects associated with this application note, one for CY8CKIT-001 and another for CY8CKIT-030, can be downloaded from the ‘Related Files’ section below.

]]>
Thu, 13 Feb 2014 03:20:34 -0600
AN73468 - PSoC® 3 and PSoC 5LP - Single-Cell Lithium-Ion (Li-ion) Battery Charger http://www.cypress.com/?rID=58095 Li-ion batteries are used in a wide range of systems such as cameras, cell phones, electric shavers, and toys. The charging circuit for the batteries can either be an integral part of the system (online charging) or an external plug-in circuit (offline charging). With its wide range of devices, PSoC offers a cost-effective solution in both segments. And with its configurable digital and analog features, PSoC 3 or PSoC 5LP enables implementation of other critical tasks required in the system.



Project
Device
PSoC Creator
Version
Development Kit
CY8CKIT-xxx
Compiler
Architecture
Silicon
Revision
V3.0 or
higher
V2.1 SP1/
V2.1
001
DVK
030/050
DVK
003/014
FTK
Keil
GCC
RVDS
MDK

AN73468.zip

Prod
YES
NO
YES
YES*
NO
YES
N/A
N/A
N/A
Prod
YES
NO
YES
YES*
NO
N/A
YES
YES
YES
AN73468_Archive.zip
ES3, Prod
NO
YES
YES
YES*
NO
YES
N/A
N/A
N/A
ES1, Prod
NO
YES
YES
YES*
NO
N/A
YES
YES
YES

*Refer to Migrating CY8CKIT-001 DVK project to CY8CKIT 030/ 050

Projects associated with this application note can be downloaded from the 'Related Files' section below. For your convenience, we have provided projects that are compatible with the two most recent versions of PSoC Creator:

  • AN73468.zip is used with PSoC Creator 3.0 or higher
  • AN73468_Archive.zip is used with PSoC Creator 2.1 SP1/2.1

The project’s default settings may not be compatible with your device or kit, and you may need to change your project settings. For more information, see:

PSoC® 3, PSoC 5, and PSoC 5LP AN Project File Naming Convention and Use
]]>
Thu, 13 Feb 2014 02:06:57 -0600
AN60317 - PSoC® 3 and PSoC 5LP I2C Bootloader http://www.cypress.com/?rID=41002 Beginning with PSoC Creator 2.1, the bootloader system has been reorganized to provide more configuration options. In previous releases, the bootloader system was part of the cy_boot component (a required component that is automatically and invisibly instantiated in all designs). From PSoC Creator 2.1 onwards the bootloader component is separated from cy_boot component and is available as a separate component in component catalogue. Please refer ‘Chapter11.Bootloader Migration’ in System Reference Guide (Help>Documentation>System Reference) to know how to migrate your older versions of bootloader/bootloadable projects to PSoC Creator 2.1.

AN60317 describes how to add an I2C bootloader to a PSoC® 3 / PSoC 5LP project. It also discusses how to use the PC based bootloader host program provided with PSoC Creator. Finally the application note illustrates how to create your own embedded bootloader host. Each of these is explained with examples.

To learn about PSoC 3 and PSoC5 Bootloader implementation refer to video: PSoC3, PSoC5, PSoC Creator Bootloader Overview

The following video describes the steps to add an I2C Bootloader to PSoC3 or PSoC5 projects.

-->

Bootloading is a process that allows you to upgrade your system firmware over a standard communication interface such as USB, I2C, UART or SPI. A bootloader communicates with a host to get new application code or data, and writes it into the device's flash memory.

This application note describes an I2C based bootloader for PSoC 3 and PSoC 5LP. To get introduced to basics of PSoC 3 and PSoC 5LP Bootloader please refer AN73854 - PSoC® 3 and PSoC 5LP - Introduction to Bootloaders. If you intend to learn how to develop USB Bootloader for PSoC 3 and PSoC 5LP, AN73503 - USB HID Bootloader for PSoC® 3 and PSoC 5LP should get you going.

The following table indicates the PSoC devices, PSoC Creator versions, compilers, and development kits that will work with this application note project:


Project
Device
PSoC Creator
Version
Development Kit
CY8CKIT-xxx
Compiler
Architecture
Silicon
Revision
V2.2
or higher
V2.1 SP1
001
DVK
030/050
DVK
003/014
FTK
Keil
GCC
RVDS
MDK

AN60317.zip

Prod
YES
NO
YES*
YES
NO
YES
N/A
N/A
N/A
Prod
YES
NO
YES*
YES
NO
N/A
YES
YES
YES
AN60317_Archive.zip
ES3, Prod
NO
YES
YES*
YES
NO
YES
N/A
N/A
N/A
ES1, Prod
NO
YES
YES*
YES
NO
N/A
YES
YES
YES

*Refer to Migrating CY8CKIT-001 DVK project to CY8CKIT 030/ 050

Notes:
  1. For PSoC 5 project and related document, please download file AN60317_Archive.zip.

Projects associated with this application note can be downloaded from the ‘Related Files’ section below. For your convenience, we have provided projects that are compatible with the two most recent versions of PSoC Creator:

  • AN60317.zip is used with PSoC Creator 2.2
  • AN60317_Archive.zip is used with PSoC Creator 2.1 SP1

The project’s default settings may not be compatible with your device or kit, and you may need to change your project settings. For more information, see:

PSoC® 3, PSoC 5, and PSoC 5LP AN Project File Naming Convention and Use
]]>
Thu, 13 Feb 2014 02:03:31 -0600
AN68403 - PSoC® 3 and PSoC 5LP Analog Signal Chain Calibration http://www.cypress.com/?rID=50320 An example of a programmable gain amplifier as part of the analog signal chain is described. This application note also shows how the gain and offset errors can be eliminated in the entire signal chain.

The following table indicates the PSoC devices, PSoC Creator versions, compilers, and development kits that will work with this application note project:


Project
Device
PSoC Creator
Version
Development Kit
CY8CKIT-xxx
Compiler
Architecture
Silicon
Revision
V2.1 SP1
or higher
V2.1/2.0
001
DVK
030/050
DVK
003/014
FTK
Keil
GCC
RVDS
MDK

AN68403.zip

Prod
YES
NO
YES
YES*
NO
YES
N/A
N/A
N/A
Prod
YES
NO
YES
YES*
NO
N/A
YES
YES
YES
AN68403_Archive.zip
ES2, ES3, Prod
NO
YES
YES
YES*
NO
YES
N/A
N/A
N/A
ES1, Prod
NO
YES
YES
YES*
NO
N/A
YES
YES
YES

*Refer to Migrating CY8CKIT-001 DVK project to CY8CKIT 030/ 050

Note:
  1. For PSoC 5 project and related document, please download file AN68403_Archive.zip.


Projects associated with this application note can be downloaded from the ‘Related Files’ section below. For your convenience, we have provided projects that are compatible with the two most recent versions of PSoC Creator:

  • AN68403.zip is used with PSoC Creator 2.1 SP1
  • AN68403_Archive.zip is used with PSoC Creator 2.1/2.0

The project’s default settings may not be compatible with your device or kit, and you may need to change your project settings. For more information, see:

PSoC® 3, PSoC 4 and PSoC 5LP AN Project File Naming Convention and Use
]]>
Thu, 13 Feb 2014 01:57:13 -0600
AN68272 - PSoC® 3, PSoC 4 and PSoC 5LP UART Bootloader http://www.cypress.com/?rID=50230

Introduction

Bootloaders are a common part of MCU system design. A bootloader makes it possible for a product's firmware to be updated in the field. At the factory, initial programming of firmware into a product is typically done through the MCU's Joint Test Action Group (JTAG) or the ARM Serial Wire Debugger (SWD) interface. However, these interfaces are usually not accessible in the field.

This is where bootloading comes in. Bootloading is a process that allows you to upgrade your system firmware over a standard communication interface such as USB, I2C, UART or SPI. A bootloader communicates with a host to get new application code or data, and writes it into the device's flash memory.

 


The following table indicates the PSoC devices, PSoC Creator versions, compilers, and development kits that will work with this application note project:

Project Device PSoC Creator
Version
Development Kit
CY8CKIT-xxx
Architecture Silicon
Revision
V2.2 SP1
or higher
V2.1 SP1
/2.1
001
DVK
030/050
DVK
042 Pioneer DVK
AN68272.zip PSoC3 Prod YES NO YES YES* N/A
PSoC4 Prod YES NO YES N/A YES**
PSoC5LP Prod YES NO YES YES* N/A
AN68272_Archive.zip PSoC3 ES2, ES3, Prod NO YES YES YES* N/A
PSoC5 ES1, Prod NO YES YES YES* N/A

* Refer to Migrating CY8CKIT-001 DVK project to CY8CKIT 030/ 050.
** The project can be easily adapted to this DVK.

Notes:
  1. For PSoC 5 project and related document, please download file AN68272_Archive.zip.

Projects associated with this application note can be downloaded from the ‘Related Files’ section below. For your convenience, we have provided projects that are compatible with the two most recent versions of PSoC Creator: 

  • AN68272.zip is used with PSoC Creator 2.2 SP1
  • AN68272_Archive.zip is used with PSoC Creator 2.1 SP1/2.1

The project’s default settings may not be compatible with your device or kit, and you may need to change your project settings. For more information, see:

PSoC® 3, PSoC 5, and PSoC 5LP AN Project File Naming Convention and Use
]]>
Thu, 13 Feb 2014 01:56:19 -0600
AN66444 - PSoC® 3 and PSoC 5LP Correlated Double Sampling to Reduce Offset, Drift, and Low Frequency Noise http://www.cypress.com/?rID=49159 This method reduces low frequency (1/f) noise and nulls DC offset in slow-changing analog signals. AN66444 provides a brief introduction to CDS and details of its implementation in PSoC 3 and PSoC 5LP. For theory of the CDS technique, see AN2226 - PSoC® 1 - Correlated Double Sampling for Thermocouple Measurement.

The following video explains the correlated double sampling technique that can be used to reduce a low frequency signal and eliminate DC offset in slow changing signals

 

The following table indicates the PSoC devices, PSoC Creator versions, compilers, and development kits that will work with this application note project:


Project
Device
PSoC Creator
Version
Development Kit
CY8CKIT-xxx
Compiler
Architecture
Silicon
Revision
V2.1 SP1
or higher
V2.1/2.0
001
DVK
030/050
DVK
003/014
FTK
Keil
GCC
RVDS
MDK

AN66444.zip

Prod
YES
NO
YES
YES*
NO
YES
N/A
N/A
N/A
Prod
YES
NO
YES
YES*
NO
N/A
YES
YES
YES
AN66444_Archive.zip
ES2, ES3, Prod
NO
YES
YES
YES*
NO
YES
N/A
N/A
N/A
ES1, Prod
NO
YES
YES
YES*
NO
N/A
YES
YES
YES

*Refer to Migrating CY8CKIT-001 DVK project to CY8CKIT 030/ 050

Note:
  1. For PSoC 5 project and related document, please download file AN66444_Archive.zip.


Projects associated with this application note can be downloaded from the ‘Related Files’ section below. For your convenience, we have provided projects that are compatible with the two most recent versions of PSoC Creator:

  • AN66444.zip is used with PSoC Creator 2.1 SP1
  • AN66444_Archive.zip is used with PSoC Creator 2.1/2.0.

The project’s default settings may not be compatible with your device or kit, and you may need to change your project settings. For more information, see:

PSoC® 3, PSoC 4 and PSoC 5LP AN Project File Naming Convention and Use
]]>
Thu, 13 Feb 2014 01:54:14 -0600
AN65977 - PSoC® 3 and PSoC 5LP - Creating an Interface to a TMP05/TMP06 Digital Temperature Sensor http://www.cypress.com/?rID=48490
 

The TMP05 Digital Temperature Sensor Interface Component is a building block for thermal management applications. It enables designers using PSoC 3 to quickly and easily interface with Analog Devices’ TMP05 or TMP06 digital temperature sensors through a simple, serial 2-wire digital interface. The sensors can be daisy-chained together, minimizing I/O requirements on the controller. For more details on the specific functions of the TMP05 Digital Temperature Sensor Interface Component, refer to the component datasheet.

Please refer to knowledge base article "PSoC® 3 and PSoC 5 AN/CE project file naming convention and usage" for naming conventions and device selection for associated projects.

Note:

  1. For PSoC 5 project and related document, please download file AN65977_Archive.zip.


Project
Device
PSoC Creator
Version
Development Kit
CY8CKIT-xxx
Compiler
Architecture
Silicon
Revision
V2.1 SP1
or higher
V2.1/2.0
001
DVK
030/050
DVK
003/014
FTK
Keil
GCC
RVDS
MDK

AN65977.zip

Prod
YES
NO
YES
YES*
NO
YES
N/A
N/A
N/A
Prod
YES
NO
YES
YES*
NO
N/A
YES
YES
YES
AN65977_Archive.zip
ES3, Prod
NO
YES
YES
YES*
NO
YES
N/A
N/A
N/A
ES1, Prod
NO
YES
YES
YES*
NO
N/A
YES
YES
YES

Projects associated with this application note can be downloaded from the 'Related Files' section below. For your convenience, we have provided projects that are compatible with the two most recent versions of PSoC Creator:

  • AN65977.zip is used with PSoC Creator 2.1 SP1
  • AN65977_Archive.zip is used with PSoC Creator 2.1/2.0

The project’s default settings may not be compatible with your device or kit, and you may need to change your project settings. For more information, see:

PSoC® 3, PSoC 4 and PSoC 5LP AN Project File Naming Convention and Use
]]>
Thu, 13 Feb 2014 01:53:07 -0600
AN62510 - Implementing State Machines with PSoC® 3, PSoC 4, and PSoC 5LP http://www.cypress.com/?rID=44402

Introduction

State machines are commonly used to implement decision making algorithms. State machines are used in applications where distinguishable states exist. A finite state machine (FSM) is based on the idea that a given system has a finite number of states.

This application note shows you how to implement both Mealy and Moore state machines using the Look Up Table (LUT) component in PSoC Creator™. Example projects are included.

The following table indicates the PSoC devices, PSoC Creator versions, compilers, and development kits that will work with this application note project:

Project Device PSoC Creator
Version
Development Kit
CY8CKIT-xxx
Architecture Silicon
Revision
V2.2 SP1
or higher
V2.1 SP1
/2.1
001
DVK
030/050
DVK
042 Pioneer DVK
AN62510.zip PSoC3 Prod YES NO YES YES* N/A
PSoC4 Prod YES NO YES N/A YES**
PSoC5LP Prod YES NO YES YES* N/A
AN62510_Archive.zip PSoC3 ES2, ES3, Prod NO YES YES YES* N/A
PSoC5 ES1, Prod NO YES YES YES* N/A

* Refer to Migrating CY8CKIT-001 DVK project to CY8CKIT 030/ 050.
** The project can be easily adapted to this DVK.

Notes:

  1. For PSoC 5 project and related document, please download file AN62510_Archive.zip.

Projects associated with this application note can be downloaded from the ‘Related Files’ section below. For your convenience, we have provided projects that are compatible with the two most recent versions of PSoC Creator:

  • AN62510.zip is used with PSoC Creator 2.2 SP1
  • AN62510_Archive.zip is used with PSoC Creator 2.1 SP1/2.1

The project’s default settings may not be compatible with your device or kit, and you may need to change your project settings. For more information, see:

PSoC® 3, PSoC 5, and PSoC 5LP AN Project File Naming Convention and Use
]]>
Thu, 13 Feb 2014 01:51:20 -0600
AN61102 - PSoC® 3 and PSoC 5LP - ADC Data Buffering Using DMA http://www.cypress.com/?rID=44335 The DMA controller in PSoC® 3 and PSoC 5LP is used to handle data transfer without CPU intervention. This is useful in applications that require ADC data buffering and allows the CPU to do simultaneous tasks.

The video describes the case of using a DMA to buffer ADC data. Buffering of 20 bit ADC data is taken as an example and discussed. The video also gives a preview of the project implementing the 20 bit data buffering and explains the DMA configuration in code.

 

 

The following table indicates the PSoC devices, PSoC Creator versions, compilers, and development kits that will work with this application note project:


Project
Device
PSoC Creator
Version
Development Kit
CY8CKIT-xxx
Compiler
Architecture
Silicon
Revision
V2.1 SP1
or higher
V2.1/2.0
001
DVK
030/050
DVK
003/014
FTK
Keil
GCC
RVDS
MDK

AN61102.zip

Prod
YES
NO
YES
YES*
NO
YES
N/A
N/A
N/A
Prod
YES
NO
YES
YES*
NO
N/A
YES
YES
YES
AN61102_Archive.zip
ES3, Prod
NO
YES
YES
YES*
NO
YES
N/A
N/A
N/A
ES1, Prod
NO
YES
YES
YES*
NO
N/A
YES
YES
YES

*Refer to Migrating CY8CKIT-001 DVK project to CY8CKIT 030/ 050

Notes:

  1. Click on AN77835 - PSoC® 3 to PSoC 5LP Migration Guide to learn differences between PSoC 3 and PSoC 5LP.
  2. For PSoC 5 project and related document, please download file AN61102_Archive.zip.

Projects associated with this application note can be downloaded from the ‘Related Files’ section below. For your convenience, we have provided projects that are compatible with the two most recent versions of PSoC Creator:

  • AN61102.zip is used with PSoC Creator 2.1 SP1
  • AN61102_Archive.zip is used with PSoC Creator 2.1/2.0

The project’s default settings may not be compatible with your device or kit, and you may need to change your project settings. For more information, see:

PSoC® 3, PSoC 4 and PSoC 5LP AN Project File Naming Convention and Use
]]>
Thu, 13 Feb 2014 01:49:38 -0600
AN60580 - SIO Tips and Tricks in PSoC® 3 / PSoC 5LP http://www.cypress.com/?rID=40989 The following video gives introduction to the features of SIO pins. 

 

The following table indicates the PSoC devices, PSoC Creator versions, compilers, and development kits that will work with this application note project:


Project
Device
PSoC Creator
Version
Development Kit
CY8CKIT-xxx
Compiler
Architecture
Silicon
Revision
V2.1 SP1
or higher
V2.1/2.0
001
DVK
030/050
DVK
003/014
FTK
Keil
GCC
RVDS
MDK

AN60580.zip

Prod
YES
NO
YES
YES*
NO
YES
N/A
N/A
N/A
Prod
YES
NO
YES
YES*
NO
N/A
YES
YES
YES
AN60580_Archive.zip
ES2, ES3, Prod
NO
YES
YES
YES*
NO
YES
N/A
N/A
N/A
ES1, Prod
NO
YES
YES
YES*
NO
N/A
YES
YES
YES

*Refer to Migrating CY8CKIT-001 DVK project to CY8CKIT 030/ 050

Notes:
  1. For PSoC 5 project and related document, please download file AN60580_Archive.zip.

Projects associated with this application note can be downloaded from the ‘Related Files’ section below. For your convenience, we have provided projects that are compatible with the two most recent versions of PSoC Creator:

  • AN60580.zip is used with PSoC Creator 2.1 SP1
  • AN60580_Archive.zip is used with PSoC Creator 2.1/2.0

The project’s default settings may not be compatible with your device or kit, and you may need to change your project settings. For more information, see:

PSoC® 3 and PSoC 5 AN/CE project file naming convention and usage
]]>
Thu, 13 Feb 2014 01:43:49 -0600
AN60220 - PSoC® 3 / PSoC 5LP Multiplexed Comparator http://www.cypress.com/?rID=40638 PSoC 3 and PSoC 5LP series of devices has 2 or 4 comparators. If the number of input signals that needs to be monitored is more than the available number of comparators, then one of the solutions is to multiplex the comparator. The other available options are to use OPAMPs and SIOs as comparators. SIO comparator details can be obtained from AN60580. In AN60220, as an example 4 channel multiplexing is implemented using configurable Digital and analog hardware, consuming 0% CPU bandwidth in multiplexing. It also explains ways to scale the design to different number of channels and scanning rate.

The following table indicates the PSoC devices, PSoC Creator versions, compilers, and development kits that will work with this application note project:


Project
Device
PSoC Creator
Version
Development Kit
CY8CKIT-xxx
Compiler
Architecture
Silicon
Revision
V2.1 SP1
or higher
V2.1/2.0
001
DVK
030/050
DVK
003/014
FTK
Keil
GCC
RVDS
MDK

AN60220.zip

Prod
YES
NO
YES
YES*
NO
YES
N/A
N/A
N/A
Prod
YES
NO
YES
YES*
NO
N/A
YES
YES
YES
AN60220_Archive.zip
ES2, ES3, Prod
NO
YES
YES
YES*
NO
YES
N/A
N/A
N/A
ES1, Prod
NO
YES
YES
YES*
NO
N/A
YES
YES
YES

*Refer to Migrating CY8CKIT-001 DVK project to CY8CKIT 030/ 050

Notes:
  1. Click on AN77835 - PSoC® 3 to PSoC 5LP Migration Guide to learn differences between PSoC 3 and PSoC 5LP.
  2. For PSoC 5 project and related document, please download file AN60220_Archive.zip.

Projects associated with this application note can be downloaded from the ‘Related Files’ section below. For your convenience, we have provided projects that are compatible with the two most recent versions of PSoC Creator:

  • AN60220.zip is used with PSoC Creator 2.1 SP1
  • AN60220_Archive.zip is used with PSoC Creator 2.1/2.0

The project’s default settings may not be compatible with your device or kit, and you may need to change your project settings. For more information, see:

PSoC® 3, PSoC 4 and PSoC 5LP AN Project File Naming Convention and Use
]]>
Thu, 13 Feb 2014 01:31:36 -0600
AN77835 - PSoC® 3 to PSoC 5LP Migration Guide http://www.cypress.com/?rID=72847 Introduction

The PSoC 3 and PSoC 5LP devices are designed for easy migration from PSoC 3 to PSoC 5LP. Although there are some differences such as the CPU cores, the programmable analog, programmable digital, programmable routing, pin functions, and other features are quite similar. Furthermore, the PSoC Creator IDE handles a lot of the migration issues for you, automatically. Often, migrating a PSoC Creator design is as simple as specifying a new part then rebuilding the project.

]]>
Thu, 13 Feb 2014 00:33:37 -0600
AN81623 - PSoC® 3, PSoC 4, and PSoC 5LP Digital Design Best Practices http://www.cypress.com/?rID=67774 Introduction

PSoC 3, PSoC 4, and PSoC 5LP have a powerful and flexible programmable digital peripheral system. In addition to a set of fixed function blocks (4 timers, I2C, USB, CAN), they offer as many as 24 programmable Universal Digital Blocks (UDBs) and an extensive signal routing system called the Digital System Interconnect (DSI).

]]>
Thu, 13 Feb 2014 00:26:46 -0600
AN54181 - Getting Started with PSoC® 3 http://www.cypress.com/?rID=39157 Introduction

PSoC 1, PSoC 3, and PSoC 5LP are all true programmable embedded system-on-chips that integrate configurable analog, programmable digital, memory, and a central processor on a single chip.

PSoC contains a processor, but it is not an MCU. The name PSoC (Programmable-System-on-Chip) defines its true identity. AN54181 introduces the Programmable-System-on-Chip concept with specific emphasis on PSoC 3. Here, you learn about PSoC 3 and what it can do for you and your projects. It also introduces PSoC Creator™, a powerful IDE development tool for PSoC 3 and PSoC 5LP.

The following video gives brief introduction for PSoC3:

 

 


The following video guides how to create projects using PSoC3:

 

 

The following table indicates the PSoC devices, PSoC Creator versions, compilers, and development kits that will work with this application note project:


Project
Device
PSoC Creator
Version
Development Kit
CY8CKIT-xxx
Compiler
Architecture
Silicon
Revision
V2.1 SP1
or higher
V2.1/2.0
001
DVK
030/050
DVK
003/014
FTK
Keil
GCC
RVDS
MDK

AN54181.zip

Prod
YES
NO
YES
YES*
NO
YES
N/A
N/A
N/A
Prod
YES
NO
YES
YES*
NO
N/A
YES
YES
YES
AN54181_Archive.zip
ES3, Prod
NO
YES
YES
YES*
YES
YES
N/A
N/A
N/A

*Refer to Migrating CY8CKIT-001 DVK project to CY8CKIT 030/050

Notes:
  1. Click on AN77835 - PSoC® 3 to PSoC 5LP Migration Guide to learn differences between PSoC 3 and PSoC 5LP.
  2. For PSoC 5 project and related document, please download file AN54181_Archive.zip.

Projects associated with this application note can be downloaded from the ‘Related Files’ section below. For your convenience, we have provided projects that are compatible with the two most recent versions of PSoC Creator:

  • AN54181.zip is used with PSoC Creator 2.1 SP1
  • AN54181_Archive.zip is used with PSoC Creator 2.1/2.0.

The project’s default settings may not be compatible with your device or kit, and you may need to change your project settings. For more information, see:

PSoC® 3, PSoC 4 and PSoC 5LP AN Project File Naming Convention and Use
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Wed, 12 Feb 2014 23:27:11 -0600
AN52927 - PSoC® 3 and PSoC 5LP - Segment LCD Direct Drive http://www.cypress.com/?rID=37795 PSoC3 device is equipped with segment LCD driver which allows segment LCD glass to be directly driven without using any external components.

Segment LCD glass interface to PSoC3

The driver supports LCDs upto 16 commons and can drive upto 768 segments. PSoC Creator tool provides Segment LCD component which simplifies the task of handling different types of segment LCD features such as 7-segment, 14-segment, 16-segment, Dot-Matrix and special symbols. This application note explains how to use Segment LCD component for a given LCD specifications.

This application note only covers segment LCD drive capability of PSoC3. Another type of LCDs- the graphic LCDs can also be interfaced to PSoC3. For details of interfacing graphic LCDs to PSoC3, click the following links-

http://www.cypress.com/?rID=48850

http://www.cypress.com/?rID=48854

 

Demo Video: PSoC3 Segment LCD Direct Drive Demo

This video explains how to create projects with Segment LCD Component of PSoC3.

 

 

The following table indicates the PSoC devices, PSoC Creator versions, compilers, and development kits that will work with this application note project:


Project
Device
PSoC Creator
Version
Development Kit
CY8CKIT-xxx
Compiler
Architecture
Silicon
Revision
V2.1 SP1
or higher
V2.1/2.0
001
DVK
030/050
DVK
003/014
FTK
Keil
GCC
RVDS
MDK

AN52927.zip

Prod
YES
NO
YES
YES*
NO
YES
N/A
N/A
N/A
Prod
YES
NO
YES
YES*
NO
N/A
YES
YES
YES
AN52927_Archive.zip
ES3, Prod
NO
YES
YES
YES*
NO
YES
N/A
N/A
N/A

*Refer to Migrating CY8CKIT-001 DVK project to CY8CKIT 030/ 050


Projects associated with this application note can be downloaded from the ‘Related Files’ section below. For your convenience, we have provided projects that are compatible with the two most recent versions of PSoC Creator:

  • AN52927.zip is used with PSoC Creator 2.1 SP1
  • AN52927_Archive.zip is used with PSoC Creator 2.1/2.0

The project’s default settings may not be compatible with your device or kit, and you may need to change your project settings. For more information, see:

PSoC® 3 and PSoC 5 AN/CE project file naming convention and usage
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Wed, 12 Feb 2014 23:26:03 -0600
AN52705 - PSoC® 3 and PSoC 5LP - Getting Started with DMA http://www.cypress.com/?rID=37793 PSoC DMA can transfer data between on-chip peripherals and memory with no CPU intervention. The application note illustrates how to configure the DMA for simple data transfers, including peripheral to memory, memory to peripheral, peripheral to peripheral and memory to memory, using example projects.

Introduction

The DMA controller (DMAC) in PSoC 3 and PSoC 5LP can transfer data from a source to a destination with no CPU intervention. This allows the CPU to handle other tasks while the DMA does data transfers, thereby achieving a „multiprocessing‟ environment.

The PSoC DMA Controller (DMAC) is highly flexible – it can seamlessly transfer data between memory and on chip peripherals including ADCs, DACs, Filter, USB, UART, and SPI. There are 24 independent DMA channels.

 The following table indicates the PSoC devices, PSoC Creator versions, compilers, and development kits that will work with this application note project:


Project
Device
PSoC Creator
Version
Development Kit
CY8CKIT-xxx
Compiler
Architecture
Silicon
Revision
V2.1 SP1
or higher
V2.1/2.0
001
DVK
030/050
DVK
003/014
FTK
Keil
GCC
RVDS
MDK

AN52705.zip

Prod
YES
NO
YES
YES*
NO
YES
N/A
N/A
N/A
Prod
YES
NO
YES
YES*
NO
N/A
YES
YES
YES
AN52705_Archive.zip
ES2, ES3, Prod
NO
YES
YES
YES*
NO
YES
N/A
N/A
N/A
ES1, Prod
NO
YES
YES
YES*
NO
N/A
YES
YES
YES

 *Refer to Migrating CY8CKIT-001 DVK project to CY8CKIT 030/ 050

Note:
  1. For PSoC 5 project and related document, please download file AN52705_Archive.zip.

Projects associated with this application note can be downloaded from the ‘Related Files’ section below. For your convenience, we have provided projects that are compatible with the two most recent versions of PSoC Creator:

  • AN52705.zip is used with PSoC Creator 2.1 SP1
  • AN52705_Archive.zip is used with PSoC Creator 2.1/2.0

The project’s default settings may not be compatible with your device or kit, and you may need to change your project settings. For more information, see:

PSoC® 3, PSoC 4 and PSoC 5LP AN Project File Naming Convention and Use
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Wed, 12 Feb 2014 23:25:06 -0600