Cypress.com: Documentation http://www.cypress.com/?app=search&searchType=advanced&id%3D209 Footprint / Landpattern of an SRAM? http://www.cypress.com/?rID=26496 The footprint sram parts can be found at ipc.org. Please click on the following link: http://ipc.org/default.aspx You would have to register to get to the calculator. Once you register in the dropbox you will be given an option to enter your choice of package and there you can find the landpattern.

]]> Wed, 12 Sep 2012 03:22:01 -0600 CYDC128B16: 1.8 V 4 K/8 K/16 K × 16 and 8 K/16 K × 8 ConsuMoBL Dual-Port Static RAM http://www.cypress.com/?rID=13454 1.8 V 4 K/8 K/16 K × 16 and 8 K/16 K × 8 ConsuMoBL Dual-Port Static RAM

Features

  • True dual-ported memory cells which allow simultaneous access of the same memory location
  • 4/8/16 K × 16 and 8/16 K × 8 organization
  • High speed access: 40 ns
  • Ultra low operating power
    • Active: ICC = 15 mA (typical) at 55 ns
    • Active: ICC = 25 mA (typical) at 40 ns
    • Standby: ISB3 = 2 μA (typical)
  • Port-independent 1.8 V, 2.5 V, and 3.0 V I/Os
  • Pb-free 14 × 14 × 1.4 mm 100-pin Thin Quad Flat Pack (TQFP) Package
  • For more, see pdf

Functional Description

The CYDC128B16 is a low power complementary metal oxide semiconductor (CMOS) 4k, 8k,16k x 16, and 8/16k x 8 dual-port static RAM. Arbitration schemes are included on the devices to handle situations when multiple processors access the same piece of data. Two ports are provided, permitting independent, asynchronous access for reads and writes to any location in memory. The devices can be used as standalone 16-bit dual-port static RAMs or multiple devices can be combined in order to function as a 32-bit or wider master/slave dual-port static RAM.

]]> Mon, 30 Jul 2012 03:49:14 -0600 CYDMX256A16, CYDMX256B16, CYDMX128A16, CYDMX128B16 ,CYDMX064A16, CYDMX064B16: 16 K/8 K/4 K × 16 MoBL® ADM Asynchronous Dual-Port Static RAM http://www.cypress.com/?rID=46259 16 K/8 K/4 K × 16 MoBL® ADM Asynchronous Dual-Port Static RAM

Features

  • True dual-ported memory block that allow simultaneous independent access
    • One port with dedicated time multiplexed address and data (ADM) interface
    • One port configurable to standard SRAM or time multiplexed address and data interface
  • 16 K/8 K/4 K × 16 memory configuration
  • High speed access
    • 65 ns or 90 ns ADM interface
    • 40 ns or 60 ns standard SRAM interface
  • Fully asynchronous operation
  • Port independent 1.8 V, 2.5 V, and 3.0 V IOs
  • For more, see pdf

Functional Description

The CYDMX256A16, CYDMX128A16, CYDMX064A16, CYDMX256B16, CYDMX128B16, and CYDMX064B16 are low power CMOS 16K/8K/4K × 16 dual-port static RAMs. The two ports are: one dedicated time multiplexed address and data (ADM) interface and one configurable standard SRAM or ADM interface. The two ports permit independent, asynchronous read and write access to any memory locations.

]]> Mon, 30 Jul 2012 03:43:03 -0600 CYDM064B16, CYDM128B16, CYDM256B16: 1.8V 4K/8K/16K x 16 MoBL® Dual-Port Static RAM http://www.cypress.com/?rID=13449 1.8V 4K/8K/16K x 16 MoBL® Dual-Port Static RAM

Features

  • True dual ported memory cells that allow simultaneous access of the same memory location
  • 4, 8, or 16K × 16 organization
  • Ultra Low operating power
    • Active: ICC = 15 mA (typical) at 55 ns
    • Standby: ISB3 = 2 μA (typical)
  • Small footprint: available in a 6x6 mm 100-pin Pb-free vfBGA
  • Port independent 1.8V, 2.5V, and 3.0V I/Os
  • Full asynchronous operation
  • Automatic power down
  • For more, see pdf

Functional Description

The CYDM256B16, CYDM128B16, and CYDM064B16 are low power CMOS 4K, 8K,16K x 16 dual-port static RAMs. Arbitration schemes are included on the devices to handle situations when multiple processors access the same piece of data. Two ports are provided that permit independent, asynchronous access for reads and writes to any location in memory.

]]> Mon, 30 Jul 2012 03:40:52 -0600 AN5036 - Interfacing Cypress MoBL® Asynchronous Dual-Port to TI OMAP1710 Multimedia Processor http://www.cypress.com/?rID=12669 Interfacing Cypress MoBL Asynchronous Dual-Port to TI OMAP1710 Multimedia Processor

The Texas Instruments OMAP1710 Multimedia Processor is a low-power, highly-integrated hardware and software platform designed to meet the application processing needs of next-generation embedded devices.The OMAPTM platform enables OEMs and ODMs to quickly bring to market devices featuring rich user interfaces, high-processing performance, and long battery life through the maximum flexibility of a fully-integrated mixed-processor solution.The OMAP1710 is primarily targeted at mobile communications applications using WLAN802.11x, Bluetooth, GSM, GPRS, EDGE, CDMA and other proprietary wireless standards. The processor provides video and image processing (MPEG, JPEG, etc.), advanced speech/audio processing, graphics and video acceleration, generalized web access and data processing.The OMAP1710 Multimedia Processor supports External Memory Interface (EMIF) that readily connects to Cypress asynchronous Dual-Ports. This application note describes the wiring, EMIF register settings, and other design considerations for connecting the OMAP1710 Multimedia Processor to the 1/4 Mb Cypress MoBL(TM) Dual-Port (CYDM256A16-55). The same design can be used in interfacing the OMAP1710 Multimedia Processor to other Cypress MoBL Dual-Ports in the x16 configuration, such as the CYDM128A16 and CYDM064A16.

]]> Wed, 09 May 2012 01:18:24 -0600 Why do your address pins not match Samsungs or other vendors? http://www.cypress.com/?rID=26499 The address can be laid out in any order. The address pinout in the case of any sram does not matter since internally you might be addressing different locations but externally you read and write from the same location. Please refer to the following appnote for further clarification. AN1083

]]> Mon, 16 Apr 2012 00:15:06 -0600 Vss and Vcc clarification http://www.cypress.com/?rID=26542  Vss refers to ground. Vcc is the supply pin.

]]> Tue, 13 Mar 2012 06:15:50 -0600 Floating data input on CMOS SRAM http://www.cypress.com/?rID=26539  It is not recommended to leave the CMOS inputs floating. None of the SRAM parts have any internal pullups or pulldowns on the data inputs to have a valid signal when an input is left floating. If the customer does not want to use the datalines for parity, they have to be pulled up or pulled down.

]]> Tue, 13 Mar 2012 06:11:11 -0600 Do Address pins have internal Pull-up or Pull-down circuits? http://www.cypress.com/?rID=26537  There are no pullups or pulldowns on address pins. If the customer doesn't want to use half of the memory, then any one of the address pins can be tied high or low and the remaining can be used to address the part.

]]> Tue, 13 Mar 2012 06:09:13 -0600 Do you have Land Patterns or layouts http://www.cypress.com/?rID=26536  There are no recommended land patterns for any devices, it is recommended that customers refer to the IPC database of land patterns for the same.

 
 

]]> Tue, 13 Mar 2012 06:07:41 -0600 Does http://www.cypress.com/?rID=26535 The "T" on the end of the part number stands for the 'Tape-and-reel' packaging option.

 

For Eg. - 'T' in CY7C1021DV33-10ZSXIT implies Tape and Reel.

You can avail the packaging details of a part in the Ordering information section of the datasheet.

]]> Tue, 13 Mar 2012 06:05:40 -0600 How to Submit Parts for FA http://www.cypress.com/?rID=26532 To request an FA, the customer should contact their local FAE or sales office. These groups are the point-of-contact for a failure analysis (FA). The customer should fill out the FA form that they receive from these groups, and follow the instructions given on the FA form. The can raise a service request on the website in the Failure Analysis catagory. They will be guided from there on.

]]> Tue, 13 Mar 2012 04:47:25 -0600 Implementing Interprocessor Communication Using Cypress MoBL(R) Dual-Ports and the Mailbox Registers - AN5074 http://www.cypress.com/?rID=12668
The Cypress Semiconductor MoBL(R) dual-ports provide an ultra low-power, high-bandwidth, flexible solution for the intercommunication of two processing elements. The MoBL dual-port removes the necessity for processing elements to communicate with a protocol such as I2C, SPI or UART. In addition, the MoBL dual-port provides a way to interconnect processing elements with different clock frequencies, bus widths, I/O voltages, and at bandwidths in excess of 400 Mbit/s. ]]> Thu, 27 Oct 2011 15:09:33 -0600 Moisture Sensitivity Level (MSL) of Cypress Parts http://www.cypress.com/?rID=54061 If you know the Cypress part number: 

1. Go to www.cypress.com.  On the top right, you will see a “Keyword / Part Number” search box (adjacent to “Contact Us.”) 

2. Select the “Part Number” tab above this text box.

3. Type the exact part number, for example CY8C29466-12PVXE.

4. The part number will be listed in the search results page.

5. Click on the part number link (1st column starting from the left). This will open a new web page.

Moisture Sensitivity Level (MSL) can be found by clicking the “Quality & Pb-free Data” link on the top, or by just scrolling down to the Quality & Pb-free Data” section about half way down the page.

All other Quality information for this part number (e.g., RoHS compliance, Lead/Ball Finish, Qualification Reports, IPC reports) can also be found on this web page. 

In case of any questions, or if the information is not available for a particular part number, please create a support case at www.cypress.com/support

If you do not know the Cypress part number: 

1. Go to www.cypress.com.  Browse the different products (“Products” tab on the top navigation menu) by family.

2. Once you choose the relevant product family (e.g., “Clocks and Buffers->Clock Distribution,” “Memory->FIFOs”), scroll down the particular page to get to the “Parametric Product Selector.”

3. Use this tool to find the part number by function/feature, and click on the part number you are interested in. This will lead you directly to step # 5 above.

]]> Thu, 08 Sep 2011 21:22:46 -0600 cross-section drawings and thickness ? http://www.cypress.com/?rID=30989  The cross-section drawings and thickness are internal design rule specs, which are not supposed to be shipped out.

]]> Sun, 26 Jun 2011 08:17:27 -0600 SRAM Environmental Testing http://www.cypress.com/?rID=26522 The environmental and mechnanical testing data are available in the Qualification report available in the part number page.

]]> Mon, 20 Jun 2011 02:19:11 -0600 AN5075 - Migrating from Cypress CYDMxxxAxx MoBL(R) Dual-Ports to CYDMxxxBxx MoBL Dual-Ports http://www.cypress.com/?rID=51171 The Cypress CYDMxxxAxx and CYDMxxxBxx MoBL® Dual-Ports are high-speed, low-power interconnects that provide two independent ports with simultaneous read/write access to the shared memory core. Both devices have full asynchronous operation and on-chip arbitration logic. The devices also offer features such as the Input Read Registers (IRR) and Output Drive Registers (ODR).  

 


]]> Tue, 10 May 2011 10:26:43 -0600 AN5093 - Cypress MoBL(R) Dual-Port 100-Ball VFBGA Printed Circuit Board (PCB) Layout Guidelines http://www.cypress.com/?rID=51164 MoBL® Dual-Port is a specialty memory product offered by Cypress Semiconductor targeted for handheld applications. It provides a flexible processor interconnect solution that is low-power and high-bandwidth.

]]> Tue, 10 May 2011 07:08:06 -0600 SRAM powerup data output http://www.cypress.com/?rID=26518  On power up, if a read occurs, the memory will put out undefined data, i.e. '1' or '0' or 'X' since nothing was written into those memory locations.

 
 
 
 

]]> Mon, 04 Apr 2011 23:13:44 -0600 tLZOE and tHZOE demystified http://www.cypress.com/?rID=26509 On the first look, it seems that there is a mistake in the datasheet.  But, please note that these parameters are tested at opposite conditions, i.e. tLZOE is tested at high Vcc, low temp and fast corner whereas tHZOE istested at low Vcc, high temp and slow corner as the former is a min. spec.and the latter is a max. spec. So, at any given temperature and voltage, the design is guaranteed such that tHZOE is less than tLZOE to prevent bus contention.

]]> Mon, 04 Apr 2011 23:13:23 -0600 UL94V-0_compliance http://www.cypress.com/?rID=26508  Yes, most of our devices are compliant. However please check with the quality reports for exact information.

]]> Mon, 04 Apr 2011 23:12:46 -0600 Extra 4 or 2 bits if 32/16 bits are used in x36/x18 part. http://www.cypress.com/?rID=26498 Some layouts do have a problem of interfacing the SRAM to a standard DSP or a processor which uses only 16/32 bits. In these cases, the extra 4/2 bits have to be tied to a LOW or a HIGH value through individual resitors. These resistors could be 10K ohms or other high values. If the extra bits are not used for parity checking better to tie them to a HIGH or a LOW.

]]> Mon, 04 Apr 2011 23:12:15 -0600 Ram 4 and Ram 5 on your Reliability report http://www.cypress.com/?rID=26497 Ram 4 and Ram 5 are the different technologies used to manufacture Cypress products. Ram 4 on the reliability report means that its a 0.35u technology and Ram 5 means its 0.25u Technology.

]]> Mon, 04 Apr 2011 23:09:15 -0600 extra 2 bits for parity check? http://www.cypress.com/?rID=26500 The extra 2 bits for parity check are an industry standard. They can be used as an extra data lines also or as parity bits. The parity has to be calculated by external controller and our SRAM's do not have any circuitry to calculate parity.

]]> Mon, 04 Apr 2011 23:06:27 -0600 Mean time between failures? http://www.cypress.com/?rID=26493 The formula for calculating the MTBF(mean time between failiures) is 1/FIT. FIT stands for failure in time. The FIT rate for a particular part can be found in the qual report, which can be obtained off the cypress website in qualification report in the part number page.

]]> Mon, 04 Apr 2011 23:06:03 -0600 Parity during read and write http://www.cypress.com/?rID=26484  In all of cypress's srams, parity check logic is not implemented on the part. The parity check is upto the discretion of the customer. If they decide not to use the parity feature then, they can use the extra 4 I/O bits as data bits. For eg; the CY7C1347B is a 128K x 36 SRAM. So, generally what most of our customers do is, if they decide to include parity check feature, they will use the four bytes(8 bits each) for data and the extra 4 I/O lines for parity check. Even parity or Odd parity check has to be decided and a logic to generate the parity bit in the memory controller has to be implemented. When a write is intiated, the external memory controller will decide (depending on the data of the 8 bits and whether to check for even or odd parity) to write either a '1' or a '0' on the parity bit. When a read is intiated, the parity decoder logic in the external memory controller will read the 8 bits coming and see whether the parity bit should be a 1 or a zero and flag if there is any discrepancy found.

]]> Mon, 04 Apr 2011 23:05:31 -0600 Failure In Time (FIT) http://www.cypress.com/?rID=38457 The FIT (Failure in Time) for a particular part is found in the Qualification Report of that part. To locate the Qualification Report please refer to the Knowledge Based article on "Qualification Report (QTP)".

]]> Mon, 04 Apr 2011 23:05:04 -0600 Qualification Report (QTP) http://www.cypress.com/?rID=38456  

Response: In most cases "Qualification report" will be available in the part number page. If it is not available, check for the following methods below.

Option-1:

1. Go to www.cypress.com

2. Enter the part number whose "Qualification Report" is needed in the "Keyword" search.

3. All the related document to this part will be displayed.

4. In the "Resource Type" select "Qualification Report", all related qualification report will be displayed.

Option-2:

1. Go to www.cypress.com,

2. Select "Design Support",

3. Select "Quality & Reliability"

4. Now in the "Qualification Report" Tab, there are two option.

a) Drop down menu to select the product family eg: Memory (All QTP related to Memory will be shown)

b) Search the QTP with a part number (eg: CY7B923) . All the related QTP will be shown.

Option-3:

1. Go to www.cypress.com

2. Select "Part Number" search.

3. Search for the part whose qualification report is required.

4. Click on the Base/Root Part.

5. Now the Qual Report download will be shown, sometimes it may require to login.

If none of the above procedure works, then create a support case to get the Qualification Report.

]]> Mon, 04 Apr 2011 23:02:52 -0600 Pb-Free option of SRAMs http://www.cypress.com/?rID=29335  

There are requirements and conditions for the Pb-Free devices reflow process and are tabulated in the Cypress Pb-Free reflow profile shown below. The product must meet two stringent requirements, zero lead and high temperature (260 ?C) reflow capability. Higher temperature reflow capability is needed because Pb-Free solder pastes melt at higher temperatures. The Pb-Free devices are marked with an 'X' on the package in the standard parts number.

 

For leadframe-based packages, Nickel Palladium Gold (Ni-Pd-Au) and Matte Tin (Sn) are the primary options. Nickel Palladium Gold (Ni-Pd-Au) for internally manufactured product and Tin (Sn) for subcontract manufactured products.

 

BGA packages will use Tin-Silver-Copper (SnAgCu) instead of Tin-Lead (SnPb) balls 

 

Cypress Semiconductor 260 Pb-Free Reflow Profile

 

PROFILE ELEMENTS

IR - INFRA RED REFLOW

Ramp Rate 217 ?C

3 ?C /sec max 

Preheat Temperature 150 ?C (+/-25?C)

 

60 to 120 seconds max 

Time 50 ?C to Peak Temperature 

3.5 minutes, 6 seconds max 

Temperature maintained above 217 ?C 

60 to 150 seconds 

Time within 5 ?C of actual peak

temperature 

10 to 20 seconds 

Peak temp range

260 ?C (-5/+0) ?C 

Ramp-down rate 

6 ?C /second max

]]> Sat, 26 Mar 2011 03:11:43 -0600 Operation of devices outside specified temperature range http://www.cypress.com/?rID=26529 The Commercial temperature rating on our datasheets guarantee an operation between 0C and 70C.   The Industrial rating on our datasheets guarantee and operation between -40C and 85C. The commercial device(C) is not tested at lower temperatures and the operation at temperatures below 0C is not guaranteed. We do not recommend operation outside of the published temperature ranges, although there is a a probablity that the Cypress device could operate beyond these temperatures. We do not guarentee the performance of the device outside the range.

]]> Sat, 05 Mar 2011 10:47:54 -0600 SRAM models link http://www.cypress.com/?rID=26520 Models can be found on the part number page of the part.

However, the models can be searched on the link given below.
http://www.cypress.com/?app=search&searchType=advanced&keyword=&rtID=114&id=0&applicationID=0&l=0
 
 
 

]]> Sat, 05 Mar 2011 03:07:39 -0600 SRAM tape and reel requirement http://www.cypress.com/?rID=26511

First, the part are sealed on the reel by tape and, although not hermetically sealed, it will offer additional shelf exposure time. However, this time is neither measured nor guaranteed. Second, the tape and reel materials can not withstand the standard bake temperature of 125C. However, if the parts do need to be baked then a lower temperature, but longer time, may be acceptable to reach level moisture content specification. The tape and reel bake requirement is temperature of less than 60C and a time limit of 24hrs.

]]> Sat, 05 Mar 2011 02:37:43 -0600 Thermal resistances http://www.cypress.com/?rID=26510 Theta Ja and Theta Jc values are present in the datasheet. If the values are not present in the datasheet. Please raise a service request under "Quality Documentation"

]]> Sat, 05 Mar 2011 02:30:28 -0600 Criteria for submitting a part for failure analysis http://www.cypress.com/?rID=26507  There are no fixed criteria to determine if the component has to be released for failure analysis.  The customer should determine to the best of their ability that it is a malfunctioning Cypress part(s) that is causing their system failure.

]]> Sat, 05 Mar 2011 02:13:58 -0600 Current (Idd) consumption at -40 and +85 degrees? http://www.cypress.com/?rID=26505  The part consumes the max current at +85degrees (High temperature)

]]> Sat, 05 Mar 2011 02:08:32 -0600 Information on Industry standard JTAG interfaces on SRAM's. http://www.cypress.com/?rID=26504 The existing JTAG functionality on the Cypress device is the same as the JTAG functionality on all compatible memories from other vendors. Let us address this in two different steps: - Standard SRAMs: - On standard SRAM's the JTAG functionality is the same for all vendors, but the BSDL file could be different depending on the design(Silicon & Package). The difference in the BSDL file is more in terms of the pin numbering and not for anything else. QDR SRAMs:- On the QDR SRAMs, we have struggled over the last couple of months to standardize the functionality and the pin ordering of the JTAG port. Quite recently we have acheived this and the BSDL file from each of the vendor will be the same for the QDR-II. The only difference in the BSDL file is from the device ID, which is supposed to remain different for every device. But users can ignore the device ID and test the device without any problems. We have been able to achieve this on the QDR-II, becuase of the fact that we are a closed consortium of 6 companies. Standard Sync SRAMs are manufactured by multiple vendors and it is very difficult to standardize the BSDL files of varied vendors.

]]> Sat, 05 Mar 2011 02:03:07 -0600 Different in pin out for T version and TA version? http://www.cypress.com/?rID=26503 Multiple chip enables for depth expansion: three chip enables for TA (GVTI) /A (CY) package version and two chip enables for B (GVTI) /BG (CY) and T (GVTI) /AJ (CY) package versions. JTAG boundary scan for B/BG and T/AJ package version. So we get: T-version= 2 chip enables w/JTAG {/AJ (CY) package } TA-version= 3 chip enables w/o JTAG {/A (CY) package}

]]> Sat, 05 Mar 2011 01:57:00 -0600 Address pins assignments in SRAMs http://www.cypress.com/?rID=26487
Once a address pin is assigned with a particular address bit, You will Read and Write from the same address. So, it doesn't affect the Read and Write operation. Hence, we do not provide the exact Address(A) pin numbers . This is true for all Asynchronous SRAMs.

Hence, the user can connect the address pins on their side to any address pins on the SRAM.

On Synchronous and NoBL SRAMs, however, address A0 and A1 have to be in place for all the vendors as these bits load into a burst counter.

]]> Tue, 01 Mar 2011 11:05:16 -0600 NC and DNU pin http://www.cypress.com/?rID=26486 NC stands for No Connect which means that the pin is not internally connected to the die. So it can be either left floating or tied to GND or tied to VCC. DNU stands for Do Not Use. DNU pins might be used for test mode entry and hence these pins have to be left unconnected/floating.

]]> Tue, 01 Mar 2011 10:41:09 -0600 IO power in SRAMs http://www.cypress.com/?rID=38113  

IO power is the power dissipated due to switching of the IO lines of the memory.
The operating current ICC mentioned in the datasheet includes only the core power, does not include the IO power. You can compute the IO power as shown below.

Assuming capacitive load only, IO power can be estimated to be ((α)* f *N * CL* V * V)
where
α is called the activity factor ; if on an average half the IO's switch per clock cycle, then α is 0.5.
f is the switching frequency or clock frequency
N is the number of IO's
CL is the capacitive load;
V is the Voltage swing of the IO.

For example: IO power for (CYD18S36V18) = (10MHz * 36 * 20pF * 3.3^2)/2 = 39.2mW.

More information can be obtained from this Application Note: http://www.cypress.com/?rID=12896

]]> Sat, 26 Feb 2011 23:21:52 -0600 MSL (Moisture sensitivity level) of SRAMs http://www.cypress.com/?rID=29542  


MSL for all the Cypress parts is available in part quality report.


Please find the quality reports for SRAMs available on following link:

http://www.cypress.com/?rID=38078

]]> Wed, 02 Feb 2011 22:46:55 -0600 Interfacing Cypress MoBL® Asynchronous Dual- Port to TI OMAP2420 Multimedia Processor - AN5056 http://www.cypress.com/?rID=48515 Tue, 25 Jan 2011 03:55:26 -0600 Developing Low-Cost Modular Handset Architectures Using Dual-Port Interconnects http://www.cypress.com/?rID=14502 Thu, 13 Nov 2008 00:00:00 -0600 Discrete Memories Trade Off with ASIC Cells http://www.cypress.com/?rID=14499 ISD Magazine (USA)

eetimes.com

Component selection is all about making hard decisions when determining what parts best suit your system needs." Common trade-offs include price vs. performance and integration vs. time-to-market. System-on-a-chip is a concept that is often discussed, written about and dreamed about. However, the realities of system design reveal flaws in the theoretical search for greater integration. To the first order, from a performance standpoint, integration is usually best. However, from a density and time-to-market standpoint, a discrete solution is often the better choice. A perfect example that illustrates these concepts can be found in the area of true dual-ported memory.

For more information on our Dual-Port products, visit: cypress.com

]]> Thu, 13 Nov 2008 00:00:00 -0600 Leveraging Cypress High-Performance FullFlex™ Dual-Port Interconnects In Next-Generation System Design http://www.cypress.com/?rID=14539 The increasing complexity in high-speed digital design creates a threat to timely system development, and therefore, to the success of the end product. Today's system architecture decisions are influenced not only by rapidly evolving families of processing elements, but also by time-to-market pressure. These challenges can be compounded in systems that have multiple processors on a single platform or multiple platforms entirely.

Dual-port interconnects have gained a reputation as highly flexible bridges between two independent sub-systems that do not have the ability to communicate with one another. In essence, the "apples" were able to talk to the "oranges." This created a greater freedom in component selection and enabled shortened design cycles. New dual-port interconnects provide much more than just a memory buffer between two processing elements. With ultra-wide data bus width and high clock speeds, new dual-port interconnects provide enough data throughput to support the most bandwidth-demanding applications.  New feature offerings such as variable impedance matching and deterministic access control also greatly simplify the development and debug of next generation, high-performance system designs.  To view more on this topic, click one of the download links above. 

]]> Thu, 13 Nov 2008 00:00:00 -0600 Optimize Inter-processor Communication in Dual Baseband Dual Mode Handsets http://www.cypress.com/?rID=14540 Mobile Handset DesignLine.]]> Thu, 13 Nov 2008 00:00:00 -0600 Using Dual Port Interconnect to Resolve Multiprocessor System Bottlenecks http://www.cypress.com/?rID=14501 http://www.embedded.com/shared/printableArticle.jhtml?articleID=177100584]]> Thu, 13 Nov 2008 00:00:00 -0600 Using low-power dual-port for inter processor communication in next generation mobile handsets http://www.cypress.com/?rID=14504 Mobile Handset DesignLine.]]> Thu, 13 Nov 2008 00:00:00 -0600 Developing Low-Cost Modular Handset Architectures Using Dual-Port Interconnects http://www.cypress.com/?rID=115 Mon, 08 Sep 2008 10:48:40 -0600 MoBL ADM Dual Port Static RAM Family R52LD-3 Technology, Fab4 http://www.cypress.com/?rID=35929 Thu, 20 Sep 2007 00:00:00 -0600 MoBL Dual Port Split Voltage RAM Device Family, R52LD3 Technology, Fab4 http://www.cypress.com/?rID=35841 Mon, 24 Apr 2006 00:00:00 -0600 MoBL Dual Port RAM Family, R52LD3 Technology, Fab4 http://www.cypress.com/?rID=35802 Mon, 07 Nov 2005 00:00:00 -0600