*Refer to Migrating CY8CKIT-001 DVK project to CY8CKIT 030/ 050.

1. Click on AN84741 - PSoC® 5 to PSoC 5LP Migration Guide to learn differences between PSoC 5 and PSoC 5LP.
2. Click on AN77835 - PSoC® 3 to PSoC 5LP Migration Guide to learn differences between PSoC 3 and PSoC 5LP.
3. For PSoC 5 project and related document, please download file AN75111_Archive.zip.

Projects associated with this application note can be downloaded from the 'Related Files' section below. For your convenience, we have provided projects that are compatible with the two most recent versions of PSoC Creator:

• AN75111.zip is used with PSoC Creator 2.1 SP1
• AN75111_Archive.zip is used with PSoC Creator 2.1/2.0

The project’s default settings may not be compatible with your device or kit, and you may need to change your project settings. For more information, see:

The architecture TRM contains complete and detailed information about how to use and design with the IP blocks that construct a PSoC device. This document describes the analog and digital architecture to give the designer a better understanding of features and limitations.

The registers TRM covers the registers of the device. The document lists all the registers in mapping tables, in address order.

The programming specifications documents explain the hardware connections, programming protocol, programming vectors, and the timing information for developing programming solutions for a PSoC device.

Cypress’s PSoC programmable system-on-chip architecture gives you the freedom to not only imagine revolutionary new products, but the capability to also get those products to market faster than anyone else.

Hardware Description

The kit contains:

• PT100 Class B Resistive Temperature Detector (RTD)
• Type K Thermocouple
• NTC Thermistor
• 2 Temperature Diodes (2N3904 transistors)
• DS600 IC temperature sensor
• Examples projects for temperature sensing measurement, combined temperature and voltage measurement and fan control
• Includes a bonus CY8CKIT-012 PSoC Prototyping and Development Expansion Board
• Quick Start Guide
• Resource CD 

For PSoC training, please visit http://www.cypress.com/go/training

Software Title	Description	Link
PSoC Creator	This kit requires PSoC Creator for development

Features

• Powerful Harvard Architecture Processor
• Flexible On-Chip Memory
• Complete Development Tools
• Precision, Programmable Clocking
• Programmable Pin Configurations
• Additional System Resources
• For more, see pdf
   

Functional Overview

The enCoRe V LV family of devices are designed to replace multiple traditional low voltage microcontroller system components with one, low cost single chip programmable component. Communication peripherals (I2C/SPI), a fast CPU, Flash program memory, SRAM data memory, and configurable I/O are included in a range of convenient pinouts.

Introduction

PSoC 3, PSoC 4 and PSoC 5LP (hereafter referred to as "PSoC") support a wide variety of functions, called components. Many of these components are implemented using the programmable logic inside the PSoC. As a result, you can create your own components and use them in PSoC Creator projects.

1. Click on AN84741 - PSoC® 5 to PSoC 5LP Migration Guide to learn differences between PSoC 5 and PSoC 5LP.
2. Click on AN77835 - PSoC® 3 to PSoC 5LP Migration Guide to learn differences between PSoC 3 and PSoC 5LP.
3. For PSoC 5 project and related document, please download file AN82156_Archive.zip.
    

Projects associated with this application note can be downloaded from the 'Related Files' section below. For your convenience, we have provided projects that are compatible with the two most recent versions of PSoC Creator:

• AN82156.zip is used with PSoC Creator 2.1 SP1
• AN82156_Archive.zip is used with PSoC Creator 2.1/2.0

The project’s default settings may not be compatible with your device or kit, and you may need to change your project settings. For more information, see:

Notes:

1. Click on AN84741 - PSoC® 5 to PSoC 5LP Migration Guide to learn differences between PSoC 5 and PSoC 5LP.
2. Click on AN77835 - PSoC® 3 to PSoC 5LP Migration Guide to learn differences between PSoC 3 and PSoC 5LP.

Features

• 256-Kbit nonvolatile static random access memory (nvSRAM)
  • Internally organized as 32 K × 8
  • STORE to QuantumTrap nonvolatile elements initiated automatically on power-down (AutoStore) or by using I2C command (Software STORE) or HSB pin (Hardware STORE)
  • RECALL to SRAM initiated on power-up (Power-Up RECALL) or by I²C command (Software RECALL)
  • Automatic STORE on power-down with a small capacitor (except for CY14MX256J1)
• High reliability
  • Infinite read, write, and RECALL cycles
  • 1 million STORE cycles to QuantumTrap
  • Data retention: 20 years at 85°C
• For more, see pdf

Overview

The Cypress CY14MC256J/CY14MB256J/CY14ME256J combines a 256-Kbit nvSRAM with a nonvolatile element in each memory cell. The memory is organized as 32 K words of 8 bits each. The embedded nonvolatile elements incorporate the QuantumTrap technology, creating the world’s most reliable nonvolatile memory. The SRAM provides infinite read and write cycles, while the QuantumTrap cells provide highly reliable nonvolatile storage of data.

Features

• Radio System-on-Chip, with built-in 8-bit MCU in a single device.
• Operates in the unlicensed worldwide Industrial, Scientific, and Medical (ISM) band (2.400 GHz to 2.483 GHz).
• On Air compatible with second generation radio WirelessUSB™ LP and PRoC LP.
• Pin-to-pin compatible with PRoC LP except the Pin31 and Pin37. 

Intelligent

• M8C based 8-bit CPU, optimized for human interface devices (HID) applications
• 256 bytes of SRAM
• 8 Kbytes of flash memory with EEPROM emulation
• In-System reprogrammable through D+/D– pins
• CPU speed up to 12 MHz
• For more, see pdf

Functional Description

PRoC LPstar devices are integrated radio and microcontroller functions in the same package to provide a dual role single-chip solution.

Communication between the microcontroller and the radio is via the SPI interface between both functions.

High Integration Device Replaces Multiple Parts

• Serial Nonvolatile Memory
• Real-time Clock (RTC)
• Low Voltage Reset
• Watchdog Timer
• Early Power-Fail Warning/NMI
• Two 16-bit Event Counters
• Serial Number with Write-lock for Security
• For more, see pdf.

Description

The FM31xx is a family of integrated devices that includes the most commonly needed functions for processor-based systems. Major features include nonvolatile memory available in various sizes, real-time clock, low-VDD reset, watchdog timer, nonvolatile event counter, lockable 64-bit serial number area, and general purpose comparator that can be used for an early power-fail (NMI) interruptor other purpose. The family operates from 2.7 to 5.5V.

Features

• Supports bus operation up to 200 MHz
• Available speed grades are 200 and 167 MHz
• Registered inputs and outputs for pipelined operation
• 3.3 V core power supply
• 2.5 V/3.3 V I/O operation
• Fast clock-to-output times
  • 3.0 ns (for 200 MHz device)
• Provide high performance 3-1-1-1 access rate
• User selectable burst counter supporting Intel® Pentium® interleaved or linear burst sequences
• For more, see pdf
   

Functional Description

The CY7C1480V33 SRAM integrates 2 M × 36 SRAM cells with advanced synchronous peripheral circuitry and a two-bit counter for internal burst operation. All synchronous inputs are gated by registers controlled by a positive-edge-triggered Clock Input (CLK).

Features

• 256-Kbit nonvolatile static random access memory (nvSRAM)
  • Internally organized as 32 K × 8
  • STORE to QuantumTrap nonvolatile elements initiated automatically on power-down (AutoStore) or by using I²C command (Software STORE) or HSB pin (Hardware STORE)
  • RECALL to SRAM initiated on power-up (Power-Up RECALL) or by I²C command (Software RECALL)
  • Automatic STORE on power-down with a small capacitor
• High reliability
  • Infinite read, write, and RECALL cycles
  • 1 million STORE cycles to QuantumTrap
  • Data retention: 20 years at 85 °C
• For more, see pdf

Overview

The Cypress CY14C256I/CY14B256I/CY14E256I combines a 256-Kbit nvSRAM with a full-featured RTC in a monolithic integrated circuit with serial I2C interface. The memory is organized as 64 K words of 8 bits each. The embedded nonvolatile elements incorporate the QuantumTrap technology, creating the world’s most reliable nonvolatile memory. The SRAM provides infinite read and write cycles, while the QuantumTrap cells provide highly reliable nonvolatile storage of data. Data transfers from SRAM to the nonvolatile elements (STORE operation) takes place automatically at power-down. On power-up, data is restored to the SRAM from the nonvolatile memory (RECALL operation). The STORE and RECALL operations can also be initiated by the user through I2C commands.

Features

• 1-Mbit nonvolatile static random access memory (nvSRAM)
  • Internally organized as 128 K × 8
  • STORE to QuantumTrap nonvolatile elements initiated automatically on power-down (AutoStore) or by using I²C command (Software STORE) or HSB pin (Hardware STORE)
  • RECALL to SRAM initiated on power-up (Power-Up RECALL) or by I²C command (Software RECALL)
  • Automatic STORE on power-down with a small capacitor (except for CY14X101J1)
• High reliability
  • Infinite read, write, and RECALL cycles
  • 1 million STORE cycles to QuantumTrap
  • Data retention: 20 years at 85 °C
• For more, see pdf
   

Overview

The Cypress CY14C101J/CY14B101J/CY14E101J combines a 1-Mbit nvSRAM with a nonvolatile element in each memory cell. The memory is organized as 128 K words of 8 bits each. The embedded nonvolatile elements incorporate the QuantumTrap technology, creating the world’s most reliable nonvolatile memory. The SRAM provides infinite read and write cycles, while the QuantumTrap cells provide highly reliable nonvolatile storage of data.

Features

• 64-Kbit nonvolatile static random access memory (nvSRAM)
  • Internally organized as 8 K × 8
  • STORE to QuantumTrap nonvolatile elements initiated automatically on power-down (AutoStore) or by using I2C command (Software STORE) or HSB pin (Hardware STORE)
  • RECALL to SRAM initiated on power-up (Power-Up RECALL) or by I2C command (Software RECALL)
  • Automatic STORE on power-down with a small capacitor (except for CY14MX064J1)
• High reliability
  • Infinite read, write, and RECALL cycles
  • 1 million STORE cycles to QuantumTrap
  • Data retention: 20 years at 85° C
• For more, see pdf

Overview

The Cypress CY14MB064J/CY14ME064J combines a 64-Kbit nvSRAM with a nonvolatile element in each memory cell. The memory is organized as 8 K words of 8 bits each. The embedded nonvolatile elements incorporate the QuantumTrap technology, creating the world’s most reliable nonvolatile memory. The SRAM provides infinite read and write cycles, while the QuantumTrap cells provide highly reliable nonvolatile storage of data.

Features

• 512-Kbit nonvolatile static random access memory (nvSRAM)
  • Internally organized as 64 K × 8
  • STORE to QuantumTrap nonvolatile elements initiated automatically on power-down (AutoStore) or by using I2C command (Software STORE) or HSB pin (Hardware STORE)
  • RECALL to SRAM initiated on power-up (Power-Up RECALL) or by I²C command (Software RECALL)
  • Automatic STORE on power-down with a small capacitor (except for CY14X512J1)
• High reliability
  • Infinite read, write, and RECALL cycles
  • 1 million STORE cycles to QuantumTrap
  • Data retention: 20 years at 85 °C
• For more, see pdf
   

Overview

The Cypress CY14C512J/CY14B512J/CY14E512J combines a 512-Kbit nvSRAM with a nonvolatile element in each memory cell. The memory is organized as 64 K words of 8 bits each. The embedded nonvolatile elements incorporate the QuantumTrap technology, creating the world’s most reliable nonvolatile memory. The SRAM provides infinite read and write cycles, while the QuantumTrap cells provide highly reliable nonvolatile storage of data. Data transfers from SRAM to the nonvolatile elements (STORE operation) takes place automatically at power-down (except for CY14X512J1). On power-up, data is restored to the SRAM from the nonvolatile memory (RECALL operation). The STORE and RECALL operations can also be initiated by the user through I2C commands.

Features

• Radio System-on-Chip with built-in 8-bit MCU in a single device.
• Operates in the unlicensed worldwide Industrial, Scientific, and Medical (ISM) band (2.400 GHz to 2.483 GHz).
• On Air compatible with second generation radio WirelessUSB™ LP and PRoC LP.
• Pin-to-pin compatible with PRoC LP except the Pin31 and Pin37.

Intelligent

• M8C based 8-bit CPU, optimized for human interface devices (HID) applications
• 256 bytes of SRAM
• 8 Kbytes of flash memory with EEPROM emulation
• In-system reprogrammable through D+/D– pins
• CPU speed up to 12 MHz
• For more, see pdf

 Functional Description

PRoC LPstar devices are integrated radio and microcontroller functions in the same package to provide a dual-role single-chip solution.

Communication between the microcontroller and the radio is through the radio’s SPI interface.

Features

• 512-Kbit nonvolatile static random access memory (nvSRAM)
  • Internally organized as 64 K × 8
  • STORE to QuantumTrap nonvolatile elements initiated automatically on power-down (AutoStore) or by using I2C command (Software STORE) or HSB pin (Hardware STORE)
  • RECALL to SRAM initiated on power-up (Power-Up RECALL) or by I2C command (Software RECALL)
  • Automatic STORE on power-down with a small capacitor
• High reliability
  • Infinite read, write, and RECALL cycles
  • 1 million STORE cycles to QuantumTrap
  • Data retention: 20 years at 85 °C
• For more, see pdf
   

Overview

The Cypress CY14C512I/CY14B512I/CY14E512I combines a 512-Kbit nvSRAM with a full-featured RTC in a monolithic integrated circuit with serial I2C interface. The memory is organized as 64 K words of 8 bits each. The embedded nonvolatile elements incorporate the QuantumTrap technology, creating the world’s most reliable nonvolatile memory. The SRAM provides infinite read and write cycles, while the QuantumTrap cells provide highly reliable nonvolatile storage of data. Data transfers from SRAM to the nonvolatile elements (STORE operation) takes place automatically at power-down. On power-up, data is restored to the SRAM from the nonvolatile memory (RECALL operation). The STORE and RECALL operations can also be initiated by the user through I2C commands.

Features

• Supports up to 100-MHz bus operations with zero wait states
  • Data is transferred on every clock
• Pin compatible and functionally equivalent to ZBT™ devices
• Internally self timed output buffer control to eliminate the need to use OE
• Registered inputs for flow-through operation
• Byte write capability
• 256 K × 18 common IO architecture
• 2.5 V / 3.3 V IO power supply (VDDQ)
• Fast clock-to-output times
• For more, see pdf
   

Functional Description

The CY7C1353G is a 3.3 V, 256 K × 18 synchronous flow-through burst SRAM designed specifically to support unlimited true back-to-back read/write operations without the insertion of wait states. The CY7C1353G is equipped with the advanced No Bus Latency™ (NoBL™) logic required to enable consecutive read/write operations with data being transferred on every clock cycle. This feature dramatically improves the throughput of data through the SRAM, especially in systems that require frequent write-read transitions.

Features

• Supports bus operation up to 250 MHz
• Available speed grades are 250, 200, and 167 MHz
• Registered inputs and outputs for pipelined operation
• 3.3V core power supply
• 2.5V or 3.3V I/O power supply
• Fast clock-to-output times
  • 2.6 ns (for 250 MHz device)
• Provides high performance 3-1-1-1 access rate
• User selectable burst counter supporting Intel Pentium® interleaved or linear burst sequences
• For more, see pdf

Functional Description

The CY7C1380D/CY7C1380F/CY7C1382D SRAM integrates 524,288 × 36 and 1,048,576 × 18 SRAM cells with advanced synchronous peripheral circuitry and a two-bit counter for internal burst operation. All synchronous inputs are gated by registers controlled by a positive edge triggered clock input (CLK). The synchronous inputs include all addresses, all data inputs, address-pipelining chip enable (CE1), depth-expansion chip enables (CE2 and CE3), burst control inputs (ADSC, ADSP, and ADV), write enables (BWX, and BWE), and global write (GW). Asynchronous inputs include the output enable (OE) and the ZZ pin. 

Features

• Can support up to 133-MHz bus operations with zero wait states
  • Data is transferred on every clock
• Pin compatible and functionally equivalent to ZBT™ devices
• Internally self-timed output buffer control to eliminate the need to use OE
• Registered inputs for flow-through operation
• Byte write capability
• 128 K × 36 common I/O architecture
• 2.5 V/3.3 V I/O power supply (VDDQ)
• Fast clock-to-output times
• For more, see pdf

Functional Description

The CY7C1351G is a 3.3 V, 128 K × 36 synchronous flow-through burst SRAM designed specifically to support unlimited true back-to-back read/write operations without the insertion of wait states. The CY7C1351G is equipped with the advanced No Bus Latency™ (NoBL™) logic required to enable consecutive Read/Write operations with data being transferred on every clock cycle. This feature dramatically improves the throughput of data through the SRAM, especially in systems that require frequent write-read transitions.

The following table indicates the PSoC devices, PSoC Creator versions, compilers, and development kits that will work with this application note project:

*Refer to Migrating CY8CKIT-001 DVK project to CY8CKIT 030/ 050. 

1. Click on AN84741 - PSoC® 5 to PSoC 5LP Migration Guide to learn differences between PSoC 5 and PSoC 5LP.
2. For PSoC 5 project and related document, please download file AN60590_Archive.zip.

Projects associated with this application note can be downloaded from the ‘Related Files’ section below. For your convenience, we have provided projects that are compatible with the two most recent versions of PSoC Creator:

• AN60590.zip is used with PSoC Creator 2.1 SP1.
• AN60590_Archive.zip is used with PSoC Creator 2.1/2.0.

The project’s default settings may not be compatible with your device or kit, and you may need to change your project settings. For more information, see:

Features

• Supports 133 MHz bus operations
• 512K × 36 and 1M × 18 common I/O
• 3.3V core power supply (VDD)
• 2.5V or 3.3V I/O supply (VDDQ)
• Fast clock-to-output time
  • 6.5 ns (133 MHz version)
• Provides high performance 2-1-1-1 access rate
• User selectable burst counter supporting Intel Pentium interleaved or linear burst sequences
• Separate processor and controller address strobes
• For more, see pdf
   

Functional Description

The CY7C1381D/CY7C1383D/CY7C1383F is a 3.3 V, 512 K × 36 and 1 M × 18 synchronous flow through SRAMs, designed to interface with high speed microprocessors with minimum glue logic. Maximum access delay from clock rise is 6.5 ns (133 MHz version). A 2-bit on-chip counter captures the first address in a burst and increments the address automatically for the rest of the burst access. All synchronous inputs are gated by registers controlled by a positive edge triggered clock input (CLK).

Features

• 64-Kbit nonvolatile static random access memory (nvSRAM)
  • Internally organized as 8 K × 8
  • STORE to QuantumTrap nonvolatile elements initiated automatically on power-down (AutoStore) or by using SPI instruction (Software STORE) or HSB pin (Hardware STORE)
  • RECALL to SRAM initiated on power-up (Power Up RECALL) or by SPI instruction (Software RECALL)
  • Automatic STORE on power-down with a small capacitor
• High reliability
  • Infinite read, write, and RECALL cycles
  • 1 million STORE cycles to QuantumTrap
  • Data retention: 20 years at 85 °C
• For more, see pdf
   

Overview

The Cypress CY14X064PA combines a 64 Kbit nvSRAM with a full-featured RTC in a monolithic integrated circuit with serial SPI interface. The memory is organized as 8 K words of 8 bits each. The embedded nonvolatile elements incorporate the QuantumTrap technology, creating the world’s most reliable nonvolatile memory. The SRAM provides infinite read and write cycles, while the QuantumTrap cells provide highly reliable nonvolatile storage of data. Data transfers from SRAM to the nonvolatile elements (STORE operation) takes place automatically at power-down. On power-up, data is restored to the SRAM from the nonvolatile memory (RECALL operation). You can also initiate the STORE and RECALL operations through SPI instruction.

High Integration Device Replaces Multiple Parts

• Serial Nonvolatile Memory
• Real-time Clock (RTC)
• Low Voltage Reset
• Watchdog Timer
• Early Power-Fail Warning/NMI
• Two 16-bit Event Counters
• Serial Number with Write-lock for Security
• For more, see pdf.

Description

The FM3127x is a family of integrated devices that includes the most commonly needed functions for processor-based systems. Major features include nonvolatile memory available in various sizes, real-time clock, low-VDD reset, watchdog timer, nonvolatile event counter, lockable 64-bit serial number area, and general purpose comparator that can be used for an early power-fail (NMI) interrupt or other purpose. The family operates from 4.0 to 5.5V.

Features

• Pin compatible and functionally equivalent to ZBT™ devices
• Internally self-timed output buffer control to eliminate the need to use OE
• Byte write capability
• 256 K × 18 common I/O architecture
• 3.3 V core power supply (VDD)
• 2.5 V/3.3 V I/O power supply (VDDQ)
• Fast clock-to-output times
  • 4.0 ns (for 133-MHz device)
• Clock enable (CEN) pin to suspend operation
• For more, see pdf

Functional Description

The CY7C1352G is a 3.3 V, 256 K × 18 synchronous-pipelined burst SRAM designed specifically to support unlimited true back-to-back read/write operations without the insertion of wait states. The CY7C1352G is equipped with the advanced No Bus atency™ (NoBL™) logic required to enable consecutive read/write operations with data being transferred on every clock cycle. This feature dramatically improves the throughput of the SRAM, especially in systems that require frequent write/read transitions.

Features

• 256-Kbit nonvolatile static random access memory (nvSRAM)
  • Internally organized as 32 K × 8
  • STORE to QuantumTrap nonvolatile elements initiated automatically on power-down (AutoStore) or by using SPI instruction (Software STORE) or HSB pin (Hardware STORE)
  • RECALL to SRAM initiated on power-up (Power Up RECALL) or by SPI instruction (Software RECALL)
  • Automatic STORE on power-down with a small capacitor
• High reliability
  • Infinite read, write, and RECALL cycles
  • 1 million STORE cycles to QuantumTrap
  • Data retention: 20 years at 85 °C
• For more, see pdf

Overview

The Cypress CY14X256PA combines a 256-Kbit nvSRAM with a full-featured RTC in a monolithic integrated circuit with serial SPI interface. The memory is organized as 32 K words of 8 bits each. The embedded nonvolatile elements incorporate the QuantumTrap technology, creating the world’s most reliable nonvolatile memory. The SRAM provides infinite read and write cycles, while the QuantumTrap cells provide highly reliable nonvolatile storage of data. Data transfers from SRAM to the nonvolatile elements (STORE operation) takes place automatically at power-down. On power-up, data is restored to the SRAM from the nonvolatile memory (RECALL operation). You can also initiate the STORE and RECALL operations through SPI instruction.

Features

• 64-Kbit nonvolatile static random access memory (nvSRAM)
  • Internally organized as 8 K × 8
  • STORE to QuantumTrap nonvolatile elements initiated automatically on power-down (AutoStore) or by using I2C command (Software STORE) or HSB pin (Hardware STORE)
  • RECALL to SRAM initiated on power-up (Power-Up RECALL) or by I2C command (Software RECALL)
  • Automatic STORE on power-down with a small capacitor
• High reliability
  • Infinite read, write, and RECALL cycles
  • 1 million STORE cycles to QuantumTrap
  • Data retention: 20 years at 85 °C
• For more, see pdf

Overview

The Cypress CY14C064I/CY14B064I/CY14E064I combines a 64-Kbit nvSRAM with a full-featured RTC in a monolithic integrated circuit with serial I2C interface. The memory is organized as 8 K words of 8 bits each. The embedded nonvolatile elements incorporate the QuantumTrap technology, creating the world’s most reliable nonvolatile memory. The SRAM provides infinite read and write cycles, while the QuantumTrap cells provide highly reliable nonvolatile storage of data. Data transfers from SRAM to the nonvolatile elements (STORE operation) takes place automatically at power-down. On power-up, data is restored to the SRAM from the nonvolatile memory (RECALL operation). The STORE and RECALL operations can also be initiated by the user through I2C commands.

Refer to Getting Started with CapSense for more information on how to use springs as CapSense sensors.

Features

• Fully integrated 2.4-GHz radio on a chip
• 1-Mbps over-the-air data rate
• Transmit power typical: 0 dBm
• Receive sensitivity typical: –87 dBm
• 1 μA typical current consumption in sleep state
• Closed-loop frequency synthesis
• Supports frequency-hopping spread spectrum
• On-chip packet framer with 64-byte first in first out (FIFO) data buffer
• Built-in auto-retry-acknowledge protocol simplifies usage
• For more, see pdf

Product Description

WirelessUSB™-NL, optimized to operate in the 2.4-GHz ISM band, is Cypress's third generation of 2.4-GHz low-power RF technology, bringing the next level of low-power performance into a small 4-mm × 4-mm footprint. WirelessUSB-NL implements a Gaussian frequency-shift keying (GFSK) radio using a differentiated single-mixer, closed-loop modulation design that optimizes power efficiency and interference immunity.

This application note provides a few example circuits, design guidelines, and PSoC®3 based sample code snippets to help users understand and design with Cypress I²C nvSRAM.

An "I²C nvRAM" component library is also created using Cypress PSoC®3 device as a reference design project and attached to this Application Note. The PSoC®3 component library configures Cypress PSoC®3 device as a standard I²C master controller and also provides the list of APIs which can directly be called in an application firmware to access the I²C nvSRAM functions.

The SDK installation package as well as zip/tar archives of individual components are available below for download. Given below is a brief description of these downloadable items to help you select the right file(s) to download.

1. EZ-USB FX3 SDK Installer - This is the master installer file that will install the firmware library with samples, USB Suite with Windows host driver and applications, Eclipse IDE & GCC tool chain. Once installed using the installer, Cypress Update Manager will enable users to look for updated versions of these software modules and facilitate upgrades.
2. Firmware Library Zip – A zip archive that contains the FX3 firmware libraries, driver sources for serial peripheral modules, header files, example code, firmware conversion utility and documentation. The following firmware source samples are also part of the library zip file.
   • USB Bulk data loopback and source/sink
   • USB Isochronous loopback and source/sink
   • DMA examples: Interleaved and multicast data
   • Serial Interface Loopback: UART, SPI, I2C and I2S
   • Slave FIFO: Synchronous and Asynchronous
   • USB Video Class: Isochronous and Bulk
   • USB Mass Storage Bulk-Only transport
   • USB Audio Class: Input (microphone) device
3. USB Suite Zip – A zip archive containing windows host driver, C++ & C# API libraries, and the control center, bulkloop and streamer applications for 32 bit platforms (Windows XP, Vista and Windows 7) and 64 bit platforms (Windows Vista and Windows 7)
4. FX3 SDK for Linux platforms – A tar archive containing the FX3 firmware libraries and examples, the ARM GNU toolchain, Eclipse IDEs (x64 and x86 versions) and the CyUSB suite for Linux platforms
5. USB Suite for MacOS - A libusb based wrapper library for Mac OS, to facilitate USB host application development.
6. Documentation
   • FX3 Programmer's Manual
   • FX3 API guide
   • FX3 Release Notes
   • Trouble shooting guide

• 

The PSoC 4 Pioneer Kit is an easy-to-use and inexpensive development platform enabling you to create unique designs with the flexibility of PSoC^®4. Featuring the PSoC 4200 device family, this kit gives you the power of an ARM Cortex-M0 combined with the fully customizable analog and digital fabric of the PSoC in the palm of your hands.

Infinitely Expandable

The PSoC 4 Pioneer Kit includes connectors for Arduino™ compatible shields and Digilent® Pmod™ daughter cards, enabling you to pick from a variety of 3rd party expansion boards. The board also features a CapSense® slider, an RGB LED, a user button, and more!

Designed for Low Power

The PSoC 4 architecture supports an extremely low-leakage hibernate mode consuming only 150nA. It features a best-in-class 20nA stop mode, eliminating the need for external power circuitry for sleep and wake-up control. While in active mode, it provides fully functional analog capabilities from 1.71 – 5.5V.

Debug like a Pro

An onboard PSoC 5LP device serves as the programmer and debugger, eliminating the need for external programmers. Interface through the USB connector to talk to your PC over SWD, USB-UART, or USB-I2C. With PSoC Creator™ you can design your system, write firmware, and step-through code using the built-in debugger.

• Kit Contents:
  • PSoC 4 Pioneer Kit Board
  • Quick Start Guide
  • USB A to mini-B Cable
  • Jumper Wires (x6)

PSoC 4 Pioneer Kit Product Brief
PSoC 4 Pioneer Kit Press Release

For PSoC training, please visit  http://www.cypress.com/go/training .

Software Title	Description	Link
PSoC Creator	This kit requires PSoC Creator for development
PSoC Programmer	This kit requires PSoC Programmer for programming

Kit Upgrade: Now it’s time to make the upgrade to PSoC® 5LP Processor Module and take advantage of all that PSoC has to offer.

These upgrades are FREE to our valued customers. Log on to http://www.cypress.com/go/psockitupgrade to know more details. Cypress appreciates your business and continued loyalty.

Kit Contents:

• PSoC Development Board 
• PSoC 1 CY8C28 Family Processor Module
• PSoC 3 CY8C38 Family Processor Module
• PSoC 5 CY8C58LP Family Processor Module
• MiniProg3 Program/Debug Device
• Program/Debug Ribbon Cable
• USB Cable
• 12V AC Power Adapter
• Quick Start Guide
• Kit CDs, which includes: PSoC Creator™, PSoC Designer™, PSoC Programmer, Projects, and Documentation

For PSoC training, please visit http://www.cypress.com/go/training.

Software Title	Description	Link
PSoC Creator	This kit requires PSoC Creator for development
PSoC Designer	This kit requires PSoC Designer for development
PSoC Programmer	This kit requires PSoC Programmer for programming

• SWD
• JTAG
• ISSP
• USB-I2C

Included with the kit is a 10-pin ribbon cable for connecting to standard 10-pin JTAG header interfaces utilized for our PSoC 3 and PSoC 5 architectures while the device itself supports the 5-pin ISSP programming header for PSoC 1 architectures. The 5-pin connector also supports the USB-I2C Bridging capabilities and is a superset of the CY3240 capabilities. Please note, the CY8CKIT-002 only contains the Miniprog3 and supporting cables.

Kit Upgrade: Now it’s time to make the upgrade to MiniProg3 revision *B if you wish to perform Power Cycle programming but have MiniProg3 revision *A (CY8CKIT-002). This upgrade is FREE to our valued customers.

Log on to www.cypress.com/go/psockitupgrade to know more details. Cypress appreciates your business and continued loyalty.

Miniprog3 *B Revision Update:

Cypress Semiconductor has completed a hardware update to the Miniprog3 to address hardware issues seen with programming, ESD, and power management. The Miniprog3 revision, either *A or *B, is indicated using sticker on the back of the programmer. The following are a list of updates made to the Miniprog3 *B programmer.

Updated Hardware to Improve Power Cycle Programming:

The Miniprog3 hardware has been updated to better improve power cycle programming for all PSoC devices. It was discovered that the Miniprog3 *A programmer revision did not correctly implement the power cycle programming methodology. Due to this issue the Miniprog3 *A programmer could not correctly support power cycle programming for PSoC 3 and PSoC 5 devices. This specifically impacts customers who do not route out the XRES line to the programming connector or disable the optional XRES line on certain devices. The *B revision of the Miniprog3 will support power cycle programming for all PSoC 3 and PSoC 5 devices.

Over-current and Non-Polarized Connection Updates:

There are known electrical risks to the Miniprog3 *A revision that have been addressed with the *B update. To address the electrical issues the Miniprog3 *B programmer has added ESD over-current protection to the USB lines and has added electrical protection to the 5 and 10-pin connectors in case of a reverse polarity condition.

Improved Voltage Detection Capabilities:

The Miniprog3 *B programmer has been updated to improve the voltage detection capabilities. The Miniprog3 will measure the target voltage within an accuracy of 20 mV for a range of 1.8V – 5.0V.

Supported Software:

The Miniprog3 *B programmer is supported on the latest release of PSoC Programmer. To download the latest release, please navigate to the PSoC Programmer web page:

www.cypress.com/go/psocprogrammer

The Miniprog3 programmer is part of a suite of programming options and programming content available to PSoC users. For customers who are looking for more information on general programming options and information please navigate to the web page linked below. On the General Programming web page we discuss all of the available programming options for customers including Software, Schematics, Programming Specifications, and 3rd party mass programming.

If you are new to the PSoC family of devices and the PSoC Creator™ development tool, read the supplemental material available within the PSoC Creator integrated development environment (IDE). Launch PSoC Creator and navigate to the following items:

• Quick Start Guide: Select the menu item: Help > Documentation > Quick Start Guide. This guide teaches you how to create projects using PSoC Creator.
• Simple Component Example Projects: Select File > Open > Example projects. These example projects demonstrate how to configure and use Creator components.
• Starter Designs: Select File > New > Project > PSoC3 Starter Designs (or) PSoC 5LP Starter Designs. These starter designs demonstrate the unique features of the PSoC 3 and PSoC 5LP product families.

The Cypress website at www.cypress.com has additional resources for your learning needs:

Training videos: Cypress website has several “Training on-Demand” videos for PSoC 3 and PSoC 5LP. These videos are located at http://www.cypress.com/?id=2232&rtID=134. Some of the listed videos are:

• PSoC 3 and PSoC 5 101: Introduction to the Architecture and Design Flow
• PSoC 3 and PSoC 5 102: Introduction to System Resources
• PSoC 3 and PSoC 5 103: Introduction to Digital Peripherals
• PSoC 3 and PSoC 5 104: Introduction to Analog Peripherals
• Introduction to PSoC Creator

Application Notes (ANs): Application notes are available on the Cypress website to assist you with designing your PSoC application:

• A list of PSoC 3 ANs is available at http://www.cypress.com/?id=2232&rtID=76
• A list of PSoC 5LP ANs is available at http://www.cypress.com/?id=4562&rtID=76

Here are a few application notes that can help you get started with developing PSoC 3 and PSoC 5LP applications:

• AN54181 - Getting Started with PSoC® 3
• AN77759 - Getting Started with PSoC® 5LP
• AN52705 - PSoC® 3 and PSoC 5LP - Getting Started with DMA
• AN77835 - PSoC® 3 to PSoC 5LP Migration Guide
• AN57821 - PSoC® 3 and PSoC 5LP Mixed Signal Circuit Board Layout Considerations
• AN61290 - PSoC® 3 and PSoC 5LP Hardware Design Considerations

Component Datasheets: PSoC Creator utilizes "components" as interfaces to functional Hardware (HW). Each component in PSoC Creator has an associated datasheet that describes the functionality, APIs, and electrical specifications for the HW. You can access component datasheets in PSoC Creator by right-clicking a component on the schematic page or by going through the component library listing. You can also access component datasheets from the Cypress website:

• PSoC 3 Component Datasheets
• PSoC 5LP Component Datasheets

In most cases, the component datasheet provides sufficient documentation for development use. If you need additional information, refer to the technical reference manual.

Technical Reference Manuals: The TRM provides detailed descriptions of the internal architecture of PSoC 3 and PSoC 5LP devices:

• PSoC 3 Technical Reference Manuals
• PSoC 5LP Technical Reference Manuals

Datasheets: Device datasheets list the features and electrical specifications of PSoC 3 and PSoC 5LP families of devices:

• PSoC 3 Datasheets
• PSoC 5LP Datasheets

Technical Support: If you have any queries or questions, our technical support team would be happy to assist you. You can create a support request at https://secure.cypress.com/myaccount/?id=25&techSupport=1, or if you are in the United States, you can talk to our technical support team by calling our toll-free number +1-800-541-4736 and then selecting option 8 at the IVR prompt.

You can also use the following support resources if you need quick assistance:

• Self-help: http://www.cypress.com/support
• Local Sales office locations: http://www.cypress.com/?id=1062

However, for production, you will need your own VID/PID to pass USB compliance and get the hub certified. You can configure the hub to use your VID/PID either of the following ways:

1. Add an external EEPROM to your design. The external EEPROM will be programmed to provide your VID/PID, descriptors, and other hub configuration settings.


2. Purchase your parts with the internal fuse links set to your VID/PID (this is a factory function only and cannot be done after packaging).

For more information, refer to the device datasheet.

Features

• XRES pin to support in-system serial programming (ISSP) and external reset control in CY8C24894
• Powerful Harvard-architecture processor
• Advanced peripherals (PSoC® Blocks)
• Full speed USB (12 Mbps)
• Flexible on-chip memory
• Programmable pin configurations
• Precision, programmable clocking
• Additional system resources
• For more, see pdf

PSoC Functional Overview

The PSoC family consists of many devices with on-chip controllers. These devices are designed to replace multiple traditional MCU-based system components with one low-cost single-chip programmable component. A PSoC device includes configurable blocks of analog and digital logic, and programmable interconnect. This architecture makes it possible for you to create customized peripheral configurations, to match the requirements of each individual application.

Each user module is a combination of information on the interconnections of PSoC resources and the software used to control them. It is possible to generate new UMs or customize existing UMs. Different UMs can be combined to produce a new UM. These new UMs can be similar to the old ones, with no hardware changes and only with API changes.

• Three modes of operation of the FX1/FX2LP
• Endpoint Configuration and Multiple Buffering
• Three Domains that form the basic component of the FIFO architecture
• Arming and committing endpoint buffers
• Endpoint operation in manual vs. auto mode

FX2LP was designed to be used in either one of the modes: Port I/O, Slave FIFO, or GPIF. For more information, refer to the application note Endpoint FIFO Architecture of EZ-USB FX1/FX2(TM) - AN4067.

It is possible to switch from one mode to another. Before switching from slave FIFO to GPIF or vice versa, you must make sure that there is no data transfer in progress as far as the physical interface is concerned or for that master on the USB end (host is not sending or receiving data from any of the endpoint).

You must make sure that the FIFO is reset and the device is in a state (no data activity in progress). When this is done, you may switch from one mode to the other. Switching from one mode of operation to another is not an intended feature, but something that you may do as long as the device is in a stable state.

For reading and writing to the external memory you can download vend_ax example to the device, and then use the A3 vendor command. Both these vendor commands use Value field to specify the memory location.

Note Install CY3684 FX2LP and CY3681 FX2 development kits for a different version of vend_ax (file path:C:\Cypress\USB\Examples).

• Limits analog routing of a signal to a specific routing resource
• All terminals on the signal must connect directly to the routing resource

Note: Routing is strict. All of the devices connected to the net with the resource constraint must have a direct hardware connection to the resource. Refer to the Analog Routing Diagram in the applicable Technical Reference Manual (TRM), which is available from the Cypress website, www.cypress.com. If the resources do not have a hardware connection to the specified constraint, an error will occur.

General Description

The Analog Resource Constraint component allows you to define the route of the analog signal to which it is connected. This is an advanced feature that is not needed for most designs, and should be used with caution. 

Required Software: PSoC Creator 2.2 and above

• Limits analog routing of an switchable mux connection to a specific routing resource
• All terminals on the signal must connect directly to the routing resource

Note: Routing is strict. All of the devices connected to the net with the resource constraint must have a direct hardware connection to the resource. Refer to the Analog Routing Diagram in the applicable Technical Reference Manual (TRM), which is available from the Cypress website, www.cypress.com. If the resources do not have a hardware connection to the specified constraint, an error will occur.


General Description

The Analog Mux Constraint component allows you to define the route of the analog signal on the switchable mux connection to which it is connected. This is an advanced feature that is not needed for most designs, and should be used with caution.

Required Software: PSoC Creator 2.2 and above

• Connects two analog routes
• Connects a constrained analog route with an unconstrained analog route
• Connects two analog routes with different routing resource constraints

General Description

The Net Tie component connects two analog routes to each other. Each of the routes may have a different analog resource constraint.
 

Required Software: PSoC Creator 2.2 and above

• Monitor up to 32 voltage inputs
• User-defined over and under voltage limits
• Simply outputs a good/bad status result

General Description

The Voltage Fault Detector component provides a simple way to monitor up to 32 voltage inputs against user-defined over and under voltage limits without using the ADC and without having to write any firmware. The component simply outputs a good/bad status result (“power good” or pgood[x]) for each voltage being monitored.

The component operates entirely in hardware without any intervention from PSoC’s CPU core resulting in known, fixed fault detection latency.

Note: This component supports PSoC 3 and PSoC 5LP devices only.

Required Software: PSoC Creator 2.1 and above

• Supports sequencing and monitoring of up to 32 power converter rails
• Supports power converter circuits with logic-level enable inputs and logic-level power good (pgood) status outputs
• Autonomous (standalone) or host driven operation
• Sequence order, timing and inter-rail dependencies can be configured through an intuitive, easy-to-use graphical configuration GUI

General Description

The Voltage Sequencer component provides a simple way to define power-up and power-down sequencing of up to 32 power converters to meet user-defined system requirements. Once the sequencing requirements have been entered into the easy-to-use graphical configuration GUI, the component will automatically take care of the sequencing implementation without requiring any firmware development by the user.

Required Software: PSoC Creator 2.1 and above

• Provides an editor to enter the assembler instructions to configure the DFB block and an assembler that converts the assembly instructions to instruction words.
• Supports simulation of the assembly instructions.
• Supports a code optimization option that provides a mechanism to incorporate up to 128 very large instruction words inside the DFB Code RAM.
• Provides hardware signals such as DMA requests, DSI inputs and outputs, and interrupt lines.
• Supports semaphores to interact with the system software and the option to tie the semaphores to hardware signals.

General Description

The digital filter block (DFB) in PSoC 3 and PSoC 5 can be used as mini DSP processor and allows you to configure the DFB using assembly instructions. The component assembles the instructions entered in the editor and generates the corresponding hex code words, which can be loaded into the DFB. It also includes a simulator, which helps the user to simulate and debug the assembly instructions.

The DFB consists of a programmable 24*24 multiplier/accumulator (MAC), an arithmetic logic unit (ALU), shifter, and various program and data memory to store instructions and data. The DFB runs on the bus clock, and can interface with both CPU and DMA. It can be used to offload the CPU and can speed up arithmetic calculations that involve intensive multiply accumulate operations. Typical operations you can use the DFB component to implement include: vector operations, matrix operations, filtering operations, and signal processing.

Required Software: PSoC Creator 2.0 Component Pack 2 and above

• Up to four Secure Digital (SD) cards in SPI mode
• FAT12/16 or FAT32 format
• Optional integration with an Operating System (OS)
• Optional Long File Name (LFN) handling

General Description

The emFile component provides an interface to SD cards formatted with a FAT file system. The SD card specification includes multiple hardware interface options for communication with an SD card. This component uses the SPI interface method for communication. Up to four independent SPI interfaces can be used for communication with one SD card each. Both FAT12/16 and FAT32 file system formats are supported. This component provides the physical interface to the SD card and works with the emFile library licensed from SEGGER Microcontroller to provide a library of functions to manipulate a FAT file system.

Required Software: PSoC Creator 2.0 Component Pack 1 and above

Firmware Installation:  The firmware files for this component are not distributed with PSoC Creator and can be downloaded below. Please refer to the component datasheet for installation instructions.

IMPORTANT NOTICE REGARDING LONG FILE NAMES:  If you configure the software to support long file names on FAT file systems, you should review the information at http://www.microsoft.com/about/legal/en/us/IntellectualProperty/IPLicensing/Programs/FATFileSystem.aspx to determine whether a license from Microsoft is required. Cypress and its suppliers grant no license under Microsoft's intellectual property rights and assume no liability for any use of the software without obtaining any license that may be required.

PSoC^® Creator^™ emFile Component Video

• Supports 4-wire resistive touchscreen interface
• Supports the Delta Sigma Converter for both the PSoC 3 and PSoC 5 devices
• Supports the ADC Successive Approximation Register for PSoC 5 devices

This resistive touchscreen component is used to interface with a 4-wire resistive touch screen. The component provides a method to integrate and configure the resistive touch elements of a touchscreen with the emWin Graphics library. It integrates hardware-dependent functions that are called by the touchscreen driver supplied with emWin when polling the touch panel.

Required Software: PSoC Creator 2.0 Component Pack 1 and above.

• The component integrates emWin 8051 Graphic Library for PSoC3 and full-featured emWin Graphic Library V5.02 for PSoC 5
• The libraries can be used with the Keil_PK51, GCC, Keil MDK, and Keil RVDS toolchains
• Drivers are available for Graphics LCD Interface and Graphics LCD Controller components

General Description

emWin is an embedded graphic library and graphical user interface (GUI) designed to provide an efficient, processor- and LCD controller-independent GUI for any application that operates with a graphical display. It is compatible with single-task and multitask environments. Developed by SEGGER Microcontroller, emWin is extremely popular in the embedded industry. Cypress has licensed the emWin library from SEGGER and offers a full-featured graphic library free to customers.

Required Software: PSoC Creator 2.0 Component Pack 1 and above

• Use routes which remain active during sleep

General Description

To protect against unintended shorts, the SC/CT and SAR blocks disconnect their terminals when the block goes to sleep. This will also disconnect any routes (static or dynamic) which use the block terminal as a via, or use the block terminal for track jumping.

We allow the user to identify those routes which must stay awake during device sleep using the Stay Awake component, which has a single connection and no parameters. The net to which the stay_awake component is attached will be routed without using the SC/CT or SAR block terminals.

Required Software: PSoC Creator 2.0 and above

• Prevents an analog router from using an analog block terminal routing resource
• Allows safe firmware access to an analog block terminal routing resource

General Description

The Terminal Reserve component reserves the analog routing resource connected to a component, such as the analog wire connected to a comparator or pin. This is an advanced feature that is not needed for most designs, and should be used with caution.

Required Software: PSoC Creator 2.0 and above
 

• 8-, 16-, 24-bit address bus width
• 8-, 16-bit data bus width
• Supports external synchronous memory
• Supports external asynchronous memory
• Supports custom interface for memory
• Supports a range of speeds of external memories (from 5 to 200 ns)
• Supports external memory power-down, sleep, and wakeup modes

General Description

The EMIF component enables access by the CPU or DMA to memory ICs external to the PSoC 3/5LP. It facilitates setup of the EMIF hardware, as well as UDBs and GPIOs as required. The EMIF can control synchronous and asynchronous memories without the need to configure any UDBs in synchronous and asynchronous modes. In UDB mode, UDBs must be configured to generate external memory control signals.

Required Software: PSoC Creator 2.0 and above

Features

• Industry-standard NXP® I2C bus interface
• Supports Slave, Master, Multi-Master and Multi-Master-Slave operation
• Requires only two pins (SDA and SCL) to interface to I2C bus
• Supports standard data rates of 100/400/1000 kbps
• High level APIs require minimal user programming

General Description

The I2C component supports I2C slave, master, and multi-master configurations. The I2C bus is an industry-standard, two-wire hardware interface developed by Philips. The master initiates all communication on the I2C bus and supplies the clock for all slave devices.

The I2C component supports standard clock speeds up to 1000 kbps. It is compatible with I2C Standard-mode, Fast-mode, and Fast-mode Plus devices as defined in the NXP I2C-bus specification. The I2C component is compatible with other third-party slave and master devices.

Note: This version of the component datasheet covers both the fixed hardware I2C block and the UDB version.

Required Software: PSoC Creator 2.0 and above

• Available for PSoC 5 devices only (For PSoC 3 and PSoC 5LP devices, use the Segment LCD version 3.10 component)
• 2 to 768 pixels or symbols
• 1/3, 1/4, and 1/5 bias supported
• 10- to 150-Hz refresh rate
• Integrated bias generation between 2.0 V and 5.2 V with up to 128 digitally controlled bias levels for dynamic contrast control
• Supports both type A (standard) and type B (low power) waveforms
• Pixel state of the display may be inverted for negative image
• 256 bytes of display memory (frame buffer)
• User-defined pixel or symbol map with optional 7-, 14-, or 16-segment character; 5x7 or 5x8 dot matrix; and bar graph calculation routines

General Description

The Segment Display (Seg_Display) component can directly drive 3.3-V and 5.0-V LCD glass at multiplex ratios up to 16x. This component provides an easy method of configuring the PSoC device to drive your custom or standard glass.

Required Software: PSoC Creator 2.0 and above

• CAN2.0 A/B protocol implementation, ISO 11898-1 compliant
• Programmable bit rate up to 1 Mbps @ 8 MHz (BUS_CLK)
• Two or three wire interface to external transceiver (Tx, Rx, and Tx Enable)
• Driver provided and supported by Vector

General Description

The Vector CANbedded environment consists of a number of adaptive source code components that cover the basic communication and diagnostic requirements in automotive applications.

The Vector CANbedded software suite is customer specific and its operation will vary according to application and OEM. This component for the Vector CANbedded suite is written to generically support the CANbedded structure regardless of the flavor of the particular OEM application. 

Required Software: PSoC Creator 2.0 and above

• Two operating modes: Sample and Hold, Track and Hold
• Four power mode settings

General Description

The Sample/Track and Hold component provides a way to sample a continuously varying analog signal and to hold or freeze its value for a finite period of time. It supports both Track and Hold and Sample and Hold functions, which can be selected in the customizer.

Required Software: PSoC Creator 2.0 and above

• Connects two analog routes
• Connects a constrained analog route with an unconstrained analog route
• Connects two analog routes with different routing resource constraints

General Description

The Net Join component connects two analog routes to each other. Each of the routes may have a different analog resource constraint.

Required Software: PSoC Creator 2.0 and above

• Allows access to device level global signals of various types

General Description

This is the GlobalSignal reference component. It allows access to device level global signals.

Required Software: PSoC Creator 2.0 and above

• Limits analog routing of a signal to a specific routing resource
• All terminals on the signal must connect directly to the routing resource

Note: Routing is strict. All of the devices connected to the net with the resource constraint must have a direct hardware connection to the resource. Refer to the Analog Routing Diagram in the applicable Technical Reference Manual (TRM), which is available from the Cypress website, www.cypress.com. If the resources do not have a hardware connection to the specified constraint, an error will occur.


General Description

The Analog Net Constraint component allows you to define the route of the analog signal to which it is connected. This is an advanced feature that is not needed for most designs, and should be used with caution.

Required Software: PSoC Creator 2.0 and above

• USB 2.0-USB-IF certified (TID # 40000552)
• Single Device, Two Functions
• Flash Based Microcontroller Function
• Industry-Leading 2.4 GHz Radio Transceiver Function
• Component Reduction
• Flexible I/O
• USB Specification Compliance
• Operating Voltage from 4.0 V to 5.5 V DC
• Operating Temperature from 0 to 70°C
• Pb-free 40-pin QFN Package
• Advanced Development Tools Based on Cypress’s PSoC® Tools
• For more,see pdf

Functional Description

PRoC LP devices are integrated radio and microcontroller functions in the same package to provide a dual role single-chip solution.

Communication between the microcontroller and the radio is via the SPI interface between both functions.

Functional Overview

The CYRF69213 is a complete Radio System-on-Chip device, providing a complete RF system solution with a single device and a few discrete components. The CYRF69213 is designed to implement low cost wireless systems operating in the worldwide 2.4 GHz Industrial, Scientific, and Medical (ISM) frequency band (2.400 GHz–2.4835 GHz).

Features

• 512-Kbit nonvolatile static random access memory (nvSRAM)
  • Internally organized as 64 K × 8
  • STORE to QuantumTrap nonvolatile elements initiated automatically on power-down (AutoStore) or by using SPI instruction (Software STORE) or HSB pin (Hardware STORE)
  • RECALL to SRAM initiated on power-up (Power-Up RECALL) or by SPI instruction (Software RECALL)
  • Automatic STORE on power-down with a small capacitor
• High reliability
  • Infinite read, write, and RECALL cycles
  • 1 million STORE cycles to QuantumTrap
  • Data retention: 20 years at 85° C
• For more, see pdf
   

Overview

The Cypress CY14X512PA combines a 512-Kbit nvSRAM with a full-featured RTC in a monolithic integrated circuit with serial SPI interface. The memory is organized as 64 K words of 8 bits each. The embedded nonvolatile elements incorporate the QuantumTrap technology, creating the world’s most reliable nonvolatile memory. The SRAM provides infinite read and write cycles, while the QuantumTrap cells provide highly reliable nonvolatile storage of data.

Features

• 1-Mbit nonvolatile static random access memory (nvSRAM)
  • Internally organized as 128 K x 8
  • STORE to QuantumTrap nonvolatile elements initiated automatically on power-down (AutoStore) or by using I2C command (Software STORE) or HSB pin (Hardware STORE)
  • RECALL to SRAM initiated on power-up (Power Up RECALL) or by I2C command (Software RECALL)
  • Automatic STORE on power-down with a small capacitor
• High reliability
  • Infinite read, write, and RECALL cycles
  • 1 million STORE cycles to QuantumTrap
  • Data retention: 20 years at 85 °C
• For more, see pdf

Overview

The Cypress CY14C101I/CY14B101I/CY14E101I combines a 1-Mbit nvSRAM[1] with a full-featured RTC in a monolithic integrated circuit with serial I2C interface. The memory is organized as 128 K words of 8 bits each. The embedded nonvolatile elements incorporate the QuantumTrap technology, creating the world’s most reliable nonvolatile memory. The SRAM provides infinite read and write cycles, while the QuantumTrap cells provide highly reliable nonvolatile storage of data. Data transfers from SRAM to the nonvolatile elements (STORE operation) takes place automatically at power-down.

Features

• 1-Mbit nonvolatile static random access memory (nvSRAM)
  • Internally organized as 128 K × 8
  • STORE to QuantumTrap nonvolatile elements initiated automatically on power-down (AutoStore) or by using SPI instruction (Software STORE) or HSB pin (Hardware STORE)
  • RECALLto SRAM initiated on power-up (Power Up RECALL) or by SPI instruction (Software RECALL)
  • Automatic STORE on power-down with a small capacitor
• High reliability
  • Infinite read, write, and RECALL cycles
  • 1 million STORE cycles to QuantumTrap
  • Data retention: 20 years at 85°C
• For more, see pdf

Overview

The Cypress CY14X101PA combines a 1 Mbit nvSRAM with a full-featured RTC in a monolithic integrated circuit with serial SPI interface. The memory is organized as 128 K words of 8 bits each. The embedded nonvolatile elements incorporate the QuantumTrap technology, creating the world’s most reliable nonvolatile memory. The SRAM provides infinite read and write cycles, while the QuantumTrap cells provide highly reliable nonvolatile storage of data.

• 50 to 166 MHz Operating Frequency Range
• Wide Range of Spread Selections: 9
• Accepts Clock and Crystal Inputs
• Low Power Dissipation
  • 70 mW-Typ at 66 MHz
• Frequency Spread Disable Function
• Center Spread Modulation
• Low Cycle-to-cycle Jitter
• 8-pin SOIC Package
   

General Description

CY25561 is a spread spectrum clock generator (SSCG) IC used to reduce electromagnetic Interference (EMI) found in today's high speed digital electronic systems.

CY25561 uses a Cypress proprietary Phase Locked Loop (PLL) and Spread Spectrum Clock (SSC) technology to synthesize and frequency modulate the input frequency of the reference clock. By doing this, the measured EMI at the fundamental and harmonic frequencies of clock (SSCLK) is reduced. 

• Digital Multiplexer
• Digital De-Multiplexer
• Up to 16 channels>

General Description

The Multiplexer component is used to select 1 of n inputs while the De-Multiplexer component is used to route 1 signal to n outputs.

The Multiplexer component implements a 2-16 input mux providing a single output, based on hardware control signals. The De-Multiplexer component implements a 2-16 output demux from a single input, based on hardware control signals. Only 1 input or output connection may be made at a time.

Required Software: PSoC Creator v2.0 and above

• 1 to 5 Inputs
• 1 to 8 Outputs
• Configuration Tool
• Optionally Registered Outputs

General Description

You can set up the Lookup Table (LUT) component to perform any logic function with up to five inputs and eight outputs. This is done by generating logic equations that are realized in the UDB PLDs. Optionally, the outputs can be registered. These registers are implemented in PLD macrocells. All macrocell flip-flops are initialized to a 0 value at power up and after any reset of the device.

Required Software: PSoC Creator v2.0 and above

• Industry standard logic gates
• Configurable number of inputs up to 8
• Optional array of gates

General Description

Logic gates provide basic boolean operations. The output of a logic gate is a boolean combinatorial function of the inputs. There are seven basic logic gates: AND, OR, Inverter (NOT), NAND, NOR, XOR, and XNOR.

Required Software: PSoC Creator v2.0 and above

• 8 or 16 bit interface to Graphic LCD Controller
• Compatible with many graphic controller devices
• Interfaces with SEGGER emWin graphics library
• Performs Read and write transaction
• 2-255 cycles for Read Low Pulse Width
• 1-255 cycles for Read High Pulse Width
• Implements typical i8080 interface

The Graphic LCD Interface (GraphicLCDIntf) component provides the interface to a graphic LCD controller and driver device. These devices are commonly integrated into an LCD panel. The interface to these devices is commonly referred to as an i8080 interface. This is a reference to the historic parallel bus interface protocol of the Intel 8080 microprocessor.    

Required Software: PSoC Creator v2.0 and above

• Fully programmable screen size support up to HVGA resolution including:
  • QVGA (320x240) @ 60 Hz 16 bpp
  • WQVGA (480x272) @ 60 Hz 16 bpp
  • HVGA (480x320) @ 60 Hz 16 bpp
• Supports virtual screen operation
• Interfaces with SEGGER emWin graphics library
•  Performs read and write transactions during the blanking intervals
• Generation of continuous timing signals to the panel without CPU intervention
• Supports up to a 23-bit address and a 16-bit data async SRAM device used as externally provided frame buffer
• Generates a selectable interrupt pulse at the entry and exit of the horizontal and vertical blanking intervals

General Description

The Graphic LCD Controller (GraphicLCDCtrl) component provides the interface to an LCD panel that has an LCD driver, but not an LCD controller. This type of panel does not include a frame buffer. The frame buffer must be provided externally.

This component also interfaces to an externally provided frame buffer implemented using a 16-bit wide async SRAM device.

Required Software: PSoC Creator v2.0 and above

• Constant digital high or low signal

General Description

The Logic High and Logic Low components provide constant digital values and are used to hard code digital inputs. Hard coding of static inputs results in optimized resource usage and is the preferred method of providing a constant input state.

Required Software: PSoC Creator v2.0 and above

• Voltage references and supplies
• Multiple options
• Bandgap principle to achieve timer, temperature, and voltage stability

General Description

This description applies to PSoC 3 and PSoC 5 devices. The Voltage Reference (Vref) component provides one of several voltage reference outputs. The 1.024 V and 0.256 V outputs are temperature compensated using the bandgap principle to achieve excellent stability.

Required Software: PSoC Creator v2.0 and above