Features

• True Dual-Ported memory cells which allow simultaneous access of the same memory location
• 32K x 16 organization (CY7C027V/027VN/027AV)
• 64K x 16 organization (CY7C028V)
• 32K x 18 organization (CY7C037V/037AV)
• 64K x 18 organization (CY7C038V)
• 0.35 micron CMOS for optimum speed and power
• High speed access: 15, 20, and 25 ns
• Low operating power
• Active: I_CC = 115 mA (typical)
• For more, see pdf
   

Functional Description

The CY7C027V/027AV/028V and CY7037AV/038V are low power CMOS 32K, 64K x 16/18 dual-port static RAMs. Various arbitration schemes are included on the devices to handle situations when multiple processors access the same piece of data. Two ports are provided, permitting independent, asynchronous access for reads and writes to any location in memory. 

PSoC Designer 5.0 SP6 will continue to be available for System Level Design users, and it will co-exist with future PSoC Designer 5.1 releases. However, we are not recommending System Level Design for production designs.

We suggest users to use the latest version of PSoC Designer located here:

www.cypress.com/go/psocdesigner

PSoC Designer 5.0 SP6 supports Internet Explorer 6 through 8, but does not support Internet Explorer 8 Beta or Internet Explorer 9 due to compatibility issues.

To Install PSoC Designer 5.0 SP6 users must first have PSoC Programmer installed first. For the latest release of PSoC Programmer please, Click Here

PSoC Designer 5.0 PS6 was tested using Beta version of Windows 7. PSoC Designer 5.0 SP6 is not supported for Windows 7 systems.

To Install:

Shut Down any currently running instances of PSoC Designer.

If an earlier service pack of PSoC Designer 5.0 is currently installed, uninstall it. To do this please navigate to Start>Control Panel>Add or Remove Programs.

• Install latest PSoC Programmer.
• Install PSoC Designer 5.0 SP6 by running the installed in the downloads table below.”

Note to HI-TECH Compiler Users:

There are new devices in this release. To compile projects containing these devices with the HI-TECH compiler, you must manually update the psoc.ini file. The HI-TECH psoc.ini file is found in the HI-TECH installation folder. The default location of the psoc.ini is here:

C:\Program Files\HI-TECH Software\HCPSOC\PRO\9.61\dat\psoc.ini

The default location of the replacement psoc.ini file that adds support for the new devices is here:

C:\Program Files\Cypress\Common\CypressSemiBuildMgr\tools\psoc.ini

PSoC Programmer: The latest version of PSoC Programmer must be installed along with PSoC Designer. For the latest release please navigate to the PSoC Programmer web page: Click Here

PSoC Designer: User Guides - Click Here

PSoC Designer Archive - Click Here

USB has long been the interface of choice between PCs and their peripherals. However, many legacy PCs still use an RS232 serial interface— in some cases referred to as a UART interface—to communicate with their peripherals.

Cypress’s USB-to-UART Bridge Controller enables seamless connectivity between USB and UART devices. It is a low-power, single-chip, plug-and-play solution that is easy to design and reuses existing application software and firmware—accelerating time to market.

Standard 8051 Interrupts:

• IE0(INT0): External Interrupt0
• IE1(INT1): External Interrupt1
• RI_0 & TI_0: USART1 Interrupt
• TF0: Timer0 Overflow
• TF1: Timer1 Overflow

Additional EZ-USB interrupts:

• TF2: Timer2 Overflow
• PF1: Wake up pin(WU2)
• RI_1 & TI_1: UART 1 Transmit and receive
• USBINT(INT2): USB specific Interrupt
• I2CINT(INT3): I2C Bus Interrupt
• IE4(INT4): External Interrupt 4
• IE5(INT5): External Interrupt 5
• IE6(INT6): External Interrupt 6
   

For more, see pdf.

General Description

With its unique array of configurable blocks, PSoC® 5LP is a true system-level solution providing microcontroller unit (MCU), memory, analog, and digital peripheral functions in a single chip. The CY8C52LP family offers a modern method of signal acquisition, signal processing, and control with high accuracy, high bandwidth, and high flexibility. Analog capability spans the range from thermocouples (near DC voltages) to ultrasonic signals.

The CY8C52LP family can handle dozens of data acquisition channels and analog inputs on every GPIO pin. The CY8C52LP family is also a high-performance configurable digital system with some part numbers including interfaces such as USB and multimaster I2C. In addition to communication interfaces, the CY8C52LP family has an easy to configure logic array, flexible routing to all I/O pins, and a high-performance 32-bit ARM®Cortex™-M3 microprocessor core.

Designers can easily create system level designs using a rich library of prebuilt components and boolean primitives using PSoC Creator™, a hierarchical schematic design entry tool. The CY8C52LP family provides unparalleled opportunities for digital bill of materials integration while easily accommodating last minute design changes through simple firmware updates.

Features

• 32-bit ARM Cortex-M3 CPU core
• Low voltage, ultra low power
• Versatile I/O system
• Digital peripherals
• Analog peripherals (1.71 V ≤ VDDA ≤ 5.50 V)
• Programming, debug, and trace
• Precision, programmable clocking
• Temperature and packaging
• For more, see data sheet pdf

General Description

With its unique array of configurable blocks, PSoC® 5LP is a true system-level solution providing microcontroller unit (MCU), memory, analog, and digital peripheral functions in a single chip. The CY8C58LP family offers a modern method of signal acquisition, signal processing, and control with high accuracy, high bandwidth, and high flexibility. Analog capability spans the range from thermocouples (near DC voltages) to ultrasonic signals.

The CY8C58LP family can handle dozens of data acquisition channels and analog inputs on every GPIO pin. The CY8C58LP family is also a high-performance configurable digital system with some part numbers including interfaces such as USB, multimaster I2C, and controller area network (CAN). In addition to communication interfaces, the CY8C58LP family has an easy to configure logic array, flexible routing to all I/O pins, and a high-performance 32-bit ARM® Cortex™-M3 microprocessor core.

Designers can easily create system-level designs using a rich library of prebuilt components and boolean primitives using PSoC Creator™, a hierarchical schematic design entry tool. The CY8C58LP family provides unparalleled opportunities for analog and digital bill of materials integration while easily accommodating last minute design changes through simple firmware updates.

Features

• 32-bit ARM Cortex-M3 CPU core
• Low voltage, ultra low power
• Versatile I/O system
• Digital peripherals
• Analog peripherals (1.71 V ≤ VDDA ≤ 5.5 V)
• Programming, debug, and trace
• Precision, programmable clocking
• Temperature and packaging
• For more, see data sheet pdf

General Description

With its unique array of configurable blocks, PSoC® 5LP is a true system level solution providing microcontroller unit (MCU), memory, analog, and digital peripheral functions in a single chip. The CY8C54LP family offers a modern method of signal acquisition, signal processing, and control with high accuracy, high bandwidth, and high flexibility. Analog capability spans the range from thermocouples (near DC voltages) to ultrasonic signals.

The CY8C54LP family can handle dozens of data acquisition channels and analog inputs on every GPIO pin. The CY8C54LP family is also a high-performance configurable digital system with some part numbers including interfaces such as USB and multi-master I2C. In addition to communication interfaces, the CY8C54LP family has an easy to configure logic array, flexible routing to all I/O pins, and a high-performance 32-bit ARM® Cortex™-M3 microprocessor core.

Designers can easily create system-level designs using a rich library of prebuilt components and boolean primitives using PSoC® Creator™, a hierarchical schematic design entry tool. The CY8C54LP family provides unparalleled opportunities for digital and analog bill of materials integration while easily accommodating last minute design changes through simple firmware updates.

Features

• 32-bit ARM Cortex-M3 CPU core
• Low voltage, ultra low power
• Versatile I/O system
• Digital peripherals
• Analog peripherals (1.71 V ≤ VDDA ≤ 5.5 V)
• Programming, debug, and trace
• Precision, programmable clocking
• Temperature and packaging
• For more, see data sheet pdf

General Description

With its unique array of configurable blocks, PSoC® 5LP is a true system level solution providing MCU, memory, analog, and digital peripheral functions in a single chip. The CY8C56LP family offers a modern method of signal acquisition, signal processing, and control with high accuracy, high bandwidth, and high flexibility. Analog capability spans the range from thermocouples (near DC voltages) to ultrasonic signals.

The CY8C56LP family can handle dozens of data acquisition channels and analog inputs on every GPIO pin. The CY8C56LP family is also a high performance configurable digital system with some part numbers including interfaces such as USB and multimaster I2C, and controller area network (CAN). In addition to communication interfaces, the CY8C56LP family has an easy to configure logic array, flexible routing to all I/O pins, and a high performance 32-bit ARM® Cortex™-M3 microprocessor core.

Designers can easily create system level designs using a rich library of prebuilt components and boolean primitives using PSoC Creator™, a hierarchical schematic design entry tool. The CY8C56LP family provides unparalleled opportunities for analog and digital bill of materials integration while easily accommodating last minute design changes through simple firmware updates.

Features

• 32-bit ARM Cortex-M3 CPU core
• Low voltage, ultra low power
• Versatile I/O system
• Digital peripherals
• Analog peripherals (1.71 V ≤ VDDA ≤ 5.5 V)
• Programming, debug, and trace
• Precision, programmable clocking
• Temperature and packaging
• For more, see pdf.

• QuietZone™ Controller
• Low power CapSense® block with SmartSense™ auto-tuning
• Driven shield available on five GPIO pins
• Powerful Harvard-architecture processor
• Flexible on-chip memory
• Four clock sources
• Programmable pin configurations
• Versatile analog mux
• Additional system resources
• Complete development tools
• Sensor and Package options
• For more, see pdf

PSoC® Functional Overview

The PSoC family consists of many devices with on-chip controllers. These devices are designed to replace multiple traditional MCU-based system components with one low-cost single-chip programmable component. A PSoC device includes configurable blocks of analog and digital logic, and programmable interconnect. This architecture makes it possible for you to create customized peripheral configurations, to match the requirements of each individual application. Additionally, a fast central processing unit (CPU), flash program memory, SRAM data memory, and configurable I/O are included in a range of convenient pinouts.

CY3236A-PIRMOTION Rev. A Kit Contents:

• PIR Motion Sensor Board using CY8C27443-24PVXI PSoC(R) device
• 12V Power Supply
• PSoC Designer(TM) and PSoC Programmer CD
• Design Files CD (Schematic, BOM, Gerber Files, PSoC Designer Example Project)

Introduction

Cypress's EZ-USB® FX3 is the next-generation USB 3.0 peripheral controller, providing integrated and flexible features. FX3 has a fully configurable, parallel, general programmable interface called GPIF II, which can connect to any processor, ASIC, or FPGA. It provides easy and glue less connectivity to popular interfaces, such as asynchronous SRAM, asynchronous and synchronous address data multiplexed interfaces, and parallel ATA. FX3 has an embedded 32-bit ARM926EJ-S microprocessor for powerful data processing and for building custom applications. It implements an architecture that enables 375-MBps data transfer from GPIF II to the USB interface. 

Cypress's FLEx18 / FLEx36® / FLEx72™ portfolio of highdensity, high-performance synchronous Dual-Port SRAMs can operate at speeds up to 167 MHz. In the fast growing data communications market, the bandwidth requirements have increased. Cypress addresses these demands with its FullFlex Dual-Port SRAMs, which can operate up to 200 MHz.

The video describes the case of using a DMA to buffer ADC data. Buffering of 20 bit ADC data is taken as an example and discussed. The video also gives a preview of the project implementing the 20 bit data buffering and explains the DMA configuration in code.

The following table indicates the PSoC devices, PSoC Creator versions, compilers, and development kits that will work with this application note project:

*Refer to Migrating CY8CKIT-001 DVK project to CY8CKIT 030/ 050. 

Notes:

1. Click on AN84741 - PSoC® 5 to PSoC 5LP Migration Guide to learn differences between PSoC 5 and PSoC 5LP.
2. Click on AN77835 - PSoC® 3 to PSoC 5LP Migration Guide to learn differences between PSoC 3 and PSoC 5LP.
3. For PSoC 5 project and related document, please download file AN61102_Archive.zip.

Projects associated with this application note can be downloaded from the ‘Related Files’ section below. For your convenience, we have provided projects that are compatible with the two most recent versions of PSoC Creator:

• AN61102.zip is used with PSoC Creator 2.1 SP1
• AN61102_Archive.zip is used with PSoC Creator 2.1/2.0

The project’s default settings may not be compatible with your device or kit, and you may need to change your project settings. For more information, see:

Overview

CYRF8935 WirelessUSB NL is Cypress’s third generation of 2.4 GHz low-power RF technology, bringing next level of low-power performance into a small 4 mm x 4 mm footprint. WirelessUSB NL implements a GFSK radio using a differentiated single-mixer, closed-loop modulation design that optimizes power ef_ciency and interference immunity. This also translates into the highest on-air throughput which makes WirelessUSB NL particularly powerful for streaming applications such as audio, along with HID applications such as wireless keyboards, mice and USB dongles.

The CY3668 WirelessUSB NL development kit provides a generic platform for developing wireless applications based on the WirelessUSB NL, enCoRe II and enCoRe V devices. The out-of-box examples that come with this kit also demonstrates the new enhanced agile HID protocol for secure and reliable wireless data transfers.
 

Kit Contents:

• CY3668 bridge/keyboard development boards (2)
• NL modules (2)
• CY3668- enCoRe II module (1)
• CY3668-enCoRe V modules (2)
• 3.3-V LCD (2)
• Power adaptor (2)
• Quick Start Guide
• Resource CD which includes, PSoC Designer, PSoC Programmer, Projects and documentation.

Software Title	Description	Link
PSoC Designer	This kit requires PSoC Designer for development
PSoC Programmer	This kit requires PSoC Programmer for programming

EZ-USB® FX3 is the next generation USB 3.0 peripheral controller, providing highly integrated and flexible features that enable developers to add USB 3.0 functionality to a wide range of applications.

FX3 supports several boot options including booting over I2C, SPI, USB, Synchronous ADMux and Asynchronous SRAM interfaces. This application note describes the details of the different booting options for FX3.

The default state of the FX3 IOs during boot are also documented. The Appendix describes the step-wise sequence for testing the different boot modes using the FX3 DVK.

Introduction

USB is so commonplace that it has almost completely replaced other communication methods between peripheral devices and a PC. This holds true both for general-purpose devices, such as flash drives and mice, and special-purpose devices for specific applications. According to the standard USB 2.0 specification, USB peripherals do not communicate directly with one another; they may communicate only with a USB host, which fully controls data traffic on the bus. The Cypress EZ-USB FX3 with integrated high-speed USB host controller, along with the USB function and On-The-Go (OTG) capabilities accomplishes two things: It retains the device functions and allows embedded systems to act as a USB host.

With PSoC Creator, you can:

• Create and share user-defined, custom peripherals using hierarchical schematic design and Verilog entry
• Automatically place and route selected components and integrate simple glue logic normally residing in discrete muxes or 22V10s
• Trade-off hardware and software design considerations allowing you to focus on what matters: getting to market fast

PSoC Creator also allows you to tap into an entire tools ecosystem with integrated compiler tool chains, RTOS solutions and top production programmers to support PSoC 3, PSoC 5 and PSoC 5LP.
 

New Features in Creator 2.2

• Project Datasheet Generation
• Component Distribution (Import/Export)
• Rename Annotation Components to External / Off-Chip
• New DWR Parameter – “Variable Vdda”
• Binding Error Symbols
• Peripheral Register Debug in IDEs
• MISRA Support for Automotive Applications
• Datapath Editor Enhancements

Additional Information and Documentation

Further details on this release are available in the Release Notes. Additionally, a Migration Guide is also available to aid in the process of porting designs into the latest PSoC Creator toolset.

System Configuration

The following minimum configuration is required for installation of the PSoC Creator 2.2 application. See the release notes for details on performance expectations in resource constrained systems.

• Windows Operating System
  • Windows XP SP2 or SP3
  • Windows Vista (32- and 64-bit supported) and SP1
  • Windows 7 (32- and 64-bit supported) and SP1
  • MacOS v10 with Parallels Desktop v6 running Windows XP SP3
• 1 GHz CPU
• 512 MB RAM (minimum), 1 GB RAM (preferred)
• 2 GB of hard disk space
• USB 2.0
• 1024x768 screen resolution  

PSoC Creator Training

Need help downloading/installing? Call 1-800-541-4736 and select 8.

• 10 mV hysteresis that can be enabled or disabled
• Programmable output polarity
• Programmable speed and power
• Direct output connection available to trip input of the HYSTCTRL User Module blocks
• Direct input selection from DualDAC8HW UM to achieve a precise, programmable comparator reference

The CMPHW User Module (UM) is a dedicated hardware comparator block (not the comparator block implemented with PSoC analog and digital blocks) that compares two input signals and switches the output to indicate the larger signal. The comparator has rail-to-rail operation with a 10 mV hysteresis that can be enabled or disabled.This UM can operate in both fast and slow mode, a useful feature depending on the end application. For example, a typical over-current protection circuit is designed to respond faster to changes in the output variable and therefore would benefit from the fast mode feature. On the other hand, an application where the comparator is used to sense a slow changing variable, such as temperature, can benefit from the slow mode of this comparator using less system power.

The ICE-Cube also serves as a single-site device programmer via an ISSP (In-System Serial Programming) Cable and MiniEval board included in the kit. The MiniEval board is a programming and evaluation board which connects to the ICE-Cube via an ISSP Cable and allows programming of DIP devices. There are also other Programming boards available for programming other packages. The MiniEval also includes LEDs and a POT for simple evaluation and demonstration.

PSoC 1 Debugger Includes:

• PSoC Designer Software CD-ROM
• ICE-Cube In-Circuit Emulator
• ICE Flex-Pod for CY8C29xxx Family
• Backward compatibility Cat-5 Adapter
• ISSP Cable
• Mini-Eval Programming Board in One
• USB 2.0 Cable and Blue Cat-5 Cable
• 110 ~ 240V Power Supply, Euro-Plug Adapter
• 2 CY8C29466-24PXI 28-PDIP Chip Samples

Supports following 8 bit PSoC1 (Programmable System-On Chip) families, including automotive, except CY8C25/26xxx devices.

PSoC 1 Getting Started Debugging - Part 1

Software Title	Description	Link
PSoC Designer	This kit requires PSoC Designer for development
PSoC Programmer	This kit requires PSoC Programmer for programming

Related Resources:

• Operates with a high common mode voltage of 36V
• Possesses high common mode rejection ratio
• Gives bandwidth adjustment capability with high bandwidth
• Gives low input offset currents and low offset voltages
• Highly accurate output

The high side current sense amplifiers (CSA) give a differential sense capability to measure the voltage across current sense resistors in power systems.

This kit is specifically designed for analog performance. The noise floor on these kits is very low. Care has been taken to separate the analog and the digital domain, separate regulators are also available. Separate ground planes are provided. We have achieved ENOB very close to 20 bits on this kit. Provision has been provided to add an external precision voltage reference if needed.

Besides the analog, this kit is also meant to demonstrate the low power operation of PSoC3/PSoC5. PSoC3 chip is soldered to the board, this way the leakage currents are reduced significantly compared to the CY8CKIT-001. Special terminals are provided to enable the boost converter operation without much modifications. Jumpers have been provided to remove power to RS232 converter, Potentiometer and to have a single regulator for Analog and digital domain and evaluate the low power operation of PSoC3.

It has got an onboard programmer(Cypress USB chip based), which lets you program PSoC3/PSoC5 without connecting Miniprog3. Provision has been provided to program using Miniprog3 as well.

Kit Contents:

• PSoC 3 Development Board
• LCD Character Display
• USB Cable
• Quick Start Guide
• Kit CD, which includes: PSoC Creator, PSoC Programmer, Projects and Documentation
   

For PSoC training, please visit http://www.cypress.com/go/training.

Software Title	Description	Link
PSoC Creator	This kit requires PSoC Creator for development
PSoC Programmer	This kit requires PSoC Programmer for programming

The TMP05 Digital Temperature Sensor Interface Component is a building block for thermal management applications. It enables designers using PSoC 3 to quickly and easily interface with Analog Devices’ TMP05 or TMP06 digital temperature sensors through a simple, serial 2-wire digital interface. The sensors can be daisy-chained together, minimizing I/O requirements on the controller. For more details on the specific functions of the TMP05 Digital Temperature Sensor Interface Component, refer to the component datasheet.

Notes:

1. Click on AN84741 - PSoC® 5 to PSoC 5LP Migration Guide to learn differences between PSoC 5 and PSoC 5LP.
2. For PSoC 5 project and related document, please download file AN65977_Archive.zip.

Projects associated with this application note can be downloaded from the 'Related Files' section below. For your convenience, we have provided projects that are compatible with the two most recent versions of PSoC Creator:

• AN65977.zip is used with PSoC Creator 2.1 SP1
• AN65977_Archive.zip is used with PSoC Creator 2.1/2.0

The project’s default settings may not be compatible with your device or kit, and you may need to change your project settings. For more information, see:

The nvSRAM architecture uses a one-to-one pairing of a nonvolatile bit and a fast SRAM bit in each memory cell. During normal operation, the IC behaves exactly as a standard fast asynchronous SRAM and is easy to interface with the microprocessor or microcontroller. When IC power is disrupted or lost, the event is detected and all the SRAM bits are saved into the nonvolatile part (within 8 ms) using the stored energy in a small capacitor (VCAP). This operation is called AutoStore and is described in more detail in the next section. When power is restored, data is automatically recalled from the nonvolatile part to SRAM on power restore and this operation is called Power Up RECALL (Hardware RECALL).
 

Sleep mode is used to reduce a PSoC’s average current consumption by entering a low-power state, whenever the CPU and other internally clocked functions are not needed. Sleep mode is most useful for battery-powered systems, but it is applicable to any design.

Features

• Device Operating Voltage Options:
  • MoBL Clock M200 Family: 1.8V
• Selectable clock output voltages for both MoBL Clock M200 and M500:
  • 1.5V, 1.8V, 2.5V, 3.0V, or 3.3V
• Fully integrated ultra low power phase-locked loops (PLLs)
• Input reference clock frequency range: 1–48 MHz
• Output clock frequency range: 3–50 MHz
• Three I2C™ programmable output clocks
• Programmable output drive strengths
• For more, see pdf
   

General Description

2 Configurable PLLs

The MoBL® Clock M200/M500 Family of products are two-PLL Clock Generator ICs designed for cell phone, portable, or consumer electronics applications. It can be used to generate two independent output frequencies ranging from 3 to 50MHz from a single input reference clock.

Features

• Low jitter crystal oscillator (XO)
• Less than 1 ps typical root mean square (RMS) phase jitter
• Differential low-voltage positive emitter coupled logic (LVPECL) output
• Output frequency from 50 MHz to 690 MHz
• Frequency margining through I²C bus
• Factory-configured or field-programmable
• Integrated phase-locked loop (PLL)
• Pb-free package: 5.0 × 3.2 mm leadless chip carrier (LCC)
• Supply voltage: 3.3 V or 2.5 V
• Commercial and industrial temperature ranges
   

Functional Description

The CY2XF24 is a high-performance and high-frequency XO. It uses a Cypress-proprietary low-noise PLL to synthesize the frequency from an integrated crystal. The output frequency can be changed using the I2C bus serial interface, allowing easy frequency margin testing in applications.

Features

• Low Jitter Crystal Oscillator (XO)
• Less than 1 ps Typical RMS Phase Jitter
• Differential LVDS Output
• Output Frequency from 50 MHz to 690 MHz
• Two Frequency Margining Control Pins (FS0, FS1)
• Factory Configured or Field Programmable
• Integrated Phase-Locked Loop (PLL)
• Supply Voltage: 3.3V or 2.5V
• Pb-Free Package: 5.0 x 3.2 mm LCC
• Commercial and Industrial Temperature Ranges
   

Functional Description

The CY2XF33 is a high performance and high frequency Crystal Oscillator (XO). It uses a Cypress proprietary low noise PLL to synthesize the frequency from an integrated crystal. The output frequency can be changed through two select pins, allowing easy frequency margin testing in applications.

Features

• True dual port memory enables simultaneous access to the shared array from each port
• Synchronous pipelined operation with single data rate (SDR) operation on each port
  • SDR interface at 200 MHz
  • Up to 28.8 Gb/s bandwidth (200 MHz × 72-bit × 2 ports)
• Selectable pipelined or flow-through mode
• 1.5 V or 1.8 V core power supply
• Commercial and Industrial temperature
• IEEE 1149.1 JTAG boundary scan
• Available in 484-ball PBGA (× 72) and 256-ball FBGA (× 36 and × 18) packages
• For more, see pdf

Functional Description

The FullFlex™ dual port SRAM families consist of 2-Mbit, 4-Mbit, 9-Mbit, 18-Mbit, and 36-Mbit synchronous, true dual port static RAMs that are high speed, low power 1.8 V or 1.5 V CMOS. Two ports are provided, enabling simultaneous access to the array. Simultaneous access to a location triggers deterministic access control. For FullFlex72 these ports operate independently with 72-bit bus widths and each port is independently configured for two pipelined stages. Each port is also configured to operate in pipelined or flow through mode.

Features

• Powerful Harvard-architecture processor
• Advanced peripherals (PSoC® blocks)
• Flexible on-chip memory
• Complete development tools
• Precision, programmable clocking
• Programmable pin configurations
• Additional system resources
   

PSoC Functional Overview

The PSoC family consists of many programmable system-on-chip controller devices. These devices are designed to replace multiple traditional MCU-based system components with a low cost single-chip programmable component. A PSoC device includes configurable blocks of analog and digital logic, and programmable interconnect. This architecture allows you to create customized peripheral configurations, to match the requirements of each individual application. Additionally, a fast CPU, Flash program memory, SRAM data memory, and configurable I/O are included in a range of convenient pinouts.

• 18 Mbit density (1 M x 18, 512 K x 36)
• 450-MHz clock for high bandwidth
• Two-word burst for reducing address bus frequency
• Double data rate (DDR) interfaces (data transferred at 900 MHz) at 450 MHz
• Available in 2.0 clock cycle latency
• For more, see pdf
   

Functional Description

The CY7C1148KV18, and CY7C1150KV18 are 1.8 V Synchronous Pipelined SRAMs equipped with DDR II+ architecture. The DDR II+ consists of an SRAM core with advanced synchronous peripheral circuitry. Addresses for read and write are latched on alternate rising edges of the input (K) clock.

• Separate independent read and write data ports
  • Supports concurrent transactions
• 550-MHz clock for high bandwidth
• Four-word burst for reducing address bus frequency
• Double data rate (DDR) interfaces on both read and write ports (data transferred at 1100 MHz) at 550 MHz
• Available in 2.5 clock cycle latency
• For more, see pdf
   

Functional Description

The CY7C1163KV18, and CY7C1165KV18 are 1.8 V Synchronous Pipelined SRAMs, equipped with QDR II+ architecture. Similar to QDR II architecture, QDR II+ architecture consists of two separate ports: the read port and the write port to access the memory array. The read port has dedicated data outputs to support read operations and the write port has dedicated data inputs to support write operations. QDR II+ architecture has separate data inputs and data outputs to completely eliminate the need to ‘turnaround’ the data bus that exists with common I/O devices. Each port is accessed through a common address bus. Addresses for read and write addresses are latched on alternate rising edges of the input (K) clock.

• 18-Mbit density (1 M × 18, 512 K × 36)
• 550-MHz clock for high bandwidth
• Two-word burst for reducing address bus frequency
• Double data rate (DDR) interfaces (data transferred at 1100 MHz) at 550 MHz
• Available in 2.5 clock cycle latency
• Two input clocks (K and K) for precise DDR timing
• Echo clocks (CQ and CQ) simplify data capture in high-speed systems
• For more, see pdf

Functional Description

The CY7C1168KV18, and CY7C1170KV18 are 1.8 V synchronous pipelined SRAMs equipped with DDR II+ architecture. The DDR II+ consists of an SRAM core with advanced synchronous peripheral circuitry. Addresses for read and write are latched on alternate rising edges of the input (K) clock.

• 18 Mbit density (2 M x 8, 1 M x 18)
• 333-MHz clock for high bandwidth
• Two-word burst for reducing address bus frequency
• Double data rate (DDR) interfaces (data transferred at 666 MHz) at 333 MHz
• For more, see pdf
   

Functional Description

The CY7C1392KV18 and CY7C1393KV18 are 1.8 V Synchronous Pipelined SRAMs, equipped with DDR II SIO (double data rate separate I/O) architecture. The DDR II SIO consists of two separate ports: the read port and the write port to access the memory array. The read port has data outputs to support read operations and the write port has data inputs to support write operations. The DDR II SIO has separate data inputs and data outputs to completely eliminate the need to ‘turnaround’ the data bus required with common I/O devices. Access to each port is accomplished through a common address bus. Addresses for read and write are latched on alternate rising edges of the input (K) clock.

• 18 Mbit density (1 M x 18, 512 K x 36)
• 333-MHz clock for high bandwidth
• Four-word burst for reducing address bus frequency
• Double data rate (DDR) interfaces (data transferred at 666 MHz) at 333 MHz
• Two input clocks (K and K) for precise DDR timing
• Two input clocks for output data (C and C) to minimize clock skew and flight time mismatches
• For more, see pdf
   

Functional Description

CY7C1319KV18 and CY7C1321KV18 are 1.8 V Synchronous Pipelined SRAMs equipped with DDR II architecture. The DDR II consists of an SRAM core with advanced synchronous peripheral circuitry and a two-bit burst counter. Addresses for read and write are latched on alternate rising edges of the input (K) clock.

• Separate independent read and write data ports
  • Supports concurrent transactions
• 450-MHz clock for high bandwidth
• Four-word burst for reducing address bus frequency
• Double data rate (DDR) Interfaces on both read and write ports (data transferred at 900 MHz) at 450 MHz
• Available in 2.0 clock cycle latency
• For more, see pdf
   

Functional Description

The CY7C1143KV18, and CY7C1145KV18 are 1.8 V Synchronous Pipelined SRAMs, equipped with QDR II+ architecture. Similar to QDR II architecture, QDR II+ architecture consists of two separate ports: the read port and the write port to access the memory array. The read port has dedicated data outputs to support read operations and the write port has dedicated data inputs to support write operations. QDR II+ architecture has separate data inputs and data outputs to completely eliminate the need to “turnaround” the data bus that exists with common I/O devices. Each port is accessed through a common address bus. Addresses for read and write addresses are latched on alternate rising edges of the input (K) clock.
 

• 18 Mbit density (1 M x 18, 512 K x 36)
• 550-MHz clock for high bandwidth
• Two-word burst for reducing address bus frequency
• Double data rate (DDR) interfaces (data transferred at 1100 MHz) at 550 MHz
• Available in 2.5 clock cycle latency
• Two input clocks (K and K) for precise DDR timing
  • SRAM uses rising edges only
• Echo clocks (CQ and CQ) simplify data capture in high-speed systems
• Data valid pin (QVLD) to indicate valid data on the output
• For more, see pdf

Functional Description

The CY7C2168KV18, and CY7C2170KV18 are 1.8 V Synchronous Pipelined SRAMs equipped with DDR II+ architecture. The DDR II+ consists of an SRAM core with advanced synchronous peripheral circuitry. Addresses for read and write are latched on alternate rising edges of the input (K) clock.

1. In the µVision2 Editor, click ‘Options for Target’ and then select the ‘Output’ Tab. Ensure that the following path is described in the ‘ Run User Program #1’:

    

   ..\..\..\Bin\hex2bix -i -f 0xC2 -o fw.iic fw.hex

2. If at power-on-reset, the EZ-USB detects an EEPROM connected to its I2C with the value 0xC2 at address zero, the EZ-USB loads the firmware in EEPROM into an on-chip RAM. It also sets the RENUM bit to ‘1’, causing standard device requests to be handled by the firmware instead of the default USB device.

Counts are calculated using Equation 1.

Where:

Sensitivity is calculated using Equation 2.

The upper limit of the capacitance measurement range is calculated using Equation 3.

For example, given the following User Module settings:

Sensitivity = 184.3 Counts/pF

Capacitance measurement range (upper limit) = 88.9 pF

Note: The “sensitivity” calculated above is the capacitive measurement module sensitivity, not the system sensitivity to button/sensor activation.

Note: It is not possible to measure capacitance values all the way down to zero because there will always be some parasitic capacitance, C_P, and pin capacitance measured by the sensor.

Where:

For example, given the following User Module settings:

Resolution = 0.00543 pF

Note: Although the calculation indicates that a change as small as 0.00543 pF can be detected, raw-count noise limits the use of such high resolution. CapSense is not recommended for measuring absolute capacitances.

Note: The “sensitivity” calculated above is the capacitive measurement module sensitivity, not the system sensitivity to button/sensor activation.

• One differential (LVPECL, LVDS, HCSL, or CML) input pair distributed to two LVPECL output pairs
• Translates any single-ended input signal to 3.3 V LVPECL levels with resistor bias on INx# input
• 20-ps maximum output-to-output skew
• 480-ps maximum propagation delay
• 0.15-ps maximum additive RMS phase jitter at 156.25 MHz (12-kHz to 20-MHz offset)
• Up to 1.5-GHz operation
• 8-pin SOIC or 8-pin TSSOP package
• 2.5-V or 3.3-V operating voltage
• Commercial and industrial operating temperature range
   

Functional Description

The CY2DP1502 is an ultra-low noise, low-skew, low-propagation delay 1:2 LVPECL fanout buffer targeted to meet the requirements of high-speed clock distribution applications. The device has a fully differential internal architecture that is optimized to achieve low additive jitter and low skew at operating frequencies of up to 1.5 GHz.    

The CY36800 InstaClock Universal Programmable Clock Generator Programming Kit contains the programming board with a USB cable, and 3 samples each of the CY22800 and CY22801 devices. You can order more samples of either CY22800 or CY22801 Online. The latest programming software is available to download from www.cypress.com/instaclock.

When using the CY22800 and InstaClock software, users can select from a list of over 100 different predefined configurations of commonly used frequencies in today's designs.  The CY22801 enables users to generate custom clock configurations that are not supported by the CY22800.  The CyberClocks software tool allows users to specify the XIN/CLKIN frequency, crystal load capacitance, and output frequencies for the CY22801.

Both the CY22800 and CY22801 devices are programmed through the same programming board included in this kit.  The selected configuration is then downloaded via USB to the programmer in a matter of moments.  Production quantities are easily supported by Cypress' distribution partners.  Simply provide your local distributor with the JEDEC code generated by the software.

Note: This is a programming kit only. This kit is not designed and intended to be used for device evaluation or testing purposes.

For more information, click here.

InstaClock™ CY36800 Kit Contents:

• 3 Samples of CY22800
• 3 Samples of CY22801
• 1 Programmer board with USB connector and socket onboard
• 1 USB Cable

Software Title	Description	Link
InstaClock Software	Jedec files pre-configured and Programmer software for CY22800
CyberClocks Software	Jedec file Creator and Programmer software for CY22801

Reprinted with permission from Electronic Design,
June 10, 2002. Copyright 2002, Penton Media Inc.
611 Route 46 West, Hasbrouck Heights, NJ  07604, USA

Read the article here.

For more information on our USB Embedded Hosts products, visit: cypress.com