Features

• Memory organization
  • Industry's largest first in first out (FIFO) memory densities: 18 Mbit, 36 Mbit, and 72 Mbit
  • Selectable memory organization: x9, x12, x16, x18, x20, x24, x32, x36
• Up to 133-MHz clock operation
• Unidirectional operation
• Independent read and write ports
  • Supports simultaneous read and write operations
  • Reads and writes operate on independent clocks, upto a maximum ratio of two, enabling data buffering across clock domains.
  • Supports multiple I/O voltage standard: low voltage complementary metal oxide semiconductor (LVCMOS) 3.3 V and 1.8 V voltage standards.
• For more, see pdf.
   

Functional Description

The Cypress programmable FIFO family offers the industry’s highest-density programmable FIFO memory device. It has independent read and write ports, which can be clocked up to 133 MHz. User can configure input and output bus sizes. The maximum bus size of 36 bits enables a maximum data throughput of 4.8 Gbps.

Features

• 3.3 V operation for low-power consumption and easy integration into low-voltage systems
• High-speed, low-power, first-in first-out (FIFO) memories
• 16 K × 9 (CY7C4261V)
• 32 K × 9 (CY7C4271V)
• 64 K × 9 (CY7C4281V)
• 128 K × 9 (CY7C4291V)
• 0.35-micron CMOS for optimum speed or power
• High-speed 100-MHz operation (10-ns read/write cycle times)
• Low power
• For more, see pdf
   

Functional Description

The CY7C4261/71/81/91V are high-speed, low-power FIFO memories with clocked read and write interfaces. All are nine bits wide. The CY7C4261/71/81/91V are pin-compatible to the CY7C42x1V Synchronous FIFO family. Programmable features include Almost Full/Almost Empty flags. These FIFOs provide solutions for a wide variety of data buffering needs, including high-speed data acquisition, multiprocessor interfaces, and communications buffering.

This document describes the errata for the 18 Mbit, 36 Mbit, and 72 Mbit programmable FIFOs. Details include errata trigger conditions, scope of impact, available workarounds, and silicon revision applicability. Compare this document to the device’s datasheet for a complete functional description.

Features

• Memory organization
  • Industry’s largest first in first out (FIFO) memory densities: 144-Mbit
  • Selectable memory organization: × 9, × 12, × 16, × 18, × 20, × 24, × 32, × 36
• Up to 100-MHz clock operation
• Unidirectional operation
• Independent read and write ports
  • Supports simultaneous read and write operations
  • Reads and writes operate on independent clocks, upto a maximum ratio of two, enabling data buffering across clock domains.
  • Supports multiple I/O voltage standard: Low voltage complementary metal oxide semiconductor (LVCMOS) 3.3 V and 1.8 V voltage standards.
• For more, see pdf.

Functional Description

The Cypress programmable FIFO family offers the industry’s highest-density programmable FIFO memory device. It has independent read and write ports, which can be clocked up to 100 MHz. User can configure input and output bus sizes. The maximum bus size of 36 bits enables a maximum data throughput of 3.6 Gbps. The read and write ports can support multiple I/O voltage standards. The user-programmable registers enable user to configure the device operation as desired.

Features

• Memory organization
  • Industry’s largest first in first out (FIFO) memory density: 144-Mbit
  • Selectable memory organization: × 9, × 12, × 16, × 18, × 20, × 24, × 32, × 36
• Up to 133-MHz clock operation
• Unidirectional operation
• Independent read and write ports
  • Supports simultaneous read and write operations
  • Reads and writes operate on independent clocks upto a maximum ratio, of two enabling data buffering across clock domains.
  • Supports multiple I/O voltage standard: low voltage complementary metal oxide semiconductor (LVCMOS) 3.3 V and 1.8 V voltage standards.
• For more, see pdf.

Functional Description

The Cypress programmable FIFO family offers the industry’s highest-density programmable FIFO memory device. It has independent read and write ports, which can be clocked up to 133 MHz. User can configure input and output bus sizes. The maximum bus size of 36 bits enables a maximum data throughput of 4.8 Gbps. The read and write ports can support multiple I/O voltage standards.

Features

• Memory organization
  • Industry’s largest first in first out (FIFO) memory densities: 18-Mbit, 36-Mbit and 72-Mbit
  • Selectable memory organization: × 9, × 12, × 16, × 18, × 20, × 24, × 32, × 36
• Up to 100-MHz clock operation
• Unidirectional operation
• Independent read and write ports
  • Supports simultaneous read and write operations
  • Reads and writes operate on independent clocks upto a maximum ratio of two enabling data buffering across clock domains
  • Supports multiple I/O voltage standard: Low voltage complementary metal oxide semiconductor (LVCMOS) 3.3 V and 1.8 V  voltage standards.
• For more, see pdf
   

Functional Description

The Cypress programmable FIFO family offers the industry’s highest-density programmable FIFO memory device. It has independent read and write ports, which can be clocked up to 100 MHz. User can configure input and output bus sizes. The maximum bus size of 36 bits enables a maximum data throughput of 3.6 Gbps. The read and write ports can support multiple I/O voltage standards.

Features

• High speed, low power, first-in first-out (FIFO) memories
• 16 K × 9 (CY7C4261)
• 32 K × 9 (CY7C4271)
• 0.5 micron CMOS for optimum speed and power
• High speed 100 MHz operation (10 ns read/write cycle times)
• Low power — ICC = 35 mA
• Fully asynchronous and simultaneous read and write operation
• Empty, full, half full, and programmable almost empty and almost full status flags
• TTL compatible
• For more, see pdf
   

Functional Description

The CY7C4261/71 are high speed, low power FIFO memories with clocked read and write interfaces. All are nine bits wide. The CY7C4261/71 are pin compatible to the CY7C42X1 synchronous FIFO family. The CY7C4261/71 can be cascaded to increase FIFO width. Programmable features include almost full/almost empty flags. These FIFOs provide solutions for a wide variety of data buffering needs, including high speed data acquisition, multiprocessor interfaces, and communications buffering.

The content of the application note has also been captured in a training module. This audio visual tutorial provides an introduction to FIFO architecture & its functionality. It also explains basic FIFO features such as flags, expansion logic, timing specifications and some additional features specific to Synchronous FIFOs. A brief introduction to Cypress’s portfolio of Synchronous FIFOs & its applications is also included.

Training Module: View Download

- How is the Vcc/SMODE# pin used?

- What should I do with the SMODE pin?

- What is the difference between tying this pin to Vcc or ground?

Response:

In the CY7C42x5 and CY7C42x5V families of synchronous FIFOs, there is a pin labeled Vcc/SMODE# that is used to change the way the programmable flags work. If this particular pin is tied to Vcc, then the Almost Empty (PAE#) and Almost Full (PAF#) flags will respond asynchronously to a particular clock. If this pin is tied to ground, then the flag will respond synchronously to a clock edge which is why it is called SMODE = synchronous mode. Specifically, in SMODE, the Almost Empty flag will update after the next RCLK rising edge while the Almost Full flag will update after the next WCLK rising edge. Otherwise the Almost Empty flag will update a certain time after the last write operation and the Almost Full flag will update after the last read operation. Depending on how the external devices will react to the flag, there is an argument to using either mode. If comparing to other Cypress synchronous FIFOs (like the CY7C436xx family) this pin should be tied to ground. More recent synchronous FIFOs have synchronous mode only flags.

Response: There are a couple of different options. One is to have a diode which would be forward-biased by a battery when the main power supply to the SRAM is turned off. The main power supply should have a decoupling capacitor to supply power to the SRAM for a few milli-seconds before the battery backs up so that the SRAM does not lose any of the data stored in it. The second option would be to have a large capacitor(super cap) which supplies charge to the SRAM when the main power supply is turned off. This might provide charge only for a few minutes.

- What design considerations are there when depth cascading multiple CY7C4231 FIFOs?

- What needs to be done with the flags when depth cascading?

Response:

Applications often require FIFO buffers deeper than those offered by discrete devices. By depth expanding multiple devices, a logically deeper FIFO can be constructed. The synchronous FIFO family offers two approaches to this common application. The CY7C42x1 family of x9 devices does not contain on-chip expansion circuitry, so another method of setting up this system is available.

These synchronous FIFOs do not have on-chip expansion circuitry. Instead, there are two write enable and two read enable signals (each with a different polarity) to allow a "ping-pong" arrangement. So if we are depth cascading 4 FIFOs, on the first write operation, we would write to one FIFO, then the next write cycle we would switch to the second FIFO, then to the third, and then the fourth. After writing to the fourth FIFO on the fourth write cycle, we would move back to the first FIFO for the fifth write cycle. This arrangement allows the use of the /PAE and /PAF signals as well as the /EF and /FF signals. This is because when any of the individual programmable flags are set off, the overall state of all four FIFOs is comparably almost empty/full. The only disadvantage of this design is that there is a little loss in the maximum speed of this system as the databus must switch every clock cycle.

The read/write enables are used to enable only one FIFO at a time. For this design to work there needs to be some external read and write enable controller. This controller would be responsible for switching /WEN1, WEN2, /REN1, and /REN2.

This is explained in much more detail in the application note Depth Expansion of Synchronous FIFOs.

- What is the advantage of FWFT mode?

- How does the AE# flag work in FWFT mode (vs. CY Standard mode)?

Response:

In the CY Standard Mode, each read operation performed on the FIFO retrieves the next piece of data to the FIFO output data bus. Thus, the first read operation performed on the FIFO retrieves the first word onto the FIFO output data bus. The device reading from the FIFO will latch the first piece of data on the second rising edge of the clock, which may also be the second read operation of the FIFO. The FWFT Mode, however, allows the first piece of data to be at the output data bus before a read operation is performed, thus the first actual read operation actually retrieves the second piece of data from the FIFO. Such an arrangement allows the device reading from the FIFO to latch the first piece of data at the first read operation.

Therefore, for CY Standard Mode, if the FIFO contains N words, ENB will need to be asserted for the duration of N CLKB rising edges, while N+1 CLKB rising edges will be required for the device reading from the FIFO to read all N words. For the FWFT mode, only N CLKB rising edges are required to read all N words (ENB needs to be asserted for the same duration of N CLKB edges). FWFT Mode is required for cascading 2 or more FIFOs, but can also be used in stand-alone mode. In FWFT mode, the very first word written into the empty FIFO is not stored in the memory array and so it is not counted. As soon as the OR flag goes HIGH, that first word is shifted to the output register. So if you set AE# to 8 in one of the 5V x36 FIFOs (CY7C436xx), because of the inherent uncertainty, it will remain asserted until EITHER X+1 or X+2 (9 or 10) words are actually in the FIFO array. Because the first data written is not stored in the FIFO array, that means you will have to actually write 10 or 11 words into the FIFO before AE# goes high.

The table on all of the CY7C436xx datasheets is confusing because it does not explain the difference between assertion and de-assertion of the AE# flag. The table is true the way it is shown for after leaving the Almost Empty state (so you have > 10 words in the memory, effectively > 11 writes). Then, when you read from the FIFO and cross the border between 9 to 8 words in the FIFO memory, the AE# flag will assert. It is also confusing because they tried to group both CY mode and FWFT mode together in that table. The problem is that in FWFT mode, as soon as OR is asserted, the first data is driven, and OR is de-asserted again. You will see that in the regular CY mode, EF# goes high 3 cycles after the first word is written. It remains high until the first read operation (when enabled and read strobed). This could be several clock cycles later. In contrast, in FWFT mode, OR goes high at the same time the first word is driven (when enabled), and returns low at the very next clock edge.