PSoC Designer 5.0 SP6 will continue to be available for System Level Design users, and it will co-exist with future PSoC Designer 5.1 releases. However, we are not recommending System Level Design for production designs.

We suggest users to use the latest version of PSoC Designer located here:

www.cypress.com/go/psocdesigner

PSoC Designer 5.0 SP6 supports Internet Explorer 6 through 8, but does not support Internet Explorer 8 Beta or Internet Explorer 9 due to compatibility issues.

To Install PSoC Designer 5.0 SP6 users must first have PSoC Programmer installed first. For the latest release of PSoC Programmer please, Click Here

PSoC Designer 5.0 PS6 was tested using Beta version of Windows 7. PSoC Designer 5.0 SP6 is not supported for Windows 7 systems.

To Install:

Shut Down any currently running instances of PSoC Designer.

If an earlier service pack of PSoC Designer 5.0 is currently installed, uninstall it. To do this please navigate to Start>Control Panel>Add or Remove Programs.

• Install latest PSoC Programmer.
• Install PSoC Designer 5.0 SP6 by running the installed in the downloads table below.”

Note to HI-TECH Compiler Users:

There are new devices in this release. To compile projects containing these devices with the HI-TECH compiler, you must manually update the psoc.ini file. The HI-TECH psoc.ini file is found in the HI-TECH installation folder. The default location of the psoc.ini is here:

C:\Program Files\HI-TECH Software\HCPSOC\PRO\9.61\dat\psoc.ini

The default location of the replacement psoc.ini file that adds support for the new devices is here:

C:\Program Files\Cypress\Common\CypressSemiBuildMgr\tools\psoc.ini

PSoC Programmer: The latest version of PSoC Programmer must be installed along with PSoC Designer. For the latest release please navigate to the PSoC Programmer web page: Click Here

PSoC Designer: User Guides - Click Here

PSoC Designer Archive - Click Here

The ICE-Cube also serves as a single-site device programmer via an ISSP (In-System Serial Programming) Cable and MiniEval board included in the kit. The MiniEval board is a programming and evaluation board which connects to the ICE-Cube via an ISSP Cable and allows programming of DIP devices. There are also other Programming boards available for programming other packages. The MiniEval also includes LEDs and a POT for simple evaluation and demonstration.

PSoC 1 Debugger Includes:

• PSoC Designer Software CD-ROM
• ICE-Cube In-Circuit Emulator
• ICE Flex-Pod for CY8C29xxx Family
• Backward compatibility Cat-5 Adapter
• ISSP Cable
• Mini-Eval Programming Board in One
• USB 2.0 Cable and Blue Cat-5 Cable
• 110 ~ 240V Power Supply, Euro-Plug Adapter
• 2 CY8C29466-24PXI 28-PDIP Chip Samples

Supports following 8 bit PSoC1 (Programmable System-On Chip) families, including automotive, except CY8C25/26xxx devices.

PSoC 1 Getting Started Debugging - Part 1

Software Title	Description	Link
PSoC Designer	This kit requires PSoC Designer for development
PSoC Programmer	This kit requires PSoC Programmer for programming

Related Resources:

Due to the deleterious effects of crosstalk, it is important to determine the amount of it that exists during worst case scenarios. Currently, there are no standard crosstalk measurement techniques for the serial domain. This article describes effective measurement techniques and how to determine if the amount of crosstalk is acceptable for reliable data transfer. The techniques described include measuring the device's jitter output with a wide-bandwidth oscilloscope and spectral output with a high-bandwidth spectrum analyzer. Also discussed are the configurations that yield the highest crosstalk scenarios. Real measurement data of a multi-channel, independent rate device is provided. The measurements are performed at video serial digital interface (SDI) data rates, but the measurement techniques apply to any high-speed standard. To read more on this topic, click the download link above, or visit Planet Analog.

PSoC Programmer 3.17 offers the user a simple GUI that connects to programming hardware to program and configure PSoC, Clock, and configurable fixed function devices. Also provided with PSoC Programmer is the Bridge Control Panel, which can be used to debug, graph and log I2C serial communications using various supported Cypress Software. PSoC Programmer also provides a hardware layer for customers to design custom applications or use existing code examples for testing hardware and Firmware designs.

PSoC Programmer 3.17 release shall support both PSoC Creator and PSoC Designer in a single installation.

PSoC Programmer 3.17 is a minor release. For additional information regarding the installation and the new features please see the release notes in the downloads table below.

PSoC Programmer:

PSoC Programmer is a flexible, integrated programming application for programming PSoC devices. PSoC Programmer can be used with PSoC Designer and PSoC Creator to program any design onto a PSoC device. PSoC Programmer supports all PSoC 1, 3, and 5 devices.

COM Hardware Layer Supported Languages:

PSoC Programmer provides the user a hardware layer with API’s to design specific applications utilizing the programmers and bridge devices. The PSoC Programmer hardware layer is fully detailed in the COM guide documentation as well as example code across the following languages: C#, C, Perl, and Python.

PSoC Programmer Secondary Software

PSoC Programmer includes additional software beyond just PSoC Programmer. For more information on that additional software please: Click Here

Third Party IDE and Programming Support

PSoC Programmer delivers a number of files and utilities that enable 3^rd party programming and debugging support for PSoC device families. In the downloads table below we include the 3^rd party user guide which will assists the user in configuring and enabling the support in the IDEs or programming utilities. The files and applications can be found in the root installation directory for each programmer installation.

Archived Software:

PSoC Programmer software is archived at the following page: Click Here

Additional Programming Links:
Prototype Programming Hardware:

PSoC Programmer is part of a suite of programming options and programming content available to PSoC users. For customers who are looking for more information on general programming options and information please navigate to the web page linked below. On the General Programming web page we discuss all of the available programming options for customers including Software, Schematics, Programming Specifications, and 3rd party mass programming.

www.cypress.com/go/programming

All PDF documents require at least a PDF reader installed prior to opening.

 
Features:

• User friendly PLC Control Panel Application available on kit CD
• CY8CPLC20-OCD – 100-pin TQFP on-chip debug (OCD) device that allows quick design and debug of a PLC application. The CY8CPLC20 100-pin TQFP is available for debug purposed only. For production quantities, CY8CPLC20 is available in 28-pin SSOP and 48-pin QFN packages.
• Chip power supply derived from 90V to 264V AC
• User configurable general purpose LEDs
• General purpose 8-bit DIP switch
• On board surge protection and isolation circuit
• RJ45 connector to use ICE debugger
• RS232 COM port for communication
• Header to attach LCD card
• I2C header for communicating to external device
• ISSP header for programming the CY8CPLC20

 
Kit Contents:

• CY3274 Quick Start Guide
• CY3274 PLC HV Development Board
• CDs containing:
  • Packet Test Software – PLC Control Panel Application
  • CY8CPLC20 Data Sheet
  • Development Board User Guide
  • Application Note – Using CY8CPLC20 in Powerline Communication (PLC) Applications
  • CY3274 Board Schematics
  • CY3274 Board Gerbers
  • PSoC Designer™
  • PSoC Programmer
• AC Power Cable
• MiniProg1 to Program CY8CPLC20
• 25 Jumper Wires
• LCD Module
• USB-I2C Bridge
• Retractable USB Cable
• Five CY8CPLC20-28PVXI Device Samples

Software Title	Description	Link
PSoC Designer	This kit requires PSoC Designer for development
PSoC Programmer	This kit requires PSoC Programmer for programming
Powerline Communcation	PLC Contol Panel Application

There are generally two types of PLC systems: high-bandwidth (video, audio, and so on) and low-bandwidth (command and control). This application note describes how to implement a low-bandwidth, half-duplex PLC solution with the PSoC 5LP family of devices.

The following table indicates the PSoC devices, PSoC Creator versions, compilers, and development kits that will work with this application note project:

1. Click on AN84741 - PSoC® 5 to PSoC 5LP Migration Guide to learn differences between PSoC 5 and PSoC 5LP.
2. For PSoC 5 project and related document, please download file AN76458_Archive.zip.

Projects associated with this application note can be downloaded from the 'Related Files' section below. For your convenience, we have provided projects that are compatible with the two most recent versions of PSoC Creator:

• AN76458.zip is used with PSoC 5LP and PSoC Creator 2.1 SP1
• AN76458_Archive.zip is used with PSoC 5 and PSoC Creator 2.1/2.1 SP1.

The project’s default settings may not be compatible with your device or kit, and you may need to change your project settings. For more information, see:

Cypress’ Powerline Communication (PLC) devices (CY8CPLC10, CY8CPLC20 and CY8CLED16P01) provide a secure and reliable solution that integrates a Powerline PHY modem and Powerline optimized network protocol with CSMA into single device. These devices work with an external Powerline coupling circuit and power supply, which may need to be designed to meet certain compliance standards and specifications. This application note describes the design of these circuits and provides an overview of the commonly encountered compliance specifications along with guidelines on selection of critical components necessary to meet these specifications. 

In this video it is shown, how Cypress's Powerline Communication solution can be used to control LED lighting.

• 6-bit resolution with 32X oversampling to 14-bit resolution with 256X oversampling
• Data in unsigned or signed 2’s complement formats
• Maximum sample rates of 65,500 sps at 6 bit resolution, 7812 sps at 14-bit resolution
• Sinc² filter fully implemented in hardware reduces CPU overhead and anti-alias requirements
• 1st-Order or 2nd-Order modulator, user selectable
• Input range defined by internal and external reference options
• Optional synchronized PWM Output

The DelSig is an integrating converter, requiring from 32 to 256 integration cycles to generate a single output sample. Changing multiplexed inputs, invalidates the first two samples following the change.

• The 8-bit general purpose counter uses one PSoC block
• Source clock rates up to 48 MHz
• Automatic reload of period on terminal count
• Programmable pulse width
• Input enables/disables continuous counter operation
• Interrupt option on compare output or terminal count
   

The 8-Bit Counter User Module provides a down counter with a programmable period and pulse width. The clock and enable signals can be selected from any system time base or external source. Once started, the counter operates continuously and reloads its internal value from the period register upon reaching terminal count. During each clock cycle, the counter compares the current count to the value stored in the compare register. Each clock cycle, the Counter tests the count against the value of the compare register for either a “less than" or “less than or equal to" condition. The comparator output provides a logic level that may be routed to pins and to other user modules. Most PSoC device families also permit the terminal count output to be routed in the same manner.

Features

• Powerline Communication Solution
• Powerful Harvard Architecture Processor
• Programmable System Resources (PSoC® Blocks)
• Flexible On-Chip Memory
• Programmable Pin Configurations
• Additional System Resources
• Complete Development Tools
• For more, see pdf
   

PLC Functional Overview

The CY8CPLC20 is an integrated Powerline Communication (PLC) chip with the Powerline Modem PHY and Network Protocol Stack running on the same device. Apart from the PLC core, the CY8CPLC20 also offers Cypress's revolutionary PSoC technology that enables system designers to integrate multiple functions on the same chip.

Features

• Second-generation HOTLink® technology
• Compliant to multiple standards
  • ESCON®, DVB-ASI, fibre channel and gigabit ethernet (IEEE802.3z)
  • CPRI™ compliant
  • CYV15G0101DXB compliant to SMPTE 259M and SMPTE 292M
  • 8B/10B encoded or 10-bit unencoded data
• Single-channel transceiver operates from 195 to 1500 MBaud serial data rate
• For more, see pdf
   

Functional Description

The CYP15G0101DXB single-channel HOTLink II™ transceiver is a point-to-point communications building block allowing the transfer of data over a high-speed serial link (optical fiber, balanced, and unbalanced copper transmission lines) at signaling speeds ranging from 195 to 1500 MBaud.

The transmit channel accepts parallel characters in an input register, encodes each character for transport, and converts it to serial data. The receive channel accepts serial data and converts it to parallel data, frames the data to character boundaries, decodes the framed characters into data and special characters, and presents these characters to an output register.

Features

• Integrated Powerline Modem PHY
• 2400 bps Frequency Shift Keying Modulation
• Powerline Optimized Network Protocol
• Integrates Data Link, Transport, and Network Layers
• Supports Bidirectional Half-Duplex Communication
• 8-bit CRC Error Detection to Minimize Data Loss
• I2C enabled Powerline Application Layer
• Supports I2C Frequencies of 50, 100, and 400 kHz
• Reference Designs for 110V to 240V AC, 12V to 24V AC/DC Powerlines
• Reference Designs Comply with CENELEC EN50065-1:2001 and FCC Part 15
   

Functional Overview

The CY8CPLC10 is an integrated Powerline Communication chip with the Powerline Modem PHY and Powerline Network Protocol Stack. This chip provides robust communication between different nodes on a Powerline.

Features

• Second-generation HOTLink® technology
• Compliant to SMPTE 292M and SMPTE 259M video standards
• Dual-channel video serializer plus dual channel video reclocking deserializer
  • 195- to 1500-Mbps serial data signaling rate
  • Simultaneous operation at different signaling rates
• Supports reception of either 1.485 or 1.485/1.001 Gbps data rate with the same training clock
• Supports half-rate and full-rate clocking
• Internal phase-locked loops (PLLs) with no external PLL components
• Selectable differential PECL-compatible serial inputs
• For more, see pdf

Functional Description

The CYV15G0204TRB Independent Clock HOTLink II™ Dual Serializer and Dual Reclocking Deserializer is a point-to-point or point-to-multipoint communications building block enabling transfer of data over a variety of high-speed serial links including SMPTE 292M and SMPTE 259M video applications. It supports signaling rates in the range of 195 to 1500 Mbps per serial link.

Features

• Second-generation HOTLink® technology
• Compliant to SMPTE 292M and SMPTE 259M video standards
• Single channel video serializer plus single channel video reclocking deserializer
  • 195- to 1500-Mbps serial data signaling rate
  • Simultaneous operation at different signaling rates
• Supports reception of either 1.485 or 1.485/1.001 Gbps data rate with the same training clock
• Internal phase-locked loops (PLLs) with no external PLL components
• Supports half-rate and full-rate clocking
• Selectable differential PECL-compatible serial inputs
• For more, see pdf

Functional Description

The CYV15G0104TRB Independent Clock HOTLink II™ Serializer and Reclocking Deserializer is a point-to-point or point-to-multipoint communications building block enabling transfer of data over a variety of high-speed serial links including SMPTE 292M and SMPTE 259M video applications. It supports signaling rates in the range of 195 to 1500 Mbps per serial link.

Features

• Second-generation HOTLink® technology
• Compliant to multiple standards
  • ESCON, DVB-ASI, SMPTE-292M, SMPTE-259M, Fibre Channel and Gigabit Ethernet (IEEE802.3z)
  • CPRI™ compliant
  • 8B/10B coded data or 10 bit uncoded data
• Quad channel transceiver operates from 195 to 1500 MBaud serial data rate
  • Aggregate throughput of up to 12 Gbits/second
• Second-generation HOTLink technology
• Truly independent channels
• For more, see pdf

Functional Description

The CYP(V)15G0403DXB Independent Clock Quad HOTLink II™ Transceiver is a point-to-point or point-to-multipoint communications building block enabling transfer of data over a variety of high-speed serial links like optical fiber, balanced, and unbalanced copper transmission lines. The signaling rate can be anywhere in the range of 195 to 1500 MBaud per serial link.

Features

• Second-generation HOTLink® technology
• Compliant to multiple standards
• Quad channel transceiver operates from 195 to 1500 MBaud serial data rate
• Selectable parity check/generate
• Selectable multi-channel bonding options
• Skew alignment support for multiple bytes of offset
• Selectable input/output clocking options
• MultiFrame™ Receive Framer
• Synchronous LVTTL parallel interface
• For more, see pdf
   

Functional Description

The CYP(V)15G0401DXB Quad HOTLink II™ Transceiveris a point-to-point or point-to-multipoint communications building block allowing the transfer of data over high-speed serial links (optical fiber, balanced, and unbalanced copper transmission lines) at signaling speeds ranging from 195-to-1500 MBaud per serial link.

Features

• Second-generation HOTLink® technology
• AMD™ AM7968/7969 TAXIchip™-compatible
• 8-bit 4B/5B or 10-bit 5B/6B NRZI encoded data transport
• 10-bit or 12-bit NRZI pre-encoded (bypass) data transport
• Synchronous TTL parallel interface
• Embedded/bypassable 256-character Transmit and Receive FIFOs
• 50- to 200-MBaud serial signaling rate
• Internal phase-locked loops (PLLs) with no external PLL components
• Dual differential PECL-compatible serial inputs and outputs
• For more, see pdf
   

Functional Description

The CY7C9689A HOTLink Transceiver is a point-to-point communications building block allowing the transfer of data over high-speed serial links (optical fiber, balanced, and unbalanced copper transmission lines) at speeds ranging between 50 and 200 MBaud. The transmit section accepts parallel data of selectable widths and converts it to serial data, while the receiver section accepts serial data and converts it to parallel data of selectable widths.

Features

• Fibre Channel-compliant
• IBM ESCON®-compliant
• DVB-ASI-compliant
• ATM-compliant
• 8B/10B-coded or 10-bit unencoded
• Standard HOTLink®: 160 to 330 Mbps
• High-speed HOTLink: 160 to 400 Mbps for high-speed applications
• Transistor-transistor logic (TTL)-synchronous I/O
• No external phase locked-loop (PLL) components
• For more, see pdf
   

Functional Description

The CY7B923 HOTLink‚ transmitter and CY7B933 HOTLink receiver are point-to-point communications building blocks that transfer data over high-speed serial links (fiber, coax, and twisted pair). Standard HOTLink data rates range from 160 to 330 Mbps. Higher speed HOTLink is also available for high-speed applications (160 to 400 Mbits/second).

Features

• Second generation HOTLink(TM) technology
• Fibre Channel and ESCON(TM) compliant 8B/10B encoder/decoder
• 10 or 12 bit preencoded data path (raw mode)
• 8 or 10 bit encoded data transport (using 8B/10B coding)
• Synchronous or asynchronous TTL parallel interface
• UTOPIA compatible host bus interface
• Embedded/Bypassable 256-character synchronous FIFOs
• Integrated support for daisy-chain and ring topologies
• Domain or individual destination device addressing
• For more, see pdf
   

Functional Description

The 200 MBaud CY7C924ADX HOTLink Transceiver is a point-to-point communications building block allowing the transfer of data over high speed serial links (optical fiber, balanced, and unbalanced copper transmission lines) at speeds ranging between 50 and 200 MBaud. The transmit section accepts parallel data of selectable width and converts it to serial data, while the receiver section accepts serial data and converts it to parallel data of  selectable width.      More...

Features

• Second-generation HOTLink® technology
• Compliant to SMPTE 292M and SMPTE 259M video standards
• Dual-channel video serializer
  • 195- to 1500-Mbps serial data signaling rate
  • Simultaneous operation at different signaling rates
• Supports half-rate and full-rate clocking
• Internal phase-locked loops (PLLs) with no external PLL components
• Redundant differential PECL-compatible serial outputs per channel
  • No external bias resistors required
• For more, see pdf

Functional Description

The CYV15G0203TB Independent Clock Dual HOTLink II™ Serializer is a point-to-point or point-to-multipoint communications building block enabling transfer of data over a variety of high-speed serial links including SMPTE 292M and SMPTE 259M video applications. It supports signaling rates in the range of 195 to 1500 Mbps per serial link.

Features

• OC-3 Compliant with Bellcore and CCITT (ITU) specifications on:
  • Jitter Generation (<0.01 UI)
  • Jitter Transfer (<130 kHz)
  • Jitter Tolerance
• SONET/SDH and ATM Compliant
• Compatible with IGT WAC013, IGT WAC413, and PMC-Sierra PM5343
• Clock and data recovery from 51.84- or 155.52-MHz datastream
• 155.52-MHz clock multiplication from 19.44-MHz source
• 51.84-MHz clock multiplication from 6.48-MHz source
• For more, see pdf

Functional Description

The SONET/SDH Serial Transceiver (SST) is used in SONET/SDH and ATM applications to recover clock and data information from a 155.52-MHz or 51.84-MHz NRZ or NRZI serial data stream and to provide differential data buffering for the Transmit side of the system.

Features

• SONET/SDH and ATM Compatible
• Compatible with PMC-Sierra PM5345 SUNI™
• Clock and data recovery from 51.84- or 155.52-MHz datastream
• 155.52-MHz clock multiplication from 19.44-MHz source
• 51.84-MHz clock multiplication from 6.48-MHz source
• ±1% frequency agility
• Line Receiver Inputs: No external buffering required
• Differential output buffering
• 100K ECL compatible I/O
• For more, see pdf

Functional Description

The Local Area Network ATM Transceiver is used in SONET/SDH and ATM applications to recover clock and data information from a 155.52-MHz or 51.84-MHz NRZ or NRZI serial data stream and to provide differential data buffering for the Transmit side of the system.

Features

• SONET OC-48 operation
• Bellcore and ITU jitter compliance
• 2.488 GBaud serial signaling rate
• Multiple selectable loopback or loop through modes
• Single 155.52 MHz reference clock
• Transmit FIFO for flexible data interface clocking
• 16-bit parallel-to-serial conversion in transmit path
• Serial-to-16-bit parallel conversion in receive path
• Synchronous parallel interface
• For more, see pdf

Functional Description

The CYS25G0101DX SONET OC-48 Transceiver is a communications building block for high speed SONET data communications. It provides complete parallel-to-serial and serial-to-parallel conversion, clock generation, and clock and data recovery operations in a single chip optimized for full SONET compliance.

Features

• Second-generation HOTLink® technology
• Compliant to multiple standards
  • ESCON, DVB-ASI, Fibre Channel and Gigabit Ethernet (IEEE802.3z)
  • CPRI™ compliant
  • 8-/10-B encoded or 10-bit unencoded data
• Dual channel transceiver operates from 195 to 1500-MBaud serial data rate
  • Aggregate throughput of 6-GBits per second
• Selectable parity check/generate
• Selectable dual-channel bonding option
• For more, see pdf
   

Functional Description

The CYP15G0201DXB dual-channel HOTLink II™ transceiver is a point-to-point or point-to-multipoint communications building block allowing the transfer of data over high-speed serial links (optical fiber, balanced, and unbalanced copper transmission lines) at signaling speeds ranging from 195- to 1500-MBaud per serial link.

• One PLC20Q Pod
• One Flex cable
• Two 48QFN Feet

 
Features:

• User friendly PLC Control Panel Application available on the kit CD
• Chip power supply derived from 110V to 240V AC
• On-chip powerline bridge application layer, powerline network protocol layer, and physical layer FSK modem
• LED status indicators for Power, Powerline Transmit and Receive, and Band in Use.
• Five-position DIP switches
  • Three DIP switches for manual powerline node logical address selection
  • One DIP switch to configure I2C slave address
  • One DIP switch to select between external crystal and oscillator
• On board surge protection and isolation circuit
• Integrated Powerline Modem PHY
   

Kit Contents:

• CY3272 Quick Start Guide
• One CY3272 PLC HV Evaluation Board
• CD containing:
  • Packet Test Software – PLC Control Panel Application
  • CY8CPLC10 Data Sheet
  • CY3272 Evaluation Board User Guide
  • Application Note – Using CY8CPLC10 in Powerline Communication (PLC) Applications
  • CY3272 Board Schematics
  • CY3272 Board Gerbers
• AC Power Cable
• USB-I2C Bridge
• Ribbon Cable for I2C communication, External Reset, and Powering External Board
• Retractable USB Cable
• Five CY8CPLC10-28PVXI Device Samples

Software Title	Description	Link
PSoC Designer	This kit requires PSoC Designer for development
PSoC Programmer	This kit requires PSoC Programmer for programming
Powerline Communcation	PLC Contol Panel Application

Kit content:

• One PLC20 Pod
• One Flex cable
• Two 28SSOP Feet
• One 28 Pin Mask

• Chip power supply derived from 12V to 24V AC/DC
• On-chip powerline bridge application layer, powerline network protocol layer, and physical layer FSK modem
• LED status indicators for Power, Powerline Transmit and Receive, and Band in Use
• Five-position DIP switches
  • Three DIP switches for node logical address selection
  • One DIP switch to configure node I2C addressing mode
  • One DIP switch to select between the external crystal and oscillator
• Integrated Powerline Modem PHY
   

Kit Contents:

• CY3273 Quick Start Guide
• CY3273 PLC LV Evaluation Board
• CD containing:
  • CY8CPLC10 Data Sheet
  • Packet Test Software – PLC Control Panel Application
  • CY3273 Evaluation Board User Guide
  • Application Note – Using CY8CPLC10 in Powerline Communication (PLC) Applications
  • CY3273 Board Schematics
  • CY3273 Board Gerbers
• 12V Power Supply
• Cable to Create LV Daisy Chain
• USB-I2C Bridge
• Five Wire Ribbon Cable for I2C communication, External Reset, and Powering External Board
• Retractable USB Cable
• Five CY8CPLC10-28PVXI Device Samples

Software Title	Description	Link
PSoC Designer	This kit requires PSoC Designer for development
PSoC Programmer	This kit requires PSoC Programmer for programming
Powerline Communcation	PLC Contol Panel Application

The CY3250-LED16P01NQ kit is obsolete as of July 6, 2011. In place of CY8CLED16P01 please consider using CY8CPLC20 device in your design and related POD kits. Links are provided below.

Please contact Cypress customer support if you have any questions. Call 1-800-541-4736 and select 8 or email us at customercare@cypress.com>

The CY3277 kit is obsolete as of June 22, 2011. If you are looking for a low voltage (12V – 24V AC/DC) Powerline Communication kit please see: CY3273 kit here: www.cypress.com/go/CY3273 and CY3275 kit here: www.cypress.com/go/CY3275

Please contact Cypress customer support if you have any questions. Call 1-800-541-4736 and select 8 or email us at customercare@cypress.com

The CY3276 kit is obsolete as of June 22, 2011. If you are looking for a high voltage (110V – 240V AC) Powerline Communication kit please see: CY3272 kit here: www.cypress.com/go/CY3272 and CY3274 kit here: www.cypress.com/go/CY3274

Please contact Cypress customer support if you have any questions. Call 1-800-541-4736 and select 8 or email us at customercare@cypress.com

Please contact Cypress customer support if you have any questions. Call 1-800-541-4736 and select 8 or email us at customercare@cypress.com

Please contact Cypress customer support if you have any questions. Call 1-800-541-4736 and select 8 or email us at customercare@cypress.com

Please contact Cypress customer support if you have any questions. Call 1-800-541-4736 and select 8 or email us at customercare@cypress.com

1. Humidity indicator card (HIC) is equal or greater than 10% when read at 23ºC +/- 5 ºC
2. After removal from bag, parts are not mounted on board within 168 hours (in equal or less 30 ºC /60%RH)
3. If they have not been stored in equal or less than 10% RH (as required on the MSL label)
    

If baking is required, devices may be baked for 24 hours at 125 ºC +5/-0 ºC.

Please note that the above baking condition is applicable for MSL-3 and MSL-5 parts only. Also, please ensure that only metal tubes or bakeable trays with rating of greater than 125 ºC must be used for baking. MSL 1 parts do not require baking.

Cypress recommends the customers to follow the Shelf Life condition of the parts as stipulated on the MSL label which can be found on the Moisture Barrier Bag (MBB) bag. A separate article on the Shelf Life of Cypress products is available at the following link: http://www.cypress.com/?id=4&rID=62201

COO on Intermediate Label:

COO on Outer Box Label:

COO on Top Mark:

Country of Origin Codes/Abbreviations:

The Independent Channel HOTLink II devices are capable of simultaneously operating each channel at a different data rate. The CYV15G0404DXB has the additional capability of performing independent reclocking on a per-channel basis.

The Independent Channel HOTLink II CYV15G0404DXB Video Demo Board demonstrates:

• The ability of the Cypress family of transceivers to pass serial digital video at signaling rates from 270 Mb/s to 1485 Mb/s
• The independent channel functionality of the applicable devices
• The ability to use a HOTLink II transceiver with an FPGA for auto rate detection and clock reconfiguration
• The ability to perform reclocking in the HOTLink II CYV15G0404DXB device
• The flexible configuration abilities of Cypress Microsystems' PSoC(TM) microcontroller
• The use of Cypress EZ-USB FX2T USB microcontroller for video data and in-system configuration applications
• On-board FPGAs that generate and receive different video test patterns.

Although this board uses the CYV15G0404DXB device, the same board can be used as an evaluation vehicle for any device in the HOTLink II Independent Channel family of devices. Please refer to the data sheets for descriptions of the HOTLink II Independent Channel family of devices.

Reflow Profiles (per Jedec J-STD-020D.1)

Table 2A
SnPb Eutectic Process - Classification Temperatures (Tc)

Table 2B
Pb-Free Process -Classification Temperatures (Tc)

Note:

1. Peak Temperature tolerance is +5/-0 °C of Classification Temp (Tc).
2. All temperatures refer to topside of the package, measured on the package body surface.
3. Package volume excludes external terminals (e.g., balls, bumps, lands, leads) and/or nonintegral heat sinks.

 For example:
To be able to get the reflow profile of a part, we need to know first the Package dimension or volume. 

MPN: CY7C65620-56LTXC
Package: QFN56, Pb-Free Part
Package Dimension: 8x8x1.0mm
Package Volume: 64mm³
Package Thickness: 1.0mm

You can get package dimension on the datasheet’s Package Diagram.

Since the part is a Pb Free Part, Table 2B should be used. Based on this table, is the package volume is <350 mm³ and the package thickness is <1.6mm, Peak Temperature = 260 °C

If the part number is SnPb Part, Table 2a is applicable.

Please note all our CPLD/PLD families of devices are Obsolete.
 

Further, due to resource / expertise constraints, we currently do not have plans to include the driver support for the Windows platform.

Please be informed our entire CPLD products are Obsolete.

This development kit is no longer available. This web page has been left in place for informational purposes only.

The HOTLink II™ transceiver is a point-to-point or point-to-multipoint communications building block allowing the transfer of data over high-speed serial links at signaling speeds ranging from 195 to 1500 MBaud.

The frequency agility of the HOTLink II transceiver enables its application in various data and video transmission standards. The HOTLink II transceiver supports serial video transmission that complies with Digital Video Broadcasting (DVB-ASI) and Society of Motion Picture Television Engineers (SMPTE) standards. DVB is a widely accepted standard for digital video transmission, especially in the video-on-demand market. SMPTE has in turn developed several standards for serial and parallel video transmission at different speeds and formats.

The HOTLink II video evaluation board demonstrates the ability of the Cypress HOTLink II family of devices to pass video at signaling rates of up to 360 Mbps. It also demonstrates the functionality of Delta39K™ CPLD as an ideal CPLD solution for SMPTE applications, the flexible clocking abilities of CyClocksRT™, and the use of EZ-USB FX2™ USB microcontroller for video data and in-system configuration applications.

• User-friendly GUI
• Video transport at multiple data rates of 270 and 360 Mbps
• Supports DVB-ASI (270 Mbps)
• SMPTE scrambler/descrambler embedded in Delta39K CPLD
• USB port to establish board configuration
• High-speed USB FX2 to configure Delta39K CPLD and programmable clock
• Flexible clocking abilities of CyClocksRT
• External and internal loop back capability for SMPTE and DVB-ASI
• Delta39K CPLD, reconfigurable via the USB or ISR(T) Header or from the boot memory
• 12V DC supply with on-board voltage regulator to prevent noise transfer from external power sources
• On-board serial equalizer and cable driver
• LED status indicators

The software GUI is available for download from the Cypress website at the following location: CYV15G0101DXB Video Evaluation Board software

Additional information about this evaluation board can be found in the user's guide: HOTLink II™ Video Evaluation Board User's Guide

The evaluation board allows users to become familiar with the functionality of the CYP15G0101DXB and perform simple tests.  Some of the features include:

• Selectable serial interface
  • SMA connectors
  • Small form factor pluggable (SFP) optical module cages
• Single 3.3V power supply
• Power-on indicator (LED)
• JTAG interface
• Selectable clock options
  • Onboard crystal
  • SMA connectors for external REFCLK
• LFI indicator (LED)
• Switches for latch control
• Selectable static control inputs
   

These features allow many evaluation modes including:

• BIST internal loopback
• BIST external loopback
• Parallel data in and parallel data out mode

More information about this evaluation board can be found in the User's Guide:  CYP15G0101DXB Evaluation Board User's Guide

The CYS25G0101DX Evaluation Board is designed for evaluating as well as understanding the characteristics of the CYS25G0101DX SONET/SDH Transceiver. The evaluation board provides the following advantages:

• Flexible and easy to operate
• On-board Cypress 120-pin thin quad flat pack (TQFP) CYS25G0101DX SONET/SDH Transceiver
• Supports LVPECL or HSTL interfaces
• Dip switch for selecting different diagnostic modes
• Four diagnostic modes - Diagnostic Loopback mode, Line Loopback mode, Analog Line Loopback mode, and factory TEST0 (Parallel Line Loopback) mode
• LFI and FIFO_ERR LEDs
• Onboard oscillator for the REFCLK
• Supports external clock source for the REFCLK
• 16-bit RxD, 16-bit TxD bus, RXCLK, TXCLKI, TXCLKO interface
• SMA connectors for CML input and output buffers
• Separate Banana Jacks for all voltage sources for measuring current individually

For more information, please refer to the user's guide: CYS25G0101DX Evaluation Board User's Guide

This development kit is no longer available. This web page has been left in place for informational purposes only.

The CYP15G0401DXB Quad HOTLink II™ transceiver is a point-to-point or point-to-multipoint communications building block allowing the transfer of data over high-speed serial links (optical fiber, balanced and unbalanced copper transmission lines) at signaling speeds ranging from 195 to 1500 MBaud per serial link. The multiple channels in each device may be combined to allow transport of wide buses across significant distances with minimal concern for offsets in clock phase or link delay.

The evaluation board allows users to become familiar with the functionality of the CYP15G0401DXB.  Some of the features include:

• Selectable serial interfaces
  • SMA connectors
  • Small form factor pluggable (SFP) optical module cages
• Single 3.3V power supply
• Power-on indicator (LED)
• JTAG interface
• Selectable clock options
  • Onboard crystal (125 MHz)
  • SMA connectors for external REFCLK
• LFI indicators (LED)
• Switches for latch control
• Selectable static control inputs
• Selectable channel bonding options
   

• BIST internal loopback
• BIST external loopback
• Parallel in - parallel out mode (encoded)
• Parallel in - parallel out mode (unencoded)
• Parallel in - serial out mode (testing the transmit side)
• Different clock source (i.e., internal vs. external, different frequency mode, etc.)
   

More information about this evaluation board can be found in the following guide: CYP15G0401DXB Evaluation Board User's Guide

The signal source for the receiver is the serial data stream and, like the transmitter, it passes the spectral components of received jitter that fall below the natural frequency of its filter (approximately 300 kHz to 1000 kHz depending on actual data transition density being received). Frequency components above the natural frequency are attenuated and there is minor jitter peaking at about the natural frequency of the PLL. Since the characteristics of the input jitter determine the jitter content on the receiver CKR output (the only place to directly measure Rx-PLL jitter) it is somewhat difficult to predict the output jitter. Maximum CKR output jitter is less than 200 ps (peak-to-peak) when the receiver is tracking normal data (BIST data is typical) that exhibits maximum tolerable peak-to-peak jitter. Jitter from normal data is wide-bandwidth, has significant high-frequency content, and can have peak-to-peak amplitude of up to about 90% of a bit time. If the serial data contains a significant low frequency jitter component (typical in crystal oscillators and some pulse generators) the output jitter measured on the CKR pin could be much higher. Jitter measurements at the receiver output can be more misleading than those associated with the transmitter serial outputs, since all measurements are made on TTL outputs. The jitter characteristics mentioned here affect system performance in the following ways. Any low-frequency jitter (below the bandwidth of either transmitter or receiver PLL) is treated as wander. For purposes of the PLLs, wander (usually caused by low-frequency power supply variations or temperature fluctuations within the timing ICs) does not reduce the system timing margins and does not contribute to bit-error-rate. Wander can affect system timing at interfaces where the transmitter clock source is used to clock information received from a receiver tracking data from another clock source. The variation in clock frequencies may violate set-up and hold times, the exact problems usually solved by FIFO memories in typical communication systems. High-frequency jitter (at or above the natural frequency of the PLL filters) may contribute to BER. High-frequency jitter can be caused by the clock source, media transfer characteristics, or external noise. The recovered internal bit-rate clock does not track high-frequency jitter above the PLL natural frequency. High-frequency jitter, therefore, may cause a bit edge to move into the receiver sampling window causing the bit to be erroneously sampled (a bit error).
 

A suitable clock source should be selected with the above effects in mind. The only clock source guaranteed to offer the required stability and high-frequency specifications is a crystal oscillator. High-frequency jitter is minimal, and low-frequency wander is usually small and very low frequency. Frequency accuracy is easily guaranteed by mechanical means, and high accuracy devices are relatively low cost. Free-running resistor-capacitor (RC) oscillators, logic gate ring oscillators, or inductor-capacitor (LC) oscillators include too much high-frequency jitter, experience wide frequency variation as a function of process and environmental conditions and thus are unsuitable for this application. See the "HOTLink Jitter Characteristics" application note for more information.


Useful Link:
HOTLink Transmitter/Receiver

HOTLink Jitter Characteristics-AN1161

HOTLink has no intrinsic distance limit. The two issues that determine the distances over which data can be sent using HOTLink are: (1) the choice of interconnect media (plastic or glass fiber-optic cable, coaxial cable, twisted-pair cable, etc.); and (2) the jitter that accumulates or is injected while the data is in transit over the selected media.

The HOTLink Receiver-FIFO interface section also includes a simple design example.A simple state machine controls this interface.The state machine addresses design issues such as reframing the serial data,BIST(Built-In Self-Test), and programming clocked FIFOs.These issues are discussed in detail.A state transition diagram is included.Critical path timing equations are derived and the advantages of pipelining the interface are discussed.Timing waveforms are shown to help illustrate the critical timing relationships.

1. Go to www.cypress.com.  On the top right, you will see a “Keyword / Part Number” search box (adjacent to “Contact Us.”) 

2. Select the “Part Number” tab above this text box.

3. Type the exact part number, for example CY8C29466-12PVXE.

4. The part number will be listed in the search results page.

5. Click on the part number link (1st column starting from the left). This will open a new web page.

Moisture Sensitivity Level (MSL) can be found by clicking the “Quality & Pb-free Data” link on the top, or by just scrolling down to the Quality & Pb-free Data” section about half way down the page.

All other Quality information for this part number (e.g., RoHS compliance, Lead/Ball Finish, Qualification Reports, IPC reports) can also be found on this web page. 

In case of any questions, or if the information is not available for a particular part number, please create a support case at www.cypress.com/support

If you do not know the Cypress part number: 

1. Go to www.cypress.com.  Browse the different products (“Products” tab on the top navigation menu) by family.

2. Once you choose the relevant product family (e.g., “Clocks and Buffers->Clock Distribution,” “Memory->FIFOs”), scroll down the particular page to get to the “Parametric Product Selector.”

3. Use this tool to find the part number by function/feature, and click on the part number you are interested in. This will lead you directly to step # 5 above.

1. Install the PLC Control Panel onto your PC. The latest version of the Control Panel can be downloaded from http://www.cypress.com/?rID=38135.
2. Install and run PSoC Programmer from the Kit CD or download the latest version from http://www.cypress.com/?rID=38050
3. Set the device family to CY8C-PLC-LED16P, programming mode to reset and enable Auto Detection. Plug the MiniProg provided with the kit into your PC.
4. The firmware for the CY8CPLC20 Kits (CY3274, CY3275) can be found in Control Panel installation folder. The default location for this is C:\Program Files\Cypress\PLC Control Panel\. The firmware for the PLC20 Kits is PLC20_FW_5.8.hex. Load the correct file for your kits from PSoC Programmer.
5. Make sure the device is powered and then program the board. Make sure the MiniProg is attached onto header J21 on the board.
6. After the programming is complete and successful, remove the MiniProg and reset the board.
7. You can now use Section 1.3 of the PLC Control Panel User Guide to connect and use the board with the GUI.

Additionally, to increase the receiver impedance of the system, the RC filter input to the receiver can be changed to an RLC filter that is tuned to 132kHz. This is shown in the attached schematics for R52, C4, C5, and the addition of L5.

The schematics labeled “CY3273 RevStarStar Modified” have the potential improvements. The changes are circled in blue in both schematics.

Additional settings that may provide a slight improvement in performance are lowering the Baud Rate from 2400bps and increasing the Transmit Delay from 7ms. If testing with 1200bps (Modem_BPS_MASK = 0b01), the Transmit Delay must be set to >=12ms (TX_Delay != 0x00). If testing with 600bps (Modem_BPS_MASK = 0b00), the Transmit Delay must be set to >=18ms (TX_Delay = 0b10 or 0b11).

The FSK Bandwidth (Deviation) should be set to 130.4kHz - 133.3kHz (Modem_FSK_BW_MASK = '1').

If using the CY8CPLC20, setting the CPU frequency to 24MHz (Sysclk/1) will give the best performance.

If using the CY8CPLC10 device, refer to the CY8CPLC10 data sheet for more details on setting these parameters. If using the CY8CPLC20 device, refer to the Powerline Transceiver (PLT) User Module data sheet for more details on setting these parameters.

elektronikpraxis.de

For more information on our SONET and SDH PHY products, visit: cypress.com

This document is a technical reference manual for all PSoCs with a base part number of CY8C2xxxx, except for the CY8C25122 and CY8C26xxx PSoC devices. It also applies to CY7C64215, CY7C603xx,CY8CNP1xx, and CYWUSB6953.

FIT for the CY7B923 is 100FIT = 100 x 10E-9/hour.
So the MTBF = 1/FIT = 1 / 100 x 10E-9 (hours) / 24 (hours/day) / 365 (days/year) = 1141.553 years.
FIT for the Cy7B933 is 100FIT = 30x 10E-9/hour.
So the MTBF = 1/FIT = 1 / 30x 10E-9 (hours) / 24 (hours/day) / 365 (days/year) = 3805.175 years.

Please be noted the Temperature grades are different.

Frequently Asked Questions about HOTLink (www.cypress.com/cfuploads/support/app_notes/faq.pdf)


 

CY9266-F = optical fiber
CY9266-P = plastic optical fiber
CY9266-T = shielded twisted pair/twinax
CY9266-C = coaxial cable

The  CY9266 HOTLink Evaluation Board User's Guide is the complete guide to setting up and testing the various evaluation boards.  It also includes schematics and layout information for reference.

Since the Evaluation Board is Obsolete. If customer wants to design the evaluation board, they can use the gerber files attached with this KB Article for CY9266-F & CY9266-C. Gerber files for CY9266-T & CY9266-F are not available. However, if you check the schematic for all the evaluation board, only difference in all the evaluation board is the connector used for various medium.