Cypress.com: Documentation

Cypress Semiconductor Leadtime Guide

Wed, 08 May 2013 06:53:19 -0600

PSoC® Programmer 3.18

Mon, 29 Apr 2013 03:34:31 -0600

PSoC Programmer 3.18 offers the user a simple GUI that connects to programming hardware to program and configure PSoC, Clock, and configurable fixed function devices. Also provided with PSoC Programmer is the Bridge Control Panel, which can be used to debug, graph and log I2C serial communications using various supported Cypress Software. PSoC Programmer also provides a hardware layer for customers to design custom applications or use existing code examples for testing hardware and Firmware designs.

PSoC Programmer 3.18 release shall support both PSoC Creator and PSoC Designer in a single installation.

PSoC Programmer 3.18 is a minor release. For additional information regarding the installation and the new features please see the release notes in the downloads table below.

PSoC Programmer:

PSoC Programmer is a flexible, integrated programming application for programming PSoC devices. PSoC Programmer can be used with PSoC Designer and PSoC Creator to program any design onto a PSoC device. PSoC Programmer supports all PSoC 1, PSoC 3 and PSoC 5LP devices.

Supported PC Operating Systems:

PSoC Programmer currently supports the following windows operating systems:

Windows XP (32/64 bit)
Windows Vista (32/64 bit)
Windows 7 (32/64 bit)

PSoC Programmer does not support installations on Windows 8 machines. We will be adding Windows 8 support by August of 2013.

COM Hardware Layer Supported Languages:

PSoC Programmer provides the user a hardware layer with API’s to design specific applications utilizing the programmers and bridge devices. The PSoC Programmer hardware layer is fully detailed in the COM guide documentation as well as example code across the following languages: C#, C, Perl, and Python.

PSoC Programmer Secondary Software

PSoC Programmer includes additional software beyond just PSoC Programmer. For more information on that additional software please: Click Here

Third Party IDE and Programming Support

PSoC Programmer delivers a number of files and utilities that enable 3^rd party programming and debugging support for PSoC device families. In the downloads table below we include the 3^rd party user guide which will assists the user in configuring and enabling the support in the IDEs or programming utilities. The files and applications can be found in the root installation directory for each programmer installation.

Archived Software:

PSoC Programmer software is archived at the following page: Click Here

Additional Programming Links:
Prototype Programming Hardware:

PSoC 1: Click Here
PSoC 3 and PSoC 5LP: Click Here

PSoC Programmer is part of a suite of programming options and programming content available to PSoC users. For customers who are looking for more information on general programming options and information please navigate to the web page linked below. On the General Programming web page we discuss all of the available programming options for customers including Software, Schematics, Programming Specifications, and 3rd party mass programming.

www.cypress.com/go/programming

All PDF documents require at least a PDF reader installed prior to opening.

AN58825 - Cypress Powerline Communication Debugging Tools

Fri, 26 Apr 2013 06:03:07 -0600

The pervasiveness of powerlines also makes it difficult to predict the characteristics and operation of PLC products. Because of the variable quality of powerlines around the world, implementing robust communication over powerline has been an engineering challenge for years. This application note describes these challenges, explains how to identify the cause for poor PLC performance, and provides solutions to ensure successful communication.

Powerline Communication Solution Video

Wed, 24 Apr 2013 12:55:53 -0600

AN76458 - PSoC® 5LP High Voltage (120-240 VAC) Powerline Communication Solution

Thu, 04 Apr 2013 03:24:43 -0600

Powerline communication (PLC) provides a mechanism to exchange data over existing powerlines. The primary benefit of PLC over most other communication methods is that there are no infrastructure costs (i.e. no new wires) to install a PLC-enabled system.

There are generally two types of PLC systems: high-bandwidth (video, audio, and so on) and low-bandwidth (command and control). This application note describes how to implement a low-bandwidth, half-duplex PLC solution with the PSoC 5LP family of devices.

The following table indicates the PSoC devices, PSoC Creator versions, compilers, and development kits that will work with this application note project:

Project	Device		PSoC Creator Version		Development Kit CY8CKIT-xxx			Compiler
Project	Architecture	Silicon Revision	V2.1 SP1 / V2.1	V2.0	001 DVK	030/050 DVK	003/014 FTK	Keil	GCC	RVDS	MDK
AN76458.zip	PSoC 5LP	Prod	YES	NO	NO	NO	NO	N/A	YES	YES	YES

Notes:

Click on AN84741 - PSoC® 5 to PSoC 5LP Migration Guide to learn differences between PSoC 5 and PSoC 5LP.
For PSoC 5 project and related document, please download file AN76458_Archive.zip.

Projects associated with this application note can be downloaded from the 'Related Files' section below. For your convenience, we have provided projects that are compatible with the two most recent versions of PSoC Creator:

AN76458.zip is used with PSoC 5LP and PSoC Creator 2.1 SP1
AN76458_Archive.zip is used with PSoC 5 and PSoC Creator 2.1/2.1 SP1.

The project’s default settings may not be compatible with your device or kit, and you may need to change your project settings. For more information, see:

Application Note Projects Compatible with PSoC® Creator™ 2.1 SP1

PSoC® 3, PSoC 5, and PSoC 5LP AN Project File Naming Convention and Use

Product Selector Guide (PSG) - Interface

Wed, 03 Apr 2013 06:52:32 -0600

Cypress has the broadest and most flexible portfolio of backplane physical layer (PHY) devices, covering data transmission rates of 50 Mbps to 1.5 Gbps. These flexible devices are ideal for proprietary serial backplane applications.

PSoC Designer 5.3

Fri, 22 Mar 2013 16:23:20 -0600

New Features

PSoC Designer 5.3 contains a host of upgrades to make the software easier to learn for and easier to use. New features include:

Download Help

Auto-routing: Vastly simplifies wiring the connections in the chip view, making it easier to learn for beginners and quicker to use for experts. Simply shift+click on a block port and a number of glowing, golden lines will show you all the possible destinations. A second click on one of those highlighted locations and you're done! This works on analog routes as well as digital routes, block-to-block or block-to-pin.

Upgraded device catalog: It is now far quicker and easier to find the device for your project. You can filter the device list based on chip characteristics (such as pin count, package or available peripherals) or by typing in a substring of your part number. You can also save frequently used devices as favorite and see the supported user module list for any device at a glance.

Cleaner user module customization: Designer 5.3 makes it far simpler to customize user modules, providing two ways to modify their behavior. First, user modules can be copied and renamed, allowing users to change the hardware configuration or APIs. These customer user modules become part of your UM library and may be used in any PSoC Designer project. You can also export these customer user modules to a single zip file and import them into any other version of Designer 5.3 or later.

For smaller changes, we have also made it easier to change the APIs for a user module instance in your project. Simply right-click on your user module instance and you can lock it, preventing any future “Generate Project” commands from over-writing your changes.

Other ease-of-use enhancements: Cypress applications engineers have specified 12 user interface changes to make the chip view more readable and usable, including the ability to zoom with the scrollwheel. In addition, we have streamlined the project creation GUI, minimizing excess clicks. Finally, we give you the ability archive your projects.

New User Modules

PSoC Designer 5.3 contains a 8 completely new user modules. Four of the existing user modules have received significant upgrades as well.

VoltageSequencer allows you to control the ramp rates and delays between your power supplies with a simple GUI.

SMBusSlave allows your PSoC to communicate with this widely used system management protocol.

FanController will control up to four fans using hardware PWM blocks in either open loop or closed loop (with tachometer) modes.

Thermistor provides the hardware interface and software APIs to measure temperature with compensation via lookup table or the Steinhart-Hart equation.

SmartSense2X eliminates the need for tuning in your dual-channel CapSense solutions. Available for CY8C2xx45 devices.

CSD2X has been enhanced to provide support for background scanning and FMEA support, which detects faults in your system.

GasSensorAFE implements a bias circuit and transimpedance amplifier to measure the output of a 3-lead electrochemical sensor with current output.

SwitchCapConfig allows easier configuration of the programmable analog blocks such that you can quickly build amplifiers, integrators and comparators with them.

EzADC streamlines the setup of your ADCs, minimizing the possibility of erroneous clocking or sample rates.

Finally, the filter accuracy of LPF2 and BPF2 have been improved up to 5%

Installation Notes

PSoC Designer 5.3 will co-exist with your previous versions of PSoC Designer. You do not need to uninstall those previous versions, and this new version will not impact the existing ones in any way

If you need help downloading or installing, please call our support line at 1-800-541-4736 and select 8 at the voice prompt.

ImageCraft Pro Users

Last year, a new version of the ImageCraft Pro compiler was released. If you have not already done so, you must update your compiler to use it with PSoC Designer 5.3. Please download the latest version of the Pro compiler here: http://www.imagecraft.com/pub/iccv8m8c_demo.exe

PSoC Designer Frequently Asked Questions

For answers to other frequently asked questions, please click here.

PSoC Designer Archives

Looking for an old release of PSoC Designer? Please click here for major Designer releases over the past few years.

CY8CPLC20, CY8CLED16P01, CY8C29x66, CY8C27x43, CY8C24x94, CY8C24x23, CY8C24x23A, CY8C22x13, CY8C21x34, CY8C21x34B, CY8C21x23,CY7C64215, CY7C603xx, CY8CNP1xx, and CYWUSB6953 PSoC® Programmable System-on-Chip

Tue, 19 Mar 2013 06:27:17 -0600

This document is a technical reference manual for all PSoCs with a base part number of CY8C2xxxx, except for the CY8C25122 and CY8C26xxx PSoC devices. It also applies to CY7C64215, CY7C603xx,CY8CNP1xx, and CYWUSB6953.

CY3215-DK In-Circuit Emulation Development Kit

Sun, 24 Feb 2013 23:25:25 -0600

The PSoC 1 Debugger includes an In-Circuit Emulator (ICE) which consists of a base unit, USB 2.0 cable, and power supply. The base unit is connected to the host PC via the USB port. The ICE is driven by the Debugger subsystem of PSoC Designer. This software interface allows the user to run, halt, and single step the processor. It also allows the user to set complex event points. Event points can start and stop the trace memory on the ICE, as well as break the program execution. In addition to the Development Kit, different Emulation Pods are available to support the range of devices in the PSoC family. They plug into (or are soldered onto) the user's circuit board to provide the physical interface. Pods are available for low-cost expansion of the ICE-Cube capability.

The ICE-Cube also serves as a single-site device programmer via an ISSP (In-System Serial Programming) Cable and MiniEval board included in the kit. The MiniEval board is a programming and evaluation board which connects to the ICE-Cube via an ISSP Cable and allows programming of DIP devices. There are also other Programming boards available for programming other packages. The MiniEval also includes LEDs and a POT for simple evaluation and demonstration.

PSoC 1 Debugger Includes:

PSoC Designer Software CD-ROM
ICE-Cube In-Circuit Emulator
ICE Flex-Pod for CY8C29xxx Family
Backward compatibility Cat-5 Adapter
ISSP Cable
Mini-Eval Programming Board in One
USB 2.0 Cable and Blue Cat-5 Cable
110 ~ 240V Power Supply, Euro-Plug Adapter
2 CY8C29466-24PXI 28-PDIP Chip Samples

Supports following 8 bit PSoC1 (Programmable System-On Chip) families, including automotive, except CY8C25/26xxx devices.

CY8C20x34

CY8C20xx6A

CY8C21x23

CY8C21x34

CY8C22xxx/CY8C21x45

CY8C23x33

CY8C24x23A/CY8C24x33

CY8C24x94

CY8C27x43

CY8C28xxx

CY8C29x66

CY8C95xx

PSoC 1 Getting Started Debugging - Part 1 - The Hardware

PSoC 1 Getting Started Debugging - Part 2 - The PSoC Designer

Software Title	Description	Link
PSoC Designer	This kit requires PSoC Designer for development
PSoC Programmer	This kit requires PSoC Programmer for programming

Related Resources:

Datasheets:	CY8C20x34, CY8C20xx6A, CY8C21x23, CY8C21x34, CY8C22xxx/CY8C21x45, CY8C23x33, CY8C24x23A/CY8C24x33, CY8C24x94, CY8C27x43, CY8C28xxx, CY8C29x66, CY8C95xx
Other Resources: PSoC Emulator Pod Dimensions

PSoC Designer 5.0 Service Pack 6

Mon, 11 Feb 2013 04:55:20 -0600

De-emphasis of System Level Design (Express)

PSoC Designer 5.0 Service Pack 6 is the last release of PSoC Designer that supports System-Level Design (PSoC Express). PSoC Designer 5.1 and beyond will not support System Level Design.

PSoC Designer 5.0 SP6 will continue to be available for System Level Design users, and it will co-exist with future PSoC Designer 5.1 releases. However, we are not recommending System Level Design for production designs.

We suggest users to use the latest version of PSoC Designer located here:

www.cypress.com/go/psocdesigner

Installation Notes

PSoC Designer 5.0 SP6 supports Internet Explorer 6 through 8, but does not support Internet Explorer 8 Beta or Internet Explorer 9 due to compatibility issues.

To Install PSoC Designer 5.0 SP6 users must first have PSoC Programmer installed first. For the latest release of PSoC Programmer please, Click Here

PSoC Designer 5.0 PS6 was tested using Beta version of Windows 7. PSoC Designer 5.0 SP6 is not supported for Windows 7 systems.

For more information regarding PC system requirements please click on the following link:

System Requirements and Recommendations for PSoC Designer 5.0 SP6

To Install:

Shut Down any currently running instances of PSoC Designer.

If an earlier service pack of PSoC Designer 5.0 is currently installed, uninstall it. To do this please navigate to Start>Control Panel>Add or Remove Programs.

Install latest PSoC Programmer.
Install PSoC Designer 5.0 SP6 by running the installed in the downloads table below.”

Note to HI-TECH Compiler Users:

There are new devices in this release. To compile projects containing these devices with the HI-TECH compiler, you must manually update the psoc.ini file. The HI-TECH psoc.ini file is found in the HI-TECH installation folder. The default location of the psoc.ini is here:

C:\Program Files\HI-TECH Software\HCPSOC\PRO\9.61\dat\psoc.ini

The default location of the replacement psoc.ini file that adds support for the new devices is here:

C:\Program Files\Cypress\Common\CypressSemiBuildMgr\tools\psoc.ini

PSoC Programmer: The latest version of PSoC Programmer must be installed along with PSoC Designer. For the latest release please navigate to the PSoC Programmer web page: Click Here

PSoC Designer: User Guides - Click Here

PSoC Designer Archive - Click Here

Crosstalk Measurement Techniques for Multi-Channel and Multi-Rate High Speed Serial Communication Systems

Sun, 06 Jan 2013 22:51:52 -0600

Crosstalk is the effect on a signal caused by the high-speed switching of a nearby signal. This effect can manifest itself as jitter, which is the deviation of a signal's edge from its expected location. A large amount of jitter can cause a timing budget failure in a parallel system or it can cause a clock and data recovery PLL to incorrectly recover the data in a serial system.

Due to the deleterious effects of crosstalk, it is important to determine the amount of it that exists during worst case scenarios. Currently, there are no standard crosstalk measurement techniques for the serial domain. This article describes effective measurement techniques and how to determine if the amount of crosstalk is acceptable for reliable data transfer. The techniques described include measuring the device's jitter output with a wide-bandwidth oscilloscope and spectral output with a high-bandwidth spectrum analyzer. Also discussed are the configurations that yield the highest crosstalk scenarios. Real measurement data of a multi-channel, independent rate device is provided. The measurements are performed at video serial digital interface (SDI) data rates, but the measurement techniques apply to any high-speed standard. To read more on this topic, click the download link above, or visit Planet Analog.

CY3275 Programmable Low Voltage Powerline Communication Development Kit

Fri, 21 Dec 2012 00:08:01 -0600

The CY3275 Programmable Low Voltage Powerline Communication Development Kit is a tool to do system design using the ability of the CY8CPLC20 devices to transmit data up to 2400 bps over Low Voltage (12-24V AC/DC) Powerlines.

Note: Cypress recommends that a user purchases two CY3275 kits to setup a two-node PLC subsystem for evaluation and development.

Features:

User friendly PLC Control Panel application available on the kit CD-ROM
Chip power supply derived from 12V to 24V AC/DC
CY8CPLC20-OCD chip -- 100-pin TQFP on chip debug (OCD) device that allows for the quick design and debug of PLC applications
User configurable general purpose LEDs
General purpose 8-bit DIP switch
RJ45 connector to use ICE debugger
RS232 COM port for communication
Header to attach LCD card
I2C header for communicating to external devices
ISSP header for programming the CY8CPLC20 chip

Kit Contents:

CY3275 PLC LV development board
CY3275 Quick start guide
CD-ROM containing:
- Packet Test software – PLC Control Panel application
- CY8CPLC20 data sheet
- User guide
- Application note – Using CY8CPLC20 in Powerline Communication (PLC) Applications
- CY3275 board schematics
- CY3275 board Gerbers
- PSoC Designer
- PSoC Programmer
12V DC power supply
MiniProg1 for programming the CY8CPLC20 device
25 Jumper wires
LCD module
USB-I2C Bridge
Retractable USB cable
Daisy chain cable
Five CY8CPLC20-28PVXI Device Samples

Software Title	Description	Link
PSoC Designer	This kit requires PSoC Designer for development
PSoC Programmer	This kit requires PSoC Programmer for programming
Powerline Communcation	PLC Contol Panel Application

CY3274 Programmable High Voltage Powerline Communication Development Kit

Fri, 21 Dec 2012 00:06:48 -0600

The CY3274 Programmable High Voltage Powerline Communication Development Kit is a tool to do system design using the ability of the CY8CPLC20 devices to transmit data up to 2400 bps over High Voltage (110V-240V AC) Powerlines. This kit is compliant with FCC(North America) and CENELEC (Europe) standards.

Note: Cypress recommends that a user purchases two CY3274 kits to setup a two-node PLC subsystem for evaluation and development.

Features:

User friendly PLC Control Panel Application available on kit CD
CY8CPLC20-OCD – 100-pin TQFP on-chip debug (OCD) device that allows quick design and debug of a PLC application. The CY8CPLC20 100-pin TQFP is available for debug purposed only. For production quantities, CY8CPLC20 is available in 28-pin SSOP and 48-pin QFN packages.
Chip power supply derived from 90V to 264V AC
User configurable general purpose LEDs
General purpose 8-bit DIP switch
On board surge protection and isolation circuit
RJ45 connector to use ICE debugger
RS232 COM port for communication
Header to attach LCD card
I2C header for communicating to external device
ISSP header for programming the CY8CPLC20

Kit Contents:

CY3274 Quick Start Guide
CY3274 PLC HV Development Board
CDs containing:
- Packet Test Software – PLC Control Panel Application
- CY8CPLC20 Data Sheet
- Development Board User Guide
- Application Note – Using CY8CPLC20 in Powerline Communication (PLC) Applications
- CY3274 Board Schematics
- CY3274 Board Gerbers
- PSoC Designer™
- PSoC Programmer
AC Power Cable
MiniProg1 to Program CY8CPLC20
25 Jumper Wires
LCD Module
USB-I2C Bridge
Retractable USB Cable
Five CY8CPLC20-28PVXI Device Samples

Software Title	Description	Link
PSoC Designer	This kit requires PSoC Designer for development
PSoC Programmer	This kit requires PSoC Programmer for programming
Powerline Communcation	PLC Contol Panel Application

AN62792 - Updating Field Firmware With PLC

Wed, 12 Dec 2012 02:17:41 -0600

Once a system is deployed to the field, it may require updates in the future to either add features or fix issues in the application. If the systems are connected on a communication bus, updates can be performed over this bus. This application note describes the concept of field updates to systems that use Cypress’ Powerline communication (PLC) solution and explains how to write application code such that it can be remotely updated using the Powerline link. The attached code examples contain transmitter side firmware that sends out user application code over Powerline, and receiver side firmware that receives data over Powerline and reconfigures itself to the new application.

AN60685 - PLC - Interfacing the Cypress Powerline Communication Solution to CyFi Low-Power RF Module

Wed, 12 Dec 2012 02:16:06 -0600

In a majority of homes, electrical power is divided into multiple phases, with appliances distributed across these phases. When using Cypress’ PLC solution, a phase coupler is required for the Powerline packets from nodes in one phase to pass through to nodes on the other phase. This application note describes the use of Cypress’ CyFi technology to build a phase coupler that bridges the two phases using a wireless link. It describes the hardware interface between the Artaflex CyFi module and CY8CPLC20 device and the firmware code for the PLC device that accomplishes this application. The code example for the CY8CPLC20 device is attached.

AN62769 - Encrypted Data Communication Using Cypress PLC Solution

Wed, 12 Dec 2012 02:14:26 -0600

This application note describes the implementation of an AES-128 encryption algorithm for the Cypress Powerline Communication (PLC) Solution. The associated project can be used to encrypt, transmit, receive, and decrypt the data.

AN54416 - Using CY8CPLC20 in Powerline Communication (PLC) Applications

Wed, 12 Dec 2012 02:12:24 -0600

The application note also includes a spreadsheet to estimate the power consumption by CY8CPLC20 and focuses on four code examples. The first provides steps to develop an example project to communicate between two nodes on the powerline. The second discusses how to develop a UART Host interface for CY8CPLC20. The third discusses how to develop an I2C Host interface for CY8CPLC20. The fourth shows how to use CY8CPLC20 with average low power consumption of <50mW.

AN52478 - Designing an External Host Application for Cypress's Powerline Communication IC CY8CPLC10

Tue, 11 Dec 2012 20:55:59 -0600

Introduction

The Cypress PLC family is a single chip solution for powerline communication (PLC). It has a robust FSK modem with a user-friendly powerline network protocol. Cypress’s PLC solution and a simple powerline coupling circuit create low-cost communication interface using the existing power lines.

AN60934 - PLC/PowerPSoC - High Brightness LED Control with Powerline Communication Interface

Mon, 10 Dec 2012 20:41:04 -0600

Cypress’ PowerPSoC devices are highly integrated programmable power controllers that can be used in LED driver circuits to create smart LED lighting applications. In order to exploit the flexibility and intelligence of these systems, there is now a need for an advanced communication interface between the light switch and the lighting fixture. This application note describes how to add a Powerline communication interface using Cypress’ PLC solution to PowerPSoC based LED driver circuits. The attached code example for PowerPSoC interfaces with CY8CPLC10 device, receives color information sent over the Powerline, and drives up to four LED channels in the circuit.

AN55427 - Cypress Powerline Communication Board Design Analysis

Mon, 10 Dec 2012 20:38:43 -0600

Cypress’ Powerline Communication (PLC) devices (CY8CPLC10, CY8CPLC20 and CY8CLED16P01) provide a secure and reliable solution that integrates a Powerline PHY modem and Powerline optimized network protocol with CSMA into single device. These devices work with an external Powerline coupling circuit and power supply, which may need to be designed to meet certain compliance standards and specifications. This application note describes the design of these circuits and provides an overview of the commonly encountered compliance specifications along with guidelines on selection of critical components necessary to meet these specifications.

AN58717 - PLC - LED Lighting Control using Powerline Communication

Mon, 10 Dec 2012 20:37:25 -0600

The CY8CLED16P01 device provides a robust solution to implement Powerline Communication (PLC) for command and control applications with LED lighting. This application note describes the design of an intelligent lighting system using CY8CLED16P01 that allows RGB LED control over Powerline and automatic node discovery of new light fixtures connected to the Powerline network. The attached code examples contain receiver firmware (LED fixture side) that can be tested on the CY3276 or CY3277 PLC kits and master firmware (control side) that can be tested on CY3274 or CY3275 kits. Also included is a GUI that can be installed on a PC and used as master side control for RGB lighting.

In this video it is shown, how Cypress's Powerline Communication solution can be used to control LED lighting.

AN62487 - Cypress Powerline Communication (PLC) Repeater Implementation

Fri, 07 Dec 2012 07:09:08 -0600

All Powerline Communication (PLC) implementations are limited by distance between nodes and the loading on the network. Cypress has developed a repeater algorithm that can overcome this limitation and makes it possible to reach any node on the network, provided there is at least one node present in range of every other node. This enables the design of a robust PLC solution especially in conditions that require high security and reliability. This application note explains the Cypress repeater algorithm which is implemented in the attached code example on CY8CPLC20 device.

User Module Datasheet: Delta Sigma ADC Datasheet DelSig V 1.40 (CY8C29xxx, CYC8C24x94, CY7C64215, CY8CLED04/16, CY8CLED0xD, CY8CLED0xG, CY8CTST120, CY8CTMG120, CY8CTMA120, CY8C28x45, CY8CPLC20, CY8CLED16P01, CY8C28x43, CY8C28x52)

Tue, 23 Oct 2012 01:24:16 -0600

Features and Overview

6-bit resolution with 32X oversampling to 14-bit resolution with 256X oversampling
Data in unsigned or signed 2’s complement formats
Maximum sample rates of 65,500 sps at 6 bit resolution, 7812 sps at 14-bit resolution
Sinc² filter fully implemented in hardware reduces CPU overhead and anti-alias requirements
1st-Order or 2nd-Order modulator, user selectable
Input range defined by internal and external reference options
Optional synchronized PWM Output

The DelSig is an integrating converter, requiring from 32 to 256 integration cycles to generate a single output sample. Changing multiplexed inputs, invalidates the first two samples following the change.

User Module Datasheet: 8-Bit Counter Datasheet Counter8 V 2.60 (CY8C29/27/24/22/21xxx, CY8C23x33, CYWUSB6953, CY7C64215, CY8CLED02/04/08/16, CY8CLED0xD, CY8CLED0xG, CY8CTST110, CY8CTMG110, CY8CTST120, CY8CTMG120, CY8CTMA120, CY8CTMA140, CY8C21x45, CY8C22x45, CY8CTMA30xx, CY8C28x45, CY8CPLC20, CY8CLED16P01, CY8C21x12)

Mon, 22 Oct 2012 06:41:09 -0600

Features and Overview

The 8-bit general purpose counter uses one PSoC block
Source clock rates up to 48 MHz
Automatic reload of period on terminal count
Programmable pulse width
Input enables/disables continuous counter operation
Interrupt option on compare output or terminal count

The 8-Bit Counter User Module provides a down counter with a programmable period and pulse width. The clock and enable signals can be selected from any system time base or external source. Once started, the counter operates continuously and reloads its internal value from the period register upon reaching terminal count. During each clock cycle, the counter compares the current count to the value stored in the compare register. Each clock cycle, the Counter tests the count against the value of the compare register for either a “less than" or “less than or equal to" condition. The comparator output provides a logic level that may be routed to pins and to other user modules. Most PSoC device families also permit the terminal count output to be routed in the same manner.

CY8CPLC20: Powerline Communication Solution

Wed, 22 Aug 2012 02:38:22 -0600

Powerline Communication Solution

Features

Powerline Communication Solution
Powerful Harvard Architecture Processor
Programmable System Resources (PSoC® Blocks)
Flexible On-Chip Memory
Programmable Pin Configurations
Additional System Resources
Complete Development Tools
For more, see pdf

PLC Functional Overview

The CY8CPLC20 is an integrated Powerline Communication (PLC) chip with the Powerline Modem PHY and Network Protocol Stack running on the same device. Apart from the PLC core, the CY8CPLC20 also offers Cypress's revolutionary PSoC technology that enables system designers to integrate multiple functions on the same chip.

CYP15G0101DXB, CYV15G0101DXB: Single-channel HOTLink II™ Transceiver

Mon, 30 Jul 2012 05:30:50 -0600

Single-channel HOTLink II™ Transceiver

Features

Second-generation HOTLink® technology
Compliant to multiple standards
- ESCON®, DVB-ASI, fibre channel and gigabit ethernet (IEEE802.3z)
- CPRI™ compliant
- CYV15G0101DXB compliant to SMPTE 259M and SMPTE 292M
- 8B/10B encoded or 10-bit unencoded data
Single-channel transceiver operates from 195 to 1500 MBaud serial data rate
For more, see pdf

Functional Description

The CYP15G0101DXB single-channel HOTLink II™ transceiver is a point-to-point communications building block allowing the transfer of data over a high-speed serial link (optical fiber, balanced, and unbalanced copper transmission lines) at signaling speeds ranging from 195 to 1500 MBaud.

The transmit channel accepts parallel characters in an input register, encodes each character for transport, and converts it to serial data. The receive channel accepts serial data and converts it to parallel data, frames the data to character boundaries, decodes the framed characters into data and special characters, and presents these characters to an output register.

CY8CPLC10: Powerline Communication Solution

Mon, 30 Jul 2012 04:58:43 -0600

Powerline Communication Solution

Features

Integrated Powerline Modem PHY
2400 bps Frequency Shift Keying Modulation
Powerline Optimized Network Protocol
Integrates Data Link, Transport, and Network Layers
Supports Bidirectional Half-Duplex Communication
8-bit CRC Error Detection to Minimize Data Loss
I2C enabled Powerline Application Layer
Supports I2C Frequencies of 50, 100, and 400 kHz
Reference Designs for 110V to 240V AC, 12V to 24V AC/DC Powerlines
Reference Designs Comply with CENELEC EN50065-1:2001 and FCC Part 15

Functional Overview

The CY8CPLC10 is an integrated Powerline Communication chip with the Powerline Modem PHY and Powerline Network Protocol Stack. This chip provides robust communication between different nodes on a Powerline.

CYV15G0204TRB: Independent Clock HOTLink II™ Dual Serializer and Dual Reclocking Deserializer

Mon, 30 Jul 2012 04:41:03 -0600

Independent Clock HOTLink II™ Dual Serializer and Dual Reclocking Deserializer

Features

Second-generation HOTLink® technology
Compliant to SMPTE 292M and SMPTE 259M video standards
Dual-channel video serializer plus dual channel video reclocking deserializer
- 195- to 1500-Mbps serial data signaling rate
- Simultaneous operation at different signaling rates
Supports reception of either 1.485 or 1.485/1.001 Gbps data rate with the same training clock
Supports half-rate and full-rate clocking
Internal phase-locked loops (PLLs) with no external PLL components
Selectable differential PECL-compatible serial inputs
For more, see pdf

Functional Description

The CYV15G0204TRB Independent Clock HOTLink II™ Dual Serializer and Dual Reclocking Deserializer is a point-to-point or point-to-multipoint communications building block enabling transfer of data over a variety of high-speed serial links including SMPTE 292M and SMPTE 259M video applications. It supports signaling rates in the range of 195 to 1500 Mbps per serial link.

CYV15G0104TRB: Independent Clock HOTLink II™ Serializer and Reclocking Deserializer

Mon, 30 Jul 2012 04:39:06 -0600

Independent Clock HOTLink II™ Serializer and Reclocking Deserializer

Features

Second-generation HOTLink® technology
Compliant to SMPTE 292M and SMPTE 259M video standards
Single channel video serializer plus single channel video reclocking deserializer
- 195- to 1500-Mbps serial data signaling rate
- Simultaneous operation at different signaling rates
Supports reception of either 1.485 or 1.485/1.001 Gbps data rate with the same training clock
Internal phase-locked loops (PLLs) with no external PLL components
Supports half-rate and full-rate clocking
Selectable differential PECL-compatible serial inputs
For more, see pdf

Functional Description

The CYV15G0104TRB Independent Clock HOTLink II™ Serializer and Reclocking Deserializer is a point-to-point or point-to-multipoint communications building block enabling transfer of data over a variety of high-speed serial links including SMPTE 292M and SMPTE 259M video applications. It supports signaling rates in the range of 195 to 1500 Mbps per serial link.

CYP15G0403DXB: Independent Clock Quad HOTLink II™ Transceiver

Mon, 30 Jul 2012 04:33:44 -0600

Independent Clock Quad HOTLink II™ Transceiver

Features

Second-generation HOTLink® technology
Compliant to multiple standards
- ESCON, DVB-ASI, SMPTE-292M, SMPTE-259M, Fibre Channel and Gigabit Ethernet (IEEE802.3z)
- CPRI™ compliant
- 8B/10B coded data or 10 bit uncoded data
Quad channel transceiver operates from 195 to 1500 MBaud serial data rate
- Aggregate throughput of up to 12 Gbits/second
Second-generation HOTLink technology
Truly independent channels
For more, see pdf

Functional Description

The CYP(V)15G0403DXB Independent Clock Quad HOTLink II™ Transceiver is a point-to-point or point-to-multipoint communications building block enabling transfer of data over a variety of high-speed serial links like optical fiber, balanced, and unbalanced copper transmission lines. The signaling rate can be anywhere in the range of 195 to 1500 MBaud per serial link.

CYP15G0401DXB, CYV15G0401DXB: Quad HOTLink II™ Transceiver

Mon, 30 Jul 2012 04:29:31 -0600

Quad HOTLink II™ Transceiver

Features

Second-generation HOTLink® technology
Compliant to multiple standards
Quad channel transceiver operates from 195 to 1500 MBaud serial data rate
Selectable parity check/generate
Selectable multi-channel bonding options
Skew alignment support for multiple bytes of offset
Selectable input/output clocking options
MultiFrame™ Receive Framer
Synchronous LVTTL parallel interface
For more, see pdf

Functional Description

The CYP(V)15G0401DXB Quad HOTLink II™ Transceiveris a point-to-point or point-to-multipoint communications building block allowing the transfer of data over high-speed serial links (optical fiber, balanced, and unbalanced copper transmission lines) at signaling speeds ranging from 195-to-1500 MBaud per serial link.

CY7C9689A: TAXI™-compatible HOTLink Transceiver

Mon, 30 Jul 2012 04:28:32 -0600

TAXI™-compatible HOTLink® Transceiver

Features

Second-generation HOTLink® technology
AMD™ AM7968/7969 TAXIchip™-compatible
8-bit 4B/5B or 10-bit 5B/6B NRZI encoded data transport
10-bit or 12-bit NRZI pre-encoded (bypass) data transport
Synchronous TTL parallel interface
Embedded/bypassable 256-character Transmit and Receive FIFOs
50- to 200-MBaud serial signaling rate
Internal phase-locked loops (PLLs) with no external PLL components
Dual differential PECL-compatible serial inputs and outputs
For more, see pdf

Functional Description

The CY7C9689A HOTLink Transceiver is a point-to-point communications building block allowing the transfer of data over high-speed serial links (optical fiber, balanced, and unbalanced copper transmission lines) at speeds ranging between 50 and 200 MBaud. The transmit section accepts parallel data of selectable widths and converts it to serial data, while the receiver section accepts serial data and converts it to parallel data of selectable widths.

CY7B923, CY7B933: HOTLink® Transmitter/Receiver

Mon, 30 Jul 2012 04:26:15 -0600

HOTLink®Transmitter/Receiver

Features

Fibre Channel-compliant
IBM ESCON®-compliant
DVB-ASI-compliant
ATM-compliant
8B/10B-coded or 10-bit unencoded
Standard HOTLink®: 160 to 330 Mbps
High-speed HOTLink: 160 to 400 Mbps for high-speed applications
Transistor-transistor logic (TTL)-synchronous I/O
No external phase locked-loop (PLL) components
For more, see pdf

Functional Description

The CY7B923 HOTLink‚ transmitter and CY7B933 HOTLink receiver are point-to-point communications building blocks that transfer data over high-speed serial links (fiber, coax, and twisted pair). Standard HOTLink data rates range from 160 to 330 Mbps. Higher speed HOTLink is also available for high-speed applications (160 to 400 Mbits/second).

CY7C924ADX: 200 MBaud HOTLink® Transceiver

Mon, 30 Jul 2012 04:25:03 -0600

200 MBaud HOTLink(TM) Transceiver

Features

Second generation HOTLink(TM) technology
Fibre Channel and ESCON(TM) compliant 8B/10B encoder/decoder
10 or 12 bit preencoded data path (raw mode)
8 or 10 bit encoded data transport (using 8B/10B coding)
Synchronous or asynchronous TTL parallel interface
UTOPIA compatible host bus interface
Embedded/Bypassable 256-character synchronous FIFOs
Integrated support for daisy-chain and ring topologies
Domain or individual destination device addressing
For more, see pdf

Functional Description

The 200 MBaud CY7C924ADX HOTLink Transceiver is a point-to-point communications building block allowing the transfer of data over high speed serial links (optical fiber, balanced, and unbalanced copper transmission lines) at speeds ranging between 50 and 200 MBaud. The transmit section accepts parallel data of selectable width and converts it to serial data, while the receiver section accepts serial data and converts it to parallel data of selectable width. More...

CYV15G0203TB: Independent Clock Dual HOTLink II™ Serializer

Mon, 30 Jul 2012 03:14:16 -0600

Independent Clock Dual HOTLink II™ Serializer

Features

Second-generation HOTLink® technology
Compliant to SMPTE 292M and SMPTE 259M video standards
Dual-channel video serializer
- 195- to 1500-Mbps serial data signaling rate
- Simultaneous operation at different signaling rates
Supports half-rate and full-rate clocking
Internal phase-locked loops (PLLs) with no external PLL components
Redundant differential PECL-compatible serial outputs per channel
- No external bias resistors required
For more, see pdf

Functional Description

The CYV15G0203TB Independent Clock Dual HOTLink II™ Serializer is a point-to-point or point-to-multipoint communications building block enabling transfer of data over a variety of high-speed serial links including SMPTE 292M and SMPTE 259M video applications. It supports signaling rates in the range of 195 to 1500 Mbps per serial link.

CY7B952: SST™ SONET/SDH Serial Transceiver

Mon, 30 Jul 2012 02:12:02 -0600

SST™ SONET/SDH Serial Transceiver

Features

OC-3 Compliant with Bellcore and CCITT (ITU) specifications on:
- Jitter Generation (<0.01 UI)
- Jitter Transfer (<130 kHz)
- Jitter Tolerance
SONET/SDH and ATM Compliant
Compatible with IGT WAC013, IGT WAC413, and PMC-Sierra PM5343
Clock and data recovery from 51.84- or 155.52-MHz datastream
155.52-MHz clock multiplication from 19.44-MHz source
51.84-MHz clock multiplication from 6.48-MHz source
For more, see pdf

Functional Description

The SONET/SDH Serial Transceiver (SST) is used in SONET/SDH and ATM applications to recover clock and data information from a 155.52-MHz or 51.84-MHz NRZ or NRZI serial data stream and to provide differential data buffering for the Transmit side of the system.

CY7B951: Local Area Network ATM Transceiver

Mon, 30 Jul 2012 02:01:40 -0600

Local Area Network ATM Transceiver

Features

SONET/SDH and ATM Compatible
Compatible with PMC-Sierra PM5345 SUNI™
Clock and data recovery from 51.84- or 155.52-MHz datastream
155.52-MHz clock multiplication from 19.44-MHz source
51.84-MHz clock multiplication from 6.48-MHz source
±1% frequency agility
Line Receiver Inputs: No external buffering required
Differential output buffering
100K ECL compatible I/O
For more, see pdf

Functional Description

The Local Area Network ATM Transceiver is used in SONET/SDH and ATM applications to recover clock and data information from a 155.52-MHz or 51.84-MHz NRZ or NRZI serial data stream and to provide differential data buffering for the Transmit side of the system.

CYS25G0101DX: SONET OC-48 Transceiver

Mon, 30 Jul 2012 02:00:21 -0600

SONET OC-48 Transceiver

Features

SONET OC-48 operation
Bellcore and ITU jitter compliance
2.488 GBaud serial signaling rate
Multiple selectable loopback or loop through modes
Single 155.52 MHz reference clock
Transmit FIFO for flexible data interface clocking
16-bit parallel-to-serial conversion in transmit path
Serial-to-16-bit parallel conversion in receive path
Synchronous parallel interface
For more, see pdf

Functional Description

The CYS25G0101DX SONET OC-48 Transceiver is a communications building block for high speed SONET data communications. It provides complete parallel-to-serial and serial-to-parallel conversion, clock generation, and clock and data recovery operations in a single chip optimized for full SONET compliance.

CYP15G0201DXB: Dual-channel HOTLink II™ Transceiver

Fri, 27 Jul 2012 06:23:49 -0600

Dual-channel HOTLink II™ Transceiver

Features

Second-generation HOTLink® technology
Compliant to multiple standards
- ESCON, DVB-ASI, Fibre Channel and Gigabit Ethernet (IEEE802.3z)
- CPRI™ compliant
- 8-/10-B encoded or 10-bit unencoded data
Dual channel transceiver operates from 195 to 1500-MBaud serial data rate
- Aggregate throughput of 6-GBits per second
Selectable parity check/generate
Selectable dual-channel bonding option
For more, see pdf

Functional Description

The CYP15G0201DXB dual-channel HOTLink II™ transceiver is a point-to-point or point-to-multipoint communications building block allowing the transfer of data over high-speed serial links (optical fiber, balanced, and unbalanced copper transmission lines) at signaling speeds ranging from 195- to 1500-MBaud per serial link.

Powerline Communication Solutions Product Overview - Japanese

Fri, 22 Jun 2012 00:56:52 -0600

CY3250-PLC20QFN In-Circuit Emulation (ICE) Debugging Pod for 48-QFN CY8CPLC20 Powerline Communication Devices

Tue, 12 Jun 2012 16:33:01 -0600

The CY3250-PLC20QFN Kit provides debugging solution for CY8CPLC20 device. It contains 1x QFN POD (CY8CPLC20-OCD), 1x Flexcable, and 2x 48 QFN Feet.

Kit contents:

One PLC20Q Pod
One Flex cable
Two 48QFN Feet

CY3272 High Voltage Powerline Communication Evaluation Kit

Tue, 12 Jun 2012 16:32:52 -0600

Note: Cypress recommends that a user purchases two CY3272 kits to setup a two-node PLC subsystem for evaluation and development.

Features:

User friendly PLC Control Panel Application available on the kit CD
Chip power supply derived from 110V to 240V AC
On-chip powerline bridge application layer, powerline network protocol layer, and physical layer FSK modem
LED status indicators for Power, Powerline Transmit and Receive, and Band in Use.
Five-position DIP switches
- Three DIP switches for manual powerline node logical address selection
- One DIP switch to configure I2C slave address
- One DIP switch to select between external crystal and oscillator
On board surge protection and isolation circuit
Integrated Powerline Modem PHY

Kit Contents:

CY3272 Quick Start Guide
One CY3272 PLC HV Evaluation Board
CD containing:
- Packet Test Software – PLC Control Panel Application
- CY8CPLC10 Data Sheet
- CY3272 Evaluation Board User Guide
- Application Note – Using CY8CPLC10 in Powerline Communication (PLC) Applications
- CY3272 Board Schematics
- CY3272 Board Gerbers
AC Power Cable
USB-I2C Bridge
Ribbon Cable for I2C communication, External Reset, and Powering External Board
Retractable USB Cable
Five CY8CPLC10-28PVXI Device Samples

Software Title	Description	Link
PSoC Designer	This kit requires PSoC Designer for development
PSoC Programmer	This kit requires PSoC Programmer for programming
Powerline Communcation	PLC Contol Panel Application

CY3250-PLC20NQ In-Circuit Emulation (ICE) Debugging Pod for 28-SSOP CY8CPLC20 Powerline Communication Devices

Tue, 12 Jun 2012 16:32:48 -0600

The CY3250-PLC20NQ Kit provides debugging solution for CY8CPLC20 device. It contains 1x SSOP POD (CY8CPLC20-OCD), 1x FlexCable, and 2x 28 SSOP Feet.

Kit content:

One PLC20 Pod
One Flex cable
Two 28SSOP Feet
One 28 Pin Mask

CY3273 Low Voltage Powerline Communication Evaluation Kit

Tue, 12 Jun 2012 16:32:39 -0600

Note: Cypress recommends that a user purchases two CY3273 kits to setup a two-node PLC subsystem for evaluation and development.

Features:

Chip power supply derived from 12V to 24V AC/DC
On-chip powerline bridge application layer, powerline network protocol layer, and physical layer FSK modem
LED status indicators for Power, Powerline Transmit and Receive, and Band in Use
Five-position DIP switches
- Three DIP switches for node logical address selection
- One DIP switch to configure node I2C addressing mode
- One DIP switch to select between the external crystal and oscillator
Integrated Powerline Modem PHY

Kit Contents:

CY3273 Quick Start Guide
CY3273 PLC LV Evaluation Board
CD containing:
- CY8CPLC10 Data Sheet
- Packet Test Software – PLC Control Panel Application
- CY3273 Evaluation Board User Guide
- Application Note – Using CY8CPLC10 in Powerline Communication (PLC) Applications
- CY3273 Board Schematics
- CY3273 Board Gerbers
12V Power Supply
Cable to Create LV Daisy Chain
USB-I2C Bridge
Five Wire Ribbon Cable for I2C communication, External Reset, and Powering External Board
Retractable USB Cable
Five CY8CPLC10-28PVXI Device Samples

Software Title	Description	Link
PSoC Designer	This kit requires PSoC Designer for development
PSoC Programmer	This kit requires PSoC Programmer for programming
Powerline Communcation	PLC Contol Panel Application

CY3277 Programmable Low Voltage Powerline Communication Development Kit with EZ-Color

Tue, 12 Jun 2012 16:32:24 -0600

The CY3277 kit is obsolete as of June 22, 2011. If you are looking for a low voltage (12V – 24V AC/DC) Powerline Communication kit please see: CY3273 kit here: www.cypress.com/go/CY3273 and CY3275 kit here: www.cypress.com/go/CY3275

Please contact Cypress customer support if you have any questions. Call 1-800-541-4736 and select 8 or email us at customercare@cypress.com

Cypress Powerline Communication Control Panel GUI

Tue, 12 Jun 2012 16:32:00 -0600

The Cypress Powerline Communication Control Panel GUI application provides the user with the ability to control the Powerline Network nodes through a Personal Computer.

CY3276 Programmable High Voltage Powerline Communication Development Kit with EZ-Color

Tue, 12 Jun 2012 16:31:41 -0600

The CY3276 kit is obsolete as of June 22, 2011. If you are looking for a high voltage (110V – 240V AC) Powerline Communication kit please see: CY3272 kit here: www.cypress.com/go/CY3272 and CY3274 kit here: www.cypress.com/go/CY3274

Please contact Cypress customer support if you have any questions. Call 1-800-541-4736 and select 8 or email us at customercare@cypress.com

CY3250-PLC20QFN-POD Replacement ICE Pod for 48-QFN CY8CPLC20 Powerline Communication Devices

Tue, 12 Jun 2012 16:31:07 -0600

The CY3250-PLC20QFN-POD - only kit contains 2x QFN PODS (CY8CPLC20-OCD).

CY3250-PLC20NQ-POD Replacement ICE Pod for 28-SSOP CY8CPLC20 Powerline Communication Devices

Tue, 12 Jun 2012 16:30:48 -0600

The CY3250-PLC20NQ-POD - only kit contains 2x SSOP PODS (CY8CPLC20-OCD)

Cypress Parts Baking Condition Information

Thu, 24 May 2012 01:42:22 -0600

Cypress products require baking before board mounting, if any of the following criteria are met:

Humidity indicator card (HIC) is equal or greater than 10% when read at 23ºC +/- 5 ºC
After removal from bag, parts are not mounted on board within 168 hours (in equal or less 30 ºC /60%RH)
If they have not been stored in equal or less than 10% RH (as required on the MSL label)

If baking is required, devices may be baked for 24 hours at 125 ºC +5/-0 ºC.

Please note that the above baking condition is applicable for MSL-3 and MSL-5 parts only. Also, please ensure that only metal tubes or bakeable trays with rating of greater than 125 ºC must be used for baking. MSL 1 parts do not require baking.

Cypress recommends the customers to follow the Shelf Life condition of the parts as stipulated on the MSL label which can be found on the Moisture Barrier Bag (MBB) bag. A separate article on the Shelf Life of Cypress products is available at the following link: http://www.cypress.com/?id=4&rID=62201

Country of Origin (COO) Information

Thu, 24 May 2012 00:59:17 -0600

The Country of Origin (COO) of any Cypress product can be found on the Shipment Label (Manufacturing Label, Intermediate Label, and Outer Label). COO can also be found on the top mark of the unit for products that do not have space limitations (i.e., certain package dimensions). For smaller packages, COO is not marked on the top of the package, and can be found on the Shipment Label.

Please see below illustrative example for COO information on label and top mark.

This example is for part number CYDMX128A16-65BVXIT, where Philippines is the COO. Philippines is designed by its 2 letter code “PH.”

COO on Manufacturing Label:

COO on Intermediate Label:

COO on Outer Box Label:

COO on Top Mark:

Country of Origin Codes/Abbreviations:

Abbreviations	Full Country Name
CHI	CHINA
HKG	HONGKONG
IDI	INDIA
IND	INDONESIA
JAP	JAPAN
KOR	KOREA
MAL	MALAYSIA
PHI	PHILIPPINES
SNG	SINGAPORE
THA	THAILAND
TWN	TAIWAN
USA	UNITED STATES OF AMERICA
GER	GERMANY
ISR	ISRAEL

CYV15G0404DX-VIDEO

Mon, 23 Apr 2012 05:48:23 -0600

The Quad Independent Channel HOTLink II(TM)CYV15G0404DXB Video Demonstration (Demo) Board is a full-fledged serial digital video reference platform that demonstrates the HOTLink II video physical layers (PHYs) interfacing to industry-standard cable drivers and equalizers. Upstream processing of the video data is performed using on-board Altera Cyclone FPGAs. The board also has a flexible clocking architecture with automatic rate detection that allows the board to pass video traffic in multiple formats.

The Independent Channel HOTLink II devices are capable of simultaneously operating each channel at a different data rate. The CYV15G0404DXB has the additional capability of performing independent reclocking on a per-channel basis.

The Independent Channel HOTLink II CYV15G0404DXB Video Demo Board demonstrates:

The ability of the Cypress family of transceivers to pass serial digital video at signaling rates from 270 Mb/s to 1485 Mb/s
The independent channel functionality of the applicable devices
The ability to use a HOTLink II transceiver with an FPGA for auto rate detection and clock reconfiguration
The ability to perform reclocking in the HOTLink II CYV15G0404DXB device
The flexible configuration abilities of Cypress Microsystems' PSoC(TM) microcontroller
The use of Cypress EZ-USB FX2T USB microcontroller for video data and in-system configuration applications
On-board FPGAs that generate and receive different video test patterns.

Although this board uses the CYV15G0404DXB device, the same board can be used as an evaluation vehicle for any device in the HOTLink II Independent Channel family of devices. Please refer to the data sheets for descriptions of the HOTLink II Independent Channel family of devices.

Recommended Reflow for Cypress Parts Information

Fri, 20 Apr 2012 05:04:46 -0600

Please see below Cypress Reflow Profile. Cypress’s Reflow Profile is compliant with Jedec J-STD-020D.1. You may also download this file by following the link http://www.cypress.com/?rID=51561

Example on how to get the Peak package body temperature is shown below.

Reflow Profiles (per Jedec J-STD-020D.1)

Profile Feature	Sn-Pb Eutectic Assembly	Pb-Free Assembly

Preheat/Soak
Temperature Min (Tsmin)	100 °C	150 °C
Temperature Max (Tsmax)	150 °C	200 °C
Time (ts) from (Tsmin to Tsmax)	60-120 seconds	60-120 seconds
Ramp-up rate (TL to Tp)	3 °C/second max.	3 °C/second max.
Liquidous temperature (TL)	183 °C	217 °C
Time (tL) maintained above TL	60-150 seconds	60-150 seconds
Peak package body temperature (Tp)	For users Tp must not exceed the Classification temp in Table 2A. For suppliers Tp must equal or exceed the Classification temp in Table 2A	For users Tp must not exceed the Classification temp in Table 2B. For suppliers Tp must equal or exceed the Classification temp in Table 2B
Time (tp)* within 5 °C of the specified classification temperature (Tc), see Table 2a & 2B	20* seconds	30* seconds
Figure 5-1. J-STD-020D.1
Ramp-down rate (Tp to TL)	6 °C/second max.	6 °C/second max.
Time 25 °C to peak temperature	6 minutes max.	8 minutes max.
* Tolerance for peak profile temperature (Tp) is defined as a supplier minimum and a user maximum .

Table 2A
SnPb Eutectic Process - Classification Temperatures (Tc)

Package Thickness

Volume mm3

<350

Volume mm3

>=350

<2.5 mm

235 °C

220 °C

>=2.5 mm

220 °C

Table 2B
Pb-Free Process -Classification Temperatures (Tc)

Package Thickness	Volume mm3 <350	Volume mm3 350 - 2000	Volume mm3 >2000
<1.6 mm	260 °C	260 °C	260 °C
1.6 mm - 2.5 mm	260 °C	250 °C	245 °C
>2.5 mm	250 °C	245 °C	245 °C

Note:

Peak Temperature tolerance is +5/-0 °C of Classification Temp (Tc).
All temperatures refer to topside of the package, measured on the package body surface.
Package volume excludes external terminals (e.g., balls, bumps, lands, leads) and/or nonintegral heat sinks.

For example:
To be able to get the reflow profile of a part, we need to know first the Package dimension or volume.

MPN: CY7C65620-56LTXC
Package: QFN56, Pb-Free Part
Package Dimension: 8x8x1.0mm
Package Volume: 64mm³
Package Thickness: 1.0mm

You can get package dimension on the datasheet’s Package Diagram.

Since the part is a Pb Free Part, Table 2B should be used. Based on this table, is the package volume is <350 mm³and the package thickness is <1.6mm, Peak Temperature = 260 °C

If the part number is SnPb Part, Table 2a is applicable.

Cypress' Parts Shelf Life Condition Information

Thu, 19 Apr 2012 06:27:08 -0600

Cypress’s standard shelf life for MSL 3 products is 12 months from the bag seal date, at conditions of <40°C and <90% Relative Humidity (R.H.)

For customer use conditions that require storage beyond this duration, Cypress advises that the packing, storage, excursion control and sample evaluation (HIC verification and other testing) recommendations outlined in JEDEC standard JEP160 be strictly followed to minimize storage/age related degradation.

Cypress’s MSL 1 products do not require special storage conditions provided they are maintained at conditions equal to or less than 30°C / 85% RH.

As a best practice, Cypress also recommends that reflow profiles for board mount be developed based on specific process needs and board designs. Cypress also recommends that for optimal profiles, the customer not only review conditions provided by the solder paste manufacturer, but also adhere to the conditions specified in industry standard IPC/JEDEC J-STD-020.

You can also download Cypress’ official statement regarding Shelf Life Condition on the link: http://www.cypress.com/?rID=62134. A current copy of JEP160 is attached on this letter for your reference.

Is PAL22V10B a valid Cypress device?

Wed, 18 Apr 2012 12:46:46 -0600

The PAL22V10B is not a CY part number. The equivalent CY part number for PAL22V10B is PALC22V10-xx.

Please note all our CPLD/PLD families of devices are Obsolete.

Windows7 driver support for CYUSBISR programming cable.

Wed, 18 Apr 2012 12:26:12 -0600

No, the ISR 4.0.1 programming software does not have the driver support for the Windows7 platform. As can be seen in the attached release notes , the Operating Systems supported are Windows 98 / Windows 98 Second Edition, Windows ME, Windows NT 4.0.1 Service Pack 5, Windows 2000 Service Pack 1 or later and Windows XP.

Further, due to resource / expertise constraints, we currently do not have plans to include the driver support for the Windows platform.

Please be informed our entire CPLD products are Obsolete.

PLC - IBIS

Fri, 16 Mar 2012 07:26:38 -0600

The zip file contains the following IBIS models:

cy8cplc10_28_ssop_50v.ibs
cy8cplc20_28_ssop_50v.ibs
cy8cplc20_48_qfn_50v.ibs
cy8cplc20_ocd_tqfp_50v.ibs

CYV15G0101DX-VIDEO

Wed, 08 Feb 2012 00:21:09 -0600

This development kit is no longer available. This web page has been left in place for informational purposes only.

The HOTLink II™ transceiver is a point-to-point or point-to-multipoint communications building block allowing the transfer of data over high-speed serial links at signaling speeds ranging from 195 to 1500 MBaud.

The frequency agility of the HOTLink II transceiver enables its application in various data and video transmission standards. The HOTLink II transceiver supports serial video transmission that complies with Digital Video Broadcasting (DVB-ASI) and Society of Motion Picture Television Engineers (SMPTE) standards. DVB is a widely accepted standard for digital video transmission, especially in the video-on-demand market. SMPTE has in turn developed several standards for serial and parallel video transmission at different speeds and formats.

The HOTLink II video evaluation board demonstrates the ability of the Cypress HOTLink II family of devices to pass video at signaling rates of up to 360 Mbps. It also demonstrates the functionality of Delta39K™ CPLD as an ideal CPLD solution for SMPTE applications, the flexible clocking abilities of CyClocksRT™, and the use of EZ-USB FX2™ USB microcontroller for video data and in-system configuration applications.

Some of the features include:

User-friendly GUI
Video transport at multiple data rates of 270 and 360 Mbps
Supports DVB-ASI (270 Mbps)
SMPTE scrambler/descrambler embedded in Delta39K CPLD
USB port to establish board configuration
High-speed USB FX2 to configure Delta39K CPLD and programmable clock
Flexible clocking abilities of CyClocksRT
External and internal loop back capability for SMPTE and DVB-ASI
Delta39K CPLD, reconfigurable via the USB or ISR(T) Header or from the boot memory
12V DC supply with on-board voltage regulator to prevent noise transfer from external power sources
On-board serial equalizer and cable driver
LED status indicators

The software GUI is available for download from the Cypress website at the following location: CYV15G0101DXB Video Evaluation Board software

Additional information about this evaluation board can be found in the user's guide: HOTLink II™ Video Evaluation Board User's Guide

CYP15G0101DX-EVAL

Wed, 08 Feb 2012 00:15:38 -0600

The CYP15G0101DXB single-channel HOTLink II(TM) transceiver is a point-to-point or point-to-multipoint communications building block allowing the transfer of data over high-speed serial links at signaling speeds ranging from 195 to 1500 MBaud.

The evaluation board allows users to become familiar with the functionality of the CYP15G0101DXB and perform simple tests. Some of the features include:

Selectable serial interface
- SMA connectors
- Small form factor pluggable (SFP) optical module cages
Single 3.3V power supply
Power-on indicator (LED)
JTAG interface
Selectable clock options
- Onboard crystal
- SMA connectors for external REFCLK
LFI indicator (LED)
Switches for latch control
Selectable static control inputs

These features allow many evaluation modes including:

BIST internal loopback
BIST external loopback
Parallel data in and parallel data out mode

More information about this evaluation board can be found in the User's Guide: CYP15G0101DXB Evaluation Board User's Guide

CYS25G0101DX-EVAL

Wed, 08 Feb 2012 00:10:52 -0600

Cypress's CYS25G0101DX SONET OC-48 Transceiver is a communications building block for high-speed SONET data communications. It provides complete parallel-to-serial and serial-to-parallel conversions, clock generation, and clock and data recovery operations in a single chip, optimized for full SONET/SDH compliance.

The CYS25G0101DX Evaluation Board is designed for evaluating as well as understanding the characteristics of the CYS25G0101DX SONET/SDH Transceiver. The evaluation board provides the following advantages:

Flexible and easy to operate
On-board Cypress 120-pin thin quad flat pack (TQFP) CYS25G0101DX SONET/SDH Transceiver
Supports LVPECL or HSTL interfaces
Dip switch for selecting different diagnostic modes
Four diagnostic modes - Diagnostic Loopback mode, Line Loopback mode, Analog Line Loopback mode, and factory TEST0 (Parallel Line Loopback) mode
LFI and FIFO_ERR LEDs
Onboard oscillator for the REFCLK
Supports external clock source for the REFCLK
16-bit RxD, 16-bit TxD bus, RXCLK, TXCLKI, TXCLKO interface
SMA connectors for CML input and output buffers
Separate Banana Jacks for all voltage sources for measuring current individually

For more information, please refer to the user's guide: CYS25G0101DX Evaluation Board User's Guide

CYP15G0401DX-EVAL

Tue, 07 Feb 2012 23:47:06 -0600

This development kit is no longer available. This web page has been left in place for informational purposes only.

The CYP15G0401DXB Quad HOTLink II™ transceiver is a point-to-point or point-to-multipoint communications building block allowing the transfer of data over high-speed serial links (optical fiber, balanced and unbalanced copper transmission lines) at signaling speeds ranging from 195 to 1500 MBaud per serial link. The multiple channels in each device may be combined to allow transport of wide buses across significant distances with minimal concern for offsets in clock phase or link delay.

The evaluation board allows users to become familiar with the functionality of the CYP15G0401DXB. Some of the features include:

Selectable serial interfaces
- SMA connectors
- Small form factor pluggable (SFP) optical module cages
Single 3.3V power supply
Power-on indicator (LED)
JTAG interface
Selectable clock options
- Onboard crystal (125 MHz)
- SMA connectors for external REFCLK
LFI indicators (LED)
Switches for latch control
Selectable static control inputs
Selectable channel bonding options

These features allow many evaluation modes including:

BIST internal loopback
BIST external loopback
Parallel in - parallel out mode (encoded)
Parallel in - parallel out mode (unencoded)
Parallel in - serial out mode (testing the transmit side)
Different clock source (i.e., internal vs. external, different frequency mode, etc.)

More information about this evaluation board can be found in the following guide: CYP15G0401DXB Evaluation Board User's Guide

installing USBisr on Windows XP x64

Thu, 26 Jan 2012 10:16:34 -0600

No, the ISR 4.0.1 programming software does not have the Driver support for the windows XP 64 bit. The Operating Systems supported are Windows 98 / Windows 98 Second Edition, Windows ME, Windows NT 4.0.1 Service Pack 5, Windows 2000 Service Pack 1 or later and Windows XP (32 bit). Further, due to resource / expertise constraints, we currently do not have plans to include the driver support for 64 bit platform. Also, our CPLD's are not recommended for new design. The driver for Windows XP operating system is located in C:\Windows\system32\drivers\ezusb.sys. Please try to bind the driver manually and check if the USBISR cable is detected.

Please be noted our entire Cypress CPLD product are Obsolete and not recommended for new design and development. For more information on CPLD product, please visit our webpage: http://www.cypress.com/go/cpld

Difference between SVF and STAPL file formats

Thu, 26 Jan 2012 10:15:53 -0600

User can select file format SVF or STAPL depending on their requirment. The Serial Vector File (SVF) format is a widely adopted standard method of describing a set of high-level IEEE 1149.1 bus operations, consisting of scan operations and movements between different stable states on the IEEE 1149.1 state diagram. SVF is an alternative to STAPL, and is more suitable in certain applications, such as the embedded programming of devices. ISR 4.0 supports the creations of SVF files in order to provide compatibility with third party tools and users that have adopted this Dependent/Chain Independent modes when using the New Device Wizard. When the Composer is run, an ISR SVF ASCII text file is created to describe the operation and device selected.

design software for CY7C343 devices

Thu, 26 Jan 2012 10:14:54 -0600

The part CY7C343 belong to MAX340 Family of devices. It was supported in Warp Software. We have stopped distributing Warp because our license agreement with Aldec simulator, an integral part of Warp, has expired. The last version of the software was Warp6.3, which supported MAX340 (c341, c342, c343, c344, c346 (84 & 100 pin) devices).

Programming CY7C374U

Thu, 26 Jan 2012 10:14:02 -0600

The CY7C374U device is programmed through some of its I/O pins. The CY7C374i is programmed through its JTAG interface and is ISR (In-system Re-programmable) capable. It is just a die revision and is same as CY7C374 in form, fit and function. Unfortunately, we do not have the datasheet for the U part. However, you can refer to datasheet for the the Cy7C374.

The CY7C374U is an old obsolete device and was limited in production. This device is not recommended for new design.

Please be noted our entire Cypress CPLD product are Obsolete and not recommended for new design and development. For more information on CPLD product, please visit our webpage: http://www.cypress.com/go/cpld

BSDL model for CY37128VP84-83YMB

Thu, 26 Jan 2012 10:10:08 -0600

BSDL file for the part is available on our website at the link: http://www.cypress.com/?mpn=CY37128VP84-83JI

Data retention life for CY7C343B-25HC

Thu, 26 Jan 2012 10:08:40 -0600

The Data Retention of CY7C343B-25HC devices is guaranteed to be 10 years under normal operating conditions. The retention of the data is independent of whether the device was in storage or was in use. In general we support the lifetime of all parts at 10 years. We use the Arrhenius model to calculate data retention. To qualify our parts for the 10-year lifetime, the CPLDs must pass High Temperature Operating Life (HTOL) tests before the part can be considered qualified. For data retention, we test the devices at 125 deg C for 1000 hours and/or 150 deg. C for 500 hours.

Program & Verify for svf file

Thu, 26 Jan 2012 09:46:01 -0600

The SVF file format has the single option "Program & Verify" by default. There is no other option to select. You will have to click "Next" to proceed with further operation. "Program and Verify" is selected by default even if it shows grayed out.

You will not be able to select only program or verify.

Reading back Jedec file

Thu, 26 Jan 2012 09:45:07 -0600

Once you open the ISR software in "Help" menu you can find "Read Operation" description.To read back the Jedec file from the device use the Operation: "Read Device" in ISR software.This operation reads the contents of the device and writes a JEDEC file.When a read operation is specified in the Edit Playlist dialog box, the user needs to specify where the data should be stored in the “Output Filename” column when reading from an Ultra37000 device, this output filename should end in a .jed extention. Please be noted device programming cable will be required to read back the device.

Programming Flash370i family of devices

Thu, 26 Jan 2012 09:44:04 -0600

The Flash370i family of devices were supported by programming cable : ISRPCCABLE, this cable is supported only with ISR2.2 software. This software can be downloaded from our website. The ISRPCCABLE is Obsolete and no replacement is available.

CPLD checksum

Thu, 26 Jan 2012 09:41:01 -0600

Checksum is a value calculated, by the programmer, from the data stream used to program the device. There is no specific checksum for a device, as this value is computed by the programmer from the code used to program the CPLD. Therefore, it will depend on the software algorithm used by the programmer. The checksum will change once the code is modified. This stored checksum value is compared to the one computed when the data is read back from the programmed device. If the two do not match, a checksum error is reported idicating that there was a programming error.

SPLDs for New Designs

Sun, 01 Jan 2012 17:29:11 -0600

We recommend using the Ultra37000 CPLD devices for new designs. The Ultra37000 CPLDs is a different family of products with a higher density. The Ultra37000 CPLDs will require PCB changes and the source code to be retargeted and recompiled. The datasheet for the Ultra37000 devices is available on our website.

Use of the CEO/A2 in a Single Chip Configuration

Sun, 01 Jan 2012 17:17:23 -0600

The /CEO output of any CY3LV drives the /CE input of the next CY3LV in a cascaded chain of EEPROMs. This is an output that will stay HIGH until the entire EEPROM is read again. This same pin duals as the A2 input pin when used in conjuction with each individual PROM's /SER_EN signal. When /SER_EN is asserted low, A2 will be used to select which PROM to be programmed.

The /CEO, A2 should be left open when configuring the 39K when using only one EEPROM.

Functionality Problem with Ultra37000V CPLD Despite Passing Simulation

Sun, 01 Jan 2012 17:13:48 -0600

Please check the power supply voltages. There are instances where a 5V power supply has been used on a 3.3V (V) part, and this resulted in functionality issues on a few pins. This difference in power supplies can also result in failed daisy chain errors when programming.

Please be noted our entire Cypress CPLD product are Obsolete and not recommended for new design and development. For more information on CPLD product, please visit our webpage:http://www.cypress.com/go/cpld

Hysteresis on Input of Cypress Quantum38K CPLDs

Sun, 01 Jan 2012 17:10:13 -0600

Quantum38K CPLD's do not have explicit input hysteresis, but the effect of the bus hold circuit (if enabled) on the input may look like hysteresis. Bus hold can be approximated as a current source. As the input rises, bus hold will continue to pull low. Eventually, the input reaches the bus hold trip point and the output changes state. That means it switches from pulling low to pulling high. This change in direction of the bushold current together with the output impedance of the driver will cause a "jump" in the input voltage which looks a lot like hysteresis.

Are military parts vacuum sealed?

Sun, 01 Jan 2012 17:04:03 -0600

Unfortunately, these devices are not vacuum sealed. They are, however, hermetically sealed, but there is atmospheric pressure inside the device. For more information on which device are available in a hermetically sealed package, please read the Knowledge Base article entitled "Hermetically Sealed Ultra 37000 Availability".

Issues with Pins Locked to a Certain Level Despite Simulation

Sun, 01 Jan 2012 16:59:53 -0600

Issues of this kind usually result from issues that are not related to the software code. This situation often occurs when the device was improperly programmed. Please check the length of the ISR cable being used to program the device. If the cable and ribbon put together is longer than 6 feet, the problem may be in the fact that the PC is unable to drive a coherent signal over the length of the cable. Another thing to check for is to see if the JTAGen pin is toggled properly after programming has completed.

Why tS > tSPT for Ultra 37000 CPLDs

Sun, 01 Jan 2012 16:47:41 -0600

Setup is the amount of time before the clock edge when the data must be static. Consider the two input paths in two arbitrary devices with made-up timing numbers -- for the "tSPT" device, the data delay is 4ns and the clock delay is 4ns. For the "tS" device, the data delay is 4ns and the clock delay is 2ns, since the clock tree is faster than the datapath. Now assume that both devices have the same register internally, and this register has a "micro-tS" of 0ns. That is, the setup-time referenced to the internal inputs of the register (not the external pins) is 0ns. When you take into account the delays for the signals from the pins, you end up with a ts of 0ns for the tspt case, and 2ns for the ts case. The skew between the two clock and data signals due to the clock tree is responsible. Since the clock gets to the register faster for ts, you've lengthened the setup window. The opposite, of course, will happen for hold time. Further, note that "true" setup + hold externally referenced is a constant determined by the register. The reason it is not reported as a constant in the datasheet is due to the fact that a negative hold time tends to confuse people. Therefore, it is reported as 0 to prevent confusion.

Please be noted our entire Cypress CPLD product are Obsolete and not recommended for new design and development. For more information on CPLD product, please visit our webpage: http://www.cypress.com/go/cpld

Thermal Information for Cypress Flash370i CPLDs

Sun, 01 Jan 2012 16:47:40 -0600

The Thermal information is located in the table that follows:

Device	Package Type	Theta JA (C/W)	Theta JC (C/W)
CY7C371i	44-Lead Thin Plastic Quad Flatpack	62	17
CY7C371i	44-Lead Plastic Leaded Chip Carrier	54	18
CY7C372i	44-Lead Plastic Leaded Chip Carrier	38	16
CY7C372i	44-Pin Thin Quad Flatpack	56	6
CY7C373i	84-Lead Plastic Leaded Chip Carrier	35	16
CY7C373i	100-Pin Thin Quad Flatpack	50	7
CY7C374i	84-Lead Plastic Leaded Chip Carrier	35	16
CY7C374i	100-Pin Thin Quad Flat Pack	29	5
CY7C374i	84-Pin Ceramic Leaded Chip Carrier	50	7
CY7C375i	160-Lead Thin Quad Flatpack	34	7
CY7C375i	160-Pin Grid Array	24	3
CY7C375i	160-Pin Ceramic Quad Flatpack	30	5

Differences Between Revision A and Revision B of Ultra 37000 CPLDs

Sun, 01 Jan 2012 16:43:45 -0600

Revision B changed the manufacturing process slightly to improve the characteristics of the revision A silicon. These changes are relatively minor and will not acutely affect device performance. The changes are listed below.

- improved device speed
- improved ESD tolerance
- improved yield
- improved latch-up performance

Please be noted our entire Cypress CPLD product are Obsolete and not recommended for new design and development. For more information on CPLD product, please visit our webpage: http://www.cypress.com/go/cpld

ISR Failures during Flash 370 and Flash 370i Programming

Sun, 01 Jan 2012 16:42:45 -0600

The Flash JAM driver uses a high performance counter located on all PC motherboards, and assumes that it counts at a certain rate. However, if the counter does not perform to standards, about 1.2 million per second, there may be timing problems when programming these devices. The best thing to do is to perform the procedure on a different machine.

Please be noted our entire Cypress CPLD product are Obsolete and not recommended for new design and development. For more information on CPLD product, please visit our webpage: http://www.cypress.com/go/cpld

Boundary Scan on Flash370 and Flash370i CPLDs

Sun, 01 Jan 2012 16:38:03 -0600

Unfortunately, there is no way to perform a boundary scan on these devices. Cypress started to incorporate this feature on the Ultra37000 family of devices.

Transparent Latches in Ultra 37000 CPLDs

Sun, 01 Jan 2012 16:30:57 -0600

Unfortunately, the CPLD's registers are unable to implement a true transparent latch. However, the same function is usually achieved by implementing a negative-edge latch.

Please be noted our entire Cypress CPLD product are Obsolete and not recommended for new design and development. For more information on CPLD product, please visit our webpage: http://www.cypress.com/go/cpld.

Security Bit in the Ultra 37000

Sun, 01 Jan 2012 16:17:56 -0600

The security bit is a programmable field in the Ultra 37000 family of devices that prevents certain operations from occuring to the device once programmed. When such a bit is set, there is no way to recover the design from a programmed device and all operations on the device are prohibited, save erasing the device and reprogramming.

Within the device itself, a '0' within the fuse map of the device indicates a "secure" device. However, the JEDEC standard states that a '1' indicates security. As a result, the ISR software flips this bit when programming the device. As a default, the designs generated from Warp are unsecure.

Please be noted our entire Cypress CPLD product are Obsolete and not recommended for new design and development. For more information on CPLD product, please visit our webpage: http://www.cypress.com/go/cpld

Do MAX340 EPLDs Have Internal Oscillators?

Sun, 01 Jan 2012 15:59:42 -0600

Unfortunately, the MAX340 series of devices do not have internal oscillators. This feature can be found on the Cypress Delta39K family of CPLDs.

Please be noted our entire Cypress CPLD product are Obsolete and not recommended for new design and development. For more information on CPLD product, please visit our webpage: http://www.cypress.com/go/cpld

In Aldec-HDL is there any way to name remerged signals other than VBUS#

Sun, 01 Jan 2012 15:24:36 -0600

Unfortunately, the "VBUS" designation is default. There is no way to rename these signals.

However, signal buses naturally contain the group signal name as the merged signal name. For instance, a signal bus defined in HDL code as std_logic_vector will automatically be collapsable to view all signals as a bus (hex or decimal output).

Please be noted our entire Cypress CPLD product are Obsolete and not recommended for new design and development. For more information on CPLD product, please visit our webpage: http://www.cypress.com/go/cpld

Creating Bi-Directional Signals in Warp

Sun, 01 Jan 2012 15:19:01 -0600

The following VHDL code provides an example on how to create and use a bi-directional signal in Warp.

library IEEE;
use ieee.std_logic_1164.all;

ENTITY tristate IS
PORT (clk : in std_logic; -- clk input
a : in std_logic; -- input to drive b
out_enable : in std_logic; -- input to set state of b (input or output)
b : inout std_logic; -- bidirectional
c : out std_logic); -- c always receives b
END tristate;

ARCHITECTURE behav OF tristate IS
signal tempx : std_logic;

BEGIN

-- First, note that 'Z' can NOT be assigned to an output inside of a clocked process.
-- when targeting Cypress PLD's that do not have registered OE's (370, 370i, 37k)
-- So, we assign the 'Z' to the output asynchronously

b <= tempx when out_enable = '1' else 'Z';

-- assign b to c
c <= b;

outputs: process (clk)
begin
if (clk'event and clk ='1') then
tempx <= a;
end if;
end process;

END behav;
--Placing the oe control inside of the process makes the output enable
--dependant on a clock signal. The error generated by Warp is:
--Error 461 "Output-enable not supported beneath a WAIT"

This code shows that the output of the signal is set to high Z when not in use.

For simulation, the only thing to consider when simulating a bi-directional signal is that the strength of the stimulator for that particular signal must be set to drive and NOT override. Setting the stimulator to override will cause the waveform to simulate improperly.

Please be noted our entire Cypress CPLD and Warp product are Obsolete and not recommended for new design and development. For more information on CPLD product, please visit our webpage: http://www.cypress.com/go/cpld

Is there an application to convert a .stp or .hex file into a C code array?

Sun, 01 Jan 2012 15:01:20 -0600

Unfortunately, there is no application that is capable of doing this.

Please be noted our entire Cypress CPLD product are Obsolete and not recommended for new design and development. For more information on CPLD product, please visit our webpage: http://www.cypress.com/go/cpld

Registering Warp

Sun, 01 Jan 2012 14:57:31 -0600

Unfortunately, registering Warp online is not possible as that area of the website has been removed. Please contact our distributor, Future Electronics for all queries on buying or registering Warp.

Please be noted our entire Cypress CPLD and Warp product are Obsolete and not recommended for new design and development. For more information on CPLD product, please visit our webpage: http://www.cypress.com/go/cpld

Why does the ISR software not show a particular revision of Delta 39K devices?

Sun, 01 Jan 2012 14:42:52 -0600

This was a bug in previous versions of ISR, and has been fixed. The workaround for this can be achieved through the following procedure:

1. Exit from ISR if it is open.

2. Go to the "My Computer" icon and select "Search..." or "Find...". The command name varies in the menu based on the OS you are running.

3. Search for the file cydev.bpf.

4. Delete the files found.

5. Re-run the ISR program.

Please be noted our entire Cypress CPLD product are Obsolete and not recommended for new design and development. For more information on CPLD product, please visit our webpage: http://www.cypress.com/go/cpld

BSDL model of CY37032P44 device

Sun, 01 Jan 2012 13:26:39 -0600

BSDL model of CY37032P44 device is attached 'BSDL 32P44A.txt' in txt format.

Who should I get in touch with to obtain pricing and availability information?

Fri, 30 Dec 2011 13:58:55 -0600

For pricing and availability information, please contact your local Cypress sales representative. For the nearest location near you, visit www.cypress.com/contacts/offices.

Avoiding overflow of RX FIFO in the CY7C924ADX and CY7C9689A.

Wed, 07 Dec 2011 03:13:52 -0600

There are only two ways to prevent receiver FIFO overflow problems:

1. Ensure that the read clock for the receive FIFO is always faster than the received character rate
2. Discard sufficient characters so that the effective character rate is less than the FIFO read clock rate. (Use the discard policy configuration).

Useful Link:
200-MBaud HOTLink Transceiver

Characteristics and considerations for HOTLink jitter

Wed, 07 Dec 2011 01:15:43 -0600

The phase-locked loops (PLLs) in the HOTLink Transmitter and Receiver act like low-pass filters to jitter that is embedded in the data or clock signal source. For the transmitter, the signal source is the CKW input. Any jitter that appears at CKW is passed unattenuated if it has frequency components below the natural frequency of the PLL filter (approximately 500 kHz). Spectral components above the natural frequency are attenuated at about 6 dB/octave. Frequency components that fall very near the natural frequency of the filter are slightly amplified (approximately 0.5 dB). These are the normal characteristics of a Type-2, second-order PLL filter. When the transmitter is fed by a low jitter clock source, typical output jitter will be less than 20 ps RMS and 200 ps peak-to-peak. It is possible to measure significantly more jitter than that which is actually present if the complete system is not well understood. A few hundred millivolts of Vcc noise, while insignificant to the logic of a normal system board, will add imaginary jitter to the measured output. This imaginary jitter appears because a single ended oscilloscope sees the waveform as if it were measured against a fixed threshold, while the differential serial interface sees Vcc noise as a common mode signal to be ignored (e.g. 100 mV of Vcc noise could create 100-200 ps of imaginary jitter). Likewise, the normal method of measuring peak-to-peak jitter, an infinite persistence scope trace, will show larger jitter than that contributed by the HOTLink Transmitter. Low frequency jitter (wander) in the oscillator, scope trigger, temperature, and voltage related delay variations will all contribute to the width of the stored scope trace. Delay variations include TTL threshold variations that cause apparent delay variation (e.g. 100 mV of TTL threshold change can cause 100-200 ps of apparent jitter).

The signal source for the receiver is the serial data stream and, like the transmitter, it passes the spectral components of received jitter that fall below the natural frequency of its filter (approximately 300 kHz to 1000 kHz depending on actual data transition density being received). Frequency components above the natural frequency are attenuated and there is minor jitter peaking at about the natural frequency of the PLL. Since the characteristics of the input jitter determine the jitter content on the receiver CKR output (the only place to directly measure Rx-PLL jitter) it is somewhat difficult to predict the output jitter. Maximum CKR output jitter is less than 200 ps (peak-to-peak) when the receiver is tracking normal data (BIST data is typical) that exhibits maximum tolerable peak-to-peak jitter. Jitter from normal data is wide-bandwidth, has significant high-frequency content, and can have peak-to-peak amplitude of up to about 90% of a bit time. If the serial data contains a significant low frequency jitter component (typical in crystal oscillators and some pulse generators) the output jitter measured on the CKR pin could be much higher. Jitter measurements at the receiver output can be more misleading than those associated with the transmitter serial outputs, since all measurements are made on TTL outputs. The jitter characteristics mentioned here affect system performance in the following ways. Any low-frequency jitter (below the bandwidth of either transmitter or receiver PLL) is treated as wander. For purposes of the PLLs, wander (usually caused by low-frequency power supply variations or temperature fluctuations within the timing ICs) does not reduce the system timing margins and does not contribute to bit-error-rate. Wander can affect system timing at interfaces where the transmitter clock source is used to clock information received from a receiver tracking data from another clock source. The variation in clock frequencies may violate set-up and hold times, the exact problems usually solved by FIFO memories in typical communication systems. High-frequency jitter (at or above the natural frequency of the PLL filters) may contribute to BER. High-frequency jitter can be caused by the clock source, media transfer characteristics, or external noise. The recovered internal bit-rate clock does not track high-frequency jitter above the PLL natural frequency. High-frequency jitter, therefore, may cause a bit edge to move into the receiver sampling window causing the bit to be erroneously sampled (a bit error).

A suitable clock source should be selected with the above effects in mind. The only clock source guaranteed to offer the required stability and high-frequency specifications is a crystal oscillator. High-frequency jitter is minimal, and low-frequency wander is usually small and very low frequency. Frequency accuracy is easily guaranteed by mechanical means, and high accuracy devices are relatively low cost. Free-running resistor-capacitor (RC) oscillators, logic gate ring oscillators, or inductor-capacitor (LC) oscillators include too much high-frequency jitter, experience wide frequency variation as a function of process and environmental conditions and thus are unsuitable for this application. See the "HOTLink Jitter Characteristics" application note for more information.

Useful Link:
HOTLink Transmitter/Receiver

HOTLink Jitter Characteristics-AN1161

Data stream is always valid when RVS is LOW

Wed, 07 Dec 2011 01:08:07 -0600

NO. The detection of RVS = HIGH is a sufficient condition to declare that the received character is INVALID. It indicates that the presently received character did not follow one or more of the encoding rules for an 8B/10B coded data stream. However, the detection of RVS = LOW is NOT a sufficient condition to declare that the received character is VALID. It still requires validation against the data packet format used to ensure that the data is OK. If for example, one bit of the character transmitted is corrupted, but it turns out that the corrupted data falls into one of the valid data characters in the encoding table, the receiver will interpret this as normal data instead of asserting RVS = HIGH to indicate error.

Useful Link:
HOTLink Transmitter/Receiver

Cannot connect to the PLC device error in the PLC Control Panel

Mon, 05 Dec 2011 11:34:41 -0600

Check for the following when this error is displayed by the Control Panel

Is any other Cypress software running that has connected to the USBI2C bridge? The USBI2C Bridge can only be connected to using one program at a time. Examples of other software that uses the bridge are PSoC Programmer and Bridge Control Panel. Close all the open Cypress programs and restart the PLC Control Panel.
Is the USBI2C bridge connect to the PC and does it appear in the USB-I2C bridges section of the Control Panel as shown below. If it does not appear please uninstall and reinstall the latest build of PSoC Programmer and restart the PLC Control Panel application. A green LED should power on the USBI2C bridge once it is successfully connected to the PC.

Is the bridge connected to the I2C header of the board? For the CY3272, the I2C header is J5. For the CY3273, the I2C header is J8. For the CY3274 and CY3275, the I2C header is J15. A picture showing the correct connection is shown below for the CY3273 kit. It is similar for all the other kits.

Is the correct I2C bridge selected? If you have two bridges connected to the PC as shown below, choose the one that is connected to the board you are trying to connect to. Use the Blink GRN LED button to blink the led on the USBI2C bridge that is currently selected.

Is the correct I2C slave address selected? For the CY3272/3, the I2C address can be configured by the I2C DIP (S1) switch on the board. When this switch is in the off position, the I2C address is 0x01 and when it is on, the I2C address is 0x7A. For the CY3274/5, the USB-I2C bridge can only connect to FSK Modem + Network Modem + I2C Bridge option of the PLT User Module. The I2C slave address is a configurable property of the User Module. The user module property value is in decimal form, while the Control Panel GUI I2C address is in hexadecimal form. For example if the user module I2C Slave Address property is set to 15, the Control Panel should connect to the PLC Address “0f” by selecting the “Other” option.
If the “USBI2C options” is set to “+5V PWR”, make sure a jumper is placed on the USBI2C bridge at the J1 position and make sure there is no jumper on the PWR jumper header of the PLC board. When the connect button is clicked, a red LED on the USBI2C bridge should turn on. If it is set to “EXT. PWR” place a jumper on the PWR jumper header of the PLC board. The red LED on the USBI2C bridge should begin to blink.

Note that the USBI2C bridge can connect with any I2C Clock Rate.

If the connection is successful, the GUI should display a PLC #0 Connected in the status bar as shown in the picture below.

PLT and CYFISNP user modules resource conflict

Mon, 05 Dec 2011 11:16:20 -0600

To use the PLT and CYFISNP user modules on the same device, you must use dynamic reconfiguration, which means the user modules will be loaded at different times based on the need for using one form of communication or the other. For a description of how to use dynamic reconfiguration, refer to the application note AN2104 “PSoC Dynamic Reconfiguration”.

Band in Use timeout during transmission on the powerline

Mon, 05 Dec 2011 11:15:32 -0600

The BIU threshold is a configurable value in the Threshold Noise register [Offset 0x30]. The default value of this register is 87 dBuV [0x03]. If noise or a signal is present on the powerline with a frequency near the carrier frequency of ~132kHz and an amplitude greater than 87 dBuV at the FSK_IN pin, the BIU will trigger and prevent transmission. The BIU threshold can be configured as each powerline has different line characteristics.

The available values can be found in the CY8CPLC10 data sheet or the PLT User Module datasheet in PSoC Designer. If you are using PSoC Designer, the value can be configured using the PLT User Module property Noise Level Threshold. Note that this property is only available for the “FSK Modem” and “FSK Modem + Network Stack” selection. The “FSK Modem + Network Stack + I2C Bridge” selection and the CY8CPLC10 device require an external host to change this value by writing to the Threshold Noise register.

The BIU can also be disabled completely by setting the Disable BIU bit in the PLC Mode register [Offset 0x05].

Jumper usage on the PLC evaluation and development kits

Mon, 05 Dec 2011 11:12:10 -0600

There are six jumpers on the CY3272 and CY3273 boards in the orientation as shown below.

Figure1.CY3272 jumper layout

Figure2. CY3273 jumper layout

The PWR jumper is used to connect pin V on the I2C header to Vdd. This can be used to power a microcontroller board of the supply of the CY3272 or CY3273 board.
The INT pin (it is not a true jumper) is the pin closest to the INT silk screen on the board. It is connected to the HOST_INT pin of the CY8CPLC10 chip. This pin can be used to connect to the host microcontroller interrupt pin to enable interrupt based processing. The polarity and status updates that trigger the interrupt can be controlled in the INT_ENABLE register (offset 0x00) in the memory map. The other part of the jumper is connected to GND and can be used to while probing the digital signals on the board.
The RES jumper is used to connect pin R on the I2C header to XRES. If the host microcontroller board can reset the CY8CPLC10 chip by momentarily forcing this pin to Vdd.
The SCL and SDA jumpers are used to pull up pins D [I2C data] and C [I2C clock] to Vdd. Note that for the CY3272 board, the jumpers have to be placed laterally as shown in Figure 1 above. These need not be connected to connect to boards such as the CY3240 USB-I2C bridge as it already has pull ups for I2C but should be there for boards such as the PSoCEval1.
The CLK jumper is used to check the external clock frequency between P1 [0] and P1 [1].

The CY3274 and CY3275 have only four out of the six jumpers present on the evaluation boards as shown in the figures below. The descriptions for these jumpers are similar to the ones above (XRES is similar to RES). Note that on the CY3274 and CY3276 the jumpers JP1 is for PWR, JP5 is for XRES, JP3 is for SCL and JP4 is for SDA.

Figure3. CY3275 jumper layout

Figure4. CY3274 jumper layout

Physical Addressing vs. Logical Addressing for Powerline Communication

Mon, 05 Dec 2011 11:08:11 -0600

Physical addressing uses a 64-bit address to represent each node on the powerline. Every PLC device has a unique 64-bit address. This is useful when initializing a system because the nodes do not have unique logical addresses on power up. However, it is inefficient to use physical addressing all the time because it requires 16 bytes when transmitting a packet from a physical source address to a physical destination address. This will increase latency and reduce throughput.
Logical addressing uses either an 8-bit or 16-bit (extended) address to represent each node on the Powerline. This addressing mode uses only 2-4 bytes for transmitting a packet and therefore, has a much lower latency and higher throughput.

When there are multiple independent networks sharing the same Powerline grid, it is important to bind the nodes (e.g. slave host only processes messages from the master’s source address, or the nodes use a unique key in the payload or the additional byte in the extended address to define the network).