Cypress.com: Documentation

USB High Speed Host - KBA87002

Fri, 12 Apr 2013 07:30:59 -0600

Answer: Cypress offers an embedded high-speed (HS) On-The-Go (OTG) host in the FX3, Bay, and Benicia products. The term "embedded host" means that it works only with a targeted list of peripherals. The embedded host in FX3, Bay, and Benicia supports Mass Storage Class (MSC) and Human Interface Device (HID) device class natively. For all other device classes, a pass-through mode is enabled such that an applications processor that is connected to FX3, Bay, or Benicia can support any required device class.

LINUX Drivers for USB Devices - KBA87010

Fri, 12 Apr 2013 05:17:36 -0600

Answer: Cypress does not directly provide drivers. In the LINUX community, there are examples of driving EZ-USB FX1, FX2, and FX3. We do provide an application note AN73609, which shows how to interface the FX2LP and FX3 to these drivers.

WINDOWS Drivers for Cypress USB Products - KBA87000

Fri, 12 Apr 2013 05:04:47 -0600

Answer: Yes. Click on this link for SuiteUSB 3.4, which is a set of USB development tools for Visual Studio. You can use these tools to create .NET Windows applications for all Cypress USB 2.0 families.

CE58786 - Implementing Pin Specific Interrupts in enCoRe™ II / enCoRe II LV

Fri, 22 Mar 2013 00:40:44 -0600

This Code Example demonstrates how to use the dedicated pin GPIO interrupt INT0. When a switch connected to the port pin corresponding to INT0 (P0.2) is pressed, an LED connected to P1.3 glows. This Code Example was developed for CY7C60123-PVXC.

CY4623 Mouse Reference Design

Tue, 15 Jan 2013 05:32:27 -0600

The CY4623 reference design kit offers a complete production-ready solution for a USB or PS/2 optical mouse. The design showcases the revolutionary new enCoRe II device family for an overall reduction in system cost.

Features

Agilent ADNS-2620 optical sensor
USB or PS/2 support, may be customized for full combi support
No external transistors or pull-ups
3 buttons with I/O for 6-10 more
Scroll wheel
CY7C638xx device family
USB 2.0 specification-compliant
WHQL-compliant

Kit Components

Evaluation 3-button combi optical mouse
PS/2 adapter
"MiniProg" programmer and USB receptacle programming adapter
Firmware source and object code
Complete hardware design files
Comprehensive design documentation

A modified version of the CY4623supporting the PixArt PAN3101 sensor is also available.

CY3664-EXT Rev Development Kit

Tue, 15 Jan 2013 03:27:57 -0600

Overview:

This part requires CY3655-DK (which includes CY3655-EXT & CY3215-DK) or CY3215-DK

The CY3664 extension kit is intended for any customer who already has the ICE-Cube emulation kit (CY3215-DK). This kit supports all items specific to enCoRe III devices in the CY7C64215 families without having to pay for a duplicate in-circuit-emulator. The CY3664-EXT Development Kit includes:

Application Board (1)
MiniProg USB Programmer (1)
CY7C64215-28PVXC samples (3)
CY7C63823-56LFXC samples (3)
Standard-A to Mini-B USB cable (1)
Jumper wire kit (1)
PSoC Designer Software CD-ROM (1)
12V power supply (1)
Cover Letter
Release Notes
Getting Started

CY3655-EXT Extension Kit

Tue, 15 Jan 2013 03:05:46 -0600

Overview:

This part requires CY3655-DK (which includes CY3655-EXT & CY3215-DK) or CY3215-DK

The CY3655 extension kit is intended for any customer who already has the ICE-Cube emulation kit (CY3215-DK). This kit provides all items specific to the enCoRe II and Wireless enCoRe II (CY7C601xx and CYC602xx) families without having to pay for a duplicate in-circuit-emulator.

The CY3655-EXT Development Kit includes:

Application Board
enCoRe II emulation pod (CY3655-PODUSB)
Wireless enCoRe II emulation pod (CY3655-PODWIR)
Collection of PDIP feet
- 40-PDIP foot
- 18-PDIP foot
- 16-PDIP foot
Modular Programmer (CY3216)
- Programmer base board
- 3 matrix cards for various packages
5-pin to USB-A-receptacle programming adaptor (CY3655-PLG)
Device samples
- (2) CY7C63913-PXC
- (2) CY7C60123-PXC
- (2) CY7C60223-PXC
Standard USB cable
PS/2 male-to-male cable
PSoC Designer Software CD-ROM
Various printed documents

CY7C63310, CY7C638xx: enCoRe™ II Low Speed USB Peripheral Controller

Wed, 28 Nov 2012 06:30:02 -0600

enCoRe™ II Low Speed USB Peripheral Controller

Features

USB 2.0-USB-IF certified (TID # 40000085)
enCoRe™ II USB - ‘enhanced Component Reduction’
- Crystalless oscillator with support for an external clock. The internal oscillator eliminates the need for an external crystal or resonator.
- Two internal 3.3 V regulators and an internal USB Pull-up resistor
- Configurable I/O for real world interface without external components
USB Specification compliance
- Conforms to USB Specification, Version 2.0
- Conforms to USB HID Specification, Version 1.1
- Supports one low speed USB device address
For more, see pdf

Introduction

Cypress has reinvented its leadership position in the low speed USB market with a new family of innovative microcontrollers. Introducing enCoRe II USB - ‘enhanced Component Reduction.’ Cypress has leveraged its design expertise in USB solutions to advance its family of low speed USB microcontrollers, which enable peripheral developers to design new products with a minimum number of components.

AN6075 - enCoRe™ II USB Bootloader

Tue, 16 Oct 2012 03:41:24 -0600

Allowing end users to upgrade their products for bug fixes or feature enhancements is a desirable feature from both a marketing and engineering perspective. enCoRe™ II, as a Flash-based microcontroller, has the potential to allow firmware upgrades in the field via the USB protocol. However, firmware assistance is required to manage the download of the new code from the USB host, re-program the Flash, and re-start operation under the new code. This application note describes a bootloader for the low-speed USB enCoRe II device to implement this capability.

Can you read out an M8 OTP once it's programmed? Assuming the answer is YES how do I prevent this?

Mon, 08 Oct 2012 01:26:47 -0600

On the Hi-Lo programmer GUI (Cystart.exe), there is a "Security" button. Once this fuse is blown, the code will be protected. When it is read, only FFh's are shown.

Cypress USB Solutions

Thu, 30 Aug 2012 01:19:26 -0600

AN023 - USB Compliance Testing Overview

Fri, 10 Aug 2012 03:24:37 -0600

One of the secrets to USB’s success has been the compliance-testing program. This program verifies that your device meets the specification and works well with other USB devices.

Mac OS X: Getting Started with USB - AN1105

Fri, 10 Aug 2012 02:57:09 -0600

Developing USB drivers for Mac OS X is completely different than developing USB drivers on Mac OS 9. This application notes describe how to develop USB driver for Mac OS X. Include introducing the kernel of Mac OS X and driver architecture. Some useful example codes also be attached.

User Module Datasheet: USB DEVICE DATASHEET, USB V 1.90 (CY7C639/638/633XX, CYRF69XX3)

Thu, 02 Aug 2012 05:42:06 -0600

Features and Overview

USB device interface driver
Support for interrupt and control transfer types
Setup wizard for easy and accurate descriptor generation
Runtime support for descriptor set selection
Optional USB string descriptors
Optional HID class support
Optional PS/2 support for USB-PS/2 combination devices (Note: PS/2 is not supported on CYRF69xx3 devices)

Functional Description

The USB Device User Module provides a USB Chapter 9 compliant device framework. The user module provides a low level driver for the control endpoint that decodes and dispatches requests from the USB host. The user module supports the HID Class. USB descriptors can be configured with the USB Setup Wizard.

CY7C63413C, CY7C63513C, CY7C63613C: Low-Speed High I/O, 1.5-Mbps USB Controller

Mon, 30 Jul 2012 02:25:58 -0600

Low-Speed High I/O, 1.5-Mbps USB Controller

Features

Low-cost solution for low-speed applications with high I/O requirements such as keyboards, keyboards with integrated pointing device, gamepads, and many others
USB Specification Compliance
- Conforms to USB Specification, Versions 1.1 and 2.0
- Conforms to USB HID Specification, Version 1.1
- Supports 1 device address and 3 data endpoints
- Integrated USB transceiver
8-bit RISC microcontroller
- Harvard architecture
- 6-MHz external ceramic resonator
For more, see pdf

Functional Overview

The CY7C63413C/513C/613C are 8-bit RISC One Time Programmable (OTP) microcontrollers. The instruction set has been optimized specifically for USB operations, although the microcontrollers can be used for a variety of non-USB embedded applications.

The CY7C63413C/513C features 32 General-Purpose I/O (GPIO) pins to support USB and other applications. The I/O pins are grouped into four ports (Port 0 to 3) where each port can be configured as inputs with internal pull-ups, open drain outputs, or traditional CMOS outputs.

AN15482 - Using Capture Timers in enCoRe™ II and enCoRe II LV Devices

Mon, 23 Jul 2012 04:44:52 -0600

This application note describes the features and architecture of the enCoRe™ II capture timer module and explains its use. Assembly language and C language code examples are also provided as PSoC Designer™ projects with this application note.

AN6062 - enCoRe to enCoRe II Conversion

Mon, 23 Jul 2012 04:43:27 -0600

Having sold hundreds of millions of units, the Cypress enCoRe low-speed USB microcontroller family is the most successful USB device in the industry, but it has not seen an update since its introduction in 2000. In order to keep up with the demands for increasing product functionality and decreasing system cost, Cypress has released the enCoRe II. This Application Note is targeted at developers who are familiar with the enCoRe devices, and who wish to migrate to the next generation enCoRe II. This highlights the differences between the products that require attention during the migration, and also provides guidance on how to use some of the enCoRe II features. Although it discusses some hardware issues, its emphasis is on firmware.

AN52970 - Windows Hardware Quality Labs (WHQL) Signing Procedure for Customer Modified Cypress USB Driver Files

Tue, 10 Jul 2012 01:52:03 -0600

Application Note "AN52970 - Windows Hardware Quality Labs (WHQL) Signing Procedure for Customer Modified Cypress USB Driver Files" not available now.

Please review knowledge base article in this link to learn about "Windows Hardware Certification Process for Customer Modified Cypress USB Driver Files".

Windows Hardware Certification Process for Customer Modified Cypress USB Driver Files

Tue, 10 Jul 2012 00:57:27 -0600

Cypress supplies a digitally signed driver with its reference designs and development kits. The signature on the driver files is invalidated when customer-specific information (VID, PID, strings, and so on) are added to the driver files. The following steps allow customers to obtain the ‘Certified for Windows’ logo digital signature by passing Microsoft’s Windows® Hardware Quality Labs (WHQL) testing for customer-modified Cypress USB driver files. More information on the logo programs offered by Microsoft (including cost, debug procedure etc.) is available at http://msdn.microsoft.com/en-us/windows/hardware/gg463010 and http://msdn.microsoft.com/en-us/windows/hardware/gg487530

Driver Signing for Windows Hardware Certification

A complete beginning-to-end walkthrough of how to digitally sign drivers is provided by Microsoft and is available at http://www.microsoft.com/whdc/winlogo/drvsign/kmcs_walkthrough.mspx

FAQs

Question 1: I get the following error while binding my device to CyUSB.sys in Windows 7/Vista 64-bit environment, “Windows encountered a problem installing the driver software for your device” or usage of CyUSB.sys in Vista 64-bit operating system gives Code 39 error (Code 52 in the case of Windows 7). What do these errors mean? How can they be resolved?

Answer: CyUSB.sys downloaded through our website is an unsigned driver. This error reported while an unsigned driver used in 64-bit operating systems in normal mode. Following are the steps to disable driver signature enforcement in 64-bit operating system:

a) During boot-up press F8.

b) In the list of options that appear select “Disable driver signature enforcement”.

This should resolve the issues.

Note: In the case of Windows Vista 64-bit operating system the error message is “Windows cannot load the device driver for this hardware. The driver may be corrupted or missing. (Code 39)”. In the case of Windows 7 64-bit operating system it is "Windows cannot verify the digital signature for the drivers required for this device. A recent hardware or software change might have installed a file that is signed incorrectly or damaged, or that might be malicious software from an unknown source. (Code 52)".

Question 2: What is the signing procedure when script files are used?

Answer:When script files are used, the Inf file should contain both VID/PID combinations while signing the driver. The procedure for signing the procedure is the same as that for regular drivers. The script file (.spt file) will need to be shipped along with the Inf/Sys files.

What do I need to develop a product based on the CY7C630xx or CY7C631xx?

Tue, 24 Apr 2012 00:34:58 -0600

To help you in your product development with the CY7C630xx/CY7C631xx, you will need to utilize the CY3650 Developers Kit. This development kit may be hard to find.

For programming the chip there are many programming vendors that support this chip. The Hi-Lo programmer (Cypress ID: CY3649) is what we use in house. The CY3649 is the Hi-Lo programmer. Please review the Hi-Lo Programmer Application Note. These chips are One Time Programmable (OTP) chips. The programmer does not have the capabilities of the development kit. You do need to have the development kit to develop your firmware. We offer programming support with the easy-to-use Hi-Lo Programming System.

The development kit comes with sample firmware and collateral which may be downloaded at the following URL:
CY3650 Software

The CY3650 Development Kit includes a CY3650 USB development board, a power supply, a USB cable, an RS-232 9-pin to 9-pin cable, and a 9-pin to 25-pin adapter.

Note1: The CY7C630xx/CY7C631xx are not recommended for new designs. Instead we recommend using the enCoRe II. It has advanced features such as the internal oscillator (no external 6MHz clock), internal 3.3V regulator (for pulling up D- as required by the USB spec), Combi USB/PS/2 interface supported, wake-up circuit (no external RC wake up circuit needed), SPI compatible, Low voltage reset, each GPIO is independently configurable in different modes,... For more info on this part, please click on enCoRe II USB.

For pricing and availability information, please visit the following URL's:
Sales Representatives
Online Store

What are the CY7C630xx and CY7C631xx parts?

Wed, 18 Apr 2012 03:10:21 -0600

Please note that these devices are obsolete. Instead we offer enhanced features in enCoRe II Low speed USB controllers.

The CY7C630/1XXA is a family of 8-bit RISC One Time Programmable (OTP) microcontrollers with a built-in 1.5-Mbps USB SerialInterface Engine (SIE). It is a low-cost solution for low-speed USB peripherals such as a mouse, joysticks, and gamepads. It conforms to the USB 1.5 Mbps Specification, Version 1.1. It supports 1 device address and 2 endpoints (1 control endpoint and 1 data endpoint). The internal memory is organized as:

- 2 Kbytes of EPROM (CY7C63000A, CY7C63100A)
- 4 Kbytes of EPROM (CY7C63001A, CY7C63101A)
- 128 bytes of RAM

It has up to 8 I/O pins with LED drive capability. It is available in space saving and low cost 20-pin PDIP, 20-pin SOIC, 24-pin SOIC, and 24-pin QSOP packages. You may review the datasheet for more details:
CY7C630xx/CY7C631xx Datasheet.

Note1: The CY7C630xx/CY7C631xx are not recommended for new designs. Instead we recommend using the enCoRe. It has advanced features such as the internal oscillator (no external 6MHz clock), internal 3.3V regulator (for pulling up D- as required by the USB spec), Combi USB/PS/2 interface supported, wake-up circuit (no external RC wake up circuit needed), SPI compatible, Low voltage reset, each GPIO is independently configurable in different modes,... For more info on this part, please click on:
enCoRe USB

For pricing and availability information, please visit the following URL's:
Sales Representatives.
Online Store.

QTP 114401: 24 QFN (4x4x0.6mm)/ 32/36 QFN(5x5x0.6mm) NiPdAu, Cu-Pd Wire MSL3, 260°C Reflow ASEK-Taiwan (G)

Mon, 02 Apr 2012 01:24:45 -0600

2.4 GHz Green Button Certified Media Center Remote Control

Tue, 20 Mar 2012 02:49:11 -0600

This is a design for a 2.4 GHz Media Center Remote Control using Cypress's patented DSSS-based WirelessUSB(TM) technology and Gyration's patented motion-sensing gyroscope. Gyration's design is the only method of cursor control approved by Microsoft for a Green Button-certified XP MCE remote control. This design also includes IR emitter and detector for home theater device control and IR learning. The remote control provides superior ease-of-use and flexibility combined with excellent interference immunity properties resulting in ultimate user experience.

Gyration Contact

Marc Harris, Marketing Manager
mharris@gyration.com
408-973-7052

Hardware Description

QTP 102902: 18/20/24/28-Lead SOIC (300 mils) NiPdAu, MSL3, 260°C Reflow CML-RA

Mon, 12 Mar 2012 04:35:52 -0600

Programmer for CY7C630xx/CY7C631xx

Mon, 12 Mar 2012 00:27:16 -0600

To program the 630xx/631xx chips we recommend using Cypress' CY3649 Hi Lo Programmer - CY3649

The Programming Software, CYASM, for the Hi-Lo programmer may also be downloaded from the previous link. There are 3rd party programmers that you may also use but we do not have support for these programmers. The following is a chart detailing everything you will need to program a particular product using the CY3649:

Part Number	Package	Adapter	Matrix Card
CY7C63001-PC	PDIP	none	none
CY7C63001A-SC	SOIC	AS-28-28-03S-6-GANG	none
CY7C63101A-QC	QSOP	130-5304-06	none
CY7C63101A-SC	SOIC	AS-28-28-03S-6-GANG	none

Note: An SOIC-to-DIP flow-through adapter (p/n AS-28-28-03S-6-GANG) is available from Emulation Technologies. You can contact Emulation Technologies by calling 1-800-ADAPTER.

A QSOP-to-DIP flow-through adapter (p/n 130-5304-06) is available from Adapters.com. You can contact Adapters.com by calling 1-408-855-8527.

For availability and pricing please visit the following URL's: Sales Representatives.

Online Store.

CY7C632XX Parts

Wed, 07 Mar 2012 03:42:35 -0600

The CY7C632xx parts are part of of our enCoRe USB Low-speed USB Peripheral Controller family. They are flexible and cost-effective solutions for low-speed and/or PS/2 applications such as mice, gamepads, joysticks and others.

These chips conform to the USB Specification, Version 2.0 and the USB HID Specification, Version 1.1. They support 1 low-speed USB device address and 1 control endpoint and 1 data endpoint. They are an enhancement over our older USB products because it has an internal oscillator which eliminates the need for an external crystal or resonator.

The interface can auto-configure to operate as PS/2 or USB without the need for external components to switch between modes. It has an internal 3.3V regulator for USB pull-up resistor and configurable GPIOs for real-world interface without external components. It has up to 10 versatile General Purpose I/O (GPIO) pins, which are individually configurable.

The Internal memory consists of 96 bytes of RAM and 3 Kbytes of EPROM. The CY7C63221A is available in DIE form or 16-pin PDIP package and the CY7C63231 is available in 18-pin SOIC and 18-pin PDIP.

For more information please refer to the following link:
CY7C632xx Datasheet.

Note: For availability and pricing please visit the following URL's:
Sales Representatives.
Online Store.

CYSTART - Current Version

Tue, 06 Mar 2012 01:18:06 -0600

The current version of CYSTART.EXE is version 2.02 and can be found at the following URL:

http://www.cypress.com/support/dev_kit.cfm?objectid=8D5836CC-494E-4771-BEA547049F8FDEDE&tid=EF028E39-2658-41C0-828715F47620AEE8

Errors or blank Check fails while using CY3649 Hi-Lo programmer

Tue, 06 Mar 2012 01:16:03 -0600

There has been some issues with the power adapter used for programming on the CY3649. A couple things that can be checked:- Voltage setting on the adapter, and check if it outputs 9V DC with 1A current (center negative). If these settings are correct and the programmer still doesn't work right, please check using another power adapter.

Also, the socket adapters that are used with the programmers were designed for Pb devices (Leaded devices). Although, using these with the Pb-Free parts shouldn't cause any issues, some parts may require a Pb-Free adapter due to potential electrical and/or mechanical contact issues. Attached is the link to BP Microsystems (one of our leading 3rd party programmers) Pb-Free device adapter issues -> BP'>http://www.bpmicro.com/Web/helpandsupport.nsf/WebKeys/BPM-67VMQF?openDocument&Cat=Issue">BP Microsystems Pb-Free socket adapters

The above should be checked for after making sure the preliminary steps (like choosing the right adapter, placement, matirx cards etc) are take care of.

Programming CY7C630xx or CY7C631xx?

Tue, 06 Mar 2012 01:09:57 -0600

For programming the 630xx/631xx, there are many programming vendors that support this chip. The Hi-Lo programmer (Cypress ID: CY3649) is what we use in house. The CY3649 is the Hi-Lo programmer. These chips are One Time Programmable (OTP) chips. The programmer does not have the capabilities of the development kit. You do need to have the development kit to develop your firmware. We offer programming support with the easy-to-use Hi-Lo Programming System. Please review the attached Hi-Lo programmers application note.

Note1: The CY7C630xx/CY7C631xx are not recommended for new designs. Instead we recommend using the enCoRe. It has advanced features such as the internal oscillator (no external 6MHz clock), internal 3.3V regulator (for pulling up D- as required by the USB spec), Combi USB/PS/2 interface supported, wake-up circuit (no external RC wake up circuit needed), SPI compatible, Low voltage reset, each GPIO is independently configurable in different modes.

For pricing and availability information, please visit the following URL's:

Sales Representatives

Online Store

What is the CY3654-P05?

Tue, 06 Mar 2012 01:01:09 -0600

The CY3654 CY3654-PO5 Base Board & Personality Board is a development environment in support of a variety of applications such as mice or other low speed USB peripherals. The CY3654 CY3654-PO5 is designed for use with Cypress's CY7C632XXA, and CY7C637XX M8 based parts. For more information on the CY3654-P05 please visit the following link: DEVELOPER KIT: CY3654-P05.

Firmware Examples for USB HID Kits-CY3655-EXT,CY4623,CY3660,CY4672,CY3631 and CY4638

Mon, 27 Feb 2012 07:41:16 -0600

Response: The USB Full speed kits based on PSOC core contains several firmware examples to demonstrate different features of the kits. The firmware examples are tested with latest PSoC Designer 5.2 release.

Following is the list of Kits tested and their respective web links

1. CY3655-EXT :Encore-II Development Kit

weblink: www.cypress.com/go/cy3655-ext

Download CY3655-EXT_Firmware_PSOC_Designer_5_2.zip

2. CY3631 :Wireless Manufacturing Test Kit

weblink: www.cypress.com/go/cy3631

Download CY3631_WirelessUSB_MTK_Firmware_PSOC_Designer_5_2.zip

3. CY4623:EncoreII Mouse Reference Design

weblink: www.cypress.com/go/cy4623

Download CY4623_RDK_Firmware_PD_5_2.zip

4. CY4672:PROC Lp Keyboard/Mouse Reference Design

weblink: www.cypress.com/go/cy4672

Download CY4672_Firmware_Examples_PSOC_Designer_5_2.zip

5.CY4638:VOIP Demo kit

weblink: www.cypress.com/go/cy4638

Download CY4638_Firmware_Examples_PSOC_Designer_5_2.zip

6.CY3660:Encore V LV Development Kit

weblink: www.cypress.com/go/cy3660

Download CY3660_Firmware_Examples_PSOC_Designer_5_2.zip

Note:Please download and install PSOC designer 5.2 prior to testing the firmware examples.The weblink to PSoC designer is mentioned on above listed Kit weblinks.

CY3655 enCoRe™ II Development Kit

Wed, 08 Feb 2012 03:42:36 -0600

This development kit is no longer available. This web page has been left in place for informational purposes only. We recommend that customers instead purchase both the CY3655-EXT and CY3215-DK.

The enCoRe(TM) II development system, based on the highly refined PSoC(TM) (Programmable System-on-Chip(TM)) tools, supplies the user with an in-circuit emulator (ICE) that works in conjunction with actual silicon to provide an accurate and efficient development system. The PSoC Designer(TM) software consists of a graphical user interface, assembler, C compiler, linker and debugger for a highly integrated code development environment. A compliant USB "User Module" along with PS/2 and other peripheral User Modules simplifies the learning curve and speeds development time.

The enCoRe II development system is available in two ways - each provides the user with the same set of tools:

The CY3655-DK provides the complete set of tools for new users.
The CY3655-EXT extension kit provides just the enCoRe II specific items for customers who already have the base in-circuit emulator in the CY3215-DK.

Please contact your local sales office for the availability of the foot parts.

Hardware Description

The complete CY3655-DK includes all items in both of the lists below.

The CY3655-EXT includes the following items:

Application Board
enCoRe II Pod
enCoRe II LV Pod
40, 18, and 16-pin PDIP feet
Modular Programmer base board (CY3216) 3 matrix cards (CY3216-01, CY3216-02, CY3216-03)
5-pin ISSP header to USB receptacle programming adapter plug (CY3655-PLG)
Standard USB cable
PS/2 male-to-male cable
PSoC Designer Software CD-ROM
Printed documents

The CY3215-DK includes:

ICE-Cube In-Circuit Emulator
ICE Flex-Pod for CY8C29X family
Backward compatibility Cat-5 Adapter
110 ~ 240V Power Supply
Euro-Plug Adapter
Mini-Eval Programming Board in one
ISSP Cable
USB 2.0 Cable
Cat-5 Cable
CY8C29466-24PXI 28-PDIP Chip Samples
PSoC Designer Software CD-ROM
Printed documents

The CY3216 Kit includes:

CY3216 Modular Programmer
CY3216 Adapter Card #1
CY3216 Adapter Card #2
CY3216 Adapter Card #3

CY3216 Modular Programmer Kit

Wed, 08 Feb 2012 00:49:39 -0600

The Modular Programmer features include

Programming support for some PSoC, enCoRe II, Wireless enCoRe II and enCoRe III devices in PDIP packages.
Programming support for some PSoC, enCoRe II, Wireless enCoRe II and enCoRe III devices in surface mount packages with purchase of an appropriate surface mount adapter socket (sold separately).
Support for programming from:
- ICE-Cube
- Miniprog1
- Miniprog3
Modular Programmer supports many other Cypress devices by obtaining the appropriate adapter card and socket adapter.

The CY3216 Module Programmer Kit is included in the larger CY3655 kit: Click Here

For more information please see the kit documentation listed in the table below.

USB device not working after restarting the Windows 7 PC

Sun, 29 Jan 2012 23:55:05 -0600

Till Windows Vista RTm, all the USB devices attached to the PC undergoes a USB reset, when the OS resumes or restarts. This makes sure that the device enumerates once the PC is restarted or resumed. However, from Windows 7 onwards, this bus wide USB reset is disabled. This enables the devices connected to the PC to maintain device-specific states even after restarting the PC. This significantly decreases the time it takes for the USB devices to be available after system resume.

However, this feature of the OS may lead to malfunctioning of the device, if the device firmware is written in such a way that enumeration of USB is done outside the main while(1) loop. In this case, the device is never reset when the PC restarts and hence, the enumeration API is never executed again.

In the attached project, enumeration of the device is done in a conditional IF statement within the main while(1) loop by checking the 'bDeviceEnumerated' which is initialised to FALSE. Once the enumeration is complete, this flag is set to TRUE . Hence, control doesn't reach the enumeration API once device is enumerated.

The firmware is written to detect the PC restart condition. This is done by monitoring the SOF packets. On reception of every SOF packets, a counter 'bCtr' is cleared in the SOF ISR. Within the SLEEP Timer ISR, the same counter is incremented. If the SOF packets are not received for some time, the bCtr counter value will get incremented above definable threshold value at which the 'bDeviceEnumerated' flag is set to FALSE value.

Once the flag is set to FALSE, the firmware control reaches the enumeration API and enumerates the device on PC. With this firmware implementation, device works even after restarting the PC

This firmware is compliant with USB chapter 9 tests

Implementing SET_REPORT/ GET_REPORT in USB full speed and low speed HID devices

Sun, 29 Jan 2012 23:49:45 -0600

Implementaion is as follows:

The RAM location for feature report data is USBFS_INTERFACE_0_FEATURE_RPT_DATA.

Transfers using feature report can be implemented by directly accessing this buffer.

This buffer is declared in the ‘USBFS_descr.asm’ file associated with the USBFS user module as follows:

_USBFS_INTERFACE_0_FEATURE_RPT_DATA:

USBFS_INTERFACE_0_FEATURE_RPT_DATA:

BLK 8 ;

Proceed by exporting this RAM buffer for use in your ‘main.c’ file. This can be done with the line of code:

externUSBFS_INTERFACE_0_FEATURE_RPT_DATA[4];

You can assign values to these locations as:

USBFS_INTERFACE_0_FEATURE_RPT_DATA[0]=0x1122;

USBFS_INTERFACE_0_FEATURE_RPT_DATA[1]=0x3344;

USBFS_INTERFACE_0_FEATURE_RPT_DATA[2]=0x5566;

USBFS_INTERFACE_0_FEATURE_RPT_DATA[3]=0x7788;

Each location is capable of handling a WORD sized data.

GET_REPORT request reads data from these locations to the HOST. Similarly, SET_REPORT request writes data from HOST to these locations.

The ‘main.c’ firmware is as follows:

#include // part specific constants and macros

#include"PSoCAPI.h" // PSoC API definitions for all User Modules

externUSBFS_INTERFACE_0_FEATURE_RPT_DATA[4];

voidmain()

{

USBFS_INTERFACE_0_FEATURE_RPT_DATA[0]=0x1122;

USBFS_INTERFACE_0_FEATURE_RPT_DATA[1]=0x3344;

USBFS_INTERFACE_0_FEATURE_RPT_DATA[2]=0x5566;

USBFS_INTERFACE_0_FEATURE_RPT_DATA[3]=0x7788;

M8C_EnableGInt;

USBFS_Start(0, USB_5V_OPERATION);

while(!USBFS_bGetConfiguration());

while(1)

{

//Application code

}

The HID report descriptor used in the project is as follows:

Usage Page 06 FF FF

Usage 09 01

Collection (Application 01)

Report ID 85 01

Usage 09 02

Logical Minimum 15 00

Logical Maximum 25 FF

Report Size 75 08

Report Count 95 08

Input (Data, Variable, Absolute 02)

Usage 09 03

Report ID 85 02

Report Count 95 01

Logical Maximum 25 10

Feature (Data, Variable, Absolute 02)

End Collection C0

Note that irrespective of the report descriptor configuration, all HID class devices are supposed to respond to the HID class requests like SET_REPORT and GET_REPORT.

To test this firmware, please follow the instructions given in the attached word document

Implementation of Multiple Report ID feature Items in HID devices

Sun, 29 Jan 2012 23:46:50 -0600

Please find the attached PSoC Designer Project and explanation document which details the implementation

Accuracy of the enCoRe's internal clock?

Sun, 01 Jan 2012 14:25:19 -0600

The internal clock circuitry needs USB traffic from the host to provide 6MHz +/- 1.5% tolerance.
Without USB traffic (general MCU mode), the internal clock accuracy is 6MHz +/- 5%.

enCoRe II and enCoRe III --- USB certified?

Sun, 01 Jan 2012 13:57:14 -0600

Yes, the enCoRe II and enCoRe III devices are USB-IF certified. Cypress gets its devices (silicon - chips) USB-IF certified through a 3rd party test house or at PlugFest.

The enCoRe II and enCoRe III devices get certified under 'silicon building blocks' in the development category. There is also an option to search for 'retail categories' where you can find certification information for consumer/retail products.

In addition Cypress also gets USB certification for complete systems like Reference Design Kits (RDKs), Evaluation Kits(EVKs) etc. Certification for systems (RDKs etc) and silicon (chips) have different requirements and can be found on www.usb.org.

Every device that passed USB comliance tests will be assigned a test ID or TID number and gets listed on the usb.org website. enCoRe II silicon has 2 TIDs (the 63310 and the 638xx are from the same die and the 639xx is from a different die). Also different silicon revisions of the same device are certified separately.

enCoRe II - TIDs
CY7C638xx/CY7C63310: 40000085
CY7C639xx: 40000005

enCoRe III - TIDs
CY7C64215: 40000110

ESD issue in enCoRe II devices

Sun, 01 Jan 2012 13:42:23 -0600

The connection between the signal ground and ground shield may give rise to a problem if they are shorted directly because the part CY7C63723 will only see the 4KV and will result in failed ESD. You may use a RC or LC combination normally to avoid this problem.

USB Analyzer for monitoring bus traffic

Fri, 30 Dec 2011 13:55:24 -0600

We recommend CATC Bus Analyzers, because we are most familiar with them. There are also some other USB Bus analyzers available for example the one offered by Catalyst.

OUT Endpoint for the CY7C632xx

Fri, 30 Dec 2011 13:51:17 -0600

The control endpoint can be used to send data from the host to the device (using SetReport/GetReport). In this case the control endpoint can serve as an extra data endpoint, but in order to send 1 bit of data over the control endpoint, the transfer has to be completed in 3 stages: Setup Stage, Data Stage, and Status Stage. This process involves a lot of overheads which take up a lot of bandwidth from the bus. This approach is not prohibited by the USB Spec, but this would make the device an bad citizen on a busy bus. Therefore, this method is recommended only in a closed system where the device is the only one on the bus.

Interrupt Service Routines for port 0, port 1, port 2, port 3 and port 4 in encore II, boot, .asm, .tpl

Wed, 28 Dec 2011 11:56:27 -0600

The boot.tpl file located in the root directory of your encoreII project contains a basic template which will contain the Interrupt Service Routines of the GPIO Port interrupts for port 0, port 1, port 2, port 3 and port 4. But, it is recommended that boot.tpl should not be changed, hence any changes required in the ISR's should be made in the boot.asm and not in boot.tpl.

There is a part in the ISR (enclosed in banners) which is especially reserved for any user defined code. Any required changes should be made between those banners only.

Implementation of SPI slave in CY7C63803-SXC

Wed, 28 Dec 2011 11:43:18 -0600

SPI slave can be implemented in CY7C63803-SXC even though there is no explicit module for SPIS. SPIM module can be used and in the main program 10 should be written in bits[5:4] of register SPICR. This will automatically configure the sclk P1.4 pin as an input making it a slave.

LV capture timer interrupt in enCoRe II

Wed, 28 Dec 2011 11:17:50 -0600

The interrupt status bits in TCAPINTS register [0x2C] must be cleared before subsequent capture timer interrupts can take place. The status bits are cleared by writing 1 to the appropriate status bit location in the register. So, in the capture timer ISR after the timer capture register is read, we need to clear the status bits right before we restore A and X registers and then exit the ISR.

lowest power consumption during sleep in enCoRe II LV devices

Wed, 28 Dec 2011 08:10:37 -0600

Before the device is put to sleep, the following must be ensured for the lowest power consumed:

All GPIO pins must be set to outputs and driven low except P1.0 and P1.1 .
P1.0 and P1.1 should be configured and inputs with pull-ups enabled.
Make sure the 32-kHz oscillator clock is not selected as clock source to ITMRCLK, TCAPCLK, and not even as clock output source onto P01_CLKOUT pin.

Availability of PDC-9051

Sat, 24 Dec 2011 23:09:27 -0600

The USB LS compliance test device PDC-9051 is not available from Cypress. You need to buy it from USB-IF.

What is the CY3654-P02?

Mon, 05 Dec 2011 05:40:59 -0600

CY3654 Development Kit includes a CY3654 Platform board, an RS-232 Cable, and a Power Supply. Personality Kits include a CY3654Px02 Personality Board, a CY3654Dx02 Applications Board, Target µC Adapters, a target Flex Cable, and application Cables. For more information on the CY3654-P02 please visit the following link: DEVELOPER KIT: CY3654-P02.

Using internal voltage regulator for enCoRe II

Tue, 29 Nov 2011 23:36:48 -0600

The voltage regulator is enabled by setting the VREG enable bit (bit [0]) in the VREGCR register. An output cap (0.1µF or larger ceramic capacitor) should be loaded (at P1.2) close to the output pin when using the VREG output. This cap should be removed when the VREG output is used as a GPIO. The voltage regulator only functions within specifications when the V_CCvoltage is above 4.35V.

The emulation pods also have a place to hold the output cap if the internal 3.3V regulator is used. This cap should be removed if the pod is used later for emulation in a design that uses the VREG pin as a GPIO.

Pins P1.3 to P1.6 can use alternate drive of 3.3V only if the Vreg capability is enabled in the enCoRe II devices

In the USB suspend mode, current drawn should be minimal. The VREG feature, when enabled draws a minimum of at least 500µA. So, in the USB suspend, VREG should be disabled or configured in the "Keep Alive" mode (Keep Alive mode can be configured by enabling a bit (bit [1]) in the VREGCR register). This feature enables light loads of up to 20µA to be loosely regulated around 3.3V.

The enCoRe II data sheet can be viewed by clicking here: enCoRe II Data-sheet

Keywords: enCoRe II, voltage regulator, VREG, VREGCR.

USB Bootloader HOST program for enCoRe III and enCore V

Fri, 14 Oct 2011 02:55:27 -0600

Cypress Bootloader Host program is available in the PSoC Programmer installation folder. (default location : C:\Program Files\Cypress\Programmer\3.13\Bootloaders\BootLoaderUSBFS\USB_BootloaderHostApp\PSoC Config_1_0_0_3).

Please note that this Host Application is coded to detect only the bootloader configurations with VID/PID set to 04B4/E006. Hence you are required to modify the USB Bootloader module for this VID/PID inorder to use this sample program

Advantage of using 'BootLdrUSBFSe' user module over 'BootLdrUSBFS'

Fri, 14 Oct 2011 02:53:51 -0600

While using a 'BootLdrUSBFS' user module, changes to the PSoC Developer environment should be avoided for the Bootloading operation to work. This includes not updating PSoC Designer, the Bootloader User Module, and the compiler. Detailed information regarding this issue is given in page10 of 'BootldrUSBFS' user module datasheet which is available in this link:

http://www.cypress.com/?docID=29282

BootLdrUSBFSe user module is the improved and evolved version of the BootLdrUSBFS which solves the above stated issue. We recommend to use BootLdrUSBFSe.

advantage of the enCore Brown-Out Reset

Sun, 02 Oct 2011 04:40:42 -0600

The major advantage of the BOR is that it consumes very little power (some uA). This feature improves the chip's power consumption during suspend. Note that LVR is turned off, and BOR is ON when the part enters suspend. This low power consumption helps the device stay within the suspend current limit set by the USB IF (in suspend, a low-power device can draw max. 500uA from the bus, and a high-power device with remote wake-up enabled can draw maximum 2.5mA).

When a port data register (00H 01H and 02H) is written and then immediately read back why are the values differen...

Sun, 02 Oct 2011 04:39:42 -0600

When performing an IORD on the port data registers, you are actually reading the voltage on the port pins themselves, not the value written to the register.

CYDB uses an IORD instruction to display register values in the I/O Register window, so again the value displayed for the data port registers pertains to the voltage on the port pins.

When using the ByteCraft C compiler you need to pay special attention to the following:

When writing C code and you try to set a bit in a port data register i.e. PORT0.0 = 1, the code has no way of reading the Port0 register's present value and only manipulating a single bit. You can't say Port0 = Port0 | 0x01 for example. What would really happen instead is Port0 = (Voltages on Port0 pins) | 0x01.

Instead you should keep a shadow register of the port data registers.

When I assemble the CY4601 reference design for the CY7C63743 EnCoRe part the following warning shows up: Warning ...

Sun, 02 Oct 2011 04:37:23 -0600

This warning is perfectly fine and expected.

With XPAGEON the assembler automatically puts an XPAGE instruction at the end of

a 256 byte page to move the last assembly code from the current page to the

next page. (If the last instruction is a 2 byte instruction, a NOP and XPAGE are

inserted). However with XPAGEOFFenabled, this doesn't occur and it is possible a two byte instruction may be split between pages causing problems.

Please see the CYASM assembler guide, Section 3.1 Address Space, and the XPAGEON, XPAGEOFF instruction for more details.

However in this design it is just a warning and doesn't cause any problems. In this design this warning always occurs for the EnCoRe build.

Migrating Firmware from the 632XX to 637XX

Sun, 02 Oct 2011 04:33:25 -0600

Generally, firmware that works on the 632xx should also work on the 637xx. An exception is that, on the 632xx, the XTALOUT pin can be used as a GPIO input. However, this is not an option on the 637xx. Therefore, if the 632xx design uses the XTALOUT pin as an input pin, some modifications are needed to bring the design to the 637xx.

ESD issues!!

Sun, 02 Oct 2011 04:32:15 -0600

In most applications, it is acceptable for there to be temporary non-functionality in case of ESD events, so long as normal operation is resumed after the event. If this is the case with your application, then we recommend modifying the watchdog reset as follows:-

If a watchdog reset event has happened then you can make no assumptions about the current state of the chip - that is the point of the watchdog. You do not even know if the device address register contents accurately reflect the DA assigned to you by the host. Therefore to be sure of operating properly with the host, you need to simulate a disconnect/reconnect event (with the enCore turn off and on the Vreg; other M8 family can use an GPIO to control an external switch; hub applications may force a SE0 upstream for a period of aproximately 100ms). This is not specifically allowed for by the USB spec, but nor is it prohibited; you may be reassured to know that several of our largest keyboard customers adopt this approach.

After the reconnect the host will send a bus reset, and with careful coding your firmware will once again start running correctly.

I hope that your ESD spec allows you to use this technique- we believe it to be very robust; if not, then we have to try to fix the root cause.

Operation with OHCI vs. UCHI host controllers

Sun, 02 Oct 2011 04:30:32 -0600

UHCI host controllers schedule one transfer per 1 ms frame. OHCI host controllers, however, can schedule more than one transfer within a 1ms frame. Due to the locking mechanism on Endpoint 0 Mode and Endpoint 0 Count registers of the M8B microcontrollers, this feature of OHCI turns to be a problem some times.

After receiving a SETUP packet successfully (i.e. sending an ACK to the SETUP), the SIE automatically changes the mode to NAK_IN_OUT and sets the "Endpoint 0 SETUP Received" and the "ACK" bits in the Ep0 Mode register. The EP0 Mode register will be locked until the firmware does a read to the EP0 Mode. While the EP0 Mode register is being locked, the SIE keeps sending NAK to any IN/OUT and sets the EP0 IN Received/EP0 OUT Received bits to "1" if any of these events (IN or OUT) occur.

Normally, after the SIE sends an ACK to the SETUP, the host adds some delay before it sends any IN or OUT. Because the microcontroller runs off a 12MHz clock which is 8 times faster than the low-speed bus (1.5Mb per sec), some low-speed bit time idle is long enough for the microcontroller to read the EP0 Mode register to unlock it, determine what caused the interrupt (a SETUP, IN, or OUT has been received) and branch to an appropriate sub-routine to handle the interrupt.

In the EP0_ISR, after you learn that a SETUP was received, the first thing you should do is to set the mode to NAK_IN_OUT. This is to set the EP0 mode and to clear the rest of the bits in the EP0 Mode register.

It's possible that while you're handling the SETUP interrupt, the host sends an OUT to EP0 (no interrupt will be generated because the EP0 interrupt is disabled). When this happens, the EP0 sends a NAK to the OUT, updates the "EP0 OUT Received" bit, and the EP0 Mode register is locked. Therefore, every time you write to the EP0 Mode, you should read back to see if the register has been locked. If EP0 Mode register has been locked by a new SETUP (EP0 SETUP Received bit set), you should exit the EP0_ISR to service the new SETUP. If EP0 Mode has been locked by an OUT...NAK, you should unlock this register and set the EP0 Mode to the mode you desire.

Verifying my firmware checksum

Sun, 02 Oct 2011 04:28:24 -0600

One easy way is to load it into the Hi-Lo buffer. There's a "Buffer Checksum" feature on the Cystart Hi-Lo software.

In-circuit programming of M-8 chips

Sun, 02 Oct 2011 04:27:08 -0600

We recommend that the M8 chips be programmed prior to being soldered on the board. This negates the possibility of other components on the board affecting the signals going into the ROM. If the customers must program the M8 chips in circuit, they'll need to make sure that the discrete components on the board will not have any impact on the programming signals that come from the programmer.

M8 Code Execution Time

Sun, 02 Oct 2011 04:25:34 -0600

Yes. The .LST file produced by the CYASM assembler includes three fields in the leftmost column of the listing. The first field is the address field, which contains the address of the instruction contained on that line. The second field contains one or two bytes that represent the actual hex code assembled for that instruction. The third field is a single-digit number in brackets. That number indicates the number of clock cycles required to execute the instruction. Assuming that you're running the part at 12 MHz, multiply that number times the clock cycle time of (1/12000000) or 82 ns to determine the time required to execute the instruction. If you have a series of instructions that you want to measure, just add all of the cycle time values in the listing and multiply the total by the clock cycle time to determine the execution time of the code section.

Related Document :

CYASM Assembler Guide

Free-running timer on M8 parts

Sun, 02 Oct 2011 04:22:55 -0600

The timer runs off a 1MHz clock, giving a clock tick every 1us. This clock cannot be modified.

Difference between the M8A and M8B processors

Sun, 02 Oct 2011 04:19:52 -0600

The A version is only used in a limited number of older products, and it supports a smaller instruction set. The B version is newer and has more instructions. The directive CPU is used to specify the target microprocessor core.

ESD protection for the M8 chips

Sun, 02 Oct 2011 04:17:39 -0600

There are on-chip ESD protection circuit for each of the pin. In a typical application, no external ESD protection circuit is needed.

Parts based on the M8B processor core

Sun, 02 Oct 2011 04:16:42 -0600

All of our other M8 products not including the 630xx/631xx products.

Interrupt service routines for INT0, INT1, INT2 in enCoReII

Sun, 02 Oct 2011 04:15:33 -0600

The boot.tpl file of the encoreII project will contain the Interrupt Service Routines for enCoRe II GPIO interrupts: INT0, INT1, INT2.

Programming Cypress' M8 family of parts

Sun, 02 Oct 2011 04:12:38 -0600

For low volume, Cypress recommends using its CY3649 HiLo programmer. The programmer base unit is all that is required to program the CY7C630xx family parts. However all other Cypress M8 parts will require an additional adaptor base and matrix card specific to the part.

Please refer to the website or your local Cypress Sales Representative for further information on ordering the programer and locating the correct adaptor base and matrix card.

Many 3rd party programmers support gang programming for our M8 parts as well.

Parts based on the M8A processor core

Sun, 02 Oct 2011 04:11:19 -0600

Our 630xx/631xx products.

M8 programming specifications

Sun, 02 Oct 2011 04:08:44 -0600

Programming specifications can only be obtained with the submission of an NDA. Please contact Cypress Technical Support for information on obtaining the specifications.

Programming M8 microcontrollers

Wed, 28 Sep 2011 22:29:22 -0600

You need to have a programmer that supports the M8. There are many programming vendors that have support for the M8. If you are going to buy a programmer, we recommend the Hi-Lo System (Part ID: CY3649). Below is some information about programming the M8 with a Hi-Lo System programmer.

Tools needed:

The programmer, Hi-Lo System - Cypress USB Programmer For Starter (Cypress Part ID: CY3649)

A center negative, 9VDC, 1000mA output wall bug (provided with the CY3649)

A RS232 cable with female connector type at one end and male connector type at the other (provided with the CY3649)

The Cypress Start Kit USB Programmer software (Cystart.exe). This is freeware and can be downloaded below.

An Adapter Base (needs to be purchased separately)

A Matrix Card (needs to be purchased separately)

For the 630xx family, the matrix card is not needed. If the package type is 630xx-PC (PDIP), the adapter is not needed as well (just a Hi-Lo programmer is enough). If the package type is SOIC, a AS-28-28-03S-6-GANG adapter is needed. This adapter can be purchased from Emulation Technologies - http://www.emulation.com/

What is included in the CY3654-P02?

Wed, 28 Sep 2011 22:26:12 -0600

Supply resistor on Vcc for CY4622

Wed, 28 Sep 2011 22:23:16 -0600

This 1.5 Ohm resistor helps with inrush current. This is extra protection that we put in the design. In fact, we have never had any problem with inrush current with or without this resistor.

Mouse 16-bit X-Y reports

Wed, 28 Sep 2011 22:22:09 -0600

You can delcare 16 bit X Y in the report descriptor. The Microsoft driver can recognize it so you will not need a customized driver, however, on Boot mode, the BIOS can not recognize the mouse's activity.

Programming the CY7C63001A in a SOIC

Wed, 28 Sep 2011 22:20:27 -0600

Because the chip is in SOIC package (CY63001A-SC), a SOIC to PDIP adapter is needed. This adapter can be purchased from Emulation Technologies at www.emulation.com or by calling 1-800-ADAPTER. The part number is: AS-28-28-03S-6-GANG.

Use of Oscillator/crystal to clock the CY630xx (or Cy631xx)

Wed, 28 Sep 2011 22:18:28 -0600

The problem with crystals is that the clock signal starts tiny and grows to normal size over a long time - several ms. During that startup time, the chip sees something out of the clock cell, but it's not a reliable clock, since the input is so small. So it gets clock pulses, even before the clock is full size. Adding a bit of noise may produce clock pulses that are too close together. i.e. too fast.

The chip only waits for about 128 us before releasing the micro. At the end of this time, the clock may still be too small to be reliable, so a fast clock cycle may occur and cause the micro to fail.

Another thing to mention here is that, again because crystals take time to start up, by the time crystals reach its full scale amplitude, a watch dog reset could have occurred. This is not a big deal at power up because we do not differentiate a POR or watchdog reset or Bus reset (under firmware control, you branch a Bus Reset interrupt to a system reset like POR). However, there could be a problem when the part comes out of suspend. During the clock restart at Resume, the host expects the part to be good, but the part may have gotten lost by then.

Resonators tend to start in about 50 us, so those are not a problem.

There is an additional circuit in the part that holds off the start-up counter until the clock amplitude reached a certain level. However, while the chip has been shown to work with some crystals over some conditions, we found that at least some customers will eventually have combinations of crystal / silicon / board layout / operating conditions that make it NOT work. So to avoid problems, a resonator is required.

With that explained, it's up to the customer to try a crystal, or implement an external RC circuit that holds the micro for a curtain time to give their crytal enough start up time.

Note that there is an internal 30pf cap at each xtalin/xtalout pin. In an AC analysis, this will give you an effective 15pf capacitive load. There will typically be 2-3pf of stray cap in the logic. Therefore, the total capacitive load that an oscillating element sees is about 18pf. The 18pf load cap is a common recommended load cap for many oscillators in the market. So, you should choose an oscillator that requires an external 18pf load.

Crystal instead of a ceramic resonator

Wed, 28 Sep 2011 22:15:38 -0600

The CY7C63X0XA, CY7C6361X, and the CY7C63X1X all require a 6MHz ceramic resonator. A crystal can not be used because it has a longer start up time and will introduce uncertain behavior.

CY630xx's Cext interrupt work

Wed, 28 Sep 2011 22:14:18 -0600

The Cext is used to wake the part up from suspend. The Cext pin should be connected to GND with an external cap and Vcc with an external resistor. Firmware needs to write 0 to Cext Register to discharge the cap, and then writes 1 to Cext to disable the open drain output driver. As soon as the voltage at the Cext pin rises above Cext threshold voltage, an interrupt will be generated. The external RC circuit determines how fast/slow the cap is charged up, and as a result, determines how often the interrupts are generated. Note that Cext threshold voltage is a variable ranging from 12 to 30% Vcc, so for a fix RC, you're guaranteed a RANGE of periodical Cext interrupts.

Kit Contents of CY3654-P05

Wed, 28 Sep 2011 22:11:01 -0600

CY3654 Development Kit includes a CY3654 Platform board, an RS-232 Cable, and a Power Supply. Personality Kits include a CY3654Px05 Personality Board, a CY3654Dx05 Applications Board, Target µC Adapters, a target Flex Cable, and application Cables.

I am using the CY63001 in my design. At power up the chip is put into suspend by the hardware. How do I prevent this...

Wed, 28 Sep 2011 22:09:02 -0600

The 630xx is put into suspend mode by hardware at POR and wait for a bus reset from the host (or D- being pulled LOW) to wake it up. The advantage of this approach is that it tolerates very long ramps on the 5V Vcc pin. If the part isn't suspended by the hardware during slow ramps, the micro may attempt to start execution after Vcc passes the POR trip point. In such cases, this could lead to operation of the micro at Vcc of 3V or less which is too low for reliable operation. Suspending the chip at POR guarantees the part will not operate until Vcc is stable and has reached its max (a bus reset is sent by the host software after a long delay, 100ms. Vcc should be stable by then).

One of the disadvantages of this approach is the issue we're dealing with. Before we try to solve this issue, let me give you some info on the enCore family.

Since you're still at the very first stage of your design, I'd like to inform you that, for new low-speed designs, we recommend the enCore II family. The enCore II offers a lot more nice features over the CY630xx. Some of the added features are crystal-less oscillator (no external oscillator needed), wake-up circuit (external RC circuit is not needed), pull-up resistors, 3.3V internal regulator, SPI compatible. All of these add up to a lower system cost. One additional feature that is VERY USEFUL in your application is that the enCore does NOT continuously stay in suspend mode after POR. We fix the above issue by adding a bit in the microcontroller that allows the user to set an appropriate delay after POR. At POR, the enCore is only suspended for this delay time, and it will start executing code at 0x00. The bus reset is treated as an interrupt, not a reset as in the 630xx. Visit our web site - www.cypress.com for more information

If for some reasons, you have to use the 630xx, you will need to have external circuit to prevent the 630xx from going into suspend at POR. The concept is that the external circuit will bring D- LOW for a few ns at POR to wake it the chip up then release the D-/+ pins for USB operation. Whatever we will do, it should not add addition load to the D-/+ lines to meet the USB Spec.

We have a document that discusses the CY630xx's POR suspend issues in details. Contact USB Apps for this document (A link to our web site will be provided later)

External serial EEPROM got modified when unplugged from CY7C63001

Wed, 28 Sep 2011 22:04:33 -0600

What may be happening is that when Vcc drops the CY7C63001 jumps to an incorrect address and wrote some data to the external EEPROM.

When the chip is powered down to about 3.5V, the microcontroller enters an unknown state where its operation is not reliable. You'll probably need to have an external circuit to detect this power down event and put the part into a known state (i.e. suspend mode).

If you are still in the early stage of the design, I would strongly suggest the enCore II family. With the enCore II micro, this shouldn't be a problem because the enCore has a Low Voltage Reset (LVR) circuit which is especially designed to handle this situation.

If moving to enCore is impossible, then here are some suggestions:

Normally, the D- pin is pulled up to Vcc through a 7.5K-ohm resistor, and this pin is also pulled down to ground through the host's internal 15K-ohm resistor. This voltage divider makes the D- pin centered around 3.3V.

Whenever Vcc is disconnected, you should have an external capacitor that charges D- pin up to Vcc, and the voltage on this pin will eventually decay to 0 through the 15K-ohm host pulldown resistor (RC circuit). You will need to design an external circuit that detects the 3.3V --> Vcc event on D- and put the chip into suspend when this happens. Because the 3.3V-->Vcc event on D- happens before Vcc goes to 3.5V (where the chip goes to an unknown state), the external circuit should be able to put the chip into suspend before the unreliable 3.5V Vcc is reached

Transmitting IN and OUT through a single endpoint

Wed, 28 Sep 2011 22:01:05 -0600

The USB Specification requires that a device have at least one data IN endpoint. The CY630/1xx has only one data endpoint, endpoint 1, which must be dedicated to the IN interrupt endpoint. In order to send data OUT to the device, you will need to use the control endpoint, endpoint 0. The SET_REPORT and GET_REPORT requests are used to send and retrieve data to/from the device through the control endpoint.

While this approach is not as efficient as using a data endpoint due to the overhead involved in control transfers (three stages - Setup, Data, and Status stages- are needed to complete the transfer), it is the only method available to send data OUT using the CY630/1xx family. If OUT data performance is an issue, consider using a part with more than one data endpoint.

Jan Axelson has a very good sample code demonstrating this method on her website at www.lvr.com.

Applies To:

CY7C63000, CY7C63001, CY7C63100, CY7C63101

What is the cost of the Mask ROM version of CY7C63xx. What is the minimum quantity required to make an order and how ...

Wed, 28 Sep 2011 21:58:58 -0600

The Cypress CY7C63xx devices use an exceptionally small PROM cell that allows us to sell OTP devices at a price nominally only achieved with masked mcus. This allows us to offer all the advantages of OTP - uncommitted inventory, fast lead time,

etc. at the same price as you would nominally pay for masked parts. There are no setup fees of any kind for this service. Contact Pam Bickel (xpb@cypress.com) in our marketing team (858- 613-7932) for information on lead times and unit cost.

When a port data register (00H and 01H) is written and then immediately read back why are the values different? Th...

Wed, 28 Sep 2011 21:57:24 -0600

I2C or SPI implementation on 630xx/631xx

Wed, 28 Sep 2011 21:55:31 -0600

There's no hardware-based I2C or SPI support built into the 630xx/631xx parts, so you will have to manually toggle GPIO pins with firmware to implement an I2C or SPI interface.

This can be done successfully. You will need to know the desired bit timing and switch the GPIO modes between resistive and open drain modes to drive the pins HIGH/LOW accordingly. Unfortunately, we do not have any example code to illustrate this method.

You should also be aware that, for new low-speed designs, Cypress recommends using the enCore II family. The enCore II family offers a lot more features over the CY630xx. Some of the added features are crystal-less oscillator (no external oscillator needed), SPI compatible (both Master and Slave), internal 3.3V regulator, wake-up circuit (external RC circuit is not needed), pull-up resistors, Combi USB and PS/2 interfaces supported. All of these add up to a lower system cost.

For more information on this part, please visit our web site at: www.cypress.com (choose Products--> USB--> Low-speed).

630xx/631xx Availability

Thu, 22 Sep 2011 22:23:45 -0600

No, the 630xx/631xx parts are not available. Instead we offer the enCoRe II(enhanced Component Reduction) series of parts for the following reasons:

(1) Some development tools for the 630xx/631xx, including the CY3640 USB Starter Kit and CY3650 Development Kit, are either no longer available or subject to limited availability. Without the CY3650 Development Kit, development of products based on the 630xx/631xx parts will be difficult.

(2) The enCoRe II parts offer improved performance and reduced overall system cost by integrating several features missing from the 630xx/631xx parts including:

Crystal-less oscillator

The crystalless oscillator offered by the enCoRe parts eliminates the need for an external crystal or resonator.

Built-in 3.3V regulator

The 3.3V regulator built into the enCoRe parts eliminates the requirement for an external regulator.

Wakeup timer

The 630xx/631xx parts require the addition of an external R/C circuit for wakeup capability. The enCoRe parts have an internal wakeup timer that eliminates the need for the external R/C circuit.

SPI

The enCoRe parts include hardware support for SPI, providing better performance and CPU utilization than achieved by bit-twiddling an SPI interface over GPIO pins.

Individually programmable GPIO pins

While the 630xx/631xx parts provide GPIO control on a port basis, the enCoRe parts allow for GPIO pin configuration on a pin-by-pin basis.

Integrated pull-ups for PS2 operation

For PS2 applications, external pullup resistors are required when using the 630xx/631xx parts. The enCoRe parts provide this pullup capability internally, eliminating the requirement for the external resistors.

Send data OUT to the device

Thu, 22 Sep 2011 22:20:06 -0600

The 630xx/631xx has two eight-byte buffers, one for the control endpoint and one for data endpoint. The USB Specification requires that a device has at least 1 IN endpoint. Therefore, the data enpoint must be configured as an IN endpoint. The only mechanism to send data OUT to the device is to use SET_REPORT over the control endpoint. To learn more about SET_REPORT, please refer to the USB Specification.

Mouse Sample Firmware for CY7C63001A-PC

Thu, 22 Sep 2011 22:18:54 -0600

The 63001 was a good chip, and it was around for a while. It is no longer recommended for new designs. For new low-speed designs, we, however, recommend the enCoRe II devices. These devices have all features that the 63000 has with added useful features that reduce the over all costs such as the internal oscillator (no external 6MHz clock), internal 3.3V regulator (for pulling D- up through a 1.3K pull up), dual USB/PS/2 interface supported, wake-up circuit (no external RC wake up circuit needed), SPI compatible, Low voltage reset, each GPIO is independently configurable in different modes,... More information on this part can be achieved from our web site at: www.cypress.com (click on Products--> USB Low-speed Peripherals --> enCoRe II).

This CY7C63001 mouse firmware has been removed from our web site. Please contact us at www.cypress.com/support for an electronic copy of the firmware.

Testing USB devices without using a PC

Thu, 22 Sep 2011 22:15:16 -0600

The CY7C66x13 hub part cannot be used because a hub is just a repeater. It does not actually generate the USB traffic sent to the attached devices.

You need a source of data with host capabilities such as generating SOF, USB traffic, suspend/resume... We do have the SL811HS family that has host capabilities. The EZ-811HS Developer's kit is the host with 4 downstream ports. For more info on this product, please go to our web site at www.cypress.com (click on Products --> USB Embedded Host -->SL811HS -->EZ-811HS Developer's Kit).

Alternately, you could use the traffic generation capability of a CATC analyzer to simulate host traffic to your device.

USB HID Specification

Thu, 22 Sep 2011 22:13:36 -0600

The HID specifications can be found at the USB-IF HID URL: http://www.usb.org/developers/hidpage.html
HID sample code that uses the M8 chips to communicate with a VB or Visual C++ host applications can be found at http://www.usb.org/developers/devclass_docs/HID1_11.pdf

IBIS models availablility for the CY7C630xx/631xx

Thu, 22 Sep 2011 22:09:40 -0600

Unfortunately, IBIS models are not available for our low-speed M8 products.

Difference between the CY7C630xx and CY7C631xx parts?

Thu, 22 Sep 2011 22:07:17 -0600

The number of General Purpose Input/Outputs is one major difference between these two parts. The CY7C6300x has twelve GPIOs and the CY7C6310x has sixteen GPIOs. Each of these products also come in different packages because of the difference in the number of IO's: The 12-GPIO CY7C6300x is available in 20-pin PDIP (-PC) and 20-pin SOIC (-SC) packages. The 16-GPIO CY7C6310x is available in 24-pin SOIC (-SC) and 24-pin QSOP (-QC) packages.

Note: The CY7C630xx/CY7C631xx are not recommended for new designs. Instead we recommend using the enCoRe II product line. It has advanced features such as the internal oscillator (no external 6MHz clock), internal 3.3V regulator (for pulling up D- as required by the USB spec), Combi USB/PS/2 interface supported, wake-up circuit (no external RC wake up circuit needed), SPI compatible, Low voltage reset, each GPIO is independently configurable in different modes,...

For more info on this part, please click on:
enCoRe II USB

Porting firmware from CY7C63000/001 to EZ-USB

Thu, 22 Sep 2011 22:02:55 -0600

There is really not an easy way since the CY7C63001 uses an M8 core and the AN2131 uses the 8051 microprocessor. We do provide various examples that demonstrate and illustrate the implementation of the USB protocol with the AN2131 EZ-USB chip. Most of the examples included with the AN2131 DK001 Development Tool software are frameworks based (includes fw.c in their project). The frameworks file fw.c implements the USB protocols. Please refer to the following files, which are included in the "C:\Cypress\USB\Doc\EZ-USB General" folder, after installing the development tools.

-Anchor Firmware FW.pdf

-EZ-USB Contents and Tutorial.pdf

Using the control endpoint (EP0) to transfer data OUT to the device

Thu, 22 Sep 2011 22:01:31 -0600

The 630xx has only one endpoint. By the USB spec, a device must have at least one IN endpoint. Therefore, this only endpoint must be dedicated to an IN endpoint. In order to send data OUT to the device, SET_REPORT must be used to send data over EP0 to the device. More than eight bytes can be sent by doing multiple OUTs in the data stage of a control transfer. That is, SETUP ---> OUT (8 bytes), OUT (8 bytes), SETUP---> IN (0 length status stage).

How does the lock bit of the CY7C63001a work?

Thu, 22 Sep 2011 22:00:28 -0600

The HI LO programmer shipped by Cypress has a similar feature known as the Security button on the programmer application. This feature destroys the security fuse and then the device is no longer readable by the application and hence is secure.

CYASM Assembler User Guide

Thu, 22 Sep 2011 21:58:37 -0600

The CYASM Assembler User Guide has detailed discussion on Cypress' M8 assembly language. This document comes with the Cypress Lab CD. If you have already installed the CYDB tool from the CD, you can go to the Cypress/Cydb/Doc/Cyasm folder to get the file. The assembler, CYASM.EXE, is located at Cypress/Cydb/Bin.

Please find attached the CYASM Assembler User's Guide and CYASM.EXE below.

When I compile my firmware with the CYASM I get the following message: Error 'Jumps can not cross 4K boundary...' Why?

Thu, 22 Sep 2011 21:57:03 -0600

You get this message because you're attempting to go across the 4K boundary with a jmp instruction. The 8K ROM is "divided" into two 4K blocks, upper and lower 4Ks.

The Index, CALL and JMP instructions are limited to 12 bit addresses and cannot transcend the 4K block limit. The CALL allows access from the lower 4K block to anywhere in the upper 4K. It does not allow access from the upper 4K to the lower 4K. After a CALL to the upper 4K, access to the lower 4K is restored by RET or RETI instructions. Therefore, Interrupt Service Routine should be located in the lower 4K block for utilizing the upper 4K.

For more details, please refer to the attached CYASM User's Guide.

CYASM

Thu, 22 Sep 2011 21:55:36 -0600

CYASM is Cypress' assembler that provides support for conditional assembly and new command line arguments for microcontroller selection and symbol definition. Please refer to the following link for details on downloading the CYASM.EXE and related documents:

http://www.cypress.com/?id=4&rID=33288

Current version of CYASM

Thu, 22 Sep 2011 21:48:27 -0600

The most current version is V1.96.

Bytecraft Compiler Error

Thu, 22 Sep 2011 21:47:04 -0600

The chip architecture prevents the program counter from "jumping" (jmp instruction) across the 4K boundary. "Calling" (call instruction) from the lower 4K to the upper 4K is OK, but "calling" from upper to lower 4K is also prohibited. For more information on this subject, please refer to Section 3.0 of the CYASM Assembler User's Guide

Keywords used: compiler error, bytecraft, jumps, 4K boundary

Table read using SSC calls in enCoRe II

Wed, 21 Sep 2011 22:39:08 -0600

Attached is an example that demonstrates how a Silicon ID is read from an enCoRe II device. The silicon ID is stored in table 0 and is returned in locations F8 and F9 in the RAM when a table read SSC call is made. The ID is then moved into another location in the RAM (done because the EEPROM write routine uses the last 8 bytes of the RAM) and the EEPROM write routine is called to write this value to the flash. Make sure the flash security file is unprotected ? to be able to write to the flash location and to be able to read out the value using a MiniProg or ICE cube.

OUT Transfer example for enCoRe II

Wed, 21 Sep 2011 22:37:39 -0600

Answer: Attached is an example that demonstrates data loop back using enCoRe II. Data is transferred from the host application (CyConsole) to the device through the OUT endpoint and then transferred back to host through the IN endpoint. This example uses the CyUSB driver. Please download and install USB Dev Studio from the link for CyConsole application -> http://www.cypress.com/?rID=34870

Application notes for encore to encore II migration

Wed, 21 Sep 2011 22:36:36 -0600

Yes the application notes to be referred for encore to encore II migration is AN6062.

http://www.cypress.com/?rID=12992