The SDK installation package as well as zip/tar archives of individual components are available below for download. Given below is a brief description of these downloadable items to help you select the right file(s) to download.

1. EZ-USB FX3 SDK Installer - This is the master installer file that will install the firmware library with samples, USB Suite with Windows host driver and applications, Eclipse IDE & GCC tool chain. Once installed using the installer, Cypress Update Manager will enable users to look for updated versions of these software modules and facilitate upgrades.
2. Firmware Library Zip – A zip archive that contains the FX3 firmware libraries, driver sources for serial peripheral modules, header files, example code, firmware conversion utility and documentation. The following firmware source samples are also part of the library zip file.
   • USB Bulk data loopback and source/sink
   • USB Isochronous loopback and source/sink
   • DMA examples: Interleaved and multicast data
   • Serial Interface Loopback: UART, SPI, I2C and I2S
   • Slave FIFO: Synchronous and Asynchronous
   • USB Video Class: Isochronous and Bulk
   • USB Mass Storage Bulk-Only transport
   • USB Audio Class: Input (microphone) device
3. USB Suite Zip – A zip archive containing windows host driver, C++ & C# API libraries, and the control center, bulkloop and streamer applications for 32 bit platforms (Windows XP, Vista and Windows 7) and 64 bit platforms (Windows Vista and Windows 7)
4. FX3 SDK for Linux platforms – A tar archive containing the FX3 firmware libraries and examples, the ARM GNU toolchain, Eclipse IDEs (x64 and x86 versions) and the CyUSB suite for Linux platforms
5. USB Suite for MacOS - A libusb based wrapper library for Mac OS, to facilitate USB host application development.
6. Documentation
   • FX3 Programmer's Manual
   • FX3 API guide
   • FX3 Release Notes
   • Trouble shooting guide

However, for production, you will need your own VID/PID to pass USB compliance and get the hub certified. You can configure the hub to use your VID/PID either of the following ways:

1. Add an external EEPROM to your design. The external EEPROM will be programmed to provide your VID/PID, descriptors, and other hub configuration settings.


2. Purchase your parts with the internal fuse links set to your VID/PID (this is a factory function only and cannot be done after packaging).

For more information, refer to the device datasheet.

• Three modes of operation of the FX1/FX2LP
• Endpoint Configuration and Multiple Buffering
• Three Domains that form the basic component of the FIFO architecture
• Arming and committing endpoint buffers
• Endpoint operation in manual vs. auto mode

FX2LP was designed to be used in either one of the modes: Port I/O, Slave FIFO, or GPIF. For more information, refer to the application note Endpoint FIFO Architecture of EZ-USB FX1/FX2(TM) - AN4067.

It is possible to switch from one mode to another. Before switching from slave FIFO to GPIF or vice versa, you must make sure that there is no data transfer in progress as far as the physical interface is concerned or for that master on the USB end (host is not sending or receiving data from any of the endpoint).

You must make sure that the FIFO is reset and the device is in a state (no data activity in progress). When this is done, you may switch from one mode to the other. Switching from one mode of operation to another is not an intended feature, but something that you may do as long as the device is in a stable state.

For reading and writing to the external memory you can download vend_ax example to the device, and then use the A3 vendor command. Both these vendor commands use Value field to specify the memory location.

Note Install CY3684 FX2LP and CY3681 FX2 development kits for a different version of vend_ax (file path:C:\Cypress\USB\Examples).

AN75705 helps you get started with FX3. It highlights the key uses, applications, and features of FX3. A comprehensive list of design resources available from Cypress is also provided. This application note walks you through the steps to get started with USB transfers using the FX3 development kit (DVK) and software development kit (SDK).

Video on EZ-USB FX3 Architecture Overview - click below

SAN JOSE, Calif., April 17, 2013 – Cypress Semiconductor Corp. (NASDAQ: CY) today announced that Pico Technology’s PicoScope 3207A and 3207B, the world’s first USB 3.0 oscilloscopes, employ Cypress’s EZ-USB® FX3™ USB 3.0 controller. The two-channel USB oscilloscopes  have 250 MHz bandwidth, 1 GS/s sampling rate, 512 MS buffer memory and a built-in function generator and arbitrary waveform generator. The scopes obtain power from the USB port, so they don’t need an external power adaptor.

“USB 3.0 ports are appearing on most new computers and laptops,” said Alan Tong, Pico Technology’s Managing Director, “so buyers of USB oscilloscopes will expect to benefit from the higher data transfer rate. With the new USB 3.0 PicoScopes, large data captures and streaming of large data sets are now much faster. Cypress’s FX3 controller enabled us to deliver these scopes to market quickly and cost-effectively.”

Cypress’s EZ-USB FX3 is the industry’s only programmable USB 3.0 peripheral controller. Its on-chip ARM9 CPU core with 512 KB RAM delivers 200 MIPS of computational power. FX3 is equipped with a fully configurable General Programmable Interface (GPIF™II), which can be programmed in 8-, 16-, and 32-bit configurations. GPIF II enables FX3 to communicate directly to any processor, FPGAs, and image sensors and provides a data transfer rate at up to 400 Megabytes per second. More information on Cypress’s EZ-USB FX3 controller is available at www.cypress.com/fx3.

“We’re pleased to enable another first for USB 3.0 with the new PicoScopes,” said Mark Fu, Senior Marketing Director for the USB 3.0 Business Unit at Cypress. “FX3 is rapidly becoming the de facto USB 3.0 industry standard due to its performance, flexibility and ease-of-use.”

About Pico Technology
Pico Technology has spent over 20 years leading the industry in the design, development and manufacture of high-performance PC Oscilloscopes and Data Loggers. During that time they have built up an impressive portfolio of products including the PicoScope PC Oscilloscope range with bandwidths up to 12 GHz, resolutions up to 16 bits and mixed-signal models; the TC-08 and PT 104 Temperature Data Loggers; and the multi-award-winning Automotive Oscilloscope Kit.

Pico Technology prides itself on offering innovative, high-quality and affordable alternatives to traditional bench-top test and measurement equipment, designed and built under the ISO9001:2008 quality system. They support a network of distributors in over 60 countries worldwide who are helping to build and maintain their enviable reputation in the industry.
More information on Pico Technology can be found at www.picotech.com.

About Cypress
Cypress delivers high-performance, mixed-signal, programmable solutions that provide customers with rapid time-to-market and exceptional system value. Cypress offerings include the flagship PSoC® 1, PSoC 3, PSoC 4, and PSoC 5 programmable system-on-chip families. Cypress is the world leader in capacitive user interface solutions including CapSense® touch sensing, TrueTouch® touchscreens, and trackpad solutions for notebook PCs and peripherals. Cypress is the world leader in USB controllers, which enhance connectivity and performance in a wide range of consumer and industrial products. Cypress is also the world leader in SRAM and nonvolatile RAM memories. Cypress serves numerous major markets, including consumer, mobile handsets, computation, data communications, automotive, industrial, and military. Cypress trades on the NASDAQ Global Select Market under the ticker symbol CY. Visit Cypress online at www.cypress.com.

# # #

Cypress, the Cypress logo, EZ-USB, PSoC, CapSense and TrueTouch are registered trademarks and FX3 and GPIF are trademarks of Cypress Semiconductor Corp. Pico Technology and PicoScope are internationally registered trademarks of Pico Technology.  Pico Technology is registered at the U.S. Patents and Trademarks Office. All other trademarks are property of their owners.

EZ-USB® FX3 is the next generation USB 3.0 peripheral controller, providing highly integrated and flexible features that enable developers to add USB 3.0 functionality to a wide range of applications.

FX3 supports several boot options including booting over I2C, SPI, USB, Synchronous ADMux and Asynchronous SRAM interfaces. This application note describes the details of the different booting options for FX3.

The default state of the FX3 IOs during boot are also documented. The Appendix describes the step-wise sequence for testing the different boot modes using the FX3 DVK.

Answer: No. CyUSB.sys is a generic USB device driver that assumes a device has only one interface. However, composite devices are bound to windows composite driver (usbccgp.sys) by default. This exposes each interface as if it were a separate USB device. Each of these interfaces can be bound to CyUSB.sys (one instance of CyUSB.sys per interface). The composite device part of the overhead is handled by usbccgp.sys.

Answer: Error codes can be converted into strings using:

CCyUSBDevice::UsbdStatusString(ULONG stat, PCHAR s)

Where:
‘stat’ is the UsbdStatus error code obtained from NtStatus
‘s’ holds the converted string

Answer: FX2LP does not support debugging over JTAG, it only support serial port debugging. PSoC3 supports JTAG debugging and is an alternative if you only require full-speed USB.

For more details on serial port debugging with FX2LP refer to AN58009.

Answer: Yes, you use SW9 on the DVK board to select self-powered or bus-powered. J53 should be populated when using bus-powered configuration.

Answer: Yes, the FX2LP I2C controller supports clock stretching. Once the master (FX2LP) drives SCL low, external slave devices can hold SCL low to extend clock-cycle times.

1. Disable the spread spectrum setting of the host
2. Update the host controller driver to the latest version
3. U3TXVDDQ and U3RXVDDQ require a 22 uF decoupling capacitor to avoid issues caused by inrush current Refer to AN70707-EZ-USB® FX3 Hardware Design Guidelines and Schematic Checklist
4. The CyU3PConnectState () API must be called in firmware with both input parameters as CyTrue

Answer: Yes, the PMODE[2:0] signals can be controlled on the DVK board using SW25 or by an external processor connected to the GPIF II interface. You make this selection with J96, J97, and J98.

Features

• USB 2.0 hub controller
• Automotive and Industrial grade option (–40 °C to 85 °C)
• Compliant with USB 2.0 specification
• USB-IF certified: TID# 30000009
• Windows Hardware Quality Lab (WHQL) Compliant
• Up to four downstream ports supported
• Supports bus powered and self powered modes
• Single transaction translator (TT)
• Bus power configurations
• For more, see pdf
   

Introduction

EZ-USB HX2LP™ is Cypress’s next generation family of high-performance, low-power USB 2.0 hub controllers. HX2LP is an ultra low power single chip USB 2.0 hub controller with integrated upstream and downstream transceivers, a USB serial interface engine (SIE), USB hub control and repeater logic, and TT logic. Cypress has also integrated many of the external passive components, such as pull-up and pull-down resistors, reducing the overall bill of materials required to implement a hub design.

To build DE3:

1. Open a BASH window Start → Programs → Cypress → BASH → EnvironmentOTG — Host → USB
2. Change directories to DE3
   [cy]$ cd Source/stand-alone/de3
3. Do a make clean to start from scratch
   [cy]$ make clean
4. Do a make all to rebuild all code
   [cy]$ make all

To download the code to the EZ-Host Development Board RAM:

1. Open a BASH environment and go to the de3 directory
2. Use a text editor to view de3.ld to see where the code is org’d at (. = 0x####)
   [cy]$ cy16-elf-objdump –f de3
   [cy]$ cy16-elf-readelf –h de3
   [cy]$ head -20 de3.ld
3. Run scanwrap on the binary image
   [cy]$ scanwrap de3.bin de3_scan.bin 0x04A4

To download the code to the EZ-Host Development Board EEPROM:

1. Set all of the board’s dipswitches to off
2. Power up the board by plugging in the power connector
3. Reset the board by pressing the reset button
4. Set the dipswitches for EEPROM 4/stand-alone mode
5. Open a BASH window and go to the de3 directory
6. Plug in a USB cable to SIE2 (Peripheral–2A)
7. Verify the device manager is using the correct driver
   Cypress USB EZ-OTG Device VID=04B4, PID=7200
8. Run qtui2c
   [cy]$ qtui2c de3_scan.bin f

Features

The Cypress MoBL-USB™ TX2UL is a low voltage high speed (HS) USB 2.0 UTMI+ Low Pin Interface (ULPI) Transceiver. The TX2UL is specifically designed for mobile handset applications by offering tiny package options and low power consumption.

• USB 2.0 Full Speed and High Speed Compliant Transceiver
• Multi Range (1.8V to 3.3V) I/O Voltages
• Fully Compliant ULPI Link Interface
• 8-bit SDR ULPI Data Path
• UTMI Level 0 Support
• Support USB Device Mode only
• Integrated Oscillator
• Integrated Phase Locked Loop (PLL) – 13, 19.2, 24, or 26 MHz Reference
• Integrated USB Pull Up and Termination Resistors
• For more, see pdf
   

Functional Overview

UTMI+ Low Pin Interface (ULPI)

This block conforms to the ULPI Specification. It supports the 8-bit wide SDR data path. The primary I/Os of this block support multi-range LVCMOS signaling from 1.8V to 3.3V (±5%). The level used is automatically selected by the voltage applied to VCCIO and is set at any voltage between 1.8V and 3.3V.

Features

• Powerful Harvard-architecture processor
• Flexible on-chip memory
• Complete development tools
• Precision, programmable clocking
• Programmable pin configurations
• Full-Speed USB (12 Mbps)
• Additional system resources
• For more, see pdf
   

Functional Overview

The enCoRe V family of devices are designed to replace multiple traditional full-speed USB microcontroller system components with one, low cost single-chip programmable component. Communication peripherals (I2C/SPI), a fast CPU, Flash program memory, SRAM data memory, and configurable I/O are included in a range of convenient pinouts.

Cypress recommends that you connect the TEST/I2C_SCL pin to the SCL of another IC on the schematic, without the pull-up resistor. HX2VL DVK designs that do not use pull-up resistors have been tested and verified.

• USB Hi-Speed Peripherals
• USB Hubs
• USB Low-Speed Peripherals
• USB Full-Speed Peripherals
• MoBL-USB
• USB Embedded Hosts
• WirelessUSB™

The EZ-USB FX2LP™ is a versatile, USB 2.0 compliant High Speed USB controller from Cypress. FX2LP has an 8051 core and a highly configurable interface (GPIF) to external memory devices and other peripherals or controllers. Cypress also provides a configurable Firmware Frameworks written in C, which implements a fully compliant USB interface for FX2LP.

Introduction

Cypress EZ-USB FX3 is the USB 3.0 peripheral controller, with highly integrated and flexible features that allow you to add USB 3.0 functionality to any system.

EZ-USB® FX3™ lets developers add USB 3.0 device functionality to any system. Its GPIF II can create an interface with virtually any processor, ASIC, image sensor, or FPGA. AN75779 introduces the basics of UVC and shows you how to design an application compatible with UVC by creating an FX3 interface with the following signals: frame valid, line valid, pixel clock, and 8-bit to 32-bit parallel data bus.

• Aptina 720p image sensor, 30 fps, 24-bit color
• Full FX3 firmware implementation of USB video class
• Highly configurable GPIF™ II interface
• ARM9 sets up transfer, video runs over DMA
• Boards and schematics available (Aptina NDA required)

• CYUSB3KIT-001, EZ-USB® FX3™ Development Kit
• MT9M114, Aptina 720p Image Sensor Headboard
• Aptina Interconnection Board
• USB 3.0 Cable

1. Sign NDA with Aptina (send request to fx3@cypress.com for expedited process)
2. Buy the Aptina MT9M114 Image Sensor Headboard from Aptina Distributors
3. Buy the $295 EZ-USB FX3 Development Kit (CYUSB3KIT-001)
4. For Aptina Interconnection Board, (please contact Cypress fx3@cypress.com)

Software Title	Description	Link
EZ-USB FX3 SDK (with GPIF II Designer)	This kit requires GPIF II Designer and SDK for image sensor firmware development
Demo Firmware (cyfxuvc.img)	Program the camera kit with the demo firmware to stream HD 720p video over USB 3.0 (also works on USB 2.0 port at reduced resolution and frame rate) * Source code available upon request. Contact fx3@cypress.com with a copy of Aptina NDA*
Camera Kit Guide	The camera kit guide provides instructions from board setup to running the demo

Flow Control. Choose this function if the two UART links have different processing speeds. If the UART receiver has a processing delay between two consecutive receptions over the UART, it can signal ‘wait’ to the UART transmitter by deasserting the CTS line. When you are ready to send data, the transmitter can use the RTS pin to signal the receiver to keep its receiving line active. The DTR/DSR pin can enable and disable the Transmit/Receive function. The RTS/CTS pin can enable and disable the transfer of individual blocks of data.

I/O. You can choose this function if the UART transmitter and receiver have similar processing speeds. You can use the CTS, RTS, DTR, and DSR pins as I/Os that can be read and written to from the PC by USB requests. In this mode, CTS and DSR serve as input pins and RTS and DTR serve as output pins.

The device can resume normal operations when the USB detects activity or a reset signal. When the device is in Suspend, and Remote wakeup is enabled, then asserting the wakeup signal generates remote wakeup signaling on the upstream. The device resumes normal operations when the host acknowledges the signal.

The ReadFile API returns are based on the following conditions:

1. A short data packet is received.
2. The ReadFile API buffer is completely filled.
3. A read timeout has occurred.
4. The device port is closed.

A short data packet is as small as one byte or as much as the maximum data packet size described in the device descriptors. You can use the User Mode Driver or the application to check the number of bytes read by the ReadFile API.

Contact Cypress Sales for more information about Windows CE Driver.

• Baud rate: 230K baud. This rate does not support flow control.
• Parity bit: ‘None’.

The current implementation takes the next available COM port number and assigns it to the Cypress USBUART driver. This avoids any COM port number conflicts. However, you can change the registry setting to use a fixed COM port number. For more information, refer to Windows CE documentation.

You can follow these steps to load the driver without using the Cypress VID and PID:

1. Change Windows registry settings to reflect the new VID and PID.
2. Add and set a new global environment variable called BSP_NO_CYP_VID. Recompile the source and build the Windows CE image.

You can download and install the kit from http://www.cypress.com/?rID=14321. After the kit contents are installed, browse to the location: Install_root_directory\CY3684_EZ-USB_FX2LP_DVK\1.0\Drivers\cyusbfx1_fx2lp. All the drivers are located in this folder.

In this file, the implementation of read occurs in the ISR. The I2C_Read function sends the Read Command and changes the I2C.PktStatus to I2C_PRIME. The I2C enters the ISR every time a byte of data is successfully transferred when the DONE bit is set High.

When the following section of code is executed for the first time, the data that has been read is stored to I2CPckt.dat and the status is changed to I2C_RECEIVING:

To read more data, the following section of the code is executed the next time the ISR is serviced:

For information on how to increase the ESD protection, refer to page 10 of the document titled High Speed USB Platform Design Guidelines at the USB-IF website www.usb.org.

To download the package, go to www.cypress.com/?rID=57990. Download the file: “FX3 SDK for Linux platforms - This is a Tar archive containing the FX3 firmware libraries and examples, the ARM GNU tool chain, Eclipse IDEs (x64 and x86 versions) and the CyUSB suite for Linux platforms.” Ignore the FX3 firmware files.

Refer to the documents cyusb_linux_user_guide.pdf and cyusb_linux_programmers_guide.pdf, which will get installed in the docs folder along with the software development kit at the location cyusb_linux_1.0.2/ docs.

The following supplies are permanently tied to 1.2V:
VDD
AVDD
VDD_SRAM
U3TXVDDQ
U3RXVDDQ

PCON (SFR 0x87) Bit 7, Serial Port 0 rate control SMOD0 (Table 14-13)

SCON0 (SFR 0x98) Serial Port 0 control (Table 14-11)

SBUF0 (SFR 0x99) Serial Port 0 transmit/receive buffer

EICON (SFR 0xD8) Bit 7, Serial Port 1 rate control SMOD1 (Table 14-12)

SCON1 (SFR 0xC0) Serial Port 1 control (Table 14-14)

SBUF1 (SFR 0xC1) Serial Port 1 transmit/receive buffer

T2CON (SFR 0xC8) Baud clock source for modes 1 and 3 (Table 14-5)

UART230 (0xE608) High-Speed Baud Rate Generator enable (Section 14.3.2)

Note: The registers PCON and EICON include functionalities that are not part of the serial interface.

Features

• Universal Serial Bus (USB) Integration
  • USB 3.0 and USB 2.0 peripherals compliant with USB 3.0 specification 1.0
  • High-speed On-The-Go (HS-OTG) host and peripheral compliant with OTG Supplement Version 2.0
  • Support for battery charging Spec 1.1 and accessory charger adaptor (ACA) detection
• General Programmable Interface (GPIF™ II)
  • Programmable 100-MHz GPIF II enables connectivity to a wide range of external devices
  • 8- and 16- bit data bus
• Mass Storage Support
  • SD 3.0 (SDXC) UHS-1
  • eMMC 4.41
  • System I/O expansion with 2 secure digital I/O (SDIO) ports
• Fully accessible ARM9 with up to 512KB embedded SRAM
• For more, see pdf.

Functional Overview

EZ-USB® FX3S™ is the latest offering in the industry leading FX3™ USB 3.0 peripheral controller family that enables developers to add USB 3.0 device functionality to any system. In addition to USB 3.0 functionality and a powerful ARM core, FX3S’s integrated storage controllers enable you to add support for SD/eMMC memories and SDIO devices to your products without adding any extra controller chip. Based on the proven FX3 Platform, FX3S leverages FX3’s familiar ecosystem and package to reduce your time-to-market and design complexity. FX3S has the fully configurable General Programmable Interface (GPIF™ II), which can interface with virtually any processor, ASIC, Image Sensor or FPGA. The FX3S’s programming flexibility makes it an ideal solution to any USB 3.0 product that wants to differentiate itself while keeping cost and time-to-market down.

Features

• Universal Serial Bus (USB) Integration
• Universal Asynchronous Receiver Transmitter (UART)
• Full device operation from a single voltage supply of 3.3 V or 5 V
• Low power consumption in suspend mode
• Integrated 24 MHz oscillator
• Integrated 3.3 V regulator
• Integrated flash to store device configuration
• Software support for ease of development
• For more, see pdf

Functional Overview

Cypress’s USB-to-UART bridge controller enables seamless PC connectivity for peripherals with UART interface. It integrates a USB 2.0 Full-Speed device controller, UART, voltage regulator, oscillator and flash memory for storing configuration parameters, offering a cost-effective solution. The controller supports bus-powered and self-powered modes, and enables efficient system power management with suspend and remote wake-up signals. It is available in 28-pin SSOP package.

• High performance, low-power USB 2.0 Hub, optimized for low cost designs with minimum Bill-of-material
• USB 2.0 hub controller
• Very low power consumption
• Highly integrated solution for reduced BOM cost
• Downstream port management
• Maximum configurability
• Available in space saving 48-pin (7 × 7 mm) TQFP and 28-pin (5 × 5 mm) QFN packages
• Supports 0 °C to 70 °C temperature range
   

Functional Overview

The Cypress CY7C6563X USB 2.0 Hubs are low power hub solutions for USB which provide maximum transfer efficiency. The CY7C6563X USB 2.0 Hubs integrate 1.5 kohm upstream pull-up resistors for full speed operation and all downstream 15 kohm pull-down resistors and series termination resistors on all upstream and downstream D+ and D- pins. This results in optimization of system costs by providing built-in support for the USB 2.0 specification.

• High-performance, low-power USB 2.0 hub, optimized for low-cost designs with minimum bill-of-material (BOM).
• USB 2.0 hub controller
• Very low-power consumption
• Highly integrated solution for reduced BOM cost
• Downstream port management
• Maximum configurability
• Available in space saving 48-pin (7 × 7 mm) TQFP and 28-pin (5 × 5 mm) QFN packages
• Supports 0 °C to +70 °C temperature range
• For more, see pdf
   

Functional Overview

The Cypress CY7C65642 USB 2.0 Hubs are low-power hub solutions for USB which provide maximum transfer efficiency with no TT multiplexing between downstream ports. The CY7C65642 USB 2.0 Hubs integrate 1.5 kΩ upstream pull-up resistors for full speed operation and all downstream 15 kΩ pull-down resistors and series termination resistors on all upstream and downstream D+ and D– pins. This results in optimization of system costs by providing built-in support for the USB 2.0 specification.

Features

• Universal serial bus (USB) integration
  • USB 3.0 and USB 2.0 peripherals compliant with USB 3.0 specification 1.0
  • 5-Gbps USB 3.0 PHY compliant with PIPE 3.0
  • High-speed On-The-Go (HS-OTG) host and peripheral compliant with OTG Supplement Version 2.0
  • Thirty-two physical endpoints
  • Support for battery charging Spec 1.1 and accessory charger adaptor (ACA) detection
• General Programmable Interface (GPIF™ II)
  • Programmable 100-MHz GPIF II enables connectivity to a wide range of external devices
  • 8-, 16-, and 32-bit data bus
  • As many as16 configurable control signals
• For more, see pdf

Functional Overview

Cypress’s EZ-USB FX3 is the next-generation USB 3.0 peripheral controller, providing integrated and flexible features. FX3 has a fully configurable, parallel, general programmable interface called GPIF II, which can connect to any processor, ASIC, or FPGA. GPIF II is an enhanced version of the GPIF in FX2LP, Cypress’s flagship USB 2.0 product. It provides easy and glueless connectivity to popular interfaces, such as asynchronous SRAM, asynchronous and synchronous address data multiplexed interfaces, and parallel ATA.

Overview

CYRF8935 WirelessUSB NL is Cypress’s third generation of 2.4 GHz low-power RF technology, bringing next level of low-power performance into a small 4 mm x 4 mm footprint. WirelessUSB NL implements a GFSK radio using a differentiated single-mixer, closed-loop modulation design that optimizes power ef_ciency and interference immunity. This also translates into the highest on-air throughput which makes WirelessUSB NL particularly powerful for streaming applications such as audio, along with HID applications such as wireless keyboards, mice and USB dongles.

The CY3668 WirelessUSB NL development kit provides a generic platform for developing wireless applications based on the WirelessUSB NL, enCoRe II and enCoRe V devices. The out-of-box examples that come with this kit also demonstrates the new enhanced agile HID protocol for secure and reliable wireless data transfers.
 

Kit Contents:

• CY3668 bridge/keyboard development boards (2)
• NL modules (2)
• CY3668- enCoRe II module (1)
• CY3668-enCoRe V modules (2)
• 3.3-V LCD (2)
• Power adaptor (2)
• Quick Start Guide
• Resource CD which includes, PSoC Designer, PSoC Programmer, Projects and documentation.

Software Title	Description	Link
PSoC Designer	This kit requires PSoC Designer for development
PSoC Programmer	This kit requires PSoC Programmer for programming

Note: Cypress does not manufacture hard drives. Cypress is not responsible for the recovery of the hard drive. If the information presented in the document does not solve your problem, please contact the HARD Disk Drive Manufacturer for further assistance.

In addition, FX3 provides interfaces to connect to serial peripherals, such as UART, SPI, I2C, and I2S.

FX3 allows you to add SuperSpeed capability to any FPGA-based design. In most applications, FPGA acts as a master and the GPIF II operates in a synchronous Slave FIFO interface.

• Industry standard Philips I2C bus compatible interface
• Master and Slave operation, Multi Master capable
• Only two pins (SDA and SCL) required to interface to I2C bus
• Standard data rate of 100/400 kbps, also supports 50 kbps
• High level API requires minimal user programming
• 7-bit addressing mode
   

The I2C Hardware User Module implements an I2C device in firmware. The I2C bus is an industry standard, two-wire hardware interface developed by Philips®. The master initiates all communication on the I2C bus and supplies the clock for all slave devices. The I2CHW User Module supports the standard mode with speeds up to 400 kbps. No digital or analog user blocks are consumed with this module. The I2CHW User Module is compatible with other slave devices on the same bus.

Features and Overview

• The 32-bit general purpose counter uses four PSoC blocks
• Source clock rates up to 48 MHz
• Automatic reload of period on terminal count
• Programmable pulse width
• Input enables/disables continuous counter operation
• Interrupt option on compare output or terminal count
   

The 32-bit Counter User Module provides a down counter with a programmable period and pulse width. The clock and enable signals can be selected from any system time base or external source. Once started, the counter operates continuously and reloads its internal value from the period register upon reaching terminal count. During each clock cycle, the counter compares the current count to the value stored in the compare register. Each clock cycle, the Counter tests the count against the value of the compare register for either a “less than" or “less than or equal to" condition. The comparator output provides a logic level that may be routed to pins and to other user modules.

• 8-bit general purpose timer uses one PSoC block
• Source clock rates up to 48 MHz
• Automatic reload of period on terminal count
• Capture for clocks up to 24 MHz
• Terminal count output pulse may be used as input clock for other analog and digital functions
• Interrupt option on terminal count, capture (on some devices), or when counter reaches a preset value
   

The 8-Bit Timer User Modules provides a down counter with programmable period and capture ability. The clock and enable signals can be selected from any system time base or external source. Once started, the timer operates continuously and reloads its internal value from the period register upon reaching terminal count. The output pulses high in the clock cycle following terminal count. Events can capture the current Timer count value by asserting the edge-sensitive capture input signal. Each clock cycle, the Timer tests the count against the value of the compare register for either a “Less Than" or “Less Than or Equal To" condition. Interrupts may be generated based on terminal count and compare signals. Some device families offer two additional features. The interrupt options include “interrupt on capture" and, in addition, the compare signal may be routed onto the row buses. If these options are available on your chosen device they will be shown in the Device Editor.

• 32-bit general purpose timer uses four PSoC blocks
• Source clock rates up to 48 MHz
• Automatic reload of period on terminal count
• Capture for clocks up to 24 MHz.
• Terminal count output pulse may be used as input clock for other analog and digital functions
• Interrupt option on terminal count, capture (on some devices), or when counter reaches a preset value
   

The 32-bit Timer User Module provides a down counter with programmable period and capture ability. The clock and enable signals can be selected from any system time base or external source. Once started, the timer operates continuously and reloads its internal value from the period register upon reaching terminal count. The output pulses high in the clock cycle following terminal count. Events can capture the current Timer count value by asserting the edge-sensitive capture input signal. Each clock cycle, the Timer tests the count against the value of the compare register for either a “Less Than" or “Less Than or Equal To" condition. Interrupts may be generated based on terminal count and compare signals. Some device families offer two additional features. The interrupt options include “interrupt on capture" and, in addition, the compare signal may be routed onto the row buses. If these options are available on your chosen device they will be shown in the Device Editor.  

• 24-bit general purpose timer three PSoC blocks
• Source clock rates up to 48 MHz
• Automatic reload of period on terminal count
• Capture for clocks up to 24 MHz
• Terminal count output pulse may be used as input clock for other analog and digital functions
• Interrupt option on terminal count, capture (on some devices), or when counter reaches a preset value
   

The 24-bit Timer User Module provides a down counter with programmable period and capture ability. The clock and enable signals can be selected from any system time base or external source. Once started, the timer operates continuously and reloads its internal value from the period register upon reaching terminal count. The output pulses high in the clock cycle following terminal count. Events can capture the current Timer count value by asserting the edge-sensitive capture input signal. Each clock cycle, the Timer tests the count against the value of the compare register for either a “Less Than" or “Less Than or Equal To" condition. Interrupts may be generated based on terminal count and compare signals. Some device families offer two additional features. The interrupt options include “interrupt on capture" and, in addition, the compare signal may be routed onto the row buses. If these options are available on your chosen device they will be shown in the Device Editor.

Features and Overview

• Industry standard Philips I2C bus compatible interface
• Only two pins (SDA and SCL) required to interface several slave I2C devices
• Standard mode data supports rate of 100 kbps
• High level API requires minimal user programming
• Low level API provided for flexibility

The I2Cm User Module implements a master I2C device in firmware. The I2C bus is an industry standard,  two-wire interface developed by Philips®. An I2C bus master may communicate with several slave devices  using only two wires. The master initiates all communication on the I2C bus and supplies the clock for all slave devices. The I2Cm User Module supports speeds up to 100 kbps. No digital or analog user blocks  are consumed with this module. 

USB has long been the interface of choice between PCs and their peripherals. However, many legacy PCs still use an RS232 serial interface— in some cases referred to as a UART interface—to communicate with their peripherals.

Cypress’s USB-to-UART Bridge Controller enables seamless connectivity between USB and UART devices. It is a low-power, single-chip, plug-and-play solution that is easy to design and reuses existing application software and firmware—accelerating time to market.

Standard 8051 Interrupts:

• IE0(INT0): External Interrupt0
• IE1(INT1): External Interrupt1
• RI_0 & TI_0: USART1 Interrupt
• TF0: Timer0 Overflow
• TF1: Timer1 Overflow

Additional EZ-USB interrupts:

• TF2: Timer2 Overflow
• PF1: Wake up pin(WU2)
• RI_1 & TI_1: UART 1 Transmit and receive
• USBINT(INT2): USB specific Interrupt
• I2CINT(INT3): I2C Bus Interrupt
• IE4(INT4): External Interrupt 4
• IE5(INT5): External Interrupt 5
• IE6(INT6): External Interrupt 6
   

For more, see pdf.

CY3236A-PIRMOTION Rev. A Kit Contents:

• PIR Motion Sensor Board using CY8C27443-24PVXI PSoC(R) device
• 12V Power Supply
• PSoC Designer(TM) and PSoC Programmer CD
• Design Files CD (Schematic, BOM, Gerber Files, PSoC Designer Example Project)

Introduction

Cypress's EZ-USB® FX3 is the next-generation USB 3.0 peripheral controller, providing integrated and flexible features. FX3 has a fully configurable, parallel, general programmable interface called GPIF II, which can connect to any processor, ASIC, or FPGA. It provides easy and glue less connectivity to popular interfaces, such as asynchronous SRAM, asynchronous and synchronous address data multiplexed interfaces, and parallel ATA. FX3 has an embedded 32-bit ARM926EJ-S microprocessor for powerful data processing and for building custom applications. It implements an architecture that enables 375-MBps data transfer from GPIF II to the USB interface. 

Introduction

USB is so commonplace that it has almost completely replaced other communication methods between peripheral devices and a PC. This holds true both for general-purpose devices, such as flash drives and mice, and special-purpose devices for specific applications. According to the standard USB 2.0 specification, USB peripherals do not communicate directly with one another; they may communicate only with a USB host, which fully controls data traffic on the bus. The Cypress EZ-USB FX3 with integrated high-speed USB host controller, along with the USB function and On-The-Go (OTG) capabilities accomplishes two things: It retains the device functions and allows embedded systems to act as a USB host.

1. In the µVision2 Editor, click ‘Options for Target’ and then select the ‘Output’ Tab. Ensure that the following path is described in the ‘ Run User Program #1’:

    

   ..\..\..\Bin\hex2bix -i -f 0xC2 -o fw.iic fw.hex

2. If at power-on-reset, the EZ-USB detects an EEPROM connected to its I2C with the value 0xC2 at address zero, the EZ-USB loads the firmware in EEPROM into an on-chip RAM. It also sets the RENUM bit to ‘1’, causing standard device requests to be handled by the firmware instead of the default USB device.