• Full byte-oriented EEPROM emulation
• Abstracts block-oriented Flash architecture
• Efficient use of memory

• 16-bit general purpose pulse width modulator (PWM) with 8-bit dead band generator, two or three PSoC blocks, respectively
• Phase1 and Phase2 underlapped outputs track the frequency of the generated PWM signal
• Programmable duty cycle
• Programmable dead time
• Dead Band Kill input drives Phase1 and Phase2 outputs low
• Counter clocking up to 48 MHz
• Interrupt option triggered on rising edge of the PWM generated signal or counter terminal count

The 16-bit PWMDB User Module is a pulse width modulator combined with an 8-bit dead band generator.The pulse width modulator provides a programmable period and pulse width input signal to the dead band generator. The dead band generator outputs two under-lapped signals, with programmable dead time at the same frequency as the input signal. When asserted, the Dead Band Kill input drives the Phase1 and Phase2 output signals low.  The clock and enable signals can be selected from several sources. The Phase1 and Phase2 output signals can be routed to the external pin ports or to the global output buses for internal use by other user modules. An interrupt can be programmed to effectively trigger on both edges of the pulse width modulator output.

• Output is digital inverted input
• Requires only one digital block
• Can be used to generate an interrupt on the falling edge of the input

The DigInv User Module is a simple digital inverter. The output is a logical NOT of the input signal.

• Two Digital Buffers
• Input1 can be inverted
• Can be used to generate an interrupt on the rising edge of Output1

• Industry standard Philips I2C bus compatible interface
• Master and Slave operation, Multi Master capable
• Only two pins (SDA and SCL) required to interface to I2C bus
• Standard data rate of 100/400 kbps, also supports 50 kbps
• High level API requires minimal user programming
• 7-bit addressing mode
   

The I2C Hardware User Module implements an I2C device in firmware. The I2C bus is an industry standard, two-wire hardware interface developed by Philips®. The master initiates all communication on the I2C bus and supplies the clock for all slave devices. The I2CHW User Module supports the standard mode with speeds up to 400 kbps. No digital or analog user blocks are consumed with this module. The I2CHW User Module is compatible with other slave devices on the same bus.

• 6-bit resolution
• Voltage output
• Four quadrant multiplication
• 2’s complement, offset binary, and sign/magnitude input data formats
• Sample and hold for analog bus and external outputs
• Update rates up to 250 ksps

The MDAC6 User Module is a 6-bit, four-quadrant multiplying DAC that scales input voltage with digital codes. The MDAC6 translates digital codes to output voltages at an update rate of up to 250k samples per second. The Application Programming Interface (API) supports offset-binary, sign-and-magnitude, and 2’s complement data formats. Offset compensation minimizes conversion error. 

Features and Overview

• The 32-bit general purpose counter uses four PSoC blocks
• Source clock rates up to 48 MHz
• Automatic reload of period on terminal count
• Programmable pulse width
• Input enables/disables continuous counter operation
• Interrupt option on compare output or terminal count
   

The 32-bit Counter User Module provides a down counter with a programmable period and pulse width. The clock and enable signals can be selected from any system time base or external source. Once started, the counter operates continuously and reloads its internal value from the period register upon reaching terminal count. During each clock cycle, the counter compares the current count to the value stored in the compare register. Each clock cycle, the Counter tests the count against the value of the compare register for either a “less than" or “less than or equal to" condition. The comparator output provides a logic level that may be routed to pins and to other user modules.

Features and Overview

• The 24-bit general purpose counter uses three PSoC blocks
• Source clock rates up to 48 MHz
• Automatic reload of period on terminal count
• Programmable pulse width
• Input enables/disables continuous counter operation
• Interrupt option on compare output or terminal count
   

The 24-bit Counter User Module provides a down counter with a programmable period and pulse width. The clock and enable signals can be selected from any system time base or external source. Once started, the counter operates continuously and reloads its internal value from the period register upon reaching terminal count. During each clock cycle, the counter compares the current count to the value stored in the compare register. Each clock cycle, the Counter tests the count against the value of the compare register for either a “less than" or “less than or equal to" condition. The comparator output provides a logic level that may be routed to pins and to other user modules.

• Flexible input sources
• Output signal latching
• Flexible functionality configuration

The Comparator User Module (COMP) provides a digital output representation of the comparison of two signal levels. The input signals can be external signals multiplexed through the analog column mux, internal signals, and fixed or adjustable reference voltages. It provides a number of standard structural options with considerable flexibility in connection, threshold limits, and noise rejection.

The COMP user module is constructed as a MUM (multi user module). The MUM lists the name, brief description, simplified schematic, and input/output waveforms. The MUM schematic is at the "system" level. It does not show physical interconnections.

• 8-bit general purpose timer uses one PSoC block
• Source clock rates up to 48 MHz
• Automatic reload of period on terminal count
• Capture for clocks up to 24 MHz
• Terminal count output pulse may be used as input clock for other analog and digital functions
• Interrupt option on terminal count, capture (on some devices), or when counter reaches a preset value
   

The 8-Bit Timer User Modules provides a down counter with programmable period and capture ability. The clock and enable signals can be selected from any system time base or external source. Once started, the timer operates continuously and reloads its internal value from the period register upon reaching terminal count. The output pulses high in the clock cycle following terminal count. Events can capture the current Timer count value by asserting the edge-sensitive capture input signal. Each clock cycle, the Timer tests the count against the value of the compare register for either a “Less Than" or “Less Than or Equal To" condition. Interrupts may be generated based on terminal count and compare signals. Some device families offer two additional features. The interrupt options include “interrupt on capture" and, in addition, the compare signal may be routed onto the row buses. If these options are available on your chosen device they will be shown in the Device Editor.

• 32-bit general purpose timer uses four PSoC blocks
• Source clock rates up to 48 MHz
• Automatic reload of period on terminal count
• Capture for clocks up to 24 MHz.
• Terminal count output pulse may be used as input clock for other analog and digital functions
• Interrupt option on terminal count, capture (on some devices), or when counter reaches a preset value
   

The 32-bit Timer User Module provides a down counter with programmable period and capture ability. The clock and enable signals can be selected from any system time base or external source. Once started, the timer operates continuously and reloads its internal value from the period register upon reaching terminal count. The output pulses high in the clock cycle following terminal count. Events can capture the current Timer count value by asserting the edge-sensitive capture input signal. Each clock cycle, the Timer tests the count against the value of the compare register for either a “Less Than" or “Less Than or Equal To" condition. Interrupts may be generated based on terminal count and compare signals. Some device families offer two additional features. The interrupt options include “interrupt on capture" and, in addition, the compare signal may be routed onto the row buses. If these options are available on your chosen device they will be shown in the Device Editor.  

• 24-bit general purpose timer three PSoC blocks
• Source clock rates up to 48 MHz
• Automatic reload of period on terminal count
• Capture for clocks up to 24 MHz
• Terminal count output pulse may be used as input clock for other analog and digital functions
• Interrupt option on terminal count, capture (on some devices), or when counter reaches a preset value
   

The 24-bit Timer User Module provides a down counter with programmable period and capture ability. The clock and enable signals can be selected from any system time base or external source. Once started, the timer operates continuously and reloads its internal value from the period register upon reaching terminal count. The output pulses high in the clock cycle following terminal count. Events can capture the current Timer count value by asserting the edge-sensitive capture input signal. Each clock cycle, the Timer tests the count against the value of the compare register for either a “Less Than" or “Less Than or Equal To" condition. Interrupts may be generated based on terminal count and compare signals. Some device families offer two additional features. The interrupt options include “interrupt on capture" and, in addition, the compare signal may be routed onto the row buses. If these options are available on your chosen device they will be shown in the Device Editor.

• Uses the industry standard Hitachi HD44780 LCD display driver chip protocol
• Requires only seven I/O pins
• Routines provided to print RAM or ROM strings
• Routines provided to print numbers
• Routines provided to display horizontal and vertical bar graphs
• Uses a single I/O port
   

The Character LCD User Module is a set of library routines that writes text strings and formatted numbers to a common two or four-line LCD module. Vertical and horizontal bar graphs are supported, using the character graphics feature of these LCD modules. This module was developed specifically for the industry standard Hitachi HD44780 two-line by 16 character LCD display driver chip, but works for many other fourline displays. This library uses the 4-bit interface mode to limit the number of I/O pins required.
 

Features and Overview

• Industry standard Philips I2C bus compatible interface
• Only two pins (SDA and SCL) required to interface several slave I2C devices
• Standard mode data supports rate of 100 kbps
• High level API requires minimal user programming
• Low level API provided for flexibility

The I2Cm User Module implements a master I2C device in firmware. The I2C bus is an industry standard,  two-wire interface developed by Philips®. An I2C bus master may communicate with several slave devices  using only two wires. The master initiates all communication on the I2C bus and supplies the clock for all slave devices. The I2Cm User Module supports speeds up to 100 kbps. No digital or analog user blocks  are consumed with this module. 

PSoC Designer 5.0 SP6 will continue to be available for System Level Design users, and it will co-exist with future PSoC Designer 5.1 releases. However, we are not recommending System Level Design for production designs.

We suggest users to use the latest version of PSoC Designer located here:

www.cypress.com/go/psocdesigner

PSoC Designer 5.0 SP6 supports Internet Explorer 6 through 8, but does not support Internet Explorer 8 Beta or Internet Explorer 9 due to compatibility issues.

To Install PSoC Designer 5.0 SP6 users must first have PSoC Programmer installed first. For the latest release of PSoC Programmer please, Click Here

PSoC Designer 5.0 PS6 was tested using Beta version of Windows 7. PSoC Designer 5.0 SP6 is not supported for Windows 7 systems.

To Install:

Shut Down any currently running instances of PSoC Designer.

If an earlier service pack of PSoC Designer 5.0 is currently installed, uninstall it. To do this please navigate to Start>Control Panel>Add or Remove Programs.

• Install latest PSoC Programmer.
• Install PSoC Designer 5.0 SP6 by running the installed in the downloads table below.”

Note to HI-TECH Compiler Users:

There are new devices in this release. To compile projects containing these devices with the HI-TECH compiler, you must manually update the psoc.ini file. The HI-TECH psoc.ini file is found in the HI-TECH installation folder. The default location of the psoc.ini is here:

C:\Program Files\HI-TECH Software\HCPSOC\PRO\9.61\dat\psoc.ini

The default location of the replacement psoc.ini file that adds support for the new devices is here:

C:\Program Files\Cypress\Common\CypressSemiBuildMgr\tools\psoc.ini

PSoC Programmer: The latest version of PSoC Programmer must be installed along with PSoC Designer. For the latest release please navigate to the PSoC Programmer web page: Click Here

PSoC Designer: User Guides - Click Here

PSoC Designer Archive - Click Here

• 10 mV hysteresis that can be enabled or disabled
• Programmable output polarity
• Programmable speed and power
• Direct output connection available to trip input of the HYSTCTRL User Module blocks
• Direct input selection from DualDAC8HW UM to achieve a precise, programmable comparator reference

The CMPHW User Module (UM) is a dedicated hardware comparator block (not the comparator block implemented with PSoC analog and digital blocks) that compares two input signals and switches the output to indicate the larger signal. The comparator has rail-to-rail operation with a 10 mV hysteresis that can be enabled or disabled.This UM can operate in both fast and slow mode, a useful feature depending on the end application. For example, a typical over-current protection circuit is designed to respond faster to changes in the output variable and therefore would benefit from the fast mode feature. On the other hand, an application where the comparator is used to sense a slow changing variable, such as temperature, can benefit from the slow mode of this comparator using less system power.

• Operates with a high common mode voltage of 36V
• Possesses high common mode rejection ratio
• Gives bandwidth adjustment capability with high bandwidth
• Gives low input offset currents and low offset voltages
• Highly accurate output

The high side current sense amplifiers (CSA) give a differential sense capability to measure the voltage across current sense resistors in power systems.

Cypress Semiconductor's CY3269N Lighting Starter Demonstration Kit leverages two key Cypress technologies for development of intelligent LED lighting fixtures. At the simple touch of a finger, users can illuminate anything from an entire room to a large architectural lighting display with warm, neutral, or cool white light of variable color temperature. Users can create rich and vibrant colored light to set moods, accents, and customize the overall feel of any venue with little effort. The CY3269N Lighting Starter Demonstration Kit showcases two world-leading Cypress technologies: EZ-Color and CapSense, which enable tunable white light control, color mixing, and capacitive touch sensing.

CY3269N Kit Contents:

• CY3269N Lighting Starter Demonstration board
• 9 V Battery
• Quick Start Guide

Software Title	Description	Link
PSoC Designer	This kit requires PSoC Designer for development
PSoC Programmer	This kit requires PSoC Programmer for programming

Features and Overview

• Supports SD, miniSD, microSD/TransFlash, MMC, RS-MMC/MMCmobile, and MMCplus.
• Handles PC FAT16/32, DOS, and Windows files with short filenames (DOS 8.3 format).
• Opens multiple files for read and write operations.
• Supports multiple file random access.
• Allows PSoC to access 2 Gb of flash storage space.
   

The SDCard User Module allows you to access PC compatible files on six different flash card form factors without the need to know the "nuts and bolts" of either file access or the flash card interface.

The SDCard User Module allows basic operation with as few as four PSoC pins. Depending upon the card type and card socket, you can use additional pins to support write protect, card insert, and others.

This article discusses the similarities and differences between designing white light applications versus colored light applications, the challenges facing LED system design, and some powerful (even code-free) options available today for aiding designers in solving these issues. To read more, click the download link above or visit Planet Analog.

To read more on this topic, click the download link above or view the full article on Planet Analog.

In Figures 1 and 2, points A and B are the Rsense pads and points C and D are the input pins to the current sensing amplifier, CSPx (+ve) and CSNx (-ve) respectively.

Figure 1 shows a correct design.The sense lines are connected to the inner edges of the Rsense pads. Also, traces A-C and B-D are symmetrical with the same length and thickness This ensures that the voltage across Rsense is the same as the difference between. CSPx and CSNx.

Figure 1: Correct Design

Figure 2 shows an incorrect design. If you tried to maintain 100mV across the sense lines, the actual voltage across Rsense would be less than 100 mV due to the voltage drop across A-X and B-Y. The measured current would be less than actual.

Figure 2: Incorrect Design

For further information refer to PowerPSoC(R) – Hardware Design Guidelines.

• Nominal 10-bit resolution
• Selectable resolution from 2-bit to 12-bit
• Input range 0 to Vdd-1
• Allows a coarse temperature measurement: range of -40°C to +125°; accuracy of ± 40°C with resolution ± 2°C
   

The ADC10 User Module implements a Single Slope A/D Converter that generates up to a 12-bit, full scale output (0 to 4095 count range). Although capable of generating a 12-bit output, it has only 10 effective bits of resolution. Further resolution is achieved by averaging multiple samples.

Please contact Innovatech Switching Power India Pvt. Ltd. to buy evaluation boards shown in this applicaiton note. Please refer http://ispipl.com/contact_us for more information.

The video demonstrates a PowerPSoC based battery charger and LED controller for standalone solar electric systems.

PowerPSoC product family provides a highly integrated platform for designing intelligent LED driver circuits that can be used in small form factors such as MR-16. This application note describes the design of a DMX512-enabled LED driver circuit for MR-16 using PowerPSoC. The application note also gives a top level description of the MR-16 fixture and the LED driver board reference design. It also briefly explains the board bring up and operation procedure. The application has an associated code example, which has sample firmware for multicolor lamps and tunable white light systems with DMX512 interface using PowerPSoC. A brief descirpion of the code example is also included in the applicaiton note.

PowerPSoC(R) - Designing LED Driver Circuits For MR-16 Lamps With DMX-512 Interface

• Nlradio.asm
• Nlradio.h
• Nlradio.inc
• Nlspi.asm

This document describes the APIs exposed by the WUSB-NL driver.

The WUSB-NL radio driver is used in wireless mouse, keyboard, and bridge application software stacks. The WUSB-NL radio driver is modular and can be used as a library. The API exported by this module is explained in this document.

• Supports Serial Peripheral Interconnect (SPI) Slave protocol
• Supports protocol modes 0, 1, 2, and 3
• Selectable input sources for MOSI, SCLK, and ~SS
• Selectable output routing for MISO
• Programmable interrupt on SPI done condition
• SS may be firmware controlled

The SPIS User Module is a Serial Peripheral Interconnect Slave. It performs full duplex synchronous 8-bit data transfers. SCLK phase, SCLK polarity, and LSB First can be specified to accommodate most SPI protocols. The SPIS PSoC block has selectable routing for the input and output signals, and programmable interrupt driven control. Application Programming Interface (API) firmware provides a highlevel programming interface for either assembly or C application software.

• 8-bit resolution
• Voltage output
• 2’s complement, offset binary and sign/magnitude input data formats
• Sample and hold for analog bus and external outputs
• Update rates to 125 ksps

The DAC8 User Module translates digital codes to output voltages. The DAC8 translates digital codes to output voltages at an update rate of up to 125k samples per second. The Application Programming Interface (API) supports offset-binary, 2’s complement, and register-image data formats. Offset compensation is employed to minimize error.   

• Range of -40°C to 85°C
• Accuracy of ± 20°C with no calibration
• Single PSoC block implementation
• 8-bit 2’s complement output in degrees Celsius
   

The FlashTemp User Module gives a coarse temperature measurement for the bFlashWriteBlock routine, which varies its programming pulse width with temperature. A single switch capacitor analog block is used and requires no calibration. The output of the FlashTemp User Module is the junction temperature of the PSoC microcontroller in a 2’s complement format, with 1 count per degree Celsius.

• Highly efficient boost control operation
• Fast hysteretic control loop
• Software integral loop for current regulation
• Easy-to-implement optional current protection
   

• 7- to 13-bit resolution, 2’s complement
• Sample rate from 4 to 10,000 sps
• Input range Vss to Vdd
• Integrating converter provides good normal-mode rejection
• Internal or external clock
   

The ADCINCVR is an integrating ADC with an adjustable resolution between 7 and 13 bits. It can be configured to remove unwanted high frequencies by optimizing the integrate time. Input voltage ranges, including rail-to-rail, may be measured by configuring the proper reference voltage and analog ground. The output is 2’s complement based on an input voltage between –Vref and Vref centered at AGND.

Sample rates from 4 to 10,000 sps are achievable depending on the selection of the resolution, DataClock, and CalcTime parameters.

The programming interface allows you to specify the number of sequential samples to be taken or to select continuous sampling. The CPU load varies with the input level. For example, when Vin = Vref, there are 5076 CPU cycles (maximum 13 bit). When Vin = AGND, there are 2708 CPU cycles (average 13 bit). When Vin = -Vref, there are 340 CPU cycles (minimum 7-13 bit).

• 6 to 14-bit resolution
• Optional synchronous 8-bit PWM output
• Optional differential Input
• Signed or unsigned data format
• Sample rate up to 15.6 ksps (6-bit resolution)
• Input range defined by internal and external reference options
• Internal or external clock
   

Note: If this user module is used with the 29K family, it consumes an extra 6 mA. As an alternative, use the ADCINCVR user module.

The ADCINC is a differential or single input ADC that returns a 6 to 14 bit result. The maximum DataClock frequency is 8 MHz, but 2 MHz is the maximum frequency recommended for improved linearity. This ADC may only be placed one time, due to its implementation which uses the hardware decimator rather than a digital block. This is the most resource efficient ADC. A 2nd order modulator may be implemented with an additional switch-capacitor block, allowing better linearity with an 8 MHz DataClock.

• 6-bit resolution
• Single PSoC block
• Conversion time of 25 μs, typical
• API optimized to help minimize aperture jitter
   

The SAR6 User Module converts an input voltage to a digital code, using a single switched-capacitor analog PSoC block. It features typical conversion times of 25 μs, producing a 2’s complement value in the closed interval of [-32..+31] for each sample. The SAR6 Application Programming Interface (API) provides a time-equalized function, so that synchronous sampling can be managed by a timing loop for minimum aperture jitter.

• Fully parameterized for custom development
• Custom block for prototypes
• Selectable power settings
   

The SCBLOCK User Module is an analog switched capacitor (SC) PSoC block that is fully parameterized. This allows for the creation of custom switched capacitor functions. Application Programming Interfaces (APIs) are included for SCBLOCK power management.

Features and Overview

• 6-bit to 14-bit resolution
• Data in unsigned or signed 2’s complement formats
• Maximum sample rates of 65,500 sps at 6 bit resolution, 7812 sps at 14-bit resolution
• Sinc2 filter fully implemented in hardware reduces CPU overhead and anti-alias requirements
• 1st-Order or 2nd-Order modulator for improved signal-to-noise ratio, user selectable
• Input range defined by internal and external reference options
• Requires no digital blocks

• Provides a global shadow register for a selected port data register
• Generates a set of macros for port pin manipulation
• Prevents corruption of GPIO pin settings during CPU control of GPIO
• Cooperates with other user modules that allocate shadow registers.
   

• Choice between three implementations:
  • FSK modem only
  • FSK modem with proprietary Powerline Communication Protocol
  • FSK modem with proprietary Powerline Communication Protocol along with built-in communication to external microcontrollers through I2C
• Bidirectional half-duplex communication
• Supports master and slave and peer-to-peer network topologies
• Multiple masters on powerline network
• Each device has a built in unique 64-bit address
• For more, see pdf

The Powerline Transceiver (PLT) User Module gives a control interface within the PLC device for communicating between the application and the FSK Modem. The application may either run on the PLC device or on a separate device that communicates with the PLC device through I2C, RS232, or SPI. The I2C communication implementation is available as a user module option and does not require additional coding to operate.

• User-programmable corner frequency and damping ratio
• Corner frequency ranging from 20 Hz to 180 kHz
• Automated design for Bessel, Butterworth, and Chebychev filters
• User-selected oversample ratio (OSR), ratio of sample frequency to corner frequency
• Built-in polarity control
• Built-in modulator for use in full-wave detection and frequency translation

The LPF2 User Module uses two switched-capacitor blocks to implement a general-purpose second order low-pass filter. Corner frequency and damping ratio are functions of the ratios of programmable on-chip capacitors and clock frequency; no external components are required. Selects your filter characteristics and clock frequency; capacitor and clock divider values are automatically calculated in the design tool (wizard). Multiple low-pass filters can be cascaded or combined with band-pass filters to achieve more complex transfer functions.

• User programmable center frequency, Q, and Gain
• No external components required
• Center frequency 20 Hz to 200 kHz
• Automated design using wizard
• User-selected over-sample ratio (OSR), a ratio of sample frequency to corner frequency
• Built-in polarity control
• Built-in comparator output for use in full-wave detection and communication applications
• Built-in modulator for use in frequency translation and signal generation

The BPF2 User Module uses two switched-capacitor blocks to implement a general-purpose second order band-pass filter. Center frequency and Q are functions of the ratios of programmable on-chip capacitors and clock frequency; no external components are required. The user selects filter characteristics and clock frequency. Capacitor and clock divider values are automatically calculated in the design tool (wizard). BPF2 can be cascaded or combined with other filter types to make more complex filter structures.

Features and Overview

• Flexible input sources
• Direct connection to digital PSoC block and interrupt

The CMP User Module gives a comparison of two selectable inputs. Both inputs have the same set of possible connections to choose from. This enables you to select the polarity of the output.

• Low voltage offset path from PMux to analog output bus
• Provides a method to route internal references (AGND, REFHI, REFLO) to an external pin
• Provides a 4 to 1 analog mux for switch capacitor blocks such as ADCs and filters, if used with the AMux4 User Module
• Signals from PMux through test mux may be rail-to-rail
• Provides a method to route external analog inputs directly to the analog output bus
   

The RefMux User Module switches one of three internal references (AGND, REFLO, or REFHI) to the analog output bus. Additionally, the output of the Continuous Time (CT) block PMux multiplexer can be selected. The RefMux User Module makes use of the TestMux in a CT block. These signals may be routed to a switch capacitor block on the bottom analog row or buffered and routed to an external pin. If used in conjunction with the AMux4 User Module, they form a four input analog multiplexer to route signals from one of four pins to the analog output bus. 

• 6-bit resolution with 32X oversampling to 14-bit resolution with 256X oversampling
• Data in unsigned or signed 2’s complement formats
• Maximum sample rates of 65,500 sps at 6 bit resolution, 7812 sps at 14-bit resolution
• Sinc² filter fully implemented in hardware reduces CPU overhead and anti-alias requirements
• 1st-Order or 2nd-Order modulator, user selectable
• Input range defined by internal and external reference options
• Optional synchronized PWM Output

The DelSig is an integrating converter, requiring from 32 to 256 integration cycles to generate a single output sample. Changing multiplexed inputs, invalidates the first two samples following the change.

Features and Overview

• 16-bit general purpose timer uses two PSoC blocks
• Source clock rates up to 48 MHz
• Automatic reload of period on terminal count
• Capture for clocks up to 24 MHz
• Terminal count output pulse may be used as input clock for other analog and digital functions
• Interrupt option on terminal count, capture (on some devices), or when counter reaches a preset value
   

The 16-bit Timer User Modules provides a down counter with programmable period and capture ability. The clock and enable signals can be selected from any system time base or external source. Once started, the timer operates continuously and reloads its internal value from the period register upon reaching terminal count. The output pulses high in the clock cycle following terminal count. Events can capture the current Timer count value by asserting the edge-sensitive capture input signal. Each clock cycle, the Timer tests the count against the value of the compare register for either a “Less Than" or “Less Than or Equal To" condition. Interrupts may be generated based on terminal count and compare signals. Some device families offer two additional features. The interrupt options include “interrupt on capture" and, in addition, the compare signal may be routed onto the row buses. If these options are available on your chosen device they will be shown in the Device Editor. 

• Flexible memory map
• Device reprogramming without engineering tools
• Product resident reprogramability
• Communication interface integrated to minimize code overhead
• Field deployment of firmware upgrades
• USB Full Speed device interface driver
• Support for interrupt and control transfer types
• Setup wizard for easy and accurate descriptor generation
• Runtime support for descriptor set selection
• Optional USB string descriptors
• Optional USB HID class support

• The 8-bit general purpose counter uses one PSoC block
• Source clock rates up to 48 MHz
• Automatic reload of period on terminal count
• Programmable pulse width
• Input enables/disables continuous counter operation
• Interrupt option on compare output or terminal count
   

The 8-Bit Counter User Module provides a down counter with a programmable period and pulse width. The clock and enable signals can be selected from any system time base or external source. Once started, the counter operates continuously and reloads its internal value from the period register upon reaching terminal count. During each clock cycle, the counter compares the current count to the value stored in the compare register. Each clock cycle, the Counter tests the count against the value of the compare register for either a “less than" or “less than or equal to" condition. The comparator output provides a logic level that may be routed to pins and to other user modules. Most PSoC device families also permit the terminal count output to be routed in the same manner.

• The 16-bit general purpose counter uses two PSoC blocks
• Source clock rates up to 48 MHz
• Automatic reload of period on terminal count
• Programmable pulse width
• Input enables/disables continuous counter operation
• Interrupt option on compare output or terminal count
   

The 16-bit Counter User Modules provide a down counter with a programmable period and pulse width. The clock and enable signals can be selected from any system time base or external source. Once started, the counter operates continuously and reloads its internal value from the period register upon reaching terminal count. During each clock cycle, the counter compares the current count to the value stored in the compare register. Each clock cycle, the Counter tests the count against the value of the compare register for either a “less than” or “less than or equal to” condition. The comparator output provides a logic level that may be routed to pins and to other user modules. Most PSoC device families also permit the terminal count output to be routed in the same manner. If your device has this ability, it is shown in the device editor. An interrupt can be programmed to trigger when the counter reaches the terminal count or when the comparator (primary) output is asserted.

• Selectable input
• Selectable output (with row interconnect)
• Selectable clock up to 48 MHz
• Data input can be inverted
• Data output is active low
• Available 8, 16, 24, 32-bit Relax Time 
   

The OneShot User Module is a device that produces a single pulse in response to an input signal. It can be used to reshape short input pulses and generate single pulses with a required duration.

• Hardware implementation of IrDA low-speed, physical-layer transmitter
• Data bit rate selectable to a maximum transmit rate of 115.2 kbps
• Optional interrupt on transmit buffer empty

• Hardware implementation of IrDA receiver
• Data format compliant with IrDA data format
• Data bit rate selectable to a maximum receive rate of 115.2 kbps
• Data framing consists of start and stop bits
• Optional interrupt on receive register full
• Overrun and framing error detection

• Burst rates up to 6 Mbits/second
• RS-232 data-format compliant with framing consisting of start, optional parity, and stop bits
• Serial data format with even, odd, or no parity
• Optional interrupt receive register full condition
• Automatic framing, overrun, and parity error detection
   

The RX8 User Module is a RS-232 data-format compliant 8-bit serial receiver with programmable clocking and selectable interrupt or polling control operation. The format of the received data consists of a start bit, an optional parity bit, and a trailing stop bit. Receiver firmware is used to initialize the device, read the received byte, and detect error conditions.

• Requires only two I/O pins to interface multiple slave devices
• Functions provided support reading and writing of both bits and bytes
• Function provided for CRC-8 data integrity checking
• Optional CRC-16 function for iButton® data integrity checking
• Optional functions provided for performing One-Wire search for handling multiple devices
• Optional functions provided for overdrive speed supported by some One-Wire devices
• Optional functions provided for parasite power supported by some One-Wire devices

The OneWire User Module is a set of library routines that read and write data as a master using the Maxim Integrated Products 1-Wire® protocol. A One-Wire master may communicate with one or many slave devices using only one signal wire and a ground. The master initiates all data transfers.

• Does not require digital blocks
• Selectable 8, 16, or 32-bit tick counter
• Three types of timer functions.

The SleepTimer User Module provides basic timing functions without the use of valuable digital blocks. This user modules makes use of the standard sleep timer to create a variety of timing functions that are often useful in a project.

• Scan 1 to 46 capacitive sensors.
• Sensing possible with up to a 15 mm glass overlay.
• Proximity detection to 20 cm with a wire-based sensor.
• High immunity to AC mains noise, EMC noise, and power supply voltage changes.
• Supports different combinations of independent and slide capacitive sensors.
• Double slide sensor physical resolution using diplexing.
• Increase slide sensor resolution using interpolation.
• Touchpad support with two slide sensors.
• Sensing support through high resistive conductive materials (ITO films for example).
• Shield electrode support for reliable operation in the presence of water film or droplets.
• Guided sensor and pin assignments using the CSD Wizard.
• Integrated baseline update algorithm for handling temperature, humidity, and electrostatic discharge (ESD) events.
• Easily adjustable operational parameters.
• PC GUI application support for raw data monitoring and parameter optimization in real time.
   

The Capacitive Sensing using a Sigma-Delta Modulator (CSD) provides CapSense® functionality using the switched capacitor technique with a sigma-delta modulator to convert the sensing switched capacitor current to digital code.

ICE Debugging Support for non-QFN CY8CLED08 EZ-Color HB LED Controllers in a Prototype System or PCB

CY3250-LED08 Kit Contents:
 

• One (1) CY8CLED08 ICE Pod
• One (1) Flex Cable
• Two (2) 28-SSOP Pod Feet
• Two (2) CY8CLED08-28PVXI
• One (1) 28-pin Mask

Hardware Description:

The ICE pod provides the interconnection between the CY3215-DK In-Circuit Emulator via a flex cable and the target EZ-Color device in a prototype system or PCB via package-specific pod feet. Two (2) 28-SSOP pod feet included but all other package feet sold separately.

• 16-bit general purpose pulse width modulator uses two PSoC blocks
• Source clock rates up to 48 MHz
• Automatic reload of period for each pulse cycle
• Programmable pulse width
• Input enables/disables continuous counter operation
• Interrupt option on rising edge of the output or terminal count
   

The 16-bit PWM User Module is a pulse width modulator with programmable period and pulse width. The clock and enable signals can be selected from several sources. The output signal can be routed to a pin or to one of the global output buses, for internal use by other user modules. An interrupt can be programmed to trigger on the rising edge of the output or when the counter reaches the terminal count condition.   

• 8 -bit general purpose pulse width modulator uses one PSoC block
• Source clock rates up to 48 MHz
• Automatic reload of period for each pulse cycle
• Programmable pulse width
• Input enables/disables continuous counter operation
• Interrupt option on rising edge of the output or terminal count
   

The 8-bit PWM User Module is a pulse width modulator with programmable period and pulse width. The clock and enable signals can be selected from several sources. The output signal can be routed to a pin or to one of the global output buses, for internal use by other user modules. An interrupt can be programmed to trigger on the rising edge of the output or when the counter reaches the terminal count condition.

• 8-bit general purpose pulse width modulator (PWM) with an 8-bit dead band generator consumes two PSoC blocks
• Phase1 and Phase2 underlapped outputs track the frequency of the generated PWM signal
• Programmable duty cycle
• Programmable dead time
• Dead Band Kill input drives Phase1 and Phase2 outputs low
• Counter clocking up to 48 MHz
• Interrupt option triggered on rising edge of the PWM generated signal or counter terminal count

The 8-bit PWMDB User Module is a pulse width modulator combined with an 8-bit dead band generator. The pulse width modulator provides a programmable period and pulse width input signal to the dead band generator. The dead band generator outputs two under-lapped signals, with programmable dead time at the same frequency as the input signal. When asserted, the Dead Band Kill input drives the Phase1 and Phase2 output signals low. The clock and enable signals can be selected from several sources. The Phase1 and Phase2 output signals can be routed to the external pin ports or to the global output buses for internal use by other user modules. An interrupt can be programmed to effectively trigger on both edges of the pulse width modulator output.

Features and Overview

• The USBUART Device uses a USB interface to emulate a COM port.
• UART-like high level functions are available on the PSoC device side.
   

Functional Description

Many embedded applications use the RS-232 interface to communicate with external systems such as PCs, especially when debugging. But in the PC world, the RS-232 COM port will soon disappear from most new computers, leaving USB as the replacement for serial communication. The simplest way to migrate a device to USB is to emulate RS-232 over the USB bus. The primary advantage of this method is that PC applications use the USB connection as an RS-232 COM connection, making it very simple to debug. This method uses a standard Windows® driver that is included with all versions Microsoft® Windows from Windows 98SE through Windows XP.

• USB Full Speed device interface driver
• Support for interrupt and control transfer types
• Setup wizard for easy and accurate descriptor generation
• Runtime support for descriptor set selection
• Optional USB string descriptors
• Optional USB HID class support
   

• Programmable dimming resolution
• Programmable output frequencies
• Dedicated DMM module frees PSoC core digital blocks for other uses
   

• Highly efficient hysteretic current-mode buck converter
• 50 kHz to 2 MHz effective switching frequency range
• Ideal topology for LED applications
• 4 independent channels
• Independent configurable linear and PWM dimming
• Optional current or temperature protection

The Floating Load Buck Regulator User Module (FLBUCK) allows you to create a fully functional LED driver with dimming and temperature protection based on a current mode buck converter. It also can be used as a general purpose buck converter that regulates the output current, not the voltage.

• Programmable resolution up to 16 bits
• Programmable output frequencies up to 48 MHz
• Dedicated PWM UM frees PSoC core digital blocks for other uses
• Automatic reload of period for each pulse cycle
• Interrupt option on rising edge of the output or terminal count
• Precise PWM phase control to reduce system current edges
   

The PWM16HW User Module (UM) features a Counter and a Pulse Width register. A comparator output asserts when the count value is less than or equal to the value in the Pulse Width register.

Features and Overview

• Hardware driver for a SPI-based CyFi™ radio transceiver
• Operates in the unlicensed worldwide Industrial, Scientific, and Medical (ISM) band (2.400 GHz–2.483 GHz)
• Supports two transmission modes (8DR and GFSK)
• DSSS data rates up to 250 Kbps, GFSK data rate of 1 Mbps
• DSSS technology provides robust noise immunity
• Selectable frequency, TX power and framing parameters (Length, CRC16, Auto ACK)
• Receive Signal Strength Indication (RSSI)
• Integrated power amplifier provides up to +4 dBm TX power
• Output power control range of 34 dB in 7 steps.
• Supports multiplexing of the IRQ and MOSI functions on the MOSI pin for reduced pin consumption.
   

• Supports Serial Peripheral Interconnect (SPI) Master protocol
• Supports SPI clocking modes 0, 1, 2, and 3
• Selectable input sources for clock and MISO
• Selectable output routing for MOSI and SCLK
• Programmable interrupt on SPI-done condition
• SPI Slave devices can be independently selected

• 14-bit resolution, 2’s complement
• Sample rate from 2 to 120 sps
• Input range from Vss to Vdd
• Integrating converter provides good normal mode rejection
• Internal or external clock

The ADCINC14 is an integrating ADC with 14 bits of resolution. It can be configured to remove unwanted high frequencies by optimizing the integrate time. Input voltage ranges, including rail-to-rail, may be measured by configuring the proper reference voltage and analog ground. The result format is selectable between signed or unsigned, based on an input voltage between -Vref and Vref centered at AGND.

Sample rates from 2 to over 120 sps are achievable, depending on the selection of the DataClock and CalcTime parameters. The programming interface allows you to specify the number of sequential samples to be taken or to select continuous sampling. The CPU load varies with the input level. For example, when Vin = Vref, there are 9832 CPU cycles (maximum 13 bit). When Vin = AGND, there are 5076 CPU cycles. When Vin = -Vref, there are 360 CPU cycles.

Features and Overview

• 9-bit resolution
• Voltage output
• 2’s complement, offset binary and sign/magnitude input data formats
• Sample and hold for analog bus and external outputs
• Update rates 125 ksps
   

The DAC9 User Module translates digital codes to output voltages. It translates digital codes to output voltages at an update rate of up to 125k samples per second. The Application Programming Interface (API) supports offset-binary, 2’s-complement, and register-image (sign-and-magnitude) data formats for maximum flexibility. Offset compensation is employed to minimize conversion error. 

• Samples two inputs simultaneously
• 8-bit resolution
• 2’s complement or unsigned result
• Sample rates from 122 to greater than 7600 sps
• Multiple input ranges including Vss to Vdd
• Integrating Converter provides good normal mode rejection
• Sample rate may be changed dynamically to sync to input signal
• Internal or external clock

The DualADC8 is a dual input integrating 8-bit Analog to digital converter. It can be configured to remove unwanted high frequencies by optimizing the integrate time. Input voltages within 40 mV or less, of the supply rails may be measured by configuring the proper reference voltage and analog ground. The output is configurable 2’s complement or unsigned chars based on an input voltage between –Vref and Vref centered at AGND.

• User-programmable gain from 2 to 16 with a two opamp topology
• User-programmable gain up to 93 for the three opamp topology (CY8C29/27/24xxx, CY8C23x33, CY8CLED04/08/16, CY8CLED0xD, CY8CLED0xG, CY8CTST120, CY8CTMG120, CY8CTMA120, CY8C28x45, CY8CPLC20, CY8CLED16P01, CY8C28x43, CY8C28x52 families only)
• High impedance differential inputs
• Single-ended output
• Selectable reference with the two opamp topology

The INSAMP User Module provides a standard two opamp instrumentation amplifier circuit topology and, for the CY8C29/27/24xxx, CY8C23x33, CY8CLED04/08/16, CY8CLED0xD, CY8CLED0xG, CY8CTST120, CY8CTMG120, CY8CTMA120, CY8C28x45, CY8CPLC20, CY8CLED16P01, CY8C28x43, CY8C28x52 families of PSoC devices, a standard three opamp topology. This amplifier has high input impedance, good rejection of common mode signals, and wide bandwidth.

Features and Overview

• 16-bit timer uses two PSoC blocks
• Source clock rates up to 24 MHz
• Automatic reload of period on terminal count
• Use terminal count output pulse as input clock for other analog and digital functions
• Interrupt on terminal count and capture
   

The16-bit TachTimer User Module provides down counters with programmable period and capture ability. You can select the clock and enable signals from any system time base or external source. Once started, the timer operates continuously and reloads its internal value from the period register when it reaches terminal count. The output pulses high in the clock cycle after terminal count. Events can capture the current TachTimer16 count value by asserting the edge sensitive capture input signal. In each clock cycle, the TachTimer16 tests the count against the value of the compare register for either a less-than or lessthan- or-equal-to condition. Interrupts are generated based upon terminal count and compare signals. The compare signal may be routed onto the row buses. The main between the TachTimer16 User Module and the Timer16 User Module is that the TachTimer16 provides both terminal count and capture interrupts. Timer16 gives you a choice of one or the other, but not both. The MSB block is the source for terminal count interrupt and the LSB block provides the capture interrupt. Another difference between the Timer 16 and the TachTimer16 is that the TachTimer16 has no parameter to choose the interrupt type. Interrupt types for both MSB and LSB are hard coded.

• Samples two inputs simultaneously
• 7- to 13-bit resolution
• 2’s complement or unsigned integer
• Sample rates from 4 to greater than 10,000 sps
• Multiple input ranges including Vss to Vdd
• Integrating Converter provides good normal mode rejection
• Internal or external clock
   

The DualADC User Module is a dual input incremental ADC with an adjustable resolution between 7 and 13 bits. It can be configured to remove unwanted high frequencies by optimizing the integrate time. Input voltage ranges, including rail-to-rail, may be measured by configuring the proper reference voltage and analog ground. The output can be configured as 2’s complement or unsigned integer. The DualADC is ideal for applications that require simultaneous sampling of two signals, such as power measurement. As with other PSoC ADCs, signals to both inputs may be multiplexed. The CPU load varies with the input level. For example, when Vin = Vref, there are 10,014 CPU cycles (maximum 13 bit). When Vin = AGND, there are 5,278 CPU cycles (average 13 bit). When Vin = -Vref, there are 542 CPU cycles (minimum 7-13 bit).

• CY8C26/25xxx: thirty-one user-programmable gain settings with a maximum gain of 16.0.
• All other PSoC Devices: thirty-three user-programmable gain settings with a maximum gain of 48.0.
• High impedance input
• Single-ended output with selectable reference
   

The PGA User Module implements an opamp based non-inverting amplifier with user-programmable gain. This amplifier has high input impedance, wide bandwidth, and selectable reference.

• Flexible clocking options
• Analog output
• Runs in background to allow system control while dialing (configuration option)
• Runs in foreground to minimize use of RAM (configuration option)
• Tones can be output continuously under program control
• Automatically adds configured tone spacing to all output tones
• Tone duration can be configured
• Output capable of -1.7 dBm un-amplified into 600 ohm load, and up to +3.1 dBm amplified drive
• Output driver capable of driving 32 ohm load at 5 Vrms

The DTMFDialer User Module is a Dual Tone Multiple Frequency signal generator. It provides a 6-bit, 2.6 volt full-scale analog output, centered around AGND. The output is a pair of simultaneously generated table sinusoids (tones) that are updated at a user-selectable update frequency. Selection of the update frequency causes a trade-off between CPU loading and signal distortion. Output tone generation is done in an interrupt routine to minimize sample skew and related distortion. Configuration options provide the ability to make design trade-off between RAM consumption and other operational features. 

• High impedance input
• Input signals may be rail-to-rail
• May be used with RefMux to multiplex input signals to switch capacitor block
• Programmable control of input source

The AMux4 User Module provides a four input analog signal multiplexer to a Continuous Time (CT) block that can be controlled programmatically by way of an API. One of four input signals may be selected to the input of the amplifier in the CT block. These input signals are connected to fixed ports, depending on which column this user module is placed. This module can also be used in conjunction with a RefMux to route the multiplexed signals to the analog column bus. 

• 2 to 16-bit CRC generator
• Data input clocking up to 48 MHz
• Programmable polynomial
• Programmable seed value
• Serial data in, parallel result out

The CRC16 User Module computes a 2 to 16-bit cyclical redundancy check (CRC) algorithm on an input serial data stream. The polynomial can be defined to implement CRC functions, such as the CRC-16 or CCITT algorithm. A seed value can be specified to initialize the starting data value.

Features and Overview

• Programmable threshold
• Direct connection to digital PSoC block and interrupt
   

The CmpLP User Module provides a comparison of an input from the input column MUX against a programmable reference threshold. Its only output is the column comparator bus.

Features and Overview

• Selectable input
• Selectable output (with row interconnect)
• Selectable clock, also it can run up to 48 MHz
• Input signal is active low
• Output signal is active low
• Data input can be inverted
• Data output can be inverted
   

• 11-bit resolution
• Data format available in 2’s complement
• Sample rate to 7.8 ksps
• 256X over sampling with sinc2 filter reduces antialias requirements
• Input range defined by internal and external reference options
• Internal or external clock
   

Note: If this user module is used with the CY8C29xxx family, it consumes an extra 6 mA. As an alternate, use the Delsig user module instead.

The DELSIG11 User Module provides an 11-bit output. It is based on a 2.6V full scale input range centered around a user selected AGND, when the reference selection in the global parameter window is set to /- Bandgap. The DELSIG11 supports sample rates from 125 sps to 7.8 ksps, and provides a 2’s complement output. The sample rate is determined by the data clock input and is selectable by the user. Data generated by the DELSIG11 is available in the interrupt routine where the data is collected or through polling functions furnished by the DELSIG11 API.

• High impedance input
• Input signals may be rail-to-rail
• Can be used with RefMux to multiplex input signals to switch capacitor block
• Programmable control of input source

The AMUX8 User Module provides an eight-input-analog-signal-multiplexer to a Continuous Time (CT) block, controlled by an API. One of four input signals may be selected to the input of the amplifier in the CT block. These input signals are connected to fixed ports, depending on which column the user module is placed. The module is also used in conjunction with a RefMux to route the multiplexed signals to the analog column bus.

The AMUX8 User Module is used when the application needs to dynamically select from two or more ports during operation.

• Samples three inputs simultaneously
• 8-bit resolution, two’s complement or unsigned results
• Sample rates from 4 to greater than 10,000 sps
• Maximum input range Vss to Vdd
• Integrating converter provides good normal mode rejection
• Internal or external clock
   

The TriADC8 is a triple input integrating ADC with 8-bits of resolution. It can be configured to remove unwanted high frequencies by optimizing the integrate time. Input voltage ranges, including rail-to-rail, may be measured by configuring the proper reference voltage and analog ground. The output is configurable two’s complement or unsigned integers based on an input voltage between -Vref and Vref centered at AGND.

Sample rates up 5000 sps are achievable, depending on the selection of the Data Clock, and CalcTime parameters. Please refer to the triADC8_SetCalcTime API for setting the CalcTime parameter.

• Samples three inputs simultaneously
• 7- to 13-bit resolution, two’s complement or unsigned integers
• Sample rates from 4 to greater than 10,000 sps
• Maximum input range Vss to Vdd
• Integrating converter provides good normal mode rejection
• Internal or external clock

The TriADC is a triple input integrating ADC with an adjustable resolution between 7 and 13 bits. It can be configured to remove unwanted high frequencies by optimizing the integrate time. Input voltage ranges, including rail-to-rail, may be measured by configuring the proper reference voltage and analog ground. The output is configurable two’s complement or unsigned integers based on an input voltage between -Vref and +Vref centered at AGND.

• 18 user-programmable gain options with a maximum gain of -47.0 for the CY8C29/27/24/23/22xxx device family
• 16 user-programmable gain options with a maximum gain of -15.0 for the CY8C26/25xxx device family
• Single-ended output referenced to analog ground
   

The AMPINV User Module implements a single opamp inverting amplifier. The gain, source and output enable are set by the user from tables of values in the Device Editor.

• Programmable threshold and reference
• Direct connection to digital PSoC block and interrupt
• Programmable speed and power

• 8-bit resolution
• Voltage output
• Four quadrant multiplication
• 2’s complement, offset binary, and sign/magnitude input data formats
• Sample and hold for analog bus and external outputs
• Update rates up to 125 ksps

The MDAC8 is an 8-bit, four-quadrant multiplying DAC that scales input voltage with digital codes. The MDAC8 translates digital codes to output voltages at an update rate of up to 125k samples per second. The Application Programming Interface (API) supports offset-binary, 2’s complement, and sign-and-magnitude data formats. Offset compensation minimizes conversion error.  

• Industry standard Philips I2C bus compatible interface
• Emulates common I2C EEPROM interface
• Only two pins (SDA and SCL) required to interface to I2C bus
• Standard data rate of 100/400 kbps
• High level API requires minimal user programming
   

The EzI2Cs User Module implements an I2C register-based slave device. The I2C bus is an industry standard, two wire hardware interface developed by Philips®. The master initiates all communication on the I2C bus and supplies the clock for all slave devices. The EzI2Cs User Module supports the standard mode with speeds up to 400 kbps. No digital or analog PSoC blocks are consumed with this module. The EzI2Cs User Module is compatible with multiple devices on the same bus.

• 7/8-bit software serial transmitter
• Data framing consists of start, optional parity, and one or two stop bits
• RS-232 serial-data compatible format with optional parity
   

The TX8SW User Module is an 7- or 8-bit RS-232 data-format compliant serial transmitter. The data transmitted is framed with a leading start bit and a final one or two stop bits. Transmitter firmware is used to start and stop device and control transmission of complex structures like strings, HEX value representations, and so on.

• 8-bit resolution
• Data format available in 2’s complement
• Sample rate up to 32 ksps
• 64X over sampling with sinc2 filter reduces antialias requirements
• Input range defined by internal and external reference options
• Internal or external clock
• Second order modulator available for the CY8C29/27/24/22xxx, CY8C23x33, CY8CLED08/16,CY8C28x45families of PSoC devices
   

Note:  If this user module is used with the 29K family, it consumes an extra 6 mA. As an alternate, use the Delsig user module instead.

The DELSIG8 User Module provides an 8-bit 2’s complement conversion of an 2.6 volt full scale input signal centered around a user selected AGND, when the reference selection in the global parameter window is set to ± Bandgap. It supports sample rates from 1.8 ksps to 31 ksps. The sample rate is determined by the data clock input and is selectable by the user. Data generated by the DELSIG8 is available in the interrupt routine where the data is collected or through polling functions furnished by the DELSIG8 API.

• 6-bit resolution
• Voltage output
• 2’s complement, offset binary and sign/magnitude input data formats
• Sample and hold for analog bus and external outputs
• Update rates 250 ksps
   

The DAC6 User Module translates digital codes to output voltages. The DAC6 translates digital codes to output voltages at an update rate of up to 250k samples per second. The Application Programming Interface (API) supports offset-binary, sign-and-magnitude, and 2’s complement data formats for maximum flexibility. Offset compensation is employed to minimize the error.    

• 250 kbps DMX512 protocol receiver
• Selectable Address
• Selectable Captured slots count
• Interrupt on byte received
• Interrupt on start-of-frame
   

The DMX512Rx User Module is used to receive data via the DMX512 bus and store it in RAM, similar to the EzI2Cs User Module. The user module is composed of two digital blocks.

• 8-bit serial transmitter with selectable clocking to 48 MHz, yielding maximum 6 Mbit data rate
• Data framing consists of start, optional parity, and stop bits
• RS-232 serial-data compliant format with even, odd, or no parity
• Optional interrupt on transmit buffer empty condition
   

The TX8 User Module is an 8-bit RS-232 data-format compliant serial transmitter with programmable clocking and selectable interrupt or polling style operation. The data transmitted is framed with a leading start bit, an optional parity bit, and a stop bit. Transmitter firmware is used to initialize, start, stop, read status, and write data to the TX8.

• LED brightness control
• 2- to 8-, 16-, 24- or 32-bit resolution
• Input clocking up to 48 MHz
• Selectable output signal density
• Interrupt on Compare true

• Asynchronous receiver and transmitter
• Data-format compliant with RS-232 serial-data format
• Burst rates up to 6 Mbits/second
• Data framing consists of start, optional parity, and stop bits
• Optional interrupt on receive register full and/or transmit buffer empty
• Parity, overrun, and framing error detection
• High level transmit and receive functions
   

The UART User Module is an 8-bit Universal Asynchronous Receiver Transmitter that supports duplex RS-232-compliant, data format serial communications over two wires. Received and transmitted data format includes a start bit, optional parity, and a stop bit. Programmable clocking and selectable interrupt or polling style operation is supported. Application Programming Interface (API) firmware routines are provided to initialize, configure, and operate the UART. An additional high level API is also given to support background command receiving and string printing.
 

• 12-bit resolution, 2’s complement
• Sample rate from 7.8 sps to 480 sps
• Input range AGND /- VRef
• Provides normal mode rejection of high frequency harmonics
• Internal or external clock

The ADCINC12 User Module implements a 12-bit incremental A/D that generates a 12-bit, full-scale 2’s complement output (2047 to -2048 count range) with several input ranges to select from. Input voltage ranges, including rail-to-rail, may be measured by configuring the proper reference voltage and analog ground. It supports sample rates from 7.8 sps to 480 sps. The ADCINC12 programming interface allows you to select from 0 to 255 samples, where zero specifies continuous sampling.

The ADCINC12 is an integrating ADC that provides removal of higher frequencies. Optimum rejection of 50 Hz, 60 Hz, and any harmonics of these two frequencies (normal mode rejection) can be achieved by setting the sample window to 100 ms (sample rate to 9.84 sps). The CPU load varies with the input level.