Cypress’s PSoC programmable system-on-chip architecture gives you the freedom to not only imagine revolutionary new products, but the capability to also get those products to market faster than anyone else.

Hardware Description

The kit contains:

• PT100 Class B Resistive Temperature Detector (RTD)
• Type K Thermocouple
• NTC Thermistor
• 2 Temperature Diodes (2N3904 transistors)
• DS600 IC temperature sensor
• Examples projects for temperature sensing measurement, combined temperature and voltage measurement and fan control
• Includes a bonus CY8CKIT-012 PSoC Prototyping and Development Expansion Board
• Quick Start Guide
• Resource CD 

For PSoC training, please visit http://www.cypress.com/go/training

Software Title	Description	Link
PSoC Creator	This kit requires PSoC Creator for development

Kit Upgrade: Now it’s time to make the upgrade to PSoC® 5LP Processor Module and take advantage of all that PSoC has to offer.

These upgrades are FREE to our valued customers. Log on to http://www.cypress.com/go/psockitupgrade to know more details. Cypress appreciates your business and continued loyalty.

Kit Contents:

• PSoC Development Board 
• PSoC 1 CY8C28 Family Processor Module
• PSoC 3 CY8C38 Family Processor Module
• PSoC 5 CY8C58LP Family Processor Module
• MiniProg3 Program/Debug Device
• Program/Debug Ribbon Cable
• USB Cable
• 12V AC Power Adapter
• Quick Start Guide
• Kit CDs, which includes: PSoC Creator™, PSoC Designer™, PSoC Programmer, Projects, and Documentation

For PSoC training, please visit http://www.cypress.com/go/training.

Software Title	Description	Link
PSoC Creator	This kit requires PSoC Creator for development
PSoC Designer	This kit requires PSoC Designer for development
PSoC Programmer	This kit requires PSoC Programmer for programming

Features

• XRES pin to support in-system serial programming (ISSP) and external reset control in CY8C24894
• Powerful Harvard-architecture processor
• Advanced peripherals (PSoC® Blocks)
• Full speed USB (12 Mbps)
• Flexible on-chip memory
• Programmable pin configurations
• Precision, programmable clocking
• Additional system resources
• For more, see pdf

PSoC Functional Overview

The PSoC family consists of many devices with on-chip controllers. These devices are designed to replace multiple traditional MCU-based system components with one low-cost single-chip programmable component. A PSoC device includes configurable blocks of analog and digital logic, and programmable interconnect. This architecture makes it possible for you to create customized peripheral configurations, to match the requirements of each individual application.

PSoC Programmer 3.18 offers the user a simple GUI that connects to programming hardware to program and configure PSoC, Clock, and configurable fixed function devices. Also provided with PSoC Programmer is the Bridge Control Panel, which can be used to debug, graph and log I2C serial communications using various supported Cypress Software. PSoC Programmer also provides a hardware layer for customers to design custom applications or use existing code examples for testing hardware and Firmware designs.

PSoC Programmer 3.18 release shall support both PSoC Creator and PSoC Designer in a single installation.

PSoC Programmer 3.18 is a minor release. For additional information regarding the installation and the new features please see the release notes in the downloads table below.

PSoC Programmer:

PSoC Programmer is a flexible, integrated programming application for programming PSoC devices. PSoC Programmer can be used with PSoC Designer and PSoC Creator to program any design onto a PSoC device. PSoC Programmer supports all PSoC 1, PSoC 3 and PSoC 5LP devices.

Supported PC Operating Systems:

PSoC Programmer currently supports the following windows operating systems:

• Windows XP (32/64 bit)
• Windows Vista (32/64 bit)
• Windows 7 (32/64 bit)

PSoC Programmer does not support installations on Windows 8 machines. We will be adding Windows 8 support by August of 2013.

COM Hardware Layer Supported Languages:

PSoC Programmer provides the user a hardware layer with API’s to design specific applications utilizing the programmers and bridge devices. The PSoC Programmer hardware layer is fully detailed in the COM guide documentation as well as example code across the following languages: C#, C, Perl, and Python.

PSoC Programmer Secondary Software

PSoC Programmer includes additional software beyond just PSoC Programmer. For more information on that additional software please: Click Here

Third Party IDE and Programming Support

PSoC Programmer delivers a number of files and utilities that enable 3^rd party programming and debugging support for PSoC device families. In the downloads table below we include the 3^rd party user guide which will assists the user in configuring and enabling the support in the IDEs or programming utilities. The files and applications can be found in the root installation directory for each programmer installation.

Archived Software:

PSoC Programmer software is archived at the following page: Click Here

Additional Programming Links:
Prototype Programming Hardware:

PSoC Programmer is part of a suite of programming options and programming content available to PSoC users. For customers who are looking for more information on general programming options and information please navigate to the web page linked below. On the General Programming web page we discuss all of the available programming options for customers including Software, Schematics, Programming Specifications, and 3rd party mass programming.

www.cypress.com/go/programming

All PDF documents require at least a PDF reader installed prior to opening.

• Automotive Electronics Council (AEC) Q100 qualified
• Powerful Harvard Architecture Processor
• Advanced Peripherals (PSoC® Blocks)
• Precision, Programmable Clocking
• Flexible On-Chip Memory
• Programmable Pin Configurations
• Additional System Resources
• Complete Development Tools
• For more, see pdf
   

• Powerful Harvard-architecture processor:
• Advanced peripherals (PSoC® Blocks)
• High speed 10-bit SAR ADC with sample and hold optimized for embedded control
• Precision, programmable clocking
• Flexible on-chip memory
• Optimized CapSense® resource
• Programmable pin configurations
• Additional system resources
• For more, see pdf
   

PSoC Functional Overview

The PSoC family consists of many On-Chip Controller devices. These devices are designed to replace multiple traditional MCU-based system components with one low cost single-chip programmable device. PSoC devices include configurable blocks of analog and digital logic, and programmable interconnects.

Features

• Powerful Harvard-architecture processor
• Advanced peripherals (PSoC® blocks)
• Precision, programmable clocking
• Flexible on-chip memory
• Programmable pin configurations
• Additional system resources
• Complete development tools
• For more, see pdf

PSoC Functional Overview

The PSoC family consists of many programmable system-on-chip controller devices. These devices are designed to replace multiple traditional microcontroller unit (MCU)-based system components with one, low-cost single-chip programmable device. PSoC devices include configurable blocks of analog and digital logic, as well as programmable interconnects. This architecture lets you to create customized peripheral configurations that match the requirements of each individual application.

• Full byte-oriented EEPROM emulation
• Abstracts block-oriented Flash architecture
• Efficient use of memory

This PSoC Evaluation Kit features an evaluation board and MiniProg programming unit. The evaluation board includes an LCD module, Potentiometer, LEDs, and plenty of breadboarding space to meet all of your evaluation needs. The MiniProg programming unit is also included with the kit and will program PSoC devices directly on the evaluation board, or on other boards via a 5-pin header.  This programming unit is small and compact, and connects to a PC via a provided USB 2.0 Cable.

Please visit the Getting Started with PSoC 1 page which will guide you through your first steps. It provides basic information about software, technical documentation, training and support infrastructure.

Kit Includes:

• Evaluation Board with LCD Module
• MiniProg Programming Unit
• PSoC Designer Software CD
• 28 Pin CY8C29466-24PXI PDIP PSoC Device Sample
• 28-pin CY8C27443-24PXI PDIP PSoC Device Sample
• USB 2.0 Cable
• Getting Started Guide

Hardware Description

Supports all PSoC 1 Mixed-Signal Array families, including automotive, except CY8C25/26xxx devices.
 

Software Title	Description	Link
PSoC Designer	This kit requires PSoC Designer for development
PSoC Programmer	This kit requires PSoC Programmer for programming

 *Refer to Migrating CY8CKIT-001 DVK project to CY8CKIT 030/ 050. 

1. Click on AN84741 - PSoC® 5 to PSoC 5LP Migration Guide to learn differences between PSoC 5 and PSoC 5LP.
2. For PSoC 5 project and related document, please download file AN2099_Archive.zip.

Projects associated with this application note can be downloaded from the 'Related Files' section below. For your convenience, we have provided projects that are compatible with the two most recent versions of PSoC Creator:

• AN2099.zip is used with PSoC Creator 2.1 SP1
• AN2099_Archive.zip is used with PSoC Creator 2.1/2.0

The project’s default settings may not be compatible with your device or kit, and you may need to change your project settings. For more information, see:

Introduction

Ultrasonic parking assistance (UPA) systems are increasingly popular in cars because they enhance safety and driver convenience, especially in large cities. This application note shows you how to create an ultrasonic distance measurement system using enclosed ultrasonic  transducers, which are typical in automotive applications.

The SMBusSlave user module (UM) is a digital communication user module similar to I2C Slave. At the physical layer, multiple devices, both masters and slaves, will be connected to the same bus. The SMBus Slave UM in PSoC 1 uses I2C Controller as its physical layer and firmware-based data link layer. This code example discusses how to use the SMBus Slave user module and its commands to communicate to a host SMBus device.

General Description:

The SMBus Slave User Module provides a SMBus slave interface that is fully compliant with the Physical and Digital Link layers described in the SMBus Specification Version 2.0. This user module can be used in conjunction with other master and slave devices connected to a single SMBus segment. This user module uses an I2C controller and its interrupt for its physical layer.

Features:

• Industry standard SMBus compatible slave interface
• Supports SMBus Host Notify Protocol (HNP) using command and through a dedicated Alert pin
• Optional Packet Error Check (PEC)
• Standard data rate of 50/100 kbps
• High-level Application Program Interface (API) requires minimal user programming

Related Pages: Application Notes, Technical Reference Manuals, Design Guides

This document is a technical reference manual for all PSoCs with a base part number of CY8C2xxxx, except for the CY8C25122 and CY8C26xxx PSoC devices. It also applies to CY7C64215, CY7C603xx,CY8CNP1xx, and CYWUSB6953.

1. Make sure that POD is connected to the ICE properly. For more details on the POD connection please refer the ‘Debugging hardware setup’ section in the Application Note AN73212: Debugging with PSoC1.
2. If using ICE-Cube to power pod: Ensure that under the Project>Settings>Debugger menu the radio button with "ICE may power pod" is checked.
3. If using external supply to power the pod, first ensure that power is applied to ICE-Cube. Next ensure if the radio button “External only” under the Project>Settings>Debugger menu is checked.
   

Other possible errors that could occur while using the ICE cube to debug are

1. Could not connect to ICE or is Incompatible with the Pod
2. ICE Disconnects During Debug Session
3. Invalid Memory Reference Occurs During Debug Session
4. The Selected ICE Port Cannot be Found
5. Program Execution Halts at Unexpected Locations
6. USB Hub Power is Exceeded
7. No Events are Ever Detected

To troubleshoot the above mentioned error, please refer the section: Troubleshooting in the Application Note AN73212: Debugging with PSoC1 . Also for more details on how to troubleshoot the error ‘Could not connect to the ICE’, please refer the KB article PSoC Designer Error Message "Could not connect to ICE”.

The first four columns of the spreadsheet provide tags for quick sorting. These tags are based on content domain, application function, type of PSoC building blocks or IP, and document complexity. The spreadsheet also lets you know if there are example projects, what version of PSoC Designer is supported, what hardware platform was used to test the project, and the supported PSoC 1 device family. You can filter and sort our application notes using any of the fields and find relevant application notes available for download.

The Pseudo Random Sequence Generator project demonstrates how to use the PRS8 User Module to generate a random bit stream with a 10 ms interval and transmit it using a TX8 serial transmitter.

Computing and communication systems are complex and comprise multiple subsystems. Each subsystem can have its own voltage domain, which is also known as a power rail. Each power rail needs to be powered up and monitored individually. This creates a need for power management. Because this activity is a health indicator of the system, it cannot be incorporated in any of the subsystems. For this reason, a dedicated chip is used.

Power management consists of the following parts:

• accurate and reliable voltage sequencing
• rapid power rail fault detection
• voltage and current monitoring of power rails to optimize power consumption
• real-time trimming for closed-loop control of power converters (voltage regulators)
• in-system margining
• fault/event logging in EEPROM
• communication with the host controller using I2C, SMBus, or PMBus

The ICE-Cube also serves as a single-site device programmer via an ISSP (In-System Serial Programming) Cable and MiniEval board included in the kit. The MiniEval board is a programming and evaluation board which connects to the ICE-Cube via an ISSP Cable and allows programming of DIP devices. There are also other Programming boards available for programming other packages. The MiniEval also includes LEDs and a POT for simple evaluation and demonstration.

PSoC 1 Debugger Includes:

• PSoC Designer Software CD-ROM
• ICE-Cube In-Circuit Emulator
• ICE Flex-Pod for CY8C29xxx Family
• Backward compatibility Cat-5 Adapter
• ISSP Cable
• Mini-Eval Programming Board in One
• USB 2.0 Cable and Blue Cat-5 Cable
• 110 ~ 240V Power Supply, Euro-Plug Adapter
• 2 CY8C29466-24PXI 28-PDIP Chip Samples

Supports following 8 bit PSoC1 (Programmable System-On Chip) families, including automotive, except CY8C25/26xxx devices.

PSoC 1 Getting Started Debugging - Part 1 - The Hardware

PSoC 1 Getting Started Debugging - Part 2 - The PSoC Designer

Software Title	Description	Link
PSoC Designer	This kit requires PSoC Designer for development
PSoC Programmer	This kit requires PSoC Programmer for programming

Related Resources:

• Output is digital inverted input
• Requires only one digital block
• Can be used to generate an interrupt on the falling edge of the input

The DigInv User Module is a simple digital inverter. The output is a logical NOT of the input signal.

• Two Digital Buffers
• Input1 can be inverted
• Can be used to generate an interrupt on the rising edge of Output1

• Industry standard Philips I2C bus compatible interface
• Master and Slave operation, Multi Master capable
• Only two pins (SDA and SCL) required to interface to I2C bus
• Standard data rate of 100/400 kbps, also supports 50 kbps
• High level API requires minimal user programming
• 7-bit addressing mode
   

The I2C Hardware User Module implements an I2C device in firmware. The I2C bus is an industry standard, two-wire hardware interface developed by Philips®. The master initiates all communication on the I2C bus and supplies the clock for all slave devices. The I2CHW User Module supports the standard mode with speeds up to 400 kbps. No digital or analog user blocks are consumed with this module. The I2CHW User Module is compatible with other slave devices on the same bus.

• 6-bit resolution
• Voltage output
• Four quadrant multiplication
• 2’s complement, offset binary, and sign/magnitude input data formats
• Sample and hold for analog bus and external outputs
• Update rates up to 250 ksps

The MDAC6 User Module is a 6-bit, four-quadrant multiplying DAC that scales input voltage with digital codes. The MDAC6 translates digital codes to output voltages at an update rate of up to 250k samples per second. The Application Programming Interface (API) supports offset-binary, sign-and-magnitude, and 2’s complement data formats. Offset compensation minimizes conversion error. 

Features and Overview

• The 32-bit general purpose counter uses four PSoC blocks
• Source clock rates up to 48 MHz
• Automatic reload of period on terminal count
• Programmable pulse width
• Input enables/disables continuous counter operation
• Interrupt option on compare output or terminal count
   

The 32-bit Counter User Module provides a down counter with a programmable period and pulse width. The clock and enable signals can be selected from any system time base or external source. Once started, the counter operates continuously and reloads its internal value from the period register upon reaching terminal count. During each clock cycle, the counter compares the current count to the value stored in the compare register. Each clock cycle, the Counter tests the count against the value of the compare register for either a “less than" or “less than or equal to" condition. The comparator output provides a logic level that may be routed to pins and to other user modules.

Features and Overview

• The 24-bit general purpose counter uses three PSoC blocks
• Source clock rates up to 48 MHz
• Automatic reload of period on terminal count
• Programmable pulse width
• Input enables/disables continuous counter operation
• Interrupt option on compare output or terminal count
   

The 24-bit Counter User Module provides a down counter with a programmable period and pulse width. The clock and enable signals can be selected from any system time base or external source. Once started, the counter operates continuously and reloads its internal value from the period register upon reaching terminal count. During each clock cycle, the counter compares the current count to the value stored in the compare register. Each clock cycle, the Counter tests the count against the value of the compare register for either a “less than" or “less than or equal to" condition. The comparator output provides a logic level that may be routed to pins and to other user modules.

• Flexible input sources
• Output signal latching
• Flexible functionality configuration

The Comparator User Module (COMP) provides a digital output representation of the comparison of two signal levels. The input signals can be external signals multiplexed through the analog column mux, internal signals, and fixed or adjustable reference voltages. It provides a number of standard structural options with considerable flexibility in connection, threshold limits, and noise rejection.

The COMP user module is constructed as a MUM (multi user module). The MUM lists the name, brief description, simplified schematic, and input/output waveforms. The MUM schematic is at the "system" level. It does not show physical interconnections.

• 8-bit general purpose timer uses one PSoC block
• Source clock rates up to 48 MHz
• Automatic reload of period on terminal count
• Capture for clocks up to 24 MHz
• Terminal count output pulse may be used as input clock for other analog and digital functions
• Interrupt option on terminal count, capture (on some devices), or when counter reaches a preset value
   

The 8-Bit Timer User Modules provides a down counter with programmable period and capture ability. The clock and enable signals can be selected from any system time base or external source. Once started, the timer operates continuously and reloads its internal value from the period register upon reaching terminal count. The output pulses high in the clock cycle following terminal count. Events can capture the current Timer count value by asserting the edge-sensitive capture input signal. Each clock cycle, the Timer tests the count against the value of the compare register for either a “Less Than" or “Less Than or Equal To" condition. Interrupts may be generated based on terminal count and compare signals. Some device families offer two additional features. The interrupt options include “interrupt on capture" and, in addition, the compare signal may be routed onto the row buses. If these options are available on your chosen device they will be shown in the Device Editor.

• 32-bit general purpose timer uses four PSoC blocks
• Source clock rates up to 48 MHz
• Automatic reload of period on terminal count
• Capture for clocks up to 24 MHz.
• Terminal count output pulse may be used as input clock for other analog and digital functions
• Interrupt option on terminal count, capture (on some devices), or when counter reaches a preset value
   

The 32-bit Timer User Module provides a down counter with programmable period and capture ability. The clock and enable signals can be selected from any system time base or external source. Once started, the timer operates continuously and reloads its internal value from the period register upon reaching terminal count. The output pulses high in the clock cycle following terminal count. Events can capture the current Timer count value by asserting the edge-sensitive capture input signal. Each clock cycle, the Timer tests the count against the value of the compare register for either a “Less Than" or “Less Than or Equal To" condition. Interrupts may be generated based on terminal count and compare signals. Some device families offer two additional features. The interrupt options include “interrupt on capture" and, in addition, the compare signal may be routed onto the row buses. If these options are available on your chosen device they will be shown in the Device Editor.  

• 24-bit general purpose timer three PSoC blocks
• Source clock rates up to 48 MHz
• Automatic reload of period on terminal count
• Capture for clocks up to 24 MHz
• Terminal count output pulse may be used as input clock for other analog and digital functions
• Interrupt option on terminal count, capture (on some devices), or when counter reaches a preset value
   

The 24-bit Timer User Module provides a down counter with programmable period and capture ability. The clock and enable signals can be selected from any system time base or external source. Once started, the timer operates continuously and reloads its internal value from the period register upon reaching terminal count. The output pulses high in the clock cycle following terminal count. Events can capture the current Timer count value by asserting the edge-sensitive capture input signal. Each clock cycle, the Timer tests the count against the value of the compare register for either a “Less Than" or “Less Than or Equal To" condition. Interrupts may be generated based on terminal count and compare signals. Some device families offer two additional features. The interrupt options include “interrupt on capture" and, in addition, the compare signal may be routed onto the row buses. If these options are available on your chosen device they will be shown in the Device Editor.

• Uses the industry standard Hitachi HD44780 LCD display driver chip protocol
• Requires only seven I/O pins
• Routines provided to print RAM or ROM strings
• Routines provided to print numbers
• Routines provided to display horizontal and vertical bar graphs
• Uses a single I/O port
   

The Character LCD User Module is a set of library routines that writes text strings and formatted numbers to a common two or four-line LCD module. Vertical and horizontal bar graphs are supported, using the character graphics feature of these LCD modules. This module was developed specifically for the industry standard Hitachi HD44780 two-line by 16 character LCD display driver chip, but works for many other fourline displays. This library uses the 4-bit interface mode to limit the number of I/O pins required.
 

Features and Overview

• Industry standard Philips I2C bus compatible interface
• Only two pins (SDA and SCL) required to interface several slave I2C devices
• Standard mode data supports rate of 100 kbps
• High level API requires minimal user programming
• Low level API provided for flexibility

The I2Cm User Module implements a master I2C device in firmware. The I2C bus is an industry standard,  two-wire interface developed by Philips®. An I2C bus master may communicate with several slave devices  using only two wires. The master initiates all communication on the I2C bus and supplies the clock for all slave devices. The I2Cm User Module supports speeds up to 100 kbps. No digital or analog user blocks  are consumed with this module. 

• Automotive Electronics Council (AEC) Q100 qualified
• Powerful Harvard Architecture Processor
• Advanced Peripherals (PSoC® Blocks)
• Flexible On-Chip Memory
• Complete Development Tools
• Precision, Programmable Clocking
• Programmable Pin Configurations
• Versatile Analog Mux
• Additional System Resources
• For more, see pdf
   

PSoC Functional Overview

The PSoC family consists of many devices with On-Chip Controllers. These devices are designed to replace multiple traditional MCU-based system components with one, low cost single-chip programmable component. A PSoC device includes configurable blocks of analog and digital logic, and programmable interconnect. This architecture allows the user to create customized peripheral configurations, to match the requirements of each individual application. Additionally, a fast CPU, Flash program memory, SRAM data memory, and configurable IO are included in a range of convenient pinouts.

今日本語で !!

Several common debugging techniques are described to help you solve common problems, such as stack overflow and memory corruption. A troubleshooting guide is included. 

Introduction

The purpose of this application note is to introduce the hardware and software debugger elements available in PSoC 1 and to describe several common debugging techniques.

The primary hardware elements of the debugging system are an In-Circuit-Emulator (ICE) and a debug pod with an on chip debugger (OCD) enabled PSoC 1 device. Those elements, and instructions on configuring and using them, are described in the Debugging Hardware portion of this application note.

PSoC 1 Getting Started Debugging - Part 1 - The Hardware

PSoC 1 Getting Started Debugging - Part 2 - The PSoC Designer

• Real time clock that keeps time with an external 32K crystal oscillator
• Flexible interrupt sources between second, minute, hour, and day
• Hour, Minute and Second time read and write in BCD format
• Normal timer if using VC1 as clock source
• Sleep mode with internal or external 32K clock source
• Reset by PPOR, IPOR, and watchdog reset
   

• Powerful Harvard-architecture processor
• Advanced peripherals (PSoC® blocks)
• Flexible on-chip memory
• Complete development tools
• Precision, programmable clocking
• Programmable pin configurations
• Versatile analog mux
• Additional system resources
• For more, see pdf

The PSoC family consists of many devices with on-chip controllers. These devices are designed to replace multiple traditional MCU-based system components with one low-cost single-chip programmable component. A PSoC device includes configurable blocks of analog and digital logic, and programmable interconnect. This architecture makes it possible for you to create customized peripheral configurations, to match the requirements of each individual application. Additionally, a fast central processing unit (CPU), flash program memory, SRAM data memory, and configurable I/O are included in a range of convenient pinouts.

INL - Integral Non-Linearity: DNL errors accumulate to produce a total Integral Non-Linearity (INL). It is defined as the maximum deviation from the ideal slope of the ADC and is measured from the center of the step. It is expressed as counts. INL is a function of each ADC's particular architecture. It is not possible to remove its effects with calibration.

Please refer attached document for details of these errors.

PSoC Designer 5.0 SP6 will continue to be available for System Level Design users, and it will co-exist with future PSoC Designer 5.1 releases. However, we are not recommending System Level Design for production designs.

We suggest users to use the latest version of PSoC Designer located here:

www.cypress.com/go/psocdesigner

PSoC Designer 5.0 SP6 supports Internet Explorer 6 through 8, but does not support Internet Explorer 8 Beta or Internet Explorer 9 due to compatibility issues.

To Install PSoC Designer 5.0 SP6 users must first have PSoC Programmer installed first. For the latest release of PSoC Programmer please, Click Here

PSoC Designer 5.0 PS6 was tested using Beta version of Windows 7. PSoC Designer 5.0 SP6 is not supported for Windows 7 systems.

To Install:

Shut Down any currently running instances of PSoC Designer.

If an earlier service pack of PSoC Designer 5.0 is currently installed, uninstall it. To do this please navigate to Start>Control Panel>Add or Remove Programs.

• Install latest PSoC Programmer.
• Install PSoC Designer 5.0 SP6 by running the installed in the downloads table below.”

Note to HI-TECH Compiler Users:

There are new devices in this release. To compile projects containing these devices with the HI-TECH compiler, you must manually update the psoc.ini file. The HI-TECH psoc.ini file is found in the HI-TECH installation folder. The default location of the psoc.ini is here:

C:\Program Files\HI-TECH Software\HCPSOC\PRO\9.61\dat\psoc.ini

The default location of the replacement psoc.ini file that adds support for the new devices is here:

C:\Program Files\Cypress\Common\CypressSemiBuildMgr\tools\psoc.ini

PSoC Programmer: The latest version of PSoC Programmer must be installed along with PSoC Designer. For the latest release please navigate to the PSoC Programmer web page: Click Here

PSoC Designer: User Guides - Click Here

PSoC Designer Archive - Click Here

CY3236A-PIRMOTION Rev. A Kit Contents:

• PIR Motion Sensor Board using CY8C27443-24PVXI PSoC(R) device
• 12V Power Supply
• PSoC Designer(TM) and PSoC Programmer CD
• Design Files CD (Schematic, BOM, Gerber Files, PSoC Designer Example Project)

Sleep mode is used to reduce a PSoC’s average current consumption by entering a low-power state, whenever the CPU and other internally clocked functions are not needed. Sleep mode is most useful for battery-powered systems, but it is applicable to any design.

Features

• Powerful Harvard-architecture processor
• Advanced peripherals (PSoC® blocks)
• Flexible on-chip memory
• Complete development tools
• Precision, programmable clocking
• Programmable pin configurations
• Additional system resources
   

PSoC Functional Overview

The PSoC family consists of many programmable system-on-chip controller devices. These devices are designed to replace multiple traditional MCU-based system components with a low cost single-chip programmable component. A PSoC device includes configurable blocks of analog and digital logic, and programmable interconnect. This architecture allows you to create customized peripheral configurations, to match the requirements of each individual application. Additionally, a fast CPU, Flash program memory, SRAM data memory, and configurable I/O are included in a range of convenient pinouts.

General-purpose input and output (GPIO) is a very critical part of any microcontroller unit (MCU) as they form the bridge between the external world and the MCU. The type and nature of this external world bridge depends on the end application. For instance, an ADC requires a GPIO to be an analog pin whereas an I2C or SPI digital communication block requires the same GPIO to be digital. In order to properly setup this external world bridge, you need to know not only the end application but also the GPIO system of the MCU that is used. PSoC like any other controller has its own GPIO system. This application note discusses the application specific parameters of the GPIO system. Detailed technical overview of the system can be found in the respective device technical reference manual (TRM) under General Purpose I/O chapter of PSoC Core section.
 

Features

• Low power CapSense® block with SmartSense Auto-tuning
• Powerful Harvard-architecture processor
• Operating Range: 1.71 V to 5.5 V
• Operating Temperature range: -40 °C to +85 °C
• Flexible on-chip memory
• Four Clock Sources
• Programmable pin configurations
• Versatile Analog functions
• Full-Speed USB
• For more, see pdf

PSoC^® Functional Overview

The PSoC family consists of on-chip controller devices, which are designed to replace multiple traditional microcontroller unit (MCU)-based components with one, low cost single-chip programmable component. A PSoC device includes configurable analog and digital blocks, and programmable interconnect. This architecture allows the user to create customized peripheral configurations, to match the requirements of each individual application.  

See how you can integrate thermal management functions in a single low-cost PSoC 1 device:

1. Closed-loop 4-wire fan control
2. Temperature measurement
3. Fan Speed Control based on temperature measurement
4. Display

Required Hardware

CY8CKIT-001 PSoC Development Kit (sold separately) The CY8CKIT-001 PSoC Development Kit (DVK) allows you to evaluate the PSoC 1, PSoC 3, and PSoC 5 families. Place the Processor Module families (included) on the DVK and program it with the CY8CKIT-016 PSoC Thermal Management kit example project using the MiniProg3 Program device.

CY8CKIT-036 PSoC Thermal Management Expansion Board Kit (sold separately) The CY8CKIT-036 PSoC Thermal Management Expansion Board Kit (EBK) connects to the CY8CKIT-001. Kit Contents: Two 4-wire fans and connectors for two additional 4-wire fans Digital (I2C-based TMP175, One-wire DS1820, PWM output TMP05) and Analog (Diode) temperature sensors I2C/SMBus/PMBus host interface   The EBK connects to the CY8CKIT-001 PSoC Development Kit for operation.

Easy to use Modular Design

The CY8CKIT-001 PSoC 1 Development Kit allows you to evaluate Cypress's PSoC 1, PSoC 3 and PSoC 5 families. The modular design allows you to interface with different types of Expansion Board Kits. In this case the CY8CKIT-036 plugs onto the CY8CKIT-001, which uses the firmware example project of the CY8CKIT-016 to demonstrate Thermal Management functions.

CY8CKIT-001 PSoC DVK	CY8CKIT-036		CY8CKIT-016
PSoC 1 CY8C28 Family Processor Module

Example Project Description

Example firmware provides a quick demonstration of a two-zone Thermal Management system. Zone 1 consists of a 4-wire fan, the I2C temperature sensor and a potentiometer that simulates a diode. Zone 2 consists of the other 4-wire fan, a PWM output temperature sensor and a 1-wire temperature sensor. Fan RPM is controlled based on the weighted average readings of temperature sensors in their zones. Fan RPM zone temperature readings and fan faults are displayed in LCD.
 

PSoC One-chip Solution
 

This Thermal Management solution is used by Tier 1 Customers in Data and Telecom equipment. It can be your solution as well. Options include:

1. Driving up to 8 fans in closed-loop or open-loop
2. Interfacing with Multiple Digital and Analog Sensors
3. Communicating via I2C, SPI, UART or PMBus* and SMBus*

*SMBus and *PMBus with PSoC 1 are under development

To learn more, download these App Notes.

To know more about PSoC 1, click here. To know more about other PSoC 1 kits, click here.
 

Software Title	Description	Link
PSoC Designer	This kit requires PSoC Designer for development
PSoC Programmer	PSoC programmer is required every time the PSoC 1 (CY8C28) Family Processor Module is programmed

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Introduction

   Cypress's Programmable System-on-Chip (PSoC®) integrates a microcontroller with programmable analog and digital peripherals. Because you can configure the resources of a PSoC, you can develop a device that is customized and tuned for your application. Moreover, as the needs of the application change during development and in production, you can reconfigure the device to adapt to these new requirements with minimal effort.   
   

Getting Started with PSoC 1 - Part 1 - Architecture and System Resources

Getting Started with PSoC 1 - Part 2 - Digital Subsystem

Getting Started with PSoC 1 - Part 3 - Analog architecture

Getting Started with PSoC 1 - Part 4 - My first PSoC Designer Project

PSoC® 1 - Getting Started with SPI

Introduction

System cooling is a critical task in any high performance electronic system. As circuit miniaturization continues, increasing demands are placed on system designers to improve the efficiency of their thermal management designs. Usually thermal management is done by forced convection. In forced convection the heat dissipation is increased by moving the air inside and around the heat source. This can be easily accomplished using Brushless DC (BLDC) based fans. The speed of these fans depends on DC voltage across these fans.

 
Features:

• User friendly PLC Control Panel Application available on kit CD
• CY8CPLC20-OCD – 100-pin TQFP on-chip debug (OCD) device that allows quick design and debug of a PLC application. The CY8CPLC20 100-pin TQFP is available for debug purposed only. For production quantities, CY8CPLC20 is available in 28-pin SSOP and 48-pin QFN packages.
• Chip power supply derived from 90V to 264V AC
• User configurable general purpose LEDs
• General purpose 8-bit DIP switch
• On board surge protection and isolation circuit
• RJ45 connector to use ICE debugger
• RS232 COM port for communication
• Header to attach LCD card
• I2C header for communicating to external device
• ISSP header for programming the CY8CPLC20

 
Kit Contents:

• CY3274 Quick Start Guide
• CY3274 PLC HV Development Board
• CDs containing:
  • Packet Test Software – PLC Control Panel Application
  • CY8CPLC20 Data Sheet
  • Development Board User Guide
  • Application Note – Using CY8CPLC20 in Powerline Communication (PLC) Applications
  • CY3274 Board Schematics
  • CY3274 Board Gerbers
  • PSoC Designer™
  • PSoC Programmer
• AC Power Cable
• MiniProg1 to Program CY8CPLC20
• 25 Jumper Wires
• LCD Module
• USB-I2C Bridge
• Retractable USB Cable
• Five CY8CPLC20-28PVXI Device Samples

Software Title	Description	Link
PSoC Designer	This kit requires PSoC Designer for development
PSoC Programmer	This kit requires PSoC Programmer for programming
Powerline Communcation	PLC Contol Panel Application

• Nominal 10-bit resolution
• Selectable resolution from 2-bit to 12-bit
• Input range 0 to Vdd-1
• Allows a coarse temperature measurement: range of -40°C to +125°; accuracy of ± 40°C with resolution ± 2°C
   

The ADC10 User Module implements a Single Slope A/D Converter that generates up to a 12-bit, full scale output (0 to 4095 count range). Although capable of generating a 12-bit output, it has only 10 effective bits of resolution. Further resolution is achieved by averaging multiple samples.

The application note describes the three modes in which the TMP05/06 sensors can be interfaced followed by sample projects interfacing the sensors with a CY8C28xxx device through a simple, serial 2-wire digital interface. After reading the application note, a designer should be able to use the project attached to interface any PSoC 1 to TMP05 and TMP06 sensors in all the three modes described.

This application note assumes that the reader is familiar with PSoC 1, PSoC Designer IDE and programming in C.

For PSoC® 3 based implementation of TMP05/06 sensor interface refer - AN65977
 

• Powerful Harvard Architecture Processor
  • M8C Processor Speeds up to 24 MHz
  • 8x8 Multiply, 32-Bit Accumulate
  • Low power at high speed
  • 3.0 to 5.25V Operating Voltage
  • Industrial Temperature Range: -40°C to +85°C
• Advanced Peripherals (PSoC® Blocks)
  • 4 Rail-to-Rail Analog PSoC Blocks Provide:
    • Up to 14-Bit ADCs
    • Up to 8-Bit DACs
    • Programmable Gain Amplifiers
    • Programmable Filters and Comparators
  • 4 Digital PSoC Blocks Provide:
    • 8 to 32-Bit Timers and Counters, 8- and 16-bit pulse-width modulators (PWMs)
    • CRC and PRS Modules
    • Full Duplex UART
    • Multiple SPI Masters or Slaves
    • Connectable to all GPIO Pins
  • Complex Peripherals by Combining Blocks
  • High speed 8-bit SAR ADC optimized for motor control
• Precision, Programmable Clocking
  • Internal ± 5% 24/48 MHz Oscillator across the Industrial Temperature Range
  • High Accuracy 24 MHz with Optional 32 kHz Crystal and PLL
  • Optional External Oscillator, up to 24 MHz
  • Internal Oscillator for Watchdog and Sleep
• Flexible On-Chip Memory
  • 8K Bytes Flash Program Storage 50,000 Erase/Write Cycles
  • 256 Bytes SRAM Data Storage
  • In-System Serial Programming (ISSP)
  • Partial Flash Updates
  • Flexible Protection Modes
  • EEPROM Emulation in Flash
• Programmable Pin Configurations
  • 25 mA Sink on all GPIO
  • Pull Up, Pull Down, High Z, Strong, or Open Drain Drive Modes on All GPIO
  • Up to eight Analog Inputs on GPIO plus two additional analog inputs with restricted routing
  • Two 30 mA Analog Outputs on GPIO
  • Configurable Interrupt on All GPIO
• Additional System Resources
  • I²C™ Slave, Master, and Multi-Master to 400 kHz
  • Watchdog and Sleep Timers
  • User Configurable Low Voltage Detection (LVD)
  • Integrated Supervisory Circuit
  • On-Chip Precision Voltage Reference
• Complete Development Tools
  • Free Development Software (PSoC Designer™)
  • Full-Featured, In-Circuit Emulator and Programmer
  • Full Speed Emulation
  • Complex Breakpoint Structure
  • 128K Trace Memory

PSoC Functional Overview
 

This AN also talks about the method to reduce the 3^rd and 5^th harmonics by using a dead band PWM generator and a band-pass filter.

In order to be able to understand the functionality better, following pre-readings are suggested:

AN2168: Understanding switched capacitor filters - Discusses how low pass, band pass and notch filters can be implemented using switched capacitor blocks.

KB Article: Generation of non-overlapping signals using dead band PWM generator.

• Nlradio.asm
• Nlradio.h
• Nlradio.inc
• Nlspi.asm

This document describes the APIs exposed by the WUSB-NL driver.

The WUSB-NL radio driver is used in wireless mouse, keyboard, and bridge application software stacks. The WUSB-NL radio driver is modular and can be used as a library. The API exported by this module is explained in this document.

Because PSoC 1 offers billions of configuration options, the PSoC device must be properly initialized after reset to fulfill its potential. The PSoC Designer boot process performs these necessary initialization tasks before entering main to provide an optimal working environment. This application note explains the device initialization procedure, but this document is not required reading for users of PSoC 1 or the PSoC Designer integrated development environment (IDE). The information is for users seeking a deeper understanding of PSoC and PSoC Designer initialization before main is executed.

PSoC® 1 Boot Process from Reset to Main

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Introduction

When designing with the PSoC 1 family of microcontrollers, you use PSoC Designer and its highlevel interface to configure the PSoC, including the analog architecture. In addition to placing and configuring the individual user modules (building blocks), several global analog parameters also require configuration. Understanding these global parameters and the overall analog architecture is important, especially when a design consists of several analog user modules that are affected by these settings.
 

In the following videos, Dave implements Analog to Digital converters in a project and shows the tools he'll be using for designing robust analog-output sensor signal paths.

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The focus of the application note is on features specific to the ImageCraft compiler that can be modified to optimize code. General code optimization techniques for C language are only handled briefly in this application note.

This application note is for PSoC1 M8C CPU.

For PSoC3 8051 CPU, please see AN60630 - PSoC® 3 - 8051 Code Optimization

For PSoC5 ARM Cortex-M3 CPU, please see ARM Documentation

Segment LCDs are available in two forms - segment LCD glass and the segment LCD module, which comes with inbuilt driver. Many times, it is difficult to get all the required display features on a LCD module. One possibility is to use a custom LCD glass and an external driver. But this increases the cost of the system. Cypress PSoC chip can do segment LCD glass drive besides executing some other major tasks with its configurable digital/analog hardware and with its 8-bit MCU. It integrates multiple functions of the system within a single chip offering significant BOM savings.

To assist in design development, PSoC Designer provides SLCD user module. It supports following features:

• Multiplexed LCD glass drive, 1/2 bias
• 2, 3 and 4 common LCD drive
• 30Hz to 150Hz refresh rate
• Type A waveform
• Contrast control 

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The source code provided can be easily ported to any microntroller used as the host in the system. However, the application note does not describe the programming protocol. For details on programming protocol, please refer to the following documents:

• PSoC1 – Device programming specifications (AN2026A) – ISSP programming specifications for following device families: CY8C21x23, CY8C21x34, CY8C23x33, CY8C24x23A, CY8C27x43, CY8CTMG110, CY8CTST110

• PSoC1 – Device programming specifications (AN2026B) – ISSP programming specifications for following device families: CY8C21x45, CY8C22x45, CY8C24x94, CY8C28xxx, CY8C29x66, CY8CTST120, CY8CTMA120, CY8CTMG120, CY7C64215

You can find the complete list of PSoC programmer hardware, software, documentation and 3^rd party vendor relationships here: General PSoC Programming.

The app note explains each parameter under the Global Resources, the relevance of each parameter to the operation of the device, points to remember while configuring these parameters, registers that affect the parameters, and code snippets to change these parameters during runtime.

This Application Note outlines a simple, almost all-hardware method for detecting FSK signals using the analog signal processing capabilities of the PSoC 1 device. It describes circuits and signal processing techniques for demodulation. This signal processing technique is readily applicable to caller ID and several modem standards but it is not a complete modem; it does not include the phone line or other interfaces; it also does not include the data processing code.

A separate project is included and outlined in the Appendix A to simplify testing of the demodulator.

In order to be able to understand the implementation, following pre-readings are suggested:

AN2041: Understanding switched capacitor blocks – Explains the operation of switched capacitor blocks, and provides practical examples for their use.

AN2168: Understanding switched capacitor filters - Discusses how low pass, band pass and notch filters can be implemented using switched capacitor blocks.

KB Article: Implementation of a full wave rectifier and low pass filtering using all hardware technique.

The thermocouple (TC) is a voltage output device that measures the temperature difference between the sensor tip and a reference junction (called the cold junction). This is a relative measurement and to be accurate, the reference lead temperature must also be known. Type K thermocouples have an average output of approximately 40.7 μV/°C. This output is approximately linear.

Correlated Double Sampling (CDS) provides a means to efficiently subtract offset and remove drift, and low frequency noise from this sensitive measurement. This technique works just as well for differential measurements such as pressure sensors and load cells.

Reading the following application notes will aid in better understanding of this application note:

AN74170 – PSoC 1 Analog structure and configuration with PSoC Designer - Discusses in detail about the architecture of analog blocks in PSoC 1 and how they can be configured to implement a particular functionality.

AN2224 – Lower noise continuous time signal processing - Provide an introduction to semiconductor noise phenomena and specifics on PSoC noise parameters.

AN2219 – Selecting Analog Ground and reference - Describes the internal ground and reference settings in detail and how they can be routed at the output to provide a reference.
 

PSoC 1 - Correlated Double Sampling Video

This video presents low noise signal processing in PSoC® 1 through the use of Correlated Double Sampling (CDS) to reduce errors due to offset, drift, and low frequency noise.

• A brief explanation of how an opamp works.
• An explanation of how a switched capacitor integrator can emulate an opamp (faux opamp).
• Examples of faux opamp circuits.
   

This application note does not give in depth information about switched capacitor blocks. For more information please refer AN2041  PSoC 1 – Understanding PSoC 1 Switched Capacitor Analog Blocks.

In the following video, Dave highlights the importance of References and Analog Ground using a PSoC Designer Project.

• Low Pass Filters
• Band Pass Filters
• High Pass Filters
• Notch Filters

This Application note discusses how these filters can be implemented using the Switched Capacitor Blocks in PSoC 1.  The application note discusses the following topics.

• Basics of filters like universal filter transfer function, various variables that construct a filter (Roll off Frequency, Damping, High pass coefficient, Band pass coefficient and Low pass coefficient)
• Detailed mathematical analysis of how the filters are implemented in PSoC 1 SC Blocks
• A tool FilterCalc.exe which can be used to calculate capacitor values for given roll off frequency, damping value and column clock
• Using FilterCalc.exe to configure a Low pass filter and a Band pass filter
• Excel spreadsheet wizard that simplifies the task of configuring filters
• Examples for Low pass filter and Band pass filters using the spread sheet
• Construction of a Notch filter and Elliptical filter

Please refer  AN2041 – Understanding PSoC 1 Switched Capacitor Analog Blocks for more details about the basics of switched capacitor blocks.

The zip file that may be found in the Related Files section, has example projects for each type of filter, example filter wizard spread sheet and the FilterCalc application.
 

In the following video, Dave explains filter choices with a PSoC Designer project.