Cypress.com: Documentation http://www.cypress.com/?app=search&searchType=advanced&id%3D148 CYP15G0101DXB, CYV15G0101DXB: Single-channel HOTLink II™ Transceiver http://www.cypress.com/?rID=14239 Single-channel HOTLink II™ Transceiver

Features

  • Second-generation HOTLink® technology
  • Compliant to multiple standards
    • ESCON®, DVB-ASI, fibre channel and gigabit ethernet (IEEE802.3z)
    • CPRI™ compliant
    • CYV15G0101DXB compliant to SMPTE 259M and SMPTE 292M
    • 8B/10B encoded or 10-bit unencoded data
  • Single-channel transceiver operates from 195 to 1500 MBaud serial data rate
  • For more, see pdf
     

Functional Description

The CYP15G0101DXB single-channel HOTLink II™ transceiver is a point-to-point communications building block allowing the transfer of data over a high-speed serial link (optical fiber, balanced, and unbalanced copper transmission lines) at signaling speeds ranging from 195 to 1500 MBaud.

The transmit channel accepts parallel characters in an input register, encodes each character for transport, and converts it to serial data. The receive channel accepts serial data and converts it to parallel data, frames the data to character boundaries, decodes the framed characters into data and special characters, and presents these characters to an output register.

]]> Mon, 30 Jul 2012 05:30:50 -0600 CYV15G0204TRB: Independent Clock HOTLink II™ Dual Serializer and Dual Reclocking Deserializer http://www.cypress.com/?rID=14228 Independent Clock HOTLink II™ Dual Serializer and Dual Reclocking Deserializer

Features

  • Second-generation HOTLink® technology
  • Compliant to SMPTE 292M and SMPTE 259M video standards
  • Dual-channel video serializer plus dual channel video reclocking deserializer
    • 195- to 1500-Mbps serial data signaling rate
    • Simultaneous operation at different signaling rates
  • Supports reception of either 1.485 or 1.485/1.001 Gbps data rate with the same training clock
  • Supports half-rate and full-rate clocking
  • Internal phase-locked loops (PLLs) with no external PLL components
  • Selectable differential PECL-compatible serial inputs
  • For more, see pdf

Functional Description

The CYV15G0204TRB Independent Clock HOTLink II™ Dual Serializer and Dual Reclocking Deserializer is a point-to-point or point-to-multipoint communications building block enabling transfer of data over a variety of high-speed serial links including SMPTE 292M and SMPTE 259M video applications. It supports signaling rates in the range of 195 to 1500 Mbps per serial link.

]]> Mon, 30 Jul 2012 04:41:03 -0600 CYV15G0104TRB: Independent Clock HOTLink II™ Serializer and Reclocking Deserializer http://www.cypress.com/?rID=14226 Independent Clock HOTLink II™ Serializer and Reclocking Deserializer

Features

  • Second-generation HOTLink® technology
  • Compliant to SMPTE 292M and SMPTE 259M video standards
  • Single channel video serializer plus single channel video reclocking deserializer
    • 195- to 1500-Mbps serial data signaling rate
    • Simultaneous operation at different signaling rates
  • Supports reception of either 1.485 or 1.485/1.001 Gbps data rate with the same training clock
  • Internal phase-locked loops (PLLs) with no external PLL components
  • Supports half-rate and full-rate clocking
  • Selectable differential PECL-compatible serial inputs
  • For more, see pdf

Functional Description

The CYV15G0104TRB Independent Clock HOTLink II™ Serializer and Reclocking Deserializer is a point-to-point or point-to-multipoint communications building block enabling transfer of data over a variety of high-speed serial links including SMPTE 292M and SMPTE 259M video applications. It supports signaling rates in the range of 195 to 1500 Mbps per serial link.

]]> Mon, 30 Jul 2012 04:39:06 -0600 CYP15G0403DXB: Independent Clock Quad HOTLink II™ Transceiver http://www.cypress.com/?rID=14242 Independent Clock Quad HOTLink II™ Transceiver

Features

  • Second-generation HOTLink® technology
  • Compliant to multiple standards
    • ESCON, DVB-ASI, SMPTE-292M, SMPTE-259M, Fibre Channel and Gigabit Ethernet (IEEE802.3z)
    • CPRI™ compliant
    • 8B/10B coded data or 10 bit uncoded data
  • Quad channel transceiver operates from 195 to 1500 MBaud serial data rate
    • Aggregate throughput of up to 12 Gbits/second
  • Second-generation HOTLink technology
  • Truly independent channels
  • For more, see pdf

Functional Description

The CYP(V)15G0403DXB Independent Clock Quad HOTLink II™ Transceiver is a point-to-point or point-to-multipoint communications building block enabling transfer of data over a variety of high-speed serial links like optical fiber, balanced, and unbalanced copper transmission lines. The signaling rate can be anywhere in the range of 195 to 1500 MBaud per serial link.

]]> Mon, 30 Jul 2012 04:33:44 -0600 CYP15G0401DXB, CYV15G0401DXB: Quad HOTLink II™ Transceiver http://www.cypress.com/?rID=13679 Quad HOTLink II™ Transceiver

Features

  • Second-generation HOTLink® technology
  • Compliant to multiple standards
  • Quad channel transceiver operates from 195 to 1500 MBaud serial data rate
  • Selectable parity check/generate
  • Selectable multi-channel bonding options
  • Skew alignment support for multiple bytes of offset
  • Selectable input/output clocking options
  • MultiFrame™ Receive Framer
  • Synchronous LVTTL parallel interface
  • For more, see pdf
     

Functional Description

The CYP(V)15G0401DXB Quad HOTLink II™ Transceiveris a point-to-point or point-to-multipoint communications building block allowing the transfer of data over high-speed serial links (optical fiber, balanced, and unbalanced copper transmission lines) at signaling speeds ranging from 195-to-1500 MBaud per serial link.

]]> Mon, 30 Jul 2012 04:29:31 -0600 CYV15G0203TB: Independent Clock Dual HOTLink II™ Serializer http://www.cypress.com/?rID=14223 Independent Clock Dual HOTLink II™ Serializer

Features

  • Second-generation HOTLink® technology
  • Compliant to SMPTE 292M and SMPTE 259M video standards
  • Dual-channel video serializer
    • 195- to 1500-Mbps serial data signaling rate
    • Simultaneous operation at different signaling rates
  • Supports half-rate and full-rate clocking
  • Internal phase-locked loops (PLLs) with no external PLL components
  • Redundant differential PECL-compatible serial outputs per channel
    • No external bias resistors required
  • For more, see pdf

Functional Description

The CYV15G0203TB Independent Clock Dual HOTLink II™ Serializer is a point-to-point or point-to-multipoint communications building block enabling transfer of data over a variety of high-speed serial links including SMPTE 292M and SMPTE 259M video applications. It supports signaling rates in the range of 195 to 1500 Mbps per serial link.

]]> Mon, 30 Jul 2012 03:14:16 -0600 CYP15G0201DXB: Dual-channel HOTLink II™ Transceiver http://www.cypress.com/?rID=14240 Dual-channel HOTLink II™ Transceiver

Features

  • Second-generation HOTLink® technology
  • Compliant to multiple standards
    • ESCON, DVB-ASI, Fibre Channel and Gigabit Ethernet (IEEE802.3z)
    • CPRI™ compliant
    • 8-/10-B encoded or 10-bit unencoded data
  • Dual channel transceiver operates from 195 to 1500-MBaud serial data rate
    • Aggregate throughput of 6-GBits per second
  • Selectable parity check/generate
  • Selectable dual-channel bonding option
  • For more, see pdf
     

Functional Description

The CYP15G0201DXB dual-channel HOTLink II™ transceiver is a point-to-point or point-to-multipoint communications building block allowing the transfer of data over high-speed serial links (optical fiber, balanced, and unbalanced copper transmission lines) at signaling speeds ranging from 195- to 1500-MBaud per serial link.

]]> Fri, 27 Jul 2012 06:23:49 -0600 CYV15G0404DX-VIDEO http://www.cypress.com/?rID=14368 The Quad Independent Channel HOTLink II(TM)CYV15G0404DXB Video Demonstration (Demo) Board is a full-fledged serial digital video reference platform that demonstrates the HOTLink II video physical layers (PHYs) interfacing to industry-standard cable drivers and equalizers. Upstream processing of the video data is performed using on-board Altera Cyclone FPGAs. The board also has a flexible clocking architecture with automatic rate detection that allows the board to pass video traffic in multiple formats.

The Independent Channel HOTLink II devices are capable of simultaneously operating each channel at a different data rate. The CYV15G0404DXB has the additional capability of performing independent reclocking on a per-channel basis.

The Independent Channel HOTLink II CYV15G0404DXB Video Demo Board demonstrates:

  • The ability of the Cypress family of transceivers to pass serial digital video at signaling rates from 270 Mb/s to 1485 Mb/s
  • The independent channel functionality of the applicable devices
  • The ability to use a HOTLink II transceiver with an FPGA for auto rate detection and clock reconfiguration
  • The ability to perform reclocking in the HOTLink II CYV15G0404DXB device
  • The flexible configuration abilities of Cypress Microsystems' PSoC(TM) microcontroller
  • The use of Cypress EZ-USB FX2T USB microcontroller for video data and in-system configuration applications
  • On-board FPGAs that generate and receive different video test patterns.

Although this board uses the CYV15G0404DXB device, the same board can be used as an evaluation vehicle for any device in the HOTLink II Independent Channel family of devices. Please refer to the data sheets for descriptions of the HOTLink II Independent Channel family of devices.

]]> Mon, 23 Apr 2012 05:48:23 -0600 CYV15G0101DX-VIDEO http://www.cypress.com/?rID=14367

This development kit is no longer available. This web page has been left in place for informational purposes only.

The HOTLink II™ transceiver is a point-to-point or point-to-multipoint communications building block allowing the transfer of data over high-speed serial links at signaling speeds ranging from 195 to 1500 MBaud.

The frequency agility of the HOTLink II transceiver enables its application in various data and video transmission standards. The HOTLink II transceiver supports serial video transmission that complies with Digital Video Broadcasting (DVB-ASI) and Society of Motion Picture Television Engineers (SMPTE) standards. DVB is a widely accepted standard for digital video transmission, especially in the video-on-demand market. SMPTE has in turn developed several standards for serial and parallel video transmission at different speeds and formats.

The HOTLink II video evaluation board demonstrates the ability of the Cypress HOTLink II family of devices to pass video at signaling rates of up to 360 Mbps. It also demonstrates the functionality of Delta39K™ CPLD as an ideal CPLD solution for SMPTE applications, the flexible clocking abilities of CyClocksRT™, and the use of EZ-USB FX2™ USB microcontroller for video data and in-system configuration applications.

Some of the features include:
  • User-friendly GUI
  • Video transport at multiple data rates of 270 and 360 Mbps
  • Supports DVB-ASI (270 Mbps)
  • SMPTE scrambler/descrambler embedded in Delta39K CPLD
  • USB port to establish board configuration
  • High-speed USB FX2 to configure Delta39K CPLD and programmable clock
  • Flexible clocking abilities of CyClocksRT
  • External and internal loop back capability for SMPTE and DVB-ASI
  • Delta39K CPLD, reconfigurable via the USB or ISR(T) Header or from the boot memory
  • 12V DC supply with on-board voltage regulator to prevent noise transfer from external power sources
  • On-board serial equalizer and cable driver
  • LED status indicators

The software GUI is available for download from the Cypress website at the following location: CYV15G0101DXB Video Evaluation Board software

Additional information about this evaluation board can be found in the user's guide: HOTLink II™ Video Evaluation Board User's Guide

]]> Wed, 08 Feb 2012 00:21:09 -0600 CYP15G0101DX-EVAL http://www.cypress.com/?rID=14360 The CYP15G0101DXB single-channel HOTLink II(TM) transceiver is a point-to-point or point-to-multipoint communications building block allowing the transfer of data over high-speed serial links at signaling speeds ranging from 195 to 1500 MBaud.

The evaluation board allows users to become familiar with the functionality of the CYP15G0101DXB and perform simple tests.  Some of the features include:

  • Selectable serial interface
    • SMA connectors
    • Small form factor pluggable (SFP) optical module cages
  • Single 3.3V power supply
  • Power-on indicator (LED)
  • JTAG interface
  • Selectable clock options
    • Onboard crystal
    • SMA connectors for external REFCLK
  • LFI indicator (LED)
  • Switches for latch control
  • Selectable static control inputs
     

These features allow many evaluation modes including:

  • BIST internal loopback
  • BIST external loopback
  • Parallel data in and parallel data out mode

More information about this evaluation board can be found in the User's Guide:  CYP15G0101DXB Evaluation Board User's Guide

]]> Wed, 08 Feb 2012 00:15:38 -0600 CYP15G0401DX-EVAL http://www.cypress.com/?rID=14361

This development kit is no longer available. This web page has been left in place for informational purposes only.

The CYP15G0401DXB Quad HOTLink II™ transceiver is a point-to-point or point-to-multipoint communications building block allowing the transfer of data over high-speed serial links (optical fiber, balanced and unbalanced copper transmission lines) at signaling speeds ranging from 195 to 1500 MBaud per serial link. The multiple channels in each device may be combined to allow transport of wide buses across significant distances with minimal concern for offsets in clock phase or link delay.

The evaluation board allows users to become familiar with the functionality of the CYP15G0401DXB.  Some of the features include:

  • Selectable serial interfaces
    • SMA connectors
    • Small form factor pluggable (SFP) optical module cages
  • Single 3.3V power supply
  • Power-on indicator (LED)
  • JTAG interface
  • Selectable clock options
    • Onboard crystal (125 MHz)
    • SMA connectors for external REFCLK
  • LFI indicators (LED)
  • Switches for latch control
  • Selectable static control inputs
  • Selectable channel bonding options
     
These features allow many evaluation modes including:
  • BIST internal loopback
  • BIST external loopback
  • Parallel in - parallel out mode (encoded)
  • Parallel in - parallel out mode (unencoded)
  • Parallel in - serial out mode (testing the transmit side)
  • Different clock source (i.e., internal vs. external, different frequency mode, etc.)
     

More information about this evaluation board can be found in the following guide: CYP15G0401DXB Evaluation Board User's Guide

]]> Tue, 07 Feb 2012 23:47:06 -0600 Which SMPTE standards does the original HOTLink family support/not support? http://www.cypress.com/?rID=32407 Title:
Which SMPTE standards does the HOTLink I family support/not support?

Questions:
- How can I use the HOTLink 1 parts in a SMPTE-259M application?
- Does Cypress have a part that supports the SMPTE 310M video standard?

Response:
Within the HOTLink I family of parts there is a SMPTE 259M video chipset. The CY7B9234/9334 (Transmitter/Receiver) and the CY7C9235/9335 (Srambler/Descrambler) provide a SMPTE 259M solution. These parts support the following Levels:
1. SMPTE 259M Level C (270 Mbps, 525/625component)
2. SMPTE 259M Level D (360 Mbps, 525/625component)

In addition, a cable driver and equalizer will need to be used. Information on how to use the HOTLink 1 parts in a SMPTE-259M application can be found in two application notes (links are attached below). Adaptive Equalizers and Cable Drivers can be purchased from National Semiconductor. The parts we recommend are:
CLC006 Serial Digital Cable Driver with Adjustable Outputs
CLC007 Serial Digital Cable Driver with Dual Complementary Outputs
CLC014 Adaptive Cable Equalizer for High-Speed Data Recovery


Neither the HOTLink product family nor any other Cypress products support the SMPTE 310M standard for the following reasons:

- SMPTE-310M uses bi-phase mark encoding, HOTLink uses the 8B/10B encoding scheme,
- SMPTE-310M requires a synchronous serial interface to carry MPEG-2 transport bit streams at rates of up to 40Mb/s, HOTLinks lowest serial rate is 50Mb/s therefore is not compliant.

For more detailed information please see the SMPTE-310M spec and compare it to HOTLink specifications.


Useful Link:
SMPTE HOTLink Transmitter/Receiver (CY7B9234 Datasheet)

SMPTE 259M/DVB-ASI Scrambler/Controller (CY7C9235A Datasheet)

SMPTE 259M/DVB-ASI Descrambler/Framer-Controller (CY7C9335A Data Sheet)

Implement a SMPTE 259M Serial Digital Interface Using SMPTE HOTLink and CY7C9235/9335 http://www.cypress.com/?rID=12997

CY7C9267 SMPTE 259M Evaluation Boards User's Guide http://www.cypress.com/?rID=12996


Keywords:
HOTLink 1, SMPTE, standards, support, CY7C9235, CY7C9335, CY7C9234, CY7C9334

]]> Tue, 29 Nov 2011 04:05:46 -0600 AN1161 - HOTLink® Jitter Characteristics http://www.cypress.com/?rID=13024 This application note describes the basics of jitter in transmission systems and, using HOTLink™ as the example, shows how it can be analyzed and measured. Specific characterization data is presented to allow system integrators to understand the parameters needed to improve the reliability of their systems.

]]> Wed, 09 Nov 2011 04:39:36 -0600 AN1184 - Frequently Asked Questions about HOTLink® http://www.cypress.com/?rID=12747 How far can HOTLink communicate over various media?

HOTLink has no intrinsic distance limit. The two issues that determine the distances over which data can be sent using HOTLink are: (1) the choice of interconnect media (plastic or glass fiber-optic cable, coaxial cable, twisted-pair cable, etc.); and (2) the jitter that accumulates or is injected while the data is in transit over the selected media.

]]> Wed, 02 Nov 2011 02:38:33 -0600 AN1032 - Using Decoupling Capacitors http://www.cypress.com/?rID=12873 Network analysis is used to prove that the conventional recommendation of using widely spaced values can, in many circumstances, cause less than ideal operation. Simpler, more reliable designs will often result from following the design guidelines of this note. 

]]> Fri, 21 Oct 2011 05:02:41 -0600 AN1162 - HOTLink® Design Considerations http://www.cypress.com/?rID=13025 The HOTLink™ family of data communications products provides a simple and low-cost solution to high-speed data transmission. While these products are easy to use, the methods used to connect them to high-speed serial interfaces are often not intuitive. This document provides a basic level of explanation of the parallel and serial interface characteristics, and provides some cookbook solutions for interfacing them to different types of parts and media.

]]> Thu, 20 Oct 2011 02:01:29 -0600 AN1055 - Termination and Biasing of HOTLink IITM High-Speed Serial I/O http://www.cypress.com/?rID=12749 This application note is one of a series of design considerations for the use of the HOTLinkII device. Its purpose is to aid in the design of circuits used to connect the serial high-speed inputs and outputs of the CYP15G0401DX Quad HOTLinkII. It discusses high-speed circuit termination techniques and the required DC-biasing for the serial drivers and receivers used in the HOTLinkII device.

]]> Wed, 19 Oct 2011 07:28:55 -0600 AN4059 - Clocking Options When Using HOTLink II™ Devices in HD-SDI Video Applications http://www.cypress.com/?rID=12999 The HOTLink II(TM) family of physical layer (PHY) devices is a point-to-point or point-to-multipoint communications building block that provide serialization, deserialization, selectable 8B/10B encoding/decoding and framing functions. The family of devices are used in both SD (Standard Definition) and HD (High Definition) SDI (Serial Digital Interface) applications, i.e. SMPTE 259M-CD (270 and 360 Mbps), and SMPTE 292M (1.485 and 1.485/1.001 Gbps). This application note discusses the various clocking options that can be used in these applications when using the HOTLink II device. The application note focuses on HD-SDI applications at the 1.485 Gbps data rate, but can equally be applied in SD- and HD-SDI 1.485/1.001 Gbps environments by simply substituting the appropriate frequency for REFCLKx, via a clock oscillator or VCXO.

]]> Tue, 11 Oct 2011 08:44:15 -0600 Moisture Sensitivity Level (MSL) of Cypress Parts http://www.cypress.com/?rID=54061 If you know the Cypress part number: 

1. Go to www.cypress.com.  On the top right, you will see a “Keyword / Part Number” search box (adjacent to “Contact Us.”) 

2. Select the “Part Number” tab above this text box.

3. Type the exact part number, for example CY8C29466-12PVXE.

4. The part number will be listed in the search results page.

5. Click on the part number link (1st column starting from the left). This will open a new web page.

Moisture Sensitivity Level (MSL) can be found by clicking the “Quality & Pb-free Data” link on the top, or by just scrolling down to the Quality & Pb-free Data” section about half way down the page.

All other Quality information for this part number (e.g., RoHS compliance, Lead/Ball Finish, Qualification Reports, IPC reports) can also be found on this web page. 

In case of any questions, or if the information is not available for a particular part number, please create a support case at www.cypress.com/support

If you do not know the Cypress part number: 

1. Go to www.cypress.com.  Browse the different products (“Products” tab on the top navigation menu) by family.

2. Once you choose the relevant product family (e.g., “Clocks and Buffers->Clock Distribution,” “Memory->FIFOs”), scroll down the particular page to get to the “Parametric Product Selector.”

3. Use this tool to find the part number by function/feature, and click on the part number you are interested in. This will lead you directly to step # 5 above.

]]> Thu, 08 Sep 2011 21:22:46 -0600 AN1027 - Using High-Speed Serial Links to Supplement Parallel Data Buses http://www.cypress.com/?rID=12758 AN1027 discusses using the high speed serial link as a solution to replace parallel data using HOTLink®.

]]> Mon, 20 Jun 2011 05:16:38 -0600 Power Consumption of HOTLink II (TM) Family of Devices - AN027 http://www.cypress.com/?rID=13023 This application note illustrates the power consumed by any device in the HOTLink II(TM) family for a given operating frequency and configuration. Apart from illustrating the power consumption for different devices, the application note also discusses the instructions for the Cypress HOTLink II(TM) Power Estimation Graphical User Interface (GUI). The GUI can be downloaded from http://www.cypress.com/?rID=14430 under Software & Drivers.

]]> Fri, 13 May 2011 00:00:00 -0600 Guidelines for Selecting Reference Clock Input of the HOTLink II(TM) Device in Datacom Applications - AN5076 http://www.cypress.com/?rID=13001 The purpose of this application note is to analyze one of the contributors of jitter in the serial output, namely the phase noise present in the reference source. The bit-rate clock that clocks the shift register is a multiple of the reference clock. Hence, a portion of the jitter on the reference clock is transferred to the serial bit rate clock which in turn translates to jitter at the serial data output.

This document presents phase noise of nine sample crystal oscillators for which the HOTLink II(TM) serial data output meets the jitter specifications for serial output jitter.

]]> Thu, 12 May 2011 09:11:33 -0600 Guidelines for Selecting the Reference Clock Input of the HOTLink II Device in SMPTE SDI Video Applications - AN5073 http://www.cypress.com/?rID=13003 The purpose of this application note is to analyze one of the contributors of jitter in the serial output, namely the phase noise present in the reference source. The bit-rate clock that clocks the shift register is a multiple of the reference clock. Hence, a portion of the jitter on the reference clock is transferred to the serial bit rate clock which in turn translates to jitter at the serial data output.

This application note presents the phase noise of five sample clock sources for which the HOTLink II(TM) serial data output meets the SMPTE jitter specifications for both alignment and timing jitter.

]]> Thu, 12 May 2011 09:08:11 -0600 Frequently Asked Questions About the CYP(V)15G0403DXB Device - AN060_B http://www.cypress.com/?rID=12756 The following are Frequently Asked Questions (FAQs) by customers who are evaluating CYP(V)15G0403DXB devices. The CYP(V)15G0403DXB is a member of Cypress's High-Speed Frequency Agile HOTLink II. product family. Within the device, all four channels can simultaneously operate at different data rates and transmit different types of data. The only difference between the CYP15G0403DXB and the CYV15G0403DXB devices is that the latter satisfies SMPTE 259M and SMPTE 292M pathological test requirements per SMPTE EG 34-1999.

]]> Fri, 06 May 2011 00:00:00 -0600 Jitter Generation and Jitter Tolerance of Independent Channel HOTLink II(TM) Devices for Datacom Applications - AN5077 http://www.cypress.com/?rID=13002 Fri, 06 May 2011 00:00:00 -0600 AN17006 - High Speed Serial Simulation with HOTLink II™ http://www.cypress.com/?rID=12670 The HOTLink II™ family of devices are point-to-point or point-to-multipoint communication building blocks, providing encoding, serialization, deserialization, and decoding at high speed and are compatible with many communication standards. A HOTLink II device is a frequency agile transceiver with the ability of the serial links to transport data at a rate between 0.2 and 1.5 Gigabits per second (Gbps) per channel. ]]> Tue, 22 Mar 2011 18:46:42 -0600 Configuring the Independent Channel HOTLink II(TM) Device for Digital VideoTransport http://www.cypress.com/?rID=13008 Thu, 17 Feb 2011 04:31:47 -0600 HOTLink(R) CY7B923/CY7B933 to HOTLink II(TM) Migration - AN1160 http://www.cypress.com/?rID=13028 This application note discusses how to migrate from HOTLink-based designs to HOTLink II-based designs. While most designs can be converted from HOTLink to HOTLink II, applications that use the device at signaling rates of less than 200 Mbaud cannot be migrated. The scope of this application note is limited to device configuration, although some information on device operation is covered as necessary. The Quad HOTLink II Transceiver (CYP15G0401DXB) is used to illustrate how to migrate your design and one of the channels is used to show how to interface the HOTLink device to the HOTLink II devices.

]]> Wed, 16 Feb 2011 00:00:00 -0600 SD-SDI and HD-SDI Checkfield Testing on HOTLink II(TM) Transceivers for SMPTE Pathological Conditions - AN084 http://www.cypress.com/?rID=13013 The HOTLink II(TM) family of physical layer (PHY) devices is a point-to-point or point-to-multipoint communications building block that provides serialization, deserialization, optional 8B/10B encoding/decoding and framing functions. It can transport serial data at rates from 195 Mbps to 1.5 Gbps per channel and is compliant with communication standards such as SMPTE 259M, SMPTE 292M, DVB-ASI, Gigabit Ethernet, Fibre Channel and ESCON(R).

]]> Wed, 16 Feb 2011 00:00:00 -0600 Crosstalk Analysis of the Quad Independent Channel HOTLink II(TM) Device - AN4047 http://www.cypress.com/?rID=13027 The HOTLink II(TM) family of physical layer (PHY) devices is a point-to-point or point-to-multipoint communications building block that provides serialization, deserialization, optional 8B/10B encoding/decoding and framing functions. The quad independent channel device is a member of this frequency agile family that can support serial data rates between 195 and 1.5 Gbps per channel. Within this device, all four channels can simultaneously operate at different data rates and transmit different types of data. In order to provide this flexible feature, each channel has its own transmit and receive Phase-Locked Loops (PLLs).

]]> Mon, 14 Feb 2011 00:00:00 -0600 HD-SDI and SD-SDI SMPTE Jitter Performance of the Independent Channel HOTLinkII(TM) Transceiver in a System - AN5004 http://www.cypress.com/?rID=13015 The HOTLink II(TM) family of physical layer (PHY) devices is a point-to-point or point-to-multipoint communications building block that provides serialization, deserialization, optional 8B/10B encoding/decoding and framing functions. It can transport serial data at rates from 195 Mbps to 1.5 Gbps per channel and is compliant to digital video standards such as SMPTE 259M, SMPTE 292M and DVB-ASI.

]]> Mon, 14 Feb 2011 00:00:00 -0600 Driving Teradyne FR4 and GETEK Backplanes with the HOTLink II(TM) Transceivers - AN072 http://www.cypress.com/?rID=48470 Fri, 21 Jan 2011 05:25:11 -0600 Interfacing the HOTLink II(TM) Transceiver with the 3.3V Gennum GS1524 Equalizer and GS1528 Cable Driver for Digital Video - AN080 http://www.cypress.com/?rID=12757 Tue, 18 Jan 2011 00:26:02 -0600 CYV15G0404DX-EVAL http://www.cypress.com/?rID=14369

This development kit is no longer available. This web page has been left in place for informational purposes only.

The CYV15G0404DXB Quad Independent-Channel HOTLink II™ Transceiver is a point-to-point or point-to-multipoint communications building block that allows the transfer of data over high-speed serial links (optical fiber, balanced, and unbalanced copper transmission lines) at signaling speeds ranging from 195 to1500 MBaud per serial link. The independence of each channel provides the ability to simultaneously transport different types of data at different signaling rates across multiple channels.

This user's guide describes the operation and interface of the CYV15G0404DXB evaluation board. The evaluation board allows users to become familiar with the functionality of the CYV15G0404DXB.

]]> Wed, 07 Apr 2010 14:01:17 -0600 CY9267-C http://www.cypress.com/?rID=14366 CY9267-C

SMPTE-259M evaluation board, No. WH016

]]> Wed, 07 Apr 2010 14:00:46 -0600 CYP15G0401DXB-Verilog http://www.cypress.com/?rID=15580 Wed, 07 Apr 2010 13:57:47 -0600 CYP15G0201DXB-VHDL http://www.cypress.com/?rID=15579 Wed, 07 Apr 2010 13:57:00 -0600 CYP15G0201DXB-Verilog http://www.cypress.com/?rID=15578 Wed, 07 Apr 2010 13:56:47 -0600 CYP15G0401DXB-VHDL http://www.cypress.com/?rID=15577 Wed, 07 Apr 2010 13:56:29 -0600 CYP15G0402DXB-VHDL http://www.cypress.com/?rID=15576 Wed, 07 Apr 2010 13:56:08 -0600 CYP15G0403DXB-VHDL http://www.cypress.com/?rID=15575 Wed, 07 Apr 2010 13:55:55 -0600 CYP15G0201DXB-BSDL http://www.cypress.com/?rID=15574 Wed, 07 Apr 2010 13:55:34 -0600 CYP15G0101DXB-BSDL http://www.cypress.com/?rID=15573 Wed, 07 Apr 2010 13:55:04 -0600 CYP15G0402DXB-BSDL http://www.cypress.com/?rID=15572 Wed, 07 Apr 2010 13:54:53 -0600 CYP15G0101DXB-Verilog http://www.cypress.com/?rID=17590 Wed, 07 Apr 2010 13:52:31 -0600 CYP15G0402DXB-Verilog http://www.cypress.com/?rID=17589 Wed, 07 Apr 2010 13:52:23 -0600 CYP15G0401DXB-BSDL http://www.cypress.com/?rID=17587 Wed, 07 Apr 2010 13:52:02 -0600 CYV15G0204TRB-BSDL http://www.cypress.com/?rID=17586 Wed, 07 Apr 2010 13:51:54 -0600 CYV15G0204RB-BSDL http://www.cypress.com/?rID=17585 Wed, 07 Apr 2010 13:51:45 -0600 CYV15G0203TB-BSDL http://www.cypress.com/?rID=17584 Wed, 07 Apr 2010 13:51:36 -0600 CYV15G0404DXB-BSDL http://www.cypress.com/?rID=17583 Wed, 07 Apr 2010 13:51:22 -0600 CYV15G0404RB-BSDL http://www.cypress.com/?rID=17582 Wed, 07 Apr 2010 13:51:06 -0600 CYV15G0403TB-BSDL http://www.cypress.com/?rID=17581 Wed, 07 Apr 2010 13:50:53 -0600 CYV15G0104TRB-BSDL http://www.cypress.com/?rID=17580 Wed, 07 Apr 2010 13:50:40 -0600 Video Equalizers photo http://www.cypress.com/?rID=14835 Wed, 07 Apr 2010 13:49:18 -0600 HOTLink Video Selector Guide http://www.cypress.com/?rID=14833 This guide aids in the proper selection of HOTLink devices for video applications using a decision tree and feature matrix.

 

]]> Wed, 07 Apr 2010 13:48:48 -0600 HD/SD Multi-Format Video Cable Driver http://www.cypress.com/?rID=14832 Wed, 07 Apr 2010 13:45:58 -0600 HOTLink-on-Demand http://www.cypress.com/?rID=14829

Building upon the success of the world's first quad independent channel video SERDES, the HOTLink-On-Demand portfolio of twelve devices provides designers with scalability and flexibility in their professional video equipment designs, including production switchers, distribution amplifiers, D/A and A/D converters, and camera control units. 

]]> Wed, 07 Apr 2010 13:45:43 -0600 HotLink II Independent Channel http://www.cypress.com/?rID=14828

The HotLink II(TM) Independent Channel is the industry's first quad independent-channel SERDES to allow simultaneous operation of SMPTE and DVB-ASI video protocols.

]]> Wed, 07 Apr 2010 13:42:53 -0600 CYV15G0101DXB Video Evaluation Board Software http://www.cypress.com/?rID=14458 The HOTLink II(TM) transceiver is a point-to-point or point-to-multipoint communications building block allowing the transfer of data over high-speed serial links at signaling speeds ranging from 195 to 1500 MBaud.

The HOTLink II video evaluation board demonstrates the ability of the Cypress HOTLink II family of devices to support serial video transmission, which complies with Digital Video Broadcasting (DVB-ASI) and Society of Motion Picture Television Engineers (SMPTE) standards.

The following file contains a self-installation GUI for the evaluation board.

The system requirements are:

  • Windows 2000/XP Operating System
  • 3.7 MB of available space
  • USB

To install the software, simply save this file on your PC and unzip it. Double-click the executable (setup.exe) file and follow the instructions on the GUI.

]]> Wed, 07 Apr 2010 13:42:24 -0600 Cypress HOTLink II (TM) Power Estimation GUI http://www.cypress.com/?rID=14430 This GUI is used to estimate power for various operating modes of the HOTLink II(TM) family of devices including the CYP15G0401DXB,  CYP15G0201DXB and CYP15G0101DXB transceivers and the CYP15G0402DXB serializer/deserializer (SERDES). The tool is opened using MS-EXCEL software. Then, when prompted, macros are enabled.

More details about the GUI can be found in the "Power Consumption of HOTLink II(TM) Family of Devices" application note.

]]> Wed, 07 Apr 2010 13:40:57 -0600 SMPTE 259M Scrambler/Descrambler IP Core http://www.cypress.com/?rID=14465 Wed, 07 Apr 2010 13:40:09 -0600 SMPTE Automatic Rate Detection 270, 360, 540, 1483.5, http://www.cypress.com/?rID=14464
Included in this IP core is necessary information regarding inputs and outputs, the FPGA VHDL code, and explanation pertaining to such code.]]> Wed, 07 Apr 2010 13:39:55 -0600 SMPTE Automatic Rate Detection 270, 1483.5, 1485 Mb/s http://www.cypress.com/?rID=14463 The automatic rate detection core allows designers to meet the multi-format requirement for SMPTE specifications. SMPTE specifies SDI rates of 270, 1483.5, and 1485 Mb/s. The automatic rate detection core gives applications the ability to differentiate between the various rates and hence support multiple formats. Therefore, with autorate detect designers do not need to worry about whether an HD or SD
input is being inserted into the application. The required parts for automatic rate detection are the HOTLink II(TM) SERDES, the HOTLink II Receiver Training Clock, a crystal, and an FPGA.

Included in this IP core is necessary information regarding inputs and outputs, the FPGA VHDL code, and explanation pertaining to such code.

]]> Wed, 07 Apr 2010 13:39:40 -0600 AN1025 - Using HOTLink® with Long Copper Cables http://www.cypress.com/?rID=13026 While "Driving Copper Cables with HOTLink" describes how to operate HOTLink with copper media, this application note discusses the additional problems that must be considered when driving very long cables. The design of equalization networks to increase the operational length of a copper interconnect is also covered.

]]> Wed, 07 Apr 2010 12:54:58 -0600 Video Equalizer (CYV15G0101/2) Photo http://www.cypress.com/?rID=14830 Sat, 15 Aug 2009 11:08:07 -0600 Quad HotLink II Family (CYP15G0101/201/401/402DX*, CYV15G0101/201/401/402DX*, CYW15G0101/201/401DX*) B53D-3 Technology, Fab 4 http://www.cypress.com/?rID=35577 Tue, 17 Mar 2009 00:00:00 -0600 Bit-Error Rate (BER) for high speed serial data communication http://www.cypress.com/?rID=14617 Thu, 13 Nov 2008 00:00:00 -0600 Wirespeed Communication Solutions Brochure http://www.cypress.com/?rID=14712 Communication systems continue to revolutionize the way we conduct our lives, both personally and professionally. With the continued growth of the Internet, specialized silicon-based solutions are necessary to provide reliable, state-of-the-art network infrastructure equipment.

To address the increasing complexity and bandwidth requirements of these communication systems, Cypress offers a comprehensive portfolio of high-performance solutions.

Cypress's broad product portfolio offers wirespeed solutions across the entire linecard. Port PHY devices and framers optimize high-speed transmissions over SONET/SDH; Flexible PHY and backplane management solutions continue to drive high-performance serial backplanes.

Cypress solutions are instrumental in enabling datapath connections from last mile to first mile.

]]> Thu, 13 Nov 2008 00:00:00 -0600 Video Cable Equalizer Family 0.18um Mixed Mode/RFCMOS Technology Fab8C, UMC-Taiwan http://www.cypress.com/?rID=36003 Thu, 22 May 2008 00:00:00 -0600 Independent Clock Quad HotLink II Family, B53D-3 Technology, Fab4 http://www.cypress.com/?rID=35627 Tue, 11 Jan 2005 00:00:00 -0600 TSMC-Fab 2B, High Performance CPLDs - 128 Macrocell, E3 Technology (CY37128P84,CY37128VP84) http://www.cypress.com/?rID=35477 Mon, 01 Jan 2001 00:00:00 -0600 Fab 2 - Hotlink Receiver (CY7B933/9331) http://www.cypress.com/?rID=36119 Fri, 01 Jul 1994 00:00:00 -0600