Cypress.com: Documentation

Product Selector Guide (PSG) - Interface

Wed, 03 Apr 2013 06:52:32 -0600

Cypress has the broadest and most flexible portfolio of backplane physical layer (PHY) devices, covering data transmission rates of 50 Mbps to 1.5 Gbps. These flexible devices are ideal for proprietary serial backplane applications.

Crosstalk Measurement Techniques for Multi-Channel and Multi-Rate High Speed Serial Communication Systems

Sun, 06 Jan 2013 22:51:52 -0600

Crosstalk is the effect on a signal caused by the high-speed switching of a nearby signal. This effect can manifest itself as jitter, which is the deviation of a signal's edge from its expected location. A large amount of jitter can cause a timing budget failure in a parallel system or it can cause a clock and data recovery PLL to incorrectly recover the data in a serial system.

Due to the deleterious effects of crosstalk, it is important to determine the amount of it that exists during worst case scenarios. Currently, there are no standard crosstalk measurement techniques for the serial domain. This article describes effective measurement techniques and how to determine if the amount of crosstalk is acceptable for reliable data transfer. The techniques described include measuring the device's jitter output with a wide-bandwidth oscilloscope and spectral output with a high-bandwidth spectrum analyzer. Also discussed are the configurations that yield the highest crosstalk scenarios. Real measurement data of a multi-channel, independent rate device is provided. The measurements are performed at video serial digital interface (SDI) data rates, but the measurement techniques apply to any high-speed standard. To read more on this topic, click the download link above, or visit Planet Analog.

CYP15G0101DXB, CYV15G0101DXB: Single-channel HOTLink II™ Transceiver

Mon, 30 Jul 2012 05:30:50 -0600

Single-channel HOTLink II™ Transceiver

Features

Second-generation HOTLink® technology
Compliant to multiple standards
- ESCON®, DVB-ASI, fibre channel and gigabit ethernet (IEEE802.3z)
- CPRI™ compliant
- CYV15G0101DXB compliant to SMPTE 259M and SMPTE 292M
- 8B/10B encoded or 10-bit unencoded data
Single-channel transceiver operates from 195 to 1500 MBaud serial data rate
For more, see pdf

Functional Description

The CYP15G0101DXB single-channel HOTLink II™ transceiver is a point-to-point communications building block allowing the transfer of data over a high-speed serial link (optical fiber, balanced, and unbalanced copper transmission lines) at signaling speeds ranging from 195 to 1500 MBaud.

The transmit channel accepts parallel characters in an input register, encodes each character for transport, and converts it to serial data. The receive channel accepts serial data and converts it to parallel data, frames the data to character boundaries, decodes the framed characters into data and special characters, and presents these characters to an output register.

CYP15G0403DXB: Independent Clock Quad HOTLink II™ Transceiver

Mon, 30 Jul 2012 04:33:44 -0600

Independent Clock Quad HOTLink II™ Transceiver

Features

Second-generation HOTLink® technology
Compliant to multiple standards
- ESCON, DVB-ASI, SMPTE-292M, SMPTE-259M, Fibre Channel and Gigabit Ethernet (IEEE802.3z)
- CPRI™ compliant
- 8B/10B coded data or 10 bit uncoded data
Quad channel transceiver operates from 195 to 1500 MBaud serial data rate
- Aggregate throughput of up to 12 Gbits/second
Second-generation HOTLink technology
Truly independent channels
For more, see pdf

Functional Description

The CYP(V)15G0403DXB Independent Clock Quad HOTLink II™ Transceiver is a point-to-point or point-to-multipoint communications building block enabling transfer of data over a variety of high-speed serial links like optical fiber, balanced, and unbalanced copper transmission lines. The signaling rate can be anywhere in the range of 195 to 1500 MBaud per serial link.

CYP15G0401DXB, CYV15G0401DXB: Quad HOTLink II™ Transceiver

Mon, 30 Jul 2012 04:29:31 -0600

Quad HOTLink II™ Transceiver

Features

Second-generation HOTLink® technology
Compliant to multiple standards
Quad channel transceiver operates from 195 to 1500 MBaud serial data rate
Selectable parity check/generate
Selectable multi-channel bonding options
Skew alignment support for multiple bytes of offset
Selectable input/output clocking options
MultiFrame™ Receive Framer
Synchronous LVTTL parallel interface
For more, see pdf

Functional Description

The CYP(V)15G0401DXB Quad HOTLink II™ Transceiveris a point-to-point or point-to-multipoint communications building block allowing the transfer of data over high-speed serial links (optical fiber, balanced, and unbalanced copper transmission lines) at signaling speeds ranging from 195-to-1500 MBaud per serial link.

CY7C9689A: TAXI™-compatible HOTLink Transceiver

Mon, 30 Jul 2012 04:28:32 -0600

TAXI™-compatible HOTLink® Transceiver

Features

Second-generation HOTLink® technology
AMD™ AM7968/7969 TAXIchip™-compatible
8-bit 4B/5B or 10-bit 5B/6B NRZI encoded data transport
10-bit or 12-bit NRZI pre-encoded (bypass) data transport
Synchronous TTL parallel interface
Embedded/bypassable 256-character Transmit and Receive FIFOs
50- to 200-MBaud serial signaling rate
Internal phase-locked loops (PLLs) with no external PLL components
Dual differential PECL-compatible serial inputs and outputs
For more, see pdf

Functional Description

The CY7C9689A HOTLink Transceiver is a point-to-point communications building block allowing the transfer of data over high-speed serial links (optical fiber, balanced, and unbalanced copper transmission lines) at speeds ranging between 50 and 200 MBaud. The transmit section accepts parallel data of selectable widths and converts it to serial data, while the receiver section accepts serial data and converts it to parallel data of selectable widths.

CY7B923, CY7B933: HOTLink® Transmitter/Receiver

Mon, 30 Jul 2012 04:26:15 -0600

HOTLink®Transmitter/Receiver

Features

Fibre Channel-compliant
IBM ESCON®-compliant
DVB-ASI-compliant
ATM-compliant
8B/10B-coded or 10-bit unencoded
Standard HOTLink®: 160 to 330 Mbps
High-speed HOTLink: 160 to 400 Mbps for high-speed applications
Transistor-transistor logic (TTL)-synchronous I/O
No external phase locked-loop (PLL) components
For more, see pdf

Functional Description

The CY7B923 HOTLink‚ transmitter and CY7B933 HOTLink receiver are point-to-point communications building blocks that transfer data over high-speed serial links (fiber, coax, and twisted pair). Standard HOTLink data rates range from 160 to 330 Mbps. Higher speed HOTLink is also available for high-speed applications (160 to 400 Mbits/second).

CY7C924ADX: 200 MBaud HOTLink® Transceiver

Mon, 30 Jul 2012 04:25:03 -0600

200 MBaud HOTLink(TM) Transceiver

Features

Second generation HOTLink(TM) technology
Fibre Channel and ESCON(TM) compliant 8B/10B encoder/decoder
10 or 12 bit preencoded data path (raw mode)
8 or 10 bit encoded data transport (using 8B/10B coding)
Synchronous or asynchronous TTL parallel interface
UTOPIA compatible host bus interface
Embedded/Bypassable 256-character synchronous FIFOs
Integrated support for daisy-chain and ring topologies
Domain or individual destination device addressing
For more, see pdf

Functional Description

The 200 MBaud CY7C924ADX HOTLink Transceiver is a point-to-point communications building block allowing the transfer of data over high speed serial links (optical fiber, balanced, and unbalanced copper transmission lines) at speeds ranging between 50 and 200 MBaud. The transmit section accepts parallel data of selectable width and converts it to serial data, while the receiver section accepts serial data and converts it to parallel data of selectable width. More...

CY7B952: SST™ SONET/SDH Serial Transceiver

Mon, 30 Jul 2012 02:12:02 -0600

SST™ SONET/SDH Serial Transceiver

Features

OC-3 Compliant with Bellcore and CCITT (ITU) specifications on:
- Jitter Generation (<0.01 UI)
- Jitter Transfer (<130 kHz)
- Jitter Tolerance
SONET/SDH and ATM Compliant
Compatible with IGT WAC013, IGT WAC413, and PMC-Sierra PM5343
Clock and data recovery from 51.84- or 155.52-MHz datastream
155.52-MHz clock multiplication from 19.44-MHz source
51.84-MHz clock multiplication from 6.48-MHz source
For more, see pdf

Functional Description

The SONET/SDH Serial Transceiver (SST) is used in SONET/SDH and ATM applications to recover clock and data information from a 155.52-MHz or 51.84-MHz NRZ or NRZI serial data stream and to provide differential data buffering for the Transmit side of the system.

CY7B951: Local Area Network ATM Transceiver

Mon, 30 Jul 2012 02:01:40 -0600

Local Area Network ATM Transceiver

Features

SONET/SDH and ATM Compatible
Compatible with PMC-Sierra PM5345 SUNI™
Clock and data recovery from 51.84- or 155.52-MHz datastream
155.52-MHz clock multiplication from 19.44-MHz source
51.84-MHz clock multiplication from 6.48-MHz source
±1% frequency agility
Line Receiver Inputs: No external buffering required
Differential output buffering
100K ECL compatible I/O
For more, see pdf

Functional Description

The Local Area Network ATM Transceiver is used in SONET/SDH and ATM applications to recover clock and data information from a 155.52-MHz or 51.84-MHz NRZ or NRZI serial data stream and to provide differential data buffering for the Transmit side of the system.

CYS25G0101DX: SONET OC-48 Transceiver

Mon, 30 Jul 2012 02:00:21 -0600

SONET OC-48 Transceiver

Features

SONET OC-48 operation
Bellcore and ITU jitter compliance
2.488 GBaud serial signaling rate
Multiple selectable loopback or loop through modes
Single 155.52 MHz reference clock
Transmit FIFO for flexible data interface clocking
16-bit parallel-to-serial conversion in transmit path
Serial-to-16-bit parallel conversion in receive path
Synchronous parallel interface
For more, see pdf

Functional Description

The CYS25G0101DX SONET OC-48 Transceiver is a communications building block for high speed SONET data communications. It provides complete parallel-to-serial and serial-to-parallel conversion, clock generation, and clock and data recovery operations in a single chip optimized for full SONET compliance.

CYP15G0201DXB: Dual-channel HOTLink II™ Transceiver

Fri, 27 Jul 2012 06:23:49 -0600

Dual-channel HOTLink II™ Transceiver

Features

Second-generation HOTLink® technology
Compliant to multiple standards
- ESCON, DVB-ASI, Fibre Channel and Gigabit Ethernet (IEEE802.3z)
- CPRI™ compliant
- 8-/10-B encoded or 10-bit unencoded data
Dual channel transceiver operates from 195 to 1500-MBaud serial data rate
- Aggregate throughput of 6-GBits per second
Selectable parity check/generate
Selectable dual-channel bonding option
For more, see pdf

Functional Description

The CYP15G0201DXB dual-channel HOTLink II™ transceiver is a point-to-point or point-to-multipoint communications building block allowing the transfer of data over high-speed serial links (optical fiber, balanced, and unbalanced copper transmission lines) at signaling speeds ranging from 195- to 1500-MBaud per serial link.

CYP15G0101DX-EVAL

Wed, 08 Feb 2012 00:15:38 -0600

The CYP15G0101DXB single-channel HOTLink II(TM) transceiver is a point-to-point or point-to-multipoint communications building block allowing the transfer of data over high-speed serial links at signaling speeds ranging from 195 to 1500 MBaud.

The evaluation board allows users to become familiar with the functionality of the CYP15G0101DXB and perform simple tests. Some of the features include:

Selectable serial interface
- SMA connectors
- Small form factor pluggable (SFP) optical module cages
Single 3.3V power supply
Power-on indicator (LED)
JTAG interface
Selectable clock options
- Onboard crystal
- SMA connectors for external REFCLK
LFI indicator (LED)
Switches for latch control
Selectable static control inputs

These features allow many evaluation modes including:

BIST internal loopback
BIST external loopback
Parallel data in and parallel data out mode

More information about this evaluation board can be found in the User's Guide: CYP15G0101DXB Evaluation Board User's Guide

CYS25G0101DX-EVAL

Wed, 08 Feb 2012 00:10:52 -0600

Cypress's CYS25G0101DX SONET OC-48 Transceiver is a communications building block for high-speed SONET data communications. It provides complete parallel-to-serial and serial-to-parallel conversions, clock generation, and clock and data recovery operations in a single chip, optimized for full SONET/SDH compliance.

The CYS25G0101DX Evaluation Board is designed for evaluating as well as understanding the characteristics of the CYS25G0101DX SONET/SDH Transceiver. The evaluation board provides the following advantages:

Flexible and easy to operate
On-board Cypress 120-pin thin quad flat pack (TQFP) CYS25G0101DX SONET/SDH Transceiver
Supports LVPECL or HSTL interfaces
Dip switch for selecting different diagnostic modes
Four diagnostic modes - Diagnostic Loopback mode, Line Loopback mode, Analog Line Loopback mode, and factory TEST0 (Parallel Line Loopback) mode
LFI and FIFO_ERR LEDs
Onboard oscillator for the REFCLK
Supports external clock source for the REFCLK
16-bit RxD, 16-bit TxD bus, RXCLK, TXCLKI, TXCLKO interface
SMA connectors for CML input and output buffers
Separate Banana Jacks for all voltage sources for measuring current individually

For more information, please refer to the user's guide: CYS25G0101DX Evaluation Board User's Guide

CYP15G0401DX-EVAL

Tue, 07 Feb 2012 23:47:06 -0600

This development kit is no longer available. This web page has been left in place for informational purposes only.

The CYP15G0401DXB Quad HOTLink II™ transceiver is a point-to-point or point-to-multipoint communications building block allowing the transfer of data over high-speed serial links (optical fiber, balanced and unbalanced copper transmission lines) at signaling speeds ranging from 195 to 1500 MBaud per serial link. The multiple channels in each device may be combined to allow transport of wide buses across significant distances with minimal concern for offsets in clock phase or link delay.

The evaluation board allows users to become familiar with the functionality of the CYP15G0401DXB. Some of the features include:

Selectable serial interfaces
- SMA connectors
- Small form factor pluggable (SFP) optical module cages
Single 3.3V power supply
Power-on indicator (LED)
JTAG interface
Selectable clock options
- Onboard crystal (125 MHz)
- SMA connectors for external REFCLK
LFI indicators (LED)
Switches for latch control
Selectable static control inputs
Selectable channel bonding options

These features allow many evaluation modes including:

BIST internal loopback
BIST external loopback
Parallel in - parallel out mode (encoded)
Parallel in - parallel out mode (unencoded)
Parallel in - serial out mode (testing the transmit side)
Different clock source (i.e., internal vs. external, different frequency mode, etc.)

More information about this evaluation board can be found in the following guide: CYP15G0401DXB Evaluation Board User's Guide

SPLDs for New Designs

Sun, 01 Jan 2012 17:29:11 -0600

We recommend using the Ultra37000 CPLD devices for new designs. The Ultra37000 CPLDs is a different family of products with a higher density. The Ultra37000 CPLDs will require PCB changes and the source code to be retargeted and recompiled. The datasheet for the Ultra37000 devices is available on our website.

Please be noted our entire Cypress CPLD product are Obsolete and not recommended for new design and development. For more information on CPLD product, please visit our webpage: http://www.cypress.com/go/cpld

Use of the CEO/A2 in a Single Chip Configuration

Sun, 01 Jan 2012 17:17:23 -0600

The /CEO output of any CY3LV drives the /CE input of the next CY3LV in a cascaded chain of EEPROMs. This is an output that will stay HIGH until the entire EEPROM is read again. This same pin duals as the A2 input pin when used in conjuction with each individual PROM's /SER_EN signal. When /SER_EN is asserted low, A2 will be used to select which PROM to be programmed.

The /CEO, A2 should be left open when configuring the 39K when using only one EEPROM.

Functionality Problem with Ultra37000V CPLD Despite Passing Simulation

Sun, 01 Jan 2012 17:13:48 -0600

Please check the power supply voltages. There are instances where a 5V power supply has been used on a 3.3V (V) part, and this resulted in functionality issues on a few pins. This difference in power supplies can also result in failed daisy chain errors when programming.

Please be noted our entire Cypress CPLD product are Obsolete and not recommended for new design and development. For more information on CPLD product, please visit our webpage:http://www.cypress.com/go/cpld

Hysteresis on Input of Cypress Quantum38K CPLDs

Sun, 01 Jan 2012 17:10:13 -0600

Quantum38K CPLD's do not have explicit input hysteresis, but the effect of the bus hold circuit (if enabled) on the input may look like hysteresis. Bus hold can be approximated as a current source. As the input rises, bus hold will continue to pull low. Eventually, the input reaches the bus hold trip point and the output changes state. That means it switches from pulling low to pulling high. This change in direction of the bushold current together with the output impedance of the driver will cause a "jump" in the input voltage which looks a lot like hysteresis.

Are military parts vacuum sealed?

Sun, 01 Jan 2012 17:04:03 -0600

Unfortunately, these devices are not vacuum sealed. They are, however, hermetically sealed, but there is atmospheric pressure inside the device. For more information on which device are available in a hermetically sealed package, please read the Knowledge Base article entitled "Hermetically Sealed Ultra 37000 Availability".

Issues with Pins Locked to a Certain Level Despite Simulation

Sun, 01 Jan 2012 16:59:53 -0600

Issues of this kind usually result from issues that are not related to the software code. This situation often occurs when the device was improperly programmed. Please check the length of the ISR cable being used to program the device. If the cable and ribbon put together is longer than 6 feet, the problem may be in the fact that the PC is unable to drive a coherent signal over the length of the cable. Another thing to check for is to see if the JTAGen pin is toggled properly after programming has completed.

Why tS > tSPT for Ultra 37000 CPLDs

Sun, 01 Jan 2012 16:47:41 -0600

Setup is the amount of time before the clock edge when the data must be static. Consider the two input paths in two arbitrary devices with made-up timing numbers -- for the "tSPT" device, the data delay is 4ns and the clock delay is 4ns. For the "tS" device, the data delay is 4ns and the clock delay is 2ns, since the clock tree is faster than the datapath. Now assume that both devices have the same register internally, and this register has a "micro-tS" of 0ns. That is, the setup-time referenced to the internal inputs of the register (not the external pins) is 0ns. When you take into account the delays for the signals from the pins, you end up with a ts of 0ns for the tspt case, and 2ns for the ts case. The skew between the two clock and data signals due to the clock tree is responsible. Since the clock gets to the register faster for ts, you've lengthened the setup window. The opposite, of course, will happen for hold time. Further, note that "true" setup + hold externally referenced is a constant determined by the register. The reason it is not reported as a constant in the datasheet is due to the fact that a negative hold time tends to confuse people. Therefore, it is reported as 0 to prevent confusion.

Please be noted our entire Cypress CPLD product are Obsolete and not recommended for new design and development. For more information on CPLD product, please visit our webpage: http://www.cypress.com/go/cpld

Thermal Information for Cypress Flash370i CPLDs

Sun, 01 Jan 2012 16:47:40 -0600

The Thermal information is located in the table that follows:

Device	Package Type	Theta JA (C/W)	Theta JC (C/W)
CY7C371i	44-Lead Thin Plastic Quad Flatpack	62	17
CY7C371i	44-Lead Plastic Leaded Chip Carrier	54	18
CY7C372i	44-Lead Plastic Leaded Chip Carrier	38	16
CY7C372i	44-Pin Thin Quad Flatpack	56	6
CY7C373i	84-Lead Plastic Leaded Chip Carrier	35	16
CY7C373i	100-Pin Thin Quad Flatpack	50	7
CY7C374i	84-Lead Plastic Leaded Chip Carrier	35	16
CY7C374i	100-Pin Thin Quad Flat Pack	29	5
CY7C374i	84-Pin Ceramic Leaded Chip Carrier	50	7
CY7C375i	160-Lead Thin Quad Flatpack	34	7
CY7C375i	160-Pin Grid Array	24	3
CY7C375i	160-Pin Ceramic Quad Flatpack	30	5

Differences Between Revision A and Revision B of Ultra 37000 CPLDs

Sun, 01 Jan 2012 16:43:45 -0600

Revision B changed the manufacturing process slightly to improve the characteristics of the revision A silicon. These changes are relatively minor and will not acutely affect device performance. The changes are listed below.

- improved device speed
- improved ESD tolerance
- improved yield
- improved latch-up performance

Please be noted our entire Cypress CPLD product are Obsolete and not recommended for new design and development. For more information on CPLD product, please visit our webpage: http://www.cypress.com/go/cpld

ISR Failures during Flash 370 and Flash 370i Programming

Sun, 01 Jan 2012 16:42:45 -0600

The Flash JAM driver uses a high performance counter located on all PC motherboards, and assumes that it counts at a certain rate. However, if the counter does not perform to standards, about 1.2 million per second, there may be timing problems when programming these devices. The best thing to do is to perform the procedure on a different machine.

Please be noted our entire Cypress CPLD product are Obsolete and not recommended for new design and development. For more information on CPLD product, please visit our webpage: http://www.cypress.com/go/cpld

Boundary Scan on Flash370 and Flash370i CPLDs

Sun, 01 Jan 2012 16:38:03 -0600

Unfortunately, there is no way to perform a boundary scan on these devices. Cypress started to incorporate this feature on the Ultra37000 family of devices.

Transparent Latches in Ultra 37000 CPLDs

Sun, 01 Jan 2012 16:30:57 -0600

Unfortunately, the CPLD's registers are unable to implement a true transparent latch. However, the same function is usually achieved by implementing a negative-edge latch.

Please be noted our entire Cypress CPLD product are Obsolete and not recommended for new design and development. For more information on CPLD product, please visit our webpage: http://www.cypress.com/go/cpld.

Security Bit in the Ultra 37000

Sun, 01 Jan 2012 16:17:56 -0600

The security bit is a programmable field in the Ultra 37000 family of devices that prevents certain operations from occuring to the device once programmed. When such a bit is set, there is no way to recover the design from a programmed device and all operations on the device are prohibited, save erasing the device and reprogramming.

Within the device itself, a '0' within the fuse map of the device indicates a "secure" device. However, the JEDEC standard states that a '1' indicates security. As a result, the ISR software flips this bit when programming the device. As a default, the designs generated from Warp are unsecure.

Please be noted our entire Cypress CPLD product are Obsolete and not recommended for new design and development. For more information on CPLD product, please visit our webpage: http://www.cypress.com/go/cpld

Do MAX340 EPLDs Have Internal Oscillators?

Sun, 01 Jan 2012 15:59:42 -0600

Unfortunately, the MAX340 series of devices do not have internal oscillators. This feature can be found on the Cypress Delta39K family of CPLDs.

Please be noted our entire Cypress CPLD product are Obsolete and not recommended for new design and development. For more information on CPLD product, please visit our webpage: http://www.cypress.com/go/cpld

In Aldec-HDL is there any way to name remerged signals other than VBUS#

Sun, 01 Jan 2012 15:24:36 -0600

Unfortunately, the "VBUS" designation is default. There is no way to rename these signals.

However, signal buses naturally contain the group signal name as the merged signal name. For instance, a signal bus defined in HDL code as std_logic_vector will automatically be collapsable to view all signals as a bus (hex or decimal output).

Please be noted our entire Cypress CPLD product are Obsolete and not recommended for new design and development. For more information on CPLD product, please visit our webpage: http://www.cypress.com/go/cpld

Creating Bi-Directional Signals in Warp

Sun, 01 Jan 2012 15:19:01 -0600

The following VHDL code provides an example on how to create and use a bi-directional signal in Warp.

library IEEE;
use ieee.std_logic_1164.all;

ENTITY tristate IS
PORT (clk : in std_logic; -- clk input
a : in std_logic; -- input to drive b
out_enable : in std_logic; -- input to set state of b (input or output)
b : inout std_logic; -- bidirectional
c : out std_logic); -- c always receives b
END tristate;

ARCHITECTURE behav OF tristate IS
signal tempx : std_logic;

BEGIN

-- First, note that 'Z' can NOT be assigned to an output inside of a clocked process.
-- when targeting Cypress PLD's that do not have registered OE's (370, 370i, 37k)
-- So, we assign the 'Z' to the output asynchronously

b <= tempx when out_enable = '1' else 'Z';

-- assign b to c
c <= b;

outputs: process (clk)
begin
if (clk'event and clk ='1') then
tempx <= a;
end if;
end process;

END behav;
--Placing the oe control inside of the process makes the output enable
--dependant on a clock signal. The error generated by Warp is:
--Error 461 "Output-enable not supported beneath a WAIT"

This code shows that the output of the signal is set to high Z when not in use.

For simulation, the only thing to consider when simulating a bi-directional signal is that the strength of the stimulator for that particular signal must be set to drive and NOT override. Setting the stimulator to override will cause the waveform to simulate improperly.

Please be noted our entire Cypress CPLD and Warp product are Obsolete and not recommended for new design and development. For more information on CPLD product, please visit our webpage: http://www.cypress.com/go/cpld

Is there an application to convert a .stp or .hex file into a C code array?

Sun, 01 Jan 2012 15:01:20 -0600

Unfortunately, there is no application that is capable of doing this.

Please be noted our entire Cypress CPLD product are Obsolete and not recommended for new design and development. For more information on CPLD product, please visit our webpage: http://www.cypress.com/go/cpld

Registering Warp

Sun, 01 Jan 2012 14:57:31 -0600

Unfortunately, registering Warp online is not possible as that area of the website has been removed. Please contact our distributor, Future Electronics for all queries on buying or registering Warp.

Please be noted our entire Cypress CPLD and Warp product are Obsolete and not recommended for new design and development. For more information on CPLD product, please visit our webpage: http://www.cypress.com/go/cpld

Why does the ISR software not show a particular revision of Delta 39K devices?

Sun, 01 Jan 2012 14:42:52 -0600

This was a bug in previous versions of ISR, and has been fixed. The workaround for this can be achieved through the following procedure:

1. Exit from ISR if it is open.

2. Go to the "My Computer" icon and select "Search..." or "Find...". The command name varies in the menu based on the OS you are running.

3. Search for the file cydev.bpf.

4. Delete the files found.

5. Re-run the ISR program.

Please be noted our entire Cypress CPLD product are Obsolete and not recommended for new design and development. For more information on CPLD product, please visit our webpage: http://www.cypress.com/go/cpld

BSDL model of CY37032P44 device

Sun, 01 Jan 2012 13:26:39 -0600

BSDL model of CY37032P44 device is attached 'BSDL 32P44A.txt' in txt format.

Avoiding overflow of RX FIFO in the CY7C924ADX and CY7C9689A.

Wed, 07 Dec 2011 03:13:52 -0600

There are only two ways to prevent receiver FIFO overflow problems:

1. Ensure that the read clock for the receive FIFO is always faster than the received character rate
2. Discard sufficient characters so that the effective character rate is less than the FIFO read clock rate. (Use the discard policy configuration).

Useful Link:
200-MBaud HOTLink Transceiver

Characteristics and considerations for HOTLink jitter

Wed, 07 Dec 2011 01:15:43 -0600

The phase-locked loops (PLLs) in the HOTLink Transmitter and Receiver act like low-pass filters to jitter that is embedded in the data or clock signal source. For the transmitter, the signal source is the CKW input. Any jitter that appears at CKW is passed unattenuated if it has frequency components below the natural frequency of the PLL filter (approximately 500 kHz). Spectral components above the natural frequency are attenuated at about 6 dB/octave. Frequency components that fall very near the natural frequency of the filter are slightly amplified (approximately 0.5 dB). These are the normal characteristics of a Type-2, second-order PLL filter. When the transmitter is fed by a low jitter clock source, typical output jitter will be less than 20 ps RMS and 200 ps peak-to-peak. It is possible to measure significantly more jitter than that which is actually present if the complete system is not well understood. A few hundred millivolts of Vcc noise, while insignificant to the logic of a normal system board, will add imaginary jitter to the measured output. This imaginary jitter appears because a single ended oscilloscope sees the waveform as if it were measured against a fixed threshold, while the differential serial interface sees Vcc noise as a common mode signal to be ignored (e.g. 100 mV of Vcc noise could create 100-200 ps of imaginary jitter). Likewise, the normal method of measuring peak-to-peak jitter, an infinite persistence scope trace, will show larger jitter than that contributed by the HOTLink Transmitter. Low frequency jitter (wander) in the oscillator, scope trigger, temperature, and voltage related delay variations will all contribute to the width of the stored scope trace. Delay variations include TTL threshold variations that cause apparent delay variation (e.g. 100 mV of TTL threshold change can cause 100-200 ps of apparent jitter).

The signal source for the receiver is the serial data stream and, like the transmitter, it passes the spectral components of received jitter that fall below the natural frequency of its filter (approximately 300 kHz to 1000 kHz depending on actual data transition density being received). Frequency components above the natural frequency are attenuated and there is minor jitter peaking at about the natural frequency of the PLL. Since the characteristics of the input jitter determine the jitter content on the receiver CKR output (the only place to directly measure Rx-PLL jitter) it is somewhat difficult to predict the output jitter. Maximum CKR output jitter is less than 200 ps (peak-to-peak) when the receiver is tracking normal data (BIST data is typical) that exhibits maximum tolerable peak-to-peak jitter. Jitter from normal data is wide-bandwidth, has significant high-frequency content, and can have peak-to-peak amplitude of up to about 90% of a bit time. If the serial data contains a significant low frequency jitter component (typical in crystal oscillators and some pulse generators) the output jitter measured on the CKR pin could be much higher. Jitter measurements at the receiver output can be more misleading than those associated with the transmitter serial outputs, since all measurements are made on TTL outputs. The jitter characteristics mentioned here affect system performance in the following ways. Any low-frequency jitter (below the bandwidth of either transmitter or receiver PLL) is treated as wander. For purposes of the PLLs, wander (usually caused by low-frequency power supply variations or temperature fluctuations within the timing ICs) does not reduce the system timing margins and does not contribute to bit-error-rate. Wander can affect system timing at interfaces where the transmitter clock source is used to clock information received from a receiver tracking data from another clock source. The variation in clock frequencies may violate set-up and hold times, the exact problems usually solved by FIFO memories in typical communication systems. High-frequency jitter (at or above the natural frequency of the PLL filters) may contribute to BER. High-frequency jitter can be caused by the clock source, media transfer characteristics, or external noise. The recovered internal bit-rate clock does not track high-frequency jitter above the PLL natural frequency. High-frequency jitter, therefore, may cause a bit edge to move into the receiver sampling window causing the bit to be erroneously sampled (a bit error).

A suitable clock source should be selected with the above effects in mind. The only clock source guaranteed to offer the required stability and high-frequency specifications is a crystal oscillator. High-frequency jitter is minimal, and low-frequency wander is usually small and very low frequency. Frequency accuracy is easily guaranteed by mechanical means, and high accuracy devices are relatively low cost. Free-running resistor-capacitor (RC) oscillators, logic gate ring oscillators, or inductor-capacitor (LC) oscillators include too much high-frequency jitter, experience wide frequency variation as a function of process and environmental conditions and thus are unsuitable for this application. See the "HOTLink Jitter Characteristics" application note for more information.

Useful Link:
HOTLink Transmitter/Receiver

HOTLink Jitter Characteristics-AN1161

Data stream is always valid when RVS is LOW

Wed, 07 Dec 2011 01:08:07 -0600

NO. The detection of RVS = HIGH is a sufficient condition to declare that the received character is INVALID. It indicates that the presently received character did not follow one or more of the encoding rules for an 8B/10B coded data stream. However, the detection of RVS = LOW is NOT a sufficient condition to declare that the received character is VALID. It still requires validation against the data packet format used to ensure that the data is OK. If for example, one bit of the character transmitted is corrupted, but it turns out that the corrupted data falls into one of the valid data characters in the encoding table, the receiver will interpret this as normal data instead of asserting RVS = HIGH to indicate error.

Useful Link:
HOTLink Transmitter/Receiver

AN1161 - HOTLink® Jitter Characteristics

Wed, 09 Nov 2011 04:39:36 -0600

This application note describes the basics of jitter in transmission systems and, using HOTLink™ as the example, shows how it can be analyzed and measured. Specific characterization data is presented to allow system integrators to understand the parameters needed to improve the reliability of their systems.

AN1184 - Frequently Asked Questions about HOTLink®

Wed, 02 Nov 2011 02:38:33 -0600

How far can HOTLink communicate over various media?

HOTLink has no intrinsic distance limit. The two issues that determine the distances over which data can be sent using HOTLink are: (1) the choice of interconnect media (plastic or glass fiber-optic cable, coaxial cable, twisted-pair cable, etc.); and (2) the jitter that accumulates or is injected while the data is in transit over the selected media.

AN1057 - TAXITM to Cypress CY7C9689A HOTLink® Transceiver Conversion Series: 1. System Parallel Interface

Wed, 02 Nov 2011 02:28:34 -0600

The Cypress CY7C9689A TAXI-compatible HOTLink® Transceiver facilitates point-to-point data communication over high-speed serial links. Systems built with the CY7C9689A are directly compatible with legacy systems made using AMD TAXI chip devices. The CY7C9689A HOTLink Transceiver is functionally equivalent to an AMD AM7968 TAXI transmitter and AM7969 receiver pair, with numerous technology enhancements and extensions.

AN1032 - Using Decoupling Capacitors

Fri, 21 Oct 2011 05:02:41 -0600

Network analysis is used to prove that the conventional recommendation of using widely spaced values can, in many circumstances, cause less than ideal operation. Simpler, more reliable designs will often result from following the design guidelines of this note.

AN1162 - HOTLink® Design Considerations

Thu, 20 Oct 2011 02:01:29 -0600

The HOTLink™ family of data communications products provides a simple and low-cost solution to high-speed data transmission. While these products are easy to use, the methods used to connect them to high-speed serial interfaces are often not intuitive. This document provides a basic level of explanation of the parallel and serial interface characteristics, and provides some cookbook solutions for interfacing them to different types of parts and media.

AN1055 - Termination and Biasing of HOTLink IITM High-Speed Serial I/O

Wed, 19 Oct 2011 07:28:55 -0600

This application note is one of a series of design considerations for the use of the HOTLinkII device. Its purpose is to aid in the design of circuits used to connect the serial high-speed inputs and outputs of the CYP15G0401DX Quad HOTLinkII. It discusses high-speed circuit termination techniques and the required DC-biasing for the serial drivers and receivers used in the HOTLinkII device.

AN35159 - TAXI™ to Cypress CY7C9689 HOTLink® Transceiver Conversion Series: 2 Serial Interface

Wed, 12 Oct 2011 04:09:55 -0600

The Cypress CY7C9689 HOTLink(R) Transceiver integrates all the functions necessary to create TAXI(TM)-compatible bidirectional data communication links. Systems built with the CY7C9689 are directly compatible with legacy systems made using AMD(TM) TAXIchip(TM) devices. The CY7C9689 HOTLink Transceiver is functionally equivalent to an AMD AM7968 TAXI tranmitter and AM7969 receiver pair, with numerous technology enhancements and extensions.

AN1130 - Interfacing the CY7B923 and CY7B933 (HOTLink®) to Clocked FIFOs

Tue, 11 Oct 2011 08:29:20 -0600

This application note considers the interface issues between the Cypress CY7B923/933(HOTLink)transmitter/receiver and Cypress Clocked FIFOs.This note is divided into two sections:HOTLink Transmitter-Clocked FIFO interfaces, and HOTLink Receiver-Clocked FIFO interfaces.The transmitter interface section provides a simple design example that uses a state machine to control the HOTLink-FIFO interface.A state transition diagram for the controller is provided.Critical path timing analysis is then discussed for this design example.The derived critical path equations and their critical datasheet parameters are provided and explained.A timing diagram is shown to help illustrate these critical timing relationships.

The HOTLink Receiver-FIFO interface section also includes a simple design example.A simple state machine controls this interface.The state machine addresses design issues such as reframing the serial data,BIST(Built-In Self-Test), and programming clocked FIFOs.These issues are discussed in detail.A state transition diagram is included.Critical path timing equations are derived and the advantages of pipelining the interface are discussed.Timing waveforms are shown to help illustrate the critical timing relationships.

AN1089 - Parallel Cyclic Redundancy Check (CRC) for HOTLink®

Tue, 11 Oct 2011 08:14:39 -0600

This note discusses using CRC codes to insure data integrity over high-speed serial links, such as Fibre Channel, ESCON and other standards supported by Cypress's CY7B923 and CY7B933 HOTLink devices.It also shows why parity is not useful and then describes the most common CRC codes(CRC-16 and CRC-32) used in high-speed communications systems.

AN1077 - Replacing Wire with Inexpensive Plastic Fiber Solutions

Tue, 11 Oct 2011 07:05:52 -0600

This application note will show how to make a data link capable of sustained operation at 15.5 mybtes/sec over 50 meters using a combination of HOTLink transmitter/receiver parts with H-P optical devices and inexpensive plastic optical fiber. Full schematics part list and operational information are included.

AN1125 - Interfacing the CYS25G0101DX to Differential LVPECL

Tue, 11 Oct 2011 06:18:56 -0600

This application note demonstrates how to connect the single-ended interface of CY25G0101DX to the differential LVPECL device. This application note also provides simple calculation formulas to help users to calculate the values of the termination circuitry.

AN1038 - Upgrade Your TAXI–275 with HOTLink®

Tue, 11 Oct 2011 06:14:27 -0600

This application note will explain how to upgrade TAXI-275 (AM79168/AM79169) devices with the HOTLink (CY7B923/CY7B933) devices from Cypress Semiconductor. It will aid in the migration of TAXI-275 designs to the HOTLink architecture. This note begins with an introduction to HOTLink and then gives advantages of HOTLink and replacement suggestions for the TAXI-275 devices.

AN17004 - Decoupling Guidelines for the CYS25G0101DX OC-48 SONET Transceiver

Tue, 04 Oct 2011 04:20:44 -0600

This application note gives some decoupling guidelines, loop-filter requirements, and CM_SER pin requirements for the CYS25G0101DX OC-48 SONET Transceiver.

AN1047 - Understanding Bit-Error-Rate with HOTLink®

Thu, 15 Sep 2011 07:49:04 -0600

This application note explains the concept of an error rate for serial interfaces. Causes of errors in both optical and copper based interfaces are explained. BER floor plots of data rate vs. distance are included for a copper media type.

Application note : Driving Copper Cables with HOTLink™

Thu, 15 Sep 2011 05:42:39 -0600

The application note is attached below.

Moisture Sensitivity Level (MSL) of Cypress Parts

Thu, 08 Sep 2011 21:22:46 -0600

If you know the Cypress part number:

1. Go to www.cypress.com. On the top right, you will see a “Keyword / Part Number” search box (adjacent to “Contact Us.”)

2. Select the “Part Number” tab above this text box.

3. Type the exact part number, for example CY8C29466-12PVXE.

4. The part number will be listed in the search results page.

5. Click on the part number link (1st column starting from the left). This will open a new web page.

Moisture Sensitivity Level (MSL) can be found by clicking the “Quality & Pb-free Data” link on the top, or by just scrolling down to the Quality & Pb-free Data” section about half way down the page.

All other Quality information for this part number (e.g., RoHS compliance, Lead/Ball Finish, Qualification Reports, IPC reports) can also be found on this web page.

In case of any questions, or if the information is not available for a particular part number, please create a support case at www.cypress.com/support

If you do not know the Cypress part number:

1. Go to www.cypress.com. Browse the different products (“Products” tab on the top navigation menu) by family.

2. Once you choose the relevant product family (e.g., “Clocks and Buffers->Clock Distribution,” “Memory->FIFOs”), scroll down the particular page to get to the “Parametric Product Selector.”

3. Use this tool to find the part number by function/feature, and click on the part number you are interested in. This will lead you directly to step # 5 above.

SONET/SDH weiter ausgereizt (German)

Mon, 08 Aug 2011 05:59:06 -0600

Elektronik Praxis (Germany)

elektronikpraxis.de

For more information on our SONET and SDH PHY products, visit: cypress.com

Interfacing the SO pin to CY7B933

Fri, 01 Jul 2011 08:40:49 -0600

Yes, the SO signal has a sensory circuit that continuously reflects what it sees. In other words, after the interfaced device comes out of configuration (and the pull-up is removed), the sensory circuit connected to SO will change modes "on the fly". Consequently, SO will now assume the same logical level as SI, and INB will become a single-ended PECL serial data input.

Are the FIFO's accessible (for either reads or writes) when the part enters BIST mode (CY7C924ADX or CY7C9689A)

Fri, 01 Jul 2011 08:37:56 -0600

Receive FIFO: (When RXBISTEN* is enabled and RXFIFO is enabled) All writes to the RXFIFO are SUSPENDED. Any data present in the RXFIFO will also remain in the FIFO and cannot be read until BIST operation is complete. RXFULL* flag will be used to present BIST progress until BIST is disabled. The RXFIFO will be bypassed, but the data present in the FIFO will remain valid. RXFULL* is used to signify the beginning of each BIST loop.

Transmit FIFO: (When TXBISTEN* is enabled and TXFIFO is enabled) All reads from TXFIFO are SUSPENDED and BIST generator is enabled. The TXFIFO remains available for loading of data. It may be written up to its normal maximum limit while BIST operation takes place. TXEMPTY* flag will be used to present BIST loop status until BIST is disabled. On the TX side, it is NOT bypassed. You can still load data to the TXFIFO while BIST is running.

This behavior is documented in more detail starting on pg. 39 of the datasheet.

Useful Link:
200-MBaud HOTLink Transceiver (Attached Below 38-02008_0D_V)

TAXI-compatible HOTLink Transceiver (Attached Below 38-02020_0C_V)

MTBF or FIT of the CY7B923/CY7B933

Fri, 01 Jul 2011 08:29:01 -0600

MTBF = Mean time between failures
FIT = Failure in time (number of times an error occurs in one million hours).
MTBF = 1 / FIT

FIT for the CY7B923 is 100FIT = 100 x 10E-9/hour.
So the MTBF = 1/FIT = 1 / 100 x 10E-9 (hours) / 24 (hours/day) / 365 (days/year) = 1141.553 years.
FIT for the Cy7B933 is 100FIT = 30x 10E-9/hour.
So the MTBF = 1/FIT = 1 / 30x 10E-9 (hours) / 24 (hours/day) / 365 (days/year) = 3805.175 years.

Is there a drop in replacement for the Cy7B923/933 LMB military package

Fri, 01 Jul 2011 08:18:09 -0600

Although the -LMB package is leadless chip carrier, the contact points for the package are spaced in such a way that the -JC or -JI packages can use the same PCB layout, and thus become drop-in replacements for the -LMB packages.

Please be noted the Temperature grades are different.

Configure the HOTLink 1 for 3.3V I/O?

Fri, 01 Jul 2011 08:12:14 -0600

Cypress does provide a family of PHY's (HOTLink II) that operate with 3.3V I/O's, however the HOTLink 1 family are all 5V parts and cannot be operated at 3.3V. For more information on using the HOTLink II family of parts in your application, please visit our website.

Useful Link:
Datasheet CYP15G0101DXB

SMPTE standards supported by HOTLink family

Fri, 01 Jul 2011 08:07:09 -0600

Within the HOTLink1 family of parts there was a SMPTE 259M video chipset. The CY7B9234/9334 (Transmitter/Receiver) and the CY7C9235/9335 (Srambler/Descrambler) was a SMPTE 259M solution, currently they are Obsolete. These parts supported the following Levels:
1. SMPTE 259M Level C (270 Mbps, 525/625component)
2. SMPTE 259M Level D (360 Mbps, 525/625component)

In addition, a cable driver and equalizer will need to be used. Information on how to use the HOTLink 1 parts in a SMPTE-259M application can be found in two application notes (links are attached below). Adaptive Equalizers and Cable Drivers can be purchased from National Semiconductor. The parts we recommend are:
CLC006 Serial Digital Cable Driver with Adjustable Outputs
CLC007 Serial Digital Cable Driver with Dual Complementary Outputs
CLC014 Adaptive Cable Equalizer for High-Speed Data Recovery

Neither the HOTLink product family nor any other Cypress products support the SMPTE 310M standard for the following reasons:

- SMPTE-310M uses bi-phase mark encoding, HOTLink uses the 8B/10B encoding scheme,
- SMPTE-310M requires a synchronous serial interface to carry MPEG-2 transport bit streams at rates of up to 40Mb/s, HOTLinks lowest serial rate is 50Mb/s therefore is not compliant.

For more detailed information please see the SMPTE-310M spec and compare it to HOTLink specifications.

Useful Link:
SMPTE HOTLink Transmitter/Receiver (http://www.cypress.com/?rID=14216)

SMPTE 259M/DVB-ASI Scrambler/Controller (http://www.cypress.com/?rID=14213)

SMPTE 259M/DVB-ASI Descrambler/Framer-Controller (http://www.cypress.com/?rID=14214)

Implement a SMPTE 259M Serial Digital Interface Using SMPTE HOTLink and CY7C9235/9335 (www.cypress.com/cfuploads/support/app_notes/smpteap.pdf)

CY7C9267 SMPTE 259M Evaluation Boards User's Guide (www.cypress.com/cfuploads/support/app_notes/smpte_eval.pdf)

Should I use HOTLink CY7C924ADX or CY7C9689A

Fri, 01 Jul 2011 07:21:14 -0600

For new design, we would recommend the CY7C924ADX. CY7C924ADX is superior to the CY7C9689A. While CY7C9689A uses 4B/5B encoding, CY7C924ADX uses 8B/10B encoding and provides superior functionality. The 8B/10B encoding has been adopted widely in the industry for applications such as Fiber Channel, DVB-ASI, Gigabit Ethernet, etc...
CY7C9689A is designed as a replacement for AMD TAXIchip. We recommend to use this chip only for such an application.

Note: TAXIchip and TAXI are registered trademarks of Advanced Micro Devices, Inc.

Useful Link:
TAXI-compatible HOTLink Transceiver (http://www.cypress.com/?rID=13677)

Configuration of the Status In (SI) and Status Out (SO) Pins

Fri, 01 Jul 2011 06:51:44 -0600

The Status Out pin controls the function of the INB/INB+ and the SI/INB- inputs. When SO is tied directly to Vcc, these two pins form INB+ and INB-, a differential line-receiver serial-data input pair. When SO is tied to a normal TTL-load without any pull-ups, then the first pin becomes a single-ended serial line receiver while the second pin becomes a single-ended Status Input pin.

This is done with a sensor circuit connected to the SO pin. It senses how this output is externally connected and changes the mode of INB/INB+ and SI/INB- as a result. This sensory circuit is always active and so it is possible to change the status of SO during operation.

If, for example, there is a pull-up during the start-up or configuration of the system, but that pull-up disappears when the system is loaded, then the state of the two pins INB/INB+ and SI/INB- will change from being a differential pair to two single-ended signals.

Can the FIFO be bypassed in CY7C924ADX when using the byte-packer

Fri, 01 Jul 2011 06:44:17 -0600

The short answer is NO. The Encoded 10-bit character stream is achieved by setting ENCBYP* = HIGH and BYTE8/10* = LOW. The byte-packer is a logical construct, used to control the efficient segmentation of 10-bit source characters into 8-bit characters. This conversion allows these characters to be transported using 8B/10B encoding with the same encoding overhead (20%) as when sending 8-bit characters. Because the serializer continues to operate using 10-bit transmission characters, this encoding mode can only operate with the transmit FIFO enabled.
For more detailed information about byte-packed mode, please refer to CY7C924ADX datasheet (link attached), specifically Figure 4.

Useful Link:
200-MBaud HOTLink Transceiver (Attached Below 38-02008_0D_V)

Unused serial inputs and outputs on HOTLink CY7B923/CY7B933

Tue, 28 Jun 2011 07:10:12 -0600

Unused serial outputs on CY7B923 can be either tied to Vcc or left floating to reduce power. One input of unused serial inputs on CY7B933 should be terminated to Vcc through a 1K-5Kohms resistor to assure that no data transitions are accidentally created.

For more information, please refer to "Frequently Asked Question About HOTLink" application note on our website.

Useful Link:
HOTLink Transmitter/Receiver (Attached Above 38-02017_0D_V)

Frequently Asked Questions about HOTLink (www.cypress.com/cfuploads/support/app_notes/faq.pdf)

CY9266 Evaluation Board documentation

Mon, 27 Jun 2011 21:51:39 -0600

The CY9266 evaluation board was provided to allow the user to fully characterize the CY7B923/CY7B933 transmitter and receiver. It was available in four 'flavors':

CY9266-F = optical fiber
CY9266-P = plastic optical fiber
CY9266-T = shielded twisted pair/twinax
CY9266-C = coaxial cable

The CY9266 HOTLink Evaluation Board User's Guide is the complete guide to setting up and testing the various evaluation boards. It also includes schematics and layout information for reference.

Since the Evaluation Board is Obsolete. If customer wants to design the evaluation board, they can use the gerber files attached with this KB Article for CY9266-F & CY9266-C. Gerber files for CY9266-T & CY9266-F are not available. However, if you check the schematic for all the evaluation board, only difference in all the evaluation board is the connector used for various medium.

Meaning in datasheet, when it says that you can write to the FIFO from DC to 50 MHz

Fri, 24 Jun 2011 09:08:15 -0600

This basically means that you can write to or read from the FIFO's at any speed up to 50 MHz (even though the maximum REFCLK frequency is 40 MHz). This adds flexibility for the designer.

Aside: Note however, that if you stop the TX FIFO clock, the "last" character written may remain in the FIFO input register and not be transferred to the FIFO core.

Useful Link:
TAXI-compatible HOTLink Transceiver (Attachment below 38-02020)

200-MBaud HOTLink Transceiver (Attachment below 38-02008)

Reducing Power Dissipation: Unused serial outputs on CY7C9689

Fri, 24 Jun 2011 07:21:58 -0600

CY7C9689 device has two differential serial output drivers that drive the same serialized data stream out on pins OUTA± and OUTB±. Having a redundant output is particularly useful in systems where the serial data stream needs to be transmitted to two different destinations.

In systems where the serial data stream is transmitted to only one destination the other serial stream is truly redundant. In such cases, to reduce power dissipation, it is recommended to leave the reduntant output pins OUTx± unconnected and the associated CURSETx input tied to V_DD. For example, if the data stream on pins OUTB± is redundant then OUTB± pins should be left unconnected and CURSETB should be tied to V_DD.

Transformers recommendation for HOTLink CY7B9234 and CY7B9334

Fri, 24 Jun 2011 07:12:59 -0600

The transformers that we recommend to use for our HOTLink CY7B9234 and CY7B9334 devices are as following:

Commercial Temp Transformer from Pulse Engineering. http://www.pulseeng.com

PE-65508 Dual transformer (Up to 531 Mbaud / 266 Mhz)

T3001 Single transformer (Up to 700 Mbaud / 350 Mhz)

Industrial Temp Transformer from Pulse Specialty. http://www.pulsespecialty.com

T-330SCT Dual Transformer (Up to 265 Mbaud / 132 Mhz)

T-1062SCT Dual Transformer (Up to 1065 Mbaud / 531 Mhz)

Latency through a CY7C924ADX/CY7C9689A Transmitter and Receiver.

Fri, 24 Jun 2011 06:58:00 -0600

While this response focusses on the CY7C924ADX, the same numbers apply to the CY7C9689 latency.

When the internal FIFOs are disabled (FIFOBYP is LOW), the input data is stored in the transmitter input register on the rising edge of REFCLK, making this time-zero. When configured for 8-bit mode, approximately 31 bit-times (i.e., 31 times the period of REFCLK÷10) following this, the first encoded bit of that character will emerge from the OUTA± and OUTB± pins.

After the transit time of the serial link (which can be significant), that bit will appear at the receiver. Transit times for typical serial links include the propagation delay of the optical modules (typically 5-10 ns for the pair), if any, and the propagation rate in the link media (i.e., approximately 1 ns/ft in copper, and 2 ns/ft in multi-mode optical cable).

Due to clocking variations in the high-speed PLL circuitry and framer logic, a best case minimum latency bound and worst case maximum latency bound is possible within the Receiver. For the best case scenario, approximately 35 bit-times after the first data bit is presented at the input of the receiver plus a minimum delay of 2 ns through the parallel output drivers, data appears at the RXDATA or RXCMD outputs relative to RXCLK. For the worst case scenario, approximately 46 bit-times after the first data bit is received at the input of the receiver plus a maximum delay of 15 ns through the output driver circuitry, data appears at the RXDATA or RXCMD outputs relative to RXCLK.

In 8-bit mode, the total latency of a CY7C924ADX Tx/Rx pair is approximately the link delay plus 66 bit-times and 2 ns best case, or the link delay plus 77 bit-times and 15 ns worst case. In 10-bit mode the latency through the transmitter is proximately 34 bit-times (i.e., 34 times the period of REFCLK÷12).

In the Receiver a similar best case minimum latency bound and worst case maximum latency bound is possible. For the best case scenario, approximately 41 bit-times after the first data bit is received at the input of the receiver plus a minimum delay of 2 ns through the output driver circuitry, data appears at the RXDATA or RXCMD outputs relative to RXCLK. For the worst case scenario, approximately 54 bit-times after the first data bit is received at the input of the receiver plus a maximum delay of 15 ns through the output driver circuitry, data appears at the RXDATA or RXCMD outputs relative to RXCLK.

Correspondingly in 10-bit mode, the total latency of a CY7C924ADX Tx/Rx pair is approximately the link delay plus 75 bit-times plus 2 ns best case, or the link delay plus 88 bit-times plus 15 ns worst case.

When the FIFOs are enabled (FIFOBYP is HIGH) additional FIFO latency is encountered in the Transmit and Receive data paths. Both transmit and receive FIFOs achieve minimal latency when the TXCLK and RXCLK rates are slower than the REFCLK rate; otherwise, the time it takes to transmit a new character is lengthened by the additional time needed to transmit the previously stored characters. In 8-bit mode, with an initial empty transmit and receive FIFO, the transmit FIFO adds 8 bit-times, plus 2 additional TXCLK cycles to the overall delay, while the receive FIFO adds 1 bit-time, plus 4 additional RXCLK cycles to the overall delay. In 10-bit mode, with an initial empty transmit and receive FIFO, the transmit FIFO adds 9 bit-times, plus 2 additional TXCLK cycles to the overall delay, while the receive FIFO adds 1 bit-time, plus 4 additional RXCLK cycles to the overall delay.

Useful Links:
TAXI- compatible HOTLink Transceiver Datasheet (CY7C9689A)

200 Mbps HOTLink Transceiver Datasheet (CY7C924ADX)

Rad hardness, Soft Error Rate (SER), Single Event Upset (SEU) rates for the CY7B923 and CY7B933.

Fri, 24 Jun 2011 06:36:10 -0600

Cypress doesn't have any measurement data on radhard-ness of the parts. However, there are many factors that suggest that they are robust:
1) These devices are used in the International Space Station (see http://www.electronicstalk.com/news/cyp/cyp328.html)
2) The majority of the circuitry in the parts is bipolar, which is inherently rad hard
3) Because all storage elements in the device are flip-flops, and they are clocked continuously, each storage element is completely refreshed millions of times per second. This is different than a memory array where data gets written once, and may never be refreshed until it is overwritten perhaps hours later (or milliseconds later in the case of dynamic memories).
4) The process geometry used was 0.8 micron, and each flip-flop has an area much greateer than that of conventional memory cells.
5) The circuits used in many of the paths in this device are balanced constant-current, with current levels well beyond what could be realized or compromised by the decay of a single atom (and subsequent release of a single alpha or beta particle).
6) These parts are built on a BiCMOS process, but the majority of the circuitry in the parts is bipolar, which is inherently rad hard.
7) Empirical testing in the lab showed the parts to succesfully transfer 6.5e14 bits without error.

CKR outputs are unusable when the serial inputs to the CY7B933 are left floating and a REFCLK of 40MHz is supplied.

Fri, 24 Jun 2011 06:19:13 -0600

The 933's inputs are very sensitive to any noise coupling (even down to a few mV). Normally, the CDR will try to track the incoming data stream. If the recovered clock is close enough (within +/-1000ppm), its within the limits and it will stick to the recovered clock. If not, then it shifts to track the REFCLK and then tries to track the data stream again. This process repeats until its stable. Now, at a lower frequency of 20MHz, the noise from the REFCLK line couples with the serial inputs (which are very sensitive) and the CKR can give a stable 20MHz output. At 40MHz, the sensitivity of the outputs decreases drastically (since the inputs have lower bandwidth at higher frequencies) and the noise coupling is not sufficient enough. Hence, the CDR keeps oscillating between the inputs and the REFCLK and does not stabilize. Hence, you have a highly unstable output on CKR.

SPDSEL and RANGESEL for 100MBaud (CY7C9689A, CY7C924ADX)

Wed, 22 Jun 2011 02:35:14 -0600

Typically serial links (including TAXI) always run at a single data rate frequency, which is derived from the REF clock. For example, if a 20MHz REF clock is used, the SPDSEL and RANGESEL can be configured to have a serial data rate of 50Mbaud, 100Mbaud, or 200Mbaud. When the link is idle (no real data is being sent), JK/LM idles will be sent by the transmitter according to the TAXI protocol to maintain the link. Thus the serial data rate will always be constant.

Using a spread spectrum clock to clock the link is not recommended because you are adding jitter to the signal, and it makes it more difficult for the receiver PLL to lock.

If you are planning on running at 100 Mbaud I we recommend using SPDSEL =LOW and RANGESEL = LOW, which will multiply the REF clock by 5 to get the serial data rate clock. We would also recommend using the CY7C9689A device in synchronous mode (without the FIFOs), since these synchronous designs tend to be easier to design and debug.

AN1027 - Using High-Speed Serial Links to Supplement Parallel Data Buses

Mon, 20 Jun 2011 05:16:38 -0600

AN1027 discusses using the high speed serial link as a solution to replace parallel data using HOTLink®.

HOTLink II Three Level Control Inputs

Mon, 13 Jun 2011 18:41:46 -0600

Controlling 3-Level select inputs (Example: SPDSEL) with an FPGA/CPLD output is not recommended, since the DC levels for the three level input HIGH and LOW have less noise margin than LVTTL DC levels. Moreover, controlling the FPGA/CPLD output in three-state mode to achieve the MID state for the 3-Level inputs is not a recommended practice. The noise immunity levels of three level inputs is less than the noise immunity levels of two level inputs. Using static signals ensures that the dc voltage level specification for the three level inputs are met.

For a given application, the 3-Level select control inputs are recommended to be static inputs. To achieve a HIGH state, we recommend to tie a strong pull-up (100 ohms) resistor to the 3-Level select pin. To achieve a LOW state, we recommend to tie a strong pull-down resistor (100 ohms) to the 3-Level select pin. To achieve a MID state, leave the pin floating. In the prototype design stage, customers might want to have the options for pull-up as well as pull-down resistor to provide more flexibility in their design.

Switching between Serial Differential Inputs

Mon, 13 Jun 2011 18:39:06 -0600

In the above scenario in which you are switching the HOTLink II serial differential inputs from Input 2 [IN2(+/-)]to Input 1 [IN1(+/-)], assuming that the data on both IN1(+/-) and IN2(+/-) are within the 1500 ppm frequency offset as described in the HOTLink II datasheet, the phase-locked loop (PLL) will acquire and lock to the new data stream within a few character times. The exact time required involves statistical probabilities related to phase, frequency, and jitter, and cannot be exactly predicted. If the PLL frequency has been moved to its offset limits, it may take more than 60-70 characters before the PLL locks to the good data. If the incoming datastream on the other input is within the ppm offset so that the PLL can track within its frequency offset limits, the PLL will reacquire lock in a few characters after a good data stream reappears.

The larger problem facing a system protocol that allows switching of serial data streams is character synchronization (byte-framing). After the data-stream has been switched, it must be reframed. This requires that a K28.5 (or two K28.5s within five characters if multi-byte framing is enabled) must be received. The time that elapses before this happens depends on the system protocol and the timing of the data input switch. Correct data may not come out of the HOTLink II Receiver for hundreds of character times due to a lack of framing, regardless of speed of phase/ data acquisition.

Essentially, you will be able to switch from IN2(+/-) to IN1(+/-) within anywhere from 10 character cycles to 70 character cycles as explained above. The essential criteria for the switching time to be within anywhere from 10 character cycles to 70 character cycles and not 376K UI is to ensure that the switching time between IN2(+/-) to IN1(+/-) is instantaineous with good data streams coming on both the inputs at the time of switching the serial differential inputs.If this criteria is not met then the switching time is going to be 376K UI. You will have to transmit framing characters at the beginning of the data stream on IN1 so that the receiver can frame to the proper character boundaries.

Considerations in Interfacing HOTLink II to Fiber Optic Module

Mon, 13 Jun 2011 18:28:30 -0600

The considerations for interfacing HOTLink II to a fiber optic module are ac coupling of the link, biasing of the optical module and termination of the transmission line [serial traces].

At the HOTLink II receiver, the serial input has weak internal biasing. Due to the weak internal biasing, if you AC couple the link between the serial driver [Optical module] and the HOTLink II, then you do not have to bias the HOTLink II at its serial differential inputs. This gives flexibility to the board designer as any serial driver can be interfaced to the HOTLink II receiver by AC coupling the link between the serial driver and the HOTLink II serial inputs at the serial driver and terminating with termination resistor between the serial traces equal to the differential impedance of the transmission line [serial traces].

You can interface an optical module to HOTLink II receiver, by AC coupling the link at the optical module, and terminate with a termination resistor between the serial traces equal to the differential impedance of the transmission line [serial traces] as close to HOTLink II serial differential inputs as possible. For example, if the differential impedance of the serial input traces on your board is 100 ohms, then you can terminate with 100 ohms resistor between the differential serial input traces close to the HOTLink II on your board. Please refer to the Optical Module data sheet for other special requirements in the interfacing.

At the HOTLink II transmitter, you can AC couple the serial link between the serial outputs and the optical module. Depending upon the optical module you are using, you might need to bias at the optical module with the biasing circuit so as to meet the input biasing requirements of the optical module as well as terminate the transmission line [serial traces] at the optical module. For example, if you have an LV-PECL optical module with no internal biasing and your serial output traces are 100 ohms differential traces, then you can bias the optical module inputs and terminate the transmission line [serial traces] with a resistor network close to the optical module comprising of 82 ohms resistor to Vcc and 130 ohms resistor to ground on each serial trace. This resistor network will bias to 2V to meet the LV-PECL signal biasing requirement and terminate each transmission line [Optical module serial input] with 50 ohms terminating impedance at the optical module.

SFP fiber optic modules are commonly used fiber optic transceivers. The MSA complient SFP fiber optic modules have internal biasing and internal termination at the transmitter. They may or may not be AC coupled. If the SFP optical module does not have internal AC coupling, you can interface HOTLink II serial outputs to the SFP fiber optic module by AC coupling the serial link between the HOTLink II and the SFP at the output of HOTLink II. At the HOTLink II receiver, the serial input has weak internal biasing, so you can AC couple the link between the SFP optical module and the HOTLink II at the SFP, and terminate with a termination resistor between the serial traces equal to the differential impedance of the transmission line [serial traces] as close to HOTLink II serial inputs as possible.

Please refer to the Optical Module data sheet for other special requirements in the interfacing.

Receive Status Bits in HOTLink II

Mon, 13 Jun 2011 18:26:44 -0600

At the HOTLink II receiver, when the 10B/8B Decoder is enabled (DECMODE not equal to LOW), each character presented at the Output Register includes three associated status bits RXST[2:0]. The purpose of the receive status bits is to identify:

1. If the contents of the data bus are valid.

2. The type of character present.

3. The state of receive BIST operations (regardless of the state of DECMODE)

These conditions normally overlap; e.g., a valid data character received with incorrect running disparity is not reported as a valid data character. It is instead reported as a Decoder violation of some specific type. This implies a hierarchy or priority level to the various status bit combinations. The priority levels determine the output of status bits when there are two conditions overlapping. In the case of overlapping conditions, the condition with the highest priority is on the output the receive status bits RXSTx[2:0]. For example, if there is an overlapping condition of loss of sync which is priority # 1 with any other condition, then the RXSTx[2:0] status pins will output status bits corresponding to loss of sync as it has the higher priority.

The priority levels of each status is listed in Table 20, when channel bonding enabled, and in Table 21, when channel bonding is disabled. Within these status codes, there are three modes of status reporting. The two data status reporting modes (Type A and Type B) are selectable through the RXMODE[0] input. These status types allow compatibility with legacy systems, while allowing full reporting in new systems. These status values are generated in part by the Receive Synchronization State Machine, and are listed in Table 20. The receive status, when the channels are operated independently with channel bonding disabled, is shown in Table 21. The receive status, when Receive BIST is enabled, is shown in Table 22.

State of the RXSC/D* signal while VLTN is asserted for the CY7C9689A

Mon, 13 Jun 2011 18:14:42 -0600

RXSC/D* will remain unchanged when VLTN is asserted.
In the pin description of VLTN on page 7 of the datasheet, it states that "When VLTN is asserted the values on the output DATA and COMMAND buses remain unchanged" and as RXSC/D* comes from the same output buffer as the DATA and COMMAND buses it behaves the same.

Useful Link:
TAXI-compatible HOTLink Transceiver (Attached Below 38-02020_0C_V)

Significance of HOTLink claim of requiring no external PLL components?

Mon, 13 Jun 2011 18:13:09 -0600

HOTLink Transmitter and Receiver have completely integrated PLL clock multiplier (CMU) and data separator functions (CDR). These functions are implemented with high-performance phase-locked loops (PLLs) that have been tuned for maximum performance and minimum system noise sensitivity. In competitive products that claim to offer similar functions, these PLL's are often implemented with external filter and frequency setting components with the goal of achieving maximum performance. These very same external components are the largest cause of end-user complaints and random system failures because they expose the most critical analog signals in the circuit to the external noises that abound in normal systems. External components require critical, costly and time consuming printed circuit board layout as well as high-speed analog and digital design techniques that are unfamiliar to many system integrators. HOTLink products are designed and built using fully differential analog and digital circuits to give the lowest possible output jitter and highest possible jitter tolerance. There are no external components to compromise system performance in unexpected and unpredictable ways.
For more information, refer to the HOTLink Transmitter Jitter section of the "HOTLink Jitter Characteristics" application note.

Useful Link:
HOTLink Transmitter/Receiver (Attached below 38-02017_0D_V)

HOTLink Jitter Characteristics -AN1161

Power consumption of the SMPTE 259M Scrambler/Controller and Descrambler/Framer-Controller

Mon, 13 Jun 2011 18:09:57 -0600

Typical Icc of CY7C9235 at 27 Mhz (Vcc = 5.0 V) is 160 mA

Typical power consumption of CY7C9235 at 27 Mhz (Vcc = 5.0 V) is 0.8 W.

Typical Icc of CY7C9335 at 27 Mhz (Vcc = 5.0 V) is 290 mA

Typical power consumption of CY7C9335 at 27 Mhz (Vcc = 5.0 V) is 1.45 W.

Useful Link:

SMPTE-259M/DVB-ASI Scrambler/Controller

SMPTE-259M/DVB-ASI Descrambler/Framer-Controller

Power (VDDA & VDD) and ground (VSSA & VSS) pins on the CY7C924ADX

Mon, 13 Jun 2011 18:05:22 -0600

All power pins should be short together and similarly all ground pins should be short together. Therefore all of the power pins should be connected to the same power plane and all grounds pins to the same ground plane as illustrated on page 57 of the datasheet. Thus there is no need to have separate planes for VDD and VDDA, and similarly for VSS and VSSA.

Useful Link:
200-MBaud HOTLink Transceiver (Attached below 38-02008_0D_V)

Configuration for connecting the HOTLink Transmitter/Receiver power and ground pins

Mon, 13 Jun 2011 18:03:25 -0600

All power pins are required to be shorted together, and all ground pins are required to be shorted together. While these enter the die on different pins, they are all shorted together ON THE DIE. If there is even a slight power offset between the quiet and noisy supplies, the bond wires will be turned into fuses.

Useful Link:
HOTLink Transmitter/Receiver (Attached below 38-02017_0D_V)

Character Rate vs Byte Rate

Mon, 13 Jun 2011 18:01:18 -0600

Characters are what the user is trying to send. There are data characters, command characters and transmission characters. The reason the term byte is not used is because different interfaces have different character sizes. For example, the CY7C924ADX (or CY7C9689A) can have 8 or 10 bit data characters, and 10 or 12-bit transmission characters (a transmission character is a character after the encoding overhead has been added).
There is a direct relationship between these. On the CY7B923/933, the character rate is always 1/10th the signaling rate; e.g. for a 270 Mbps signaling rate the character rate is 27 MHz. On the 924ADX/9689A this relationship depends on the SPDSEL and RANGESEL inputs (see Table 4 pg. 17 of 924ADX datasheet for example).

Useful Link:
HOTLink Transmitter/Receiver (Attached below 38_02017)

TAXI-compatible HOTLink Transceiver ( Attached below 38-02020_0C_V)

200-MBaud HOTLink Transceiver (Attached below 38-02008_0D_V)

Built-In Selt-Test (BIST) and why should I use it?

Mon, 13 Jun 2011 17:55:47 -0600

HOTLink Built-In Self-Test allows a clear and unambiguous check of the HOTLink Transmitter and Receiver, and the serial link connecting them. As part of an off-line diagnostic, this feature allows the user to ensure that the interconnect link is fully operational and that any other diagnostic failure indications are caused by system blocks above the physical layer.

BIST allows the HOTLink adapter card manufacturer to do a quick link-quality test (or node quality test with the use of the loop-back functionality of HOTLink) without the necessity of bringing up a fully functional system to do link testing. BIST is controlled by extra HOTLink data-enable inputs. Only a few connections and minimal external logic are necessary to add BIST to an otherwise complete system. (See the CY9266 Evaluation Board User's Guide). BIST status indications appear on the RP, RVS(Qj) and RDY* outputs which are easily monitored by logic internal or external to the data flow controller. In BIST mode, the HOTLink Transmitter generates a 29 - 1 (511 character) pseudo-random pattern using its Input register configured as a Linear Feedback Shift Register (LFSR). The HOTLink Receiver compares the serial BIST data stream with identical BIST patterns generated in its Output register. All of the logic in the transmitter (except the input pins) and all of the logic in the receiver (including the output pins and their attached loads) are checked by BIST. All of the serial link interconnect components are exercised with normal data patterns, which are checked character-by-character in real time and at full link operating speed.

Useful Link:
HOTLink Transmitter/Receiver (Attached below 38-02017_0D_V)

CY9266 HOTLink Evaluation Board User's Guide (Attached below)

Power supply decoupling required for HOTLink products

Fri, 10 Jun 2011 06:55:49 -0600

HOTLink requires no special considerations for power-supply bypassing beyond that normally associated with high-speed logic. This typically includes the use of a ground plane, a Vcc plane, and bypassing using multiple RF quality chip capacitors. Each of the ground pins of a HOTLink IC should connect directly to the ground plane using short (<6 mm) traces and vias. All of the Vcc pins should connect to a Vcc area under the HOTLink, which is then connect to the board Vcc through a single via. Connect one 10- to 22-nF capacitor (based on operating character clock rate) for each Vcc pin directly from the pin to GND. For more information see the "Using Decoupling Capacitors" application note.

Useful Link:
Using Decoupling Capacitors

Relationships between TXCLK, RXCLK and REFCLK for the CY7C924ADX in asynchronous mode

Fri, 10 Jun 2011 06:42:44 -0600

In asynchronous mode (i.e with the FIFO's enabled FIFOBYP* = HIGH):

REFCLK is the clock used:
1. by the transmit PLL, it is the character clock and is multiplied up to become the bit clock and,
2. by the receive PLL, to keep it in or around lock when there is no serial data stream.

TXCLK and RXCLK are the clocks associated with the t/x and r/x FIFO's respectively. They are the clocks that clock the data in to and out of the respective FIFO's. These FIFO clocks can run at any speed from DC to 50 MHz and do not need to be at the same frequency as REFCLK. What you do need to consider however is that:
1. you must not write to the t/x FIFO faster than the data can be transmitted serially (this will eventually lead to FIFO overflow), unless managed by an external switching element, and,
2. you must read from the receive FIFO faster than it will fill up so as to avoid overflow i.e. if it fills up faster than you read from it it will overflow.

You must also avoid underflow situations (where you are reading data from an empty FIFO on the r/x side) as this will lead to garbage data. On the t/x side if the FIFO is empty K28.5's will pad the serial stream and you can delete these or use them at the receive side depending on what you want to do using the receiver dicard policies (see datasheet for more details).

Useful Link:
200-MBaud HOTLink Transceiver (Attached Below 38-02008_0D_V)

Are the receiver discard policies affected when the FIFO's are bypassed in the CY7C924ADX?

Fri, 10 Jun 2011 06:28:42 -0600

When the FIFOs are bypassed (FIFOBYP* LOW), no characters are actually discarded, but the receiver discard policy can be used to control external filtering of the data. The RXEMPTY* FIFO flag is used to indicate if the character on the output bus is valid or not. In discard policy 0, the RXEMPTY* flag is always deasserted to indicate that valid data is always present. In discard policy 1, the RXEMPTY* flag indicates an empty condition for all but the last C5.0 character before any other character is presented. In discard policies 2 or 3, the RXEMPTY* flag indicates an empty condition for all C5.0 characters. When any other character is present, this flag indicates that valid or 'interesting' Data or Special Characters are present.

AN014 - Channel Bonding with HOTLink II Transceiver

Tue, 17 May 2011 09:26:58 -0600

The HOTLink II™ family of devices are point-to-point or point-to-multipoint communications building block that provide serialization, deserialization and framing functions. They can transport serial data at rates between 0.2 and1.5 Gigabits per second (Gbps) per channel and are compatible with communication standards such as Gigabit Ethernet, Fibre Channel, SMPTE-259M, SMPTE-292M, DVB-ASI and ESCON®.

Power Consumption of HOTLink II (TM) Family of Devices - AN027

Fri, 13 May 2011 00:00:00 -0600

This application note illustrates the power consumed by any device in the HOTLink II(TM) family for a given operating frequency and configuration. Apart from illustrating the power consumption for different devices, the application note also discusses the instructions for the Cypress HOTLink II(TM) Power Estimation Graphical User Interface (GUI). The GUI can be downloaded from http://www.cypress.com/?rID=14430 under Software & Drivers.

Configuring the HOTLink II(TM) CYP15G0403DXB - AN067

Thu, 12 May 2011 09:14:30 -0600

This application note focuses on the benefits of independent clocking of CYP(V)15G0403DXB and how each channel of the device can be configured independently to operate at a different protocol. It shows the configuration settings required for four different protocols: Fiber Channel, ESCON, Gigabit Ethernet and DVB-ASI.

Frequently Asked Questions About the CYP(V)15G0403DXB Device - AN060_B

Fri, 06 May 2011 00:00:00 -0600

The following are Frequently Asked Questions (FAQs) by customers who are evaluating CYP(V)15G0403DXB devices. The CYP(V)15G0403DXB is a member of Cypress's High-Speed Frequency Agile HOTLink II. product family. Within the device, all four channels can simultaneously operate at different data rates and transmit different types of data. The only difference between the CYP15G0403DXB and the CYV15G0403DXB devices is that the latter satisfies SMPTE 259M and SMPTE 292M pathological test requirements per SMPTE EG 34-1999.

CY7C924ADX-AC-Ibis

Tue, 22 Mar 2011 18:48:59 -0600

AN17006 - High Speed Serial Simulation with HOTLink II™

Tue, 22 Mar 2011 18:46:42 -0600

The HOTLink II™ family of devices are point-to-point or point-to-multipoint communication building blocks, providing encoding, serialization, deserialization, and decoding at high speed and are compatible with many communication standards. A HOTLink II device is a frequency agile transceiver with the ability of the serial links to transport data at a rate between 0.2 and 1.5 Gigabits per second (Gbps) per channel.

Part Naming conventions for HOTLink 2 parts

Sat, 26 Feb 2011 23:18:02 -0600

Attached is the nomenclature for HOTLink 2 parts.

HOTLink(R) CY7B923/CY7B933 to HOTLink II(TM) Migration - AN1160

Wed, 16 Feb 2011 00:00:00 -0600

This application note discusses how to migrate from HOTLink-based designs to HOTLink II-based designs. While most designs can be converted from HOTLink to HOTLink II, applications that use the device at signaling rates of less than 200 Mbaud cannot be migrated. The scope of this application note is limited to device configuration, although some information on device operation is covered as necessary. The Quad HOTLink II Transceiver (CYP15G0401DXB) is used to illustrate how to migrate your design and one of the channels is used to show how to interface the HOTLink device to the HOTLink II devices.

Crosstalk Analysis of the Quad Independent Channel HOTLink II(TM) Device - AN4047

Mon, 14 Feb 2011 00:00:00 -0600

The HOTLink II(TM) family of physical layer (PHY) devices is a point-to-point or point-to-multipoint communications building block that provides serialization, deserialization, optional 8B/10B encoding/decoding and framing functions. The quad independent channel device is a member of this frequency agile family that can support serial data rates between 195 and 1.5 Gbps per channel. Within this device, all four channels can simultaneously operate at different data rates and transmit different types of data. In order to provide this flexible feature, each channel has its own transmit and receive Phase-Locked Loops (PLLs).

What is the FIT (Failure in Time) rate, or MTBF (Mean Time Before Failures) of the CY7C9689A?

Thu, 03 Feb 2011 07:04:26 -0600

The Failure In Time (FIT) number for the CY7C9689A device is 34 which is mentioned in the Qualification report.

The Mean Time Before Failure (MTBF) number is calculated as follows:

MTBF = 1,000,000,000 X 1/FR
where FR = Failure Rate

29,411,764 hours =1,000,000,000 X 1/34

HOTLink DX PECL Output to LVTTL Input

Thu, 03 Feb 2011 06:59:49 -0600

An LVTTL input requires a larger voltage swing than what is provided by a single PECL output of the CY7C924ADX or CY7C9689A. To make the differential to single-ended transition, we typically use a transformer. By providing both outputs to the input of a transformer, we create a single output that has twice the swing of a single PECL output.

The CY7C924ADX PECL signals have a 600-1100mV swing with voltage levels between 3 and 4 volts. LVTTL inputs usually require V_IH = 2V and V_IL = 0.8V. This translates to a swing of at least 1.2V centered on 1.4V.

In order to meet that requirement, we can use the transformer to create the 1.2V swing. Then we need to bias the single output to 1.4V. Please see attached diagram for an example.

Useful Links:
For more information regarding transformers and how they're used, please refer to the following Knowledge Base articles:

Transformer recommendations for HOTLink II
Do I need a transformer if I want to use a single-ended serial interface?

IBIS/SPICE models for the CY7B923/933

Thu, 03 Feb 2011 06:55:03 -0600

There are no IBIS models for these parts, but there are SPICE models. These can be obtained through an NDA (Non-Disclosure agreement), please contact Technical Support.

Points of interest:
Many board designers are not set-up to handle SPICE models. In the past, we have told people that the reason for giving SPICE models was because traditional IBIS models lack accuracy at these signaling speeds, and because they tend to poorly represent differential or balanced signals. While a number of these items have been upgraded in the newer releases of IBIS, all of them have not been fully addresed yet.

HOTLink Transmitter/Receiver (Attached below 38-020170D_V )

Cypress.com: Documentation

Product Selector Guide (PSG) - Interface

Crosstalk Measurement Techniques for Multi-Channel and Multi-Rate High Speed Serial Communication Systems

CYP15G0101DXB, CYV15G0101DXB: Single-channel HOTLink II™ Transceiver

CYP15G0403DXB: Independent Clock Quad HOTLink II™ Transceiver

CYP15G0401DXB, CYV15G0401DXB: Quad HOTLink II™ Transceiver

CY7C9689A: TAXI™-compatible HOTLink Transceiver

CY7B923, CY7B933: HOTLink® Transmitter/Receiver

CY7C924ADX: 200 MBaud HOTLink® Transceiver

CY7B952: SST™ SONET/SDH Serial Transceiver

CY7B951: Local Area Network ATM Transceiver

CYS25G0101DX: SONET OC-48 Transceiver

CYP15G0201DXB: Dual-channel HOTLink II™ Transceiver

CYP15G0101DX-EVAL

CYS25G0101DX-EVAL

CYP15G0401DX-EVAL

SPLDs for New Designs

Use of the CEO/A2 in a Single Chip Configuration

Functionality Problem with Ultra37000V CPLD Despite Passing Simulation

Hysteresis on Input of Cypress Quantum38K CPLDs

Are military parts vacuum sealed?

Issues with Pins Locked to a Certain Level Despite Simulation

Why tS > tSPT for Ultra 37000 CPLDs

Thermal Information for Cypress Flash370i CPLDs

Differences Between Revision A and Revision B of Ultra 37000 CPLDs

ISR Failures during Flash 370 and Flash 370i Programming

Boundary Scan on Flash370 and Flash370i CPLDs

Transparent Latches in Ultra 37000 CPLDs

Security Bit in the Ultra 37000

Do MAX340 EPLDs Have Internal Oscillators?

In Aldec-HDL is there any way to name remerged signals other than VBUS#

Creating Bi-Directional Signals in Warp

Is there an application to convert a *.stp or *.hex file into a C code array?

Registering Warp

Why does the ISR software not show a particular revision of Delta 39K devices?

BSDL model of CY37032P44 device

Avoiding overflow of RX FIFO in the CY7C924ADX and CY7C9689A.

Characteristics and considerations for HOTLink jitter

Data stream is always valid when RVS is LOW

AN1161 - HOTLink® Jitter Characteristics

AN1184 - Frequently Asked Questions about HOTLink®

AN1057 - TAXITM to Cypress CY7C9689A HOTLink® Transceiver Conversion Series: 1. System Parallel Interface

AN1032 - Using Decoupling Capacitors

AN1162 - HOTLink® Design Considerations

AN1055 - Termination and Biasing of HOTLink IITM High-Speed Serial I/O

AN35159 - TAXI™ to Cypress CY7C9689 HOTLink® Transceiver Conversion Series: 2 Serial Interface

AN1130 - Interfacing the CY7B923 and CY7B933 (HOTLink®) to Clocked FIFOs

AN1089 - Parallel Cyclic Redundancy Check (CRC) for HOTLink®

AN1077 - Replacing Wire with Inexpensive Plastic Fiber Solutions

AN1125 - Interfacing the CYS25G0101DX to Differential LVPECL

AN1038 - Upgrade Your TAXI–275 with HOTLink®

AN17004 - Decoupling Guidelines for the CYS25G0101DX OC-48 SONET Transceiver

AN1047 - Understanding Bit-Error-Rate with HOTLink®

Application note : Driving Copper Cables with HOTLink™

Moisture Sensitivity Level (MSL) of Cypress Parts

SONET/SDH weiter ausgereizt (German)

Interfacing the SO pin to CY7B933

Are the FIFO's accessible (for either reads or writes) when the part enters BIST mode (CY7C924ADX or CY7C9689A)

MTBF or FIT of the CY7B923/CY7B933

Is there a drop in replacement for the Cy7B923/933 LMB military package

Configure the HOTLink 1 for 3.3V I/O?

SMPTE standards supported by HOTLink family

Should I use HOTLink CY7C924ADX or CY7C9689A

Configuration of the Status In (SI) and Status Out (SO) Pins

Can the FIFO be bypassed in CY7C924ADX when using the byte-packer

Unused serial inputs and outputs on HOTLink CY7B923/CY7B933

CY9266 Evaluation Board documentation

Meaning in datasheet, when it says that you can write to the FIFO from DC to 50 MHz

Reducing Power Dissipation: Unused serial outputs on CY7C9689

Transformers recommendation for HOTLink CY7B9234 and CY7B9334

Latency through a CY7C924ADX/CY7C9689A Transmitter and Receiver.

Rad hardness, Soft Error Rate (SER), Single Event Upset (SEU) rates for the CY7B923 and CY7B933.

CKR outputs are unusable when the serial inputs to the CY7B933 are left floating and a REFCLK of 40MHz is supplied.

SPDSEL and RANGESEL for 100MBaud (CY7C9689A, CY7C924ADX)

AN1027 - Using High-Speed Serial Links to Supplement Parallel Data Buses

HOTLink II Three Level Control Inputs

Switching between Serial Differential Inputs

Considerations in Interfacing HOTLink II to Fiber Optic Module

Receive Status Bits in HOTLink II

State of the RXSC/D* signal while VLTN is asserted for the CY7C9689A

Is there an application to convert a .stp or .hex file into a C code array?