PSoC Designer 5.0 SP6 will continue to be available for System Level Design users, and it will co-exist with future PSoC Designer 5.1 releases. However, we are not recommending System Level Design for production designs.

We suggest users to use the latest version of PSoC Designer located here:

www.cypress.com/go/psocdesigner

PSoC Designer 5.0 SP6 supports Internet Explorer 6 through 8, but does not support Internet Explorer 8 Beta or Internet Explorer 9 due to compatibility issues.

To Install PSoC Designer 5.0 SP6 users must first have PSoC Programmer installed first. For the latest release of PSoC Programmer please, Click Here

PSoC Designer 5.0 PS6 was tested using Beta version of Windows 7. PSoC Designer 5.0 SP6 is not supported for Windows 7 systems.

To Install:

Shut Down any currently running instances of PSoC Designer.

If an earlier service pack of PSoC Designer 5.0 is currently installed, uninstall it. To do this please navigate to Start>Control Panel>Add or Remove Programs.

• Install latest PSoC Programmer.
• Install PSoC Designer 5.0 SP6 by running the installed in the downloads table below.”

Note to HI-TECH Compiler Users:

There are new devices in this release. To compile projects containing these devices with the HI-TECH compiler, you must manually update the psoc.ini file. The HI-TECH psoc.ini file is found in the HI-TECH installation folder. The default location of the psoc.ini is here:

C:\Program Files\HI-TECH Software\HCPSOC\PRO\9.61\dat\psoc.ini

The default location of the replacement psoc.ini file that adds support for the new devices is here:

C:\Program Files\Cypress\Common\CypressSemiBuildMgr\tools\psoc.ini

PSoC Programmer: The latest version of PSoC Programmer must be installed along with PSoC Designer. For the latest release please navigate to the PSoC Programmer web page: Click Here

PSoC Designer: User Guides - Click Here

PSoC Designer Archive - Click Here

General Description

With its unique array of configurable blocks, PSoC® 5LP is a true system-level solution providing microcontroller unit (MCU), memory, analog, and digital peripheral functions in a single chip. The CY8C52LP family offers a modern method of signal acquisition, signal processing, and control with high accuracy, high bandwidth, and high flexibility. Analog capability spans the range from thermocouples (near DC voltages) to ultrasonic signals.

The CY8C52LP family can handle dozens of data acquisition channels and analog inputs on every GPIO pin. The CY8C52LP family is also a high-performance configurable digital system with some part numbers including interfaces such as USB and multimaster I2C. In addition to communication interfaces, the CY8C52LP family has an easy to configure logic array, flexible routing to all I/O pins, and a high-performance 32-bit ARM®Cortex™-M3 microprocessor core.

Designers can easily create system level designs using a rich library of prebuilt components and boolean primitives using PSoC Creator™, a hierarchical schematic design entry tool. The CY8C52LP family provides unparalleled opportunities for digital bill of materials integration while easily accommodating last minute design changes through simple firmware updates.

Features

• 32-bit ARM Cortex-M3 CPU core
• Low voltage, ultra low power
• Versatile I/O system
• Digital peripherals
• Analog peripherals (1.71 V ≤ VDDA ≤ 5.50 V)
• Programming, debug, and trace
• Precision, programmable clocking
• Temperature and packaging
• For more, see data sheet pdf

General Description

With its unique array of configurable blocks, PSoC® 5LP is a true system-level solution providing microcontroller unit (MCU), memory, analog, and digital peripheral functions in a single chip. The CY8C58LP family offers a modern method of signal acquisition, signal processing, and control with high accuracy, high bandwidth, and high flexibility. Analog capability spans the range from thermocouples (near DC voltages) to ultrasonic signals.

The CY8C58LP family can handle dozens of data acquisition channels and analog inputs on every GPIO pin. The CY8C58LP family is also a high-performance configurable digital system with some part numbers including interfaces such as USB, multimaster I2C, and controller area network (CAN). In addition to communication interfaces, the CY8C58LP family has an easy to configure logic array, flexible routing to all I/O pins, and a high-performance 32-bit ARM® Cortex™-M3 microprocessor core.

Designers can easily create system-level designs using a rich library of prebuilt components and boolean primitives using PSoC Creator™, a hierarchical schematic design entry tool. The CY8C58LP family provides unparalleled opportunities for analog and digital bill of materials integration while easily accommodating last minute design changes through simple firmware updates.

Features

• 32-bit ARM Cortex-M3 CPU core
• Low voltage, ultra low power
• Versatile I/O system
• Digital peripherals
• Analog peripherals (1.71 V ≤ VDDA ≤ 5.5 V)
• Programming, debug, and trace
• Precision, programmable clocking
• Temperature and packaging
• For more, see data sheet pdf

General Description

With its unique array of configurable blocks, PSoC® 5LP is a true system level solution providing microcontroller unit (MCU), memory, analog, and digital peripheral functions in a single chip. The CY8C54LP family offers a modern method of signal acquisition, signal processing, and control with high accuracy, high bandwidth, and high flexibility. Analog capability spans the range from thermocouples (near DC voltages) to ultrasonic signals.

The CY8C54LP family can handle dozens of data acquisition channels and analog inputs on every GPIO pin. The CY8C54LP family is also a high-performance configurable digital system with some part numbers including interfaces such as USB and multi-master I2C. In addition to communication interfaces, the CY8C54LP family has an easy to configure logic array, flexible routing to all I/O pins, and a high-performance 32-bit ARM® Cortex™-M3 microprocessor core.

Designers can easily create system-level designs using a rich library of prebuilt components and boolean primitives using PSoC® Creator™, a hierarchical schematic design entry tool. The CY8C54LP family provides unparalleled opportunities for digital and analog bill of materials integration while easily accommodating last minute design changes through simple firmware updates.

Features

• 32-bit ARM Cortex-M3 CPU core
• Low voltage, ultra low power
• Versatile I/O system
• Digital peripherals
• Analog peripherals (1.71 V ≤ VDDA ≤ 5.5 V)
• Programming, debug, and trace
• Precision, programmable clocking
• Temperature and packaging
• For more, see data sheet pdf

General Description

With its unique array of configurable blocks, PSoC® 5LP is a true system level solution providing MCU, memory, analog, and digital peripheral functions in a single chip. The CY8C56LP family offers a modern method of signal acquisition, signal processing, and control with high accuracy, high bandwidth, and high flexibility. Analog capability spans the range from thermocouples (near DC voltages) to ultrasonic signals.

The CY8C56LP family can handle dozens of data acquisition channels and analog inputs on every GPIO pin. The CY8C56LP family is also a high performance configurable digital system with some part numbers including interfaces such as USB and multimaster I2C, and controller area network (CAN). In addition to communication interfaces, the CY8C56LP family has an easy to configure logic array, flexible routing to all I/O pins, and a high performance 32-bit ARM® Cortex™-M3 microprocessor core.

Designers can easily create system level designs using a rich library of prebuilt components and boolean primitives using PSoC Creator™, a hierarchical schematic design entry tool. The CY8C56LP family provides unparalleled opportunities for analog and digital bill of materials integration while easily accommodating last minute design changes through simple firmware updates.

Features

• 32-bit ARM Cortex-M3 CPU core
• Low voltage, ultra low power
• Versatile I/O system
• Digital peripherals
• Analog peripherals (1.71 V ≤ VDDA ≤ 5.5 V)
• Programming, debug, and trace
• Precision, programmable clocking
• Temperature and packaging
• For more, see pdf.

CY3236A-PIRMOTION Rev. A Kit Contents:

• PIR Motion Sensor Board using CY8C27443-24PVXI PSoC(R) device
• 12V Power Supply
• PSoC Designer(TM) and PSoC Programmer CD
• Design Files CD (Schematic, BOM, Gerber Files, PSoC Designer Example Project)

The video describes the case of using a DMA to buffer ADC data. Buffering of 20 bit ADC data is taken as an example and discussed. The video also gives a preview of the project implementing the 20 bit data buffering and explains the DMA configuration in code.

The following table indicates the PSoC devices, PSoC Creator versions, compilers, and development kits that will work with this application note project:

*Refer to Migrating CY8CKIT-001 DVK project to CY8CKIT 030/ 050. 

Notes:

1. Click on AN84741 - PSoC® 5 to PSoC 5LP Migration Guide to learn differences between PSoC 5 and PSoC 5LP.
2. Click on AN77835 - PSoC® 3 to PSoC 5LP Migration Guide to learn differences between PSoC 3 and PSoC 5LP.
3. For PSoC 5 project and related document, please download file AN61102_Archive.zip.

Projects associated with this application note can be downloaded from the ‘Related Files’ section below. For your convenience, we have provided projects that are compatible with the two most recent versions of PSoC Creator:

• AN61102.zip is used with PSoC Creator 2.1 SP1
• AN61102_Archive.zip is used with PSoC Creator 2.1/2.0

The project’s default settings may not be compatible with your device or kit, and you may need to change your project settings. For more information, see:

With PSoC Creator, you can:

• Create and share user-defined, custom peripherals using hierarchical schematic design and Verilog entry
• Automatically place and route selected components and integrate simple glue logic normally residing in discrete muxes or 22V10s
• Trade-off hardware and software design considerations allowing you to focus on what matters: getting to market fast

PSoC Creator also allows you to tap into an entire tools ecosystem with integrated compiler tool chains, RTOS solutions and top production programmers to support PSoC 3, PSoC 5 and PSoC 5LP.
 

New Features in Creator 2.2

• Project Datasheet Generation
• Component Distribution (Import/Export)
• Rename Annotation Components to External / Off-Chip
• New DWR Parameter – “Variable Vdda”
• Binding Error Symbols
• Peripheral Register Debug in IDEs
• MISRA Support for Automotive Applications
• Datapath Editor Enhancements

Additional Information and Documentation

Further details on this release are available in the Release Notes. Additionally, a Migration Guide is also available to aid in the process of porting designs into the latest PSoC Creator toolset.

System Configuration

The following minimum configuration is required for installation of the PSoC Creator 2.2 application. See the release notes for details on performance expectations in resource constrained systems.

• Windows Operating System
  • Windows XP SP2 or SP3
  • Windows Vista (32- and 64-bit supported) and SP1
  • Windows 7 (32- and 64-bit supported) and SP1
  • MacOS v10 with Parallels Desktop v6 running Windows XP SP3
• 1 GHz CPU
• 512 MB RAM (minimum), 1 GB RAM (preferred)
• 2 GB of hard disk space
• USB 2.0
• 1024x768 screen resolution  

PSoC Creator Training

Need help downloading/installing? Call 1-800-541-4736 and select 8.

The ICE-Cube also serves as a single-site device programmer via an ISSP (In-System Serial Programming) Cable and MiniEval board included in the kit. The MiniEval board is a programming and evaluation board which connects to the ICE-Cube via an ISSP Cable and allows programming of DIP devices. There are also other Programming boards available for programming other packages. The MiniEval also includes LEDs and a POT for simple evaluation and demonstration.

PSoC 1 Debugger Includes:

• PSoC Designer Software CD-ROM
• ICE-Cube In-Circuit Emulator
• ICE Flex-Pod for CY8C29xxx Family
• Backward compatibility Cat-5 Adapter
• ISSP Cable
• Mini-Eval Programming Board in One
• USB 2.0 Cable and Blue Cat-5 Cable
• 110 ~ 240V Power Supply, Euro-Plug Adapter
• 2 CY8C29466-24PXI 28-PDIP Chip Samples

Supports following 8 bit PSoC1 (Programmable System-On Chip) families, including automotive, except CY8C25/26xxx devices.

PSoC 1 Getting Started Debugging - Part 1

Software Title	Description	Link
PSoC Designer	This kit requires PSoC Designer for development
PSoC Programmer	This kit requires PSoC Programmer for programming

Related Resources:

This kit is specifically designed for analog performance. The noise floor on these kits is very low. Care has been taken to separate the analog and the digital domain, separate regulators are also available. Separate ground planes are provided. We have achieved ENOB very close to 20 bits on this kit. Provision has been provided to add an external precision voltage reference if needed.

Besides the analog, this kit is also meant to demonstrate the low power operation of PSoC3/PSoC5. PSoC3 chip is soldered to the board, this way the leakage currents are reduced significantly compared to the CY8CKIT-001. Special terminals are provided to enable the boost converter operation without much modifications. Jumpers have been provided to remove power to RS232 converter, Potentiometer and to have a single regulator for Analog and digital domain and evaluate the low power operation of PSoC3.

It has got an onboard programmer(Cypress USB chip based), which lets you program PSoC3/PSoC5 without connecting Miniprog3. Provision has been provided to program using Miniprog3 as well.

Kit Contents:

• PSoC 3 Development Board
• LCD Character Display
• USB Cable
• Quick Start Guide
• Kit CD, which includes: PSoC Creator, PSoC Programmer, Projects and Documentation
   

For PSoC training, please visit http://www.cypress.com/go/training.

Software Title	Description	Link
PSoC Creator	This kit requires PSoC Creator for development
PSoC Programmer	This kit requires PSoC Programmer for programming

The TMP05 Digital Temperature Sensor Interface Component is a building block for thermal management applications. It enables designers using PSoC 3 to quickly and easily interface with Analog Devices’ TMP05 or TMP06 digital temperature sensors through a simple, serial 2-wire digital interface. The sensors can be daisy-chained together, minimizing I/O requirements on the controller. For more details on the specific functions of the TMP05 Digital Temperature Sensor Interface Component, refer to the component datasheet.

Notes:

1. Click on AN84741 - PSoC® 5 to PSoC 5LP Migration Guide to learn differences between PSoC 5 and PSoC 5LP.
2. For PSoC 5 project and related document, please download file AN65977_Archive.zip.

Projects associated with this application note can be downloaded from the 'Related Files' section below. For your convenience, we have provided projects that are compatible with the two most recent versions of PSoC Creator:

• AN65977.zip is used with PSoC Creator 2.1 SP1
• AN65977_Archive.zip is used with PSoC Creator 2.1/2.0

The project’s default settings may not be compatible with your device or kit, and you may need to change your project settings. For more information, see:

Sleep mode is used to reduce a PSoC’s average current consumption by entering a low-power state, whenever the CPU and other internally clocked functions are not needed. Sleep mode is most useful for battery-powered systems, but it is applicable to any design.

Features

• Powerful Harvard-architecture processor
• Advanced peripherals (PSoC® blocks)
• Flexible on-chip memory
• Complete development tools
• Precision, programmable clocking
• Programmable pin configurations
• Additional system resources
   

PSoC Functional Overview

The PSoC family consists of many programmable system-on-chip controller devices. These devices are designed to replace multiple traditional MCU-based system components with a low cost single-chip programmable component. A PSoC device includes configurable blocks of analog and digital logic, and programmable interconnect. This architecture allows you to create customized peripheral configurations, to match the requirements of each individual application. Additionally, a fast CPU, Flash program memory, SRAM data memory, and configurable I/O are included in a range of convenient pinouts.

The document AN66477 - PSoC® 3 and PSoC 5 Temperature Measurement with Thermistor is currently being reviewed and updated to support the new Thermistor Component available in PSoC Creator 2.1. The updated application note is expected by 11/30/2012. The below abstract describes what this application note covers. If you have an immediate need for this document, please click here to create a technical support case requesting this material. 

Please note that the Thermistor Component is now provided in PSoC Creator 2.1. Please access the Thermistor Component Datasheet for features and configuration details. 

AN66477 Abstract:

AN66477 explains how to measure temperature with a thermistor using PSoC® 3 or PSoC 5LP®. This application note describes the PSoC Creator™ Thermistor Calculator Component, which simplifies the math-intensive resistance-to-temperature conversion. In addition, we discuss a PSoC Creator thermistor measurement project.

1. Click on AN84741 - PSoC® 5 to PSoC 5LP Migration Guide to learn differences between PSoC 5 and PSoC 5LP.
2. Click on AN77835 - PSoC® 3 to PSoC 5LP Migration Guide to learn differences between PSoC 3 and PSoC 5LP.

General-purpose input and output (GPIO) is a very critical part of any microcontroller unit (MCU) as they form the bridge between the external world and the MCU. The type and nature of this external world bridge depends on the end application. For instance, an ADC requires a GPIO to be an analog pin whereas an I2C or SPI digital communication block requires the same GPIO to be digital. In order to properly setup this external world bridge, you need to know not only the end application but also the GPIO system of the MCU that is used. PSoC like any other controller has its own GPIO system. This application note discusses the application specific parameters of the GPIO system. Detailed technical overview of the system can be found in the respective device technical reference manual (TRM) under General Purpose I/O chapter of PSoC Core section.
 

• 8-, 16-, 24-bit address bus width
• 8-, 16-bit data bus width
• Supports external synchronous memory
• Supports external asynchronous memory
• Supports custom interface for memory
• Supports a range of speeds of external memories (from 5 to 200 ns)
• Supports external memory power-down, sleep, and wakeup modes

General Description

The EMIF component enables access by the CPU or DMA to memory ICs external to the PSoC 3/5LP. It facilitates setup of the EMIF hardware, as well as UDBs and GPIOs as required. The EMIF can control synchronous and asynchronous memories without the need to configure any UDBs in synchronous and asynchronous modes. In UDB mode, UDBs must be configured to generate external memory control signals.

1. Click on AN84741 - PSoC® 5 to PSoC 5LP Migration Guide to learn differences between PSoC 5 and PSoC 5LP.

In addition, this application note walks you through an example project for PSoC 5LP. Through this project example, PSoC Creator is introduced. The first part of the project guides you on how to blink an LED like a typical MCU. In the second part you develop a "breathing" LED using the Programmable-System-On-Chip concept.

An additional bonus project is included with this application note that takes a design example a little farther than simply blinking LEDs. The bonus project uses some of the mixed signal functionality of PSoC 5LP to create an ambient light/dark detector using one of the LEDs on the CY8CKIT-050 demonstration board. 

The following table indicates the PSoC devices, PSoC Creator versions, compilers, and development kits that will work with this application note project:

*Refer to Migrating CY8CKIT-001 DVK project to CY8CKIT 030/050.

1. Click on AN84741 - PSoC® 5 to PSoC 5LP Migration Guide to learn differences between PSoC 5 and PSoC 5LP.
2. For PSoC 5 project and related document, please download file AN77759_Archive.zip.
3. Click on AN77835, PSoC 3 to PSoC 5LP Migration Guide. to learn differences between PSoC 3 and PSoC 5LP

Projects associated with this application note can be downloaded from the 'Related Files' section below. For your convenience, we have provided projects that are compatible with the two most recent versions of PSoC Creator:

• AN77759.zip is used with PSoC Creator 2.1 SP1
• AN77759_Archive.zip is used with PSoC Creator 2.1/2.0

The project’s default settings may not be compatible with your device or kit, and you may need to change your project settings. For more information, see:

Features

• Low power CapSense® block with SmartSense Auto-tuning
• Powerful Harvard-architecture processor
• Operating Range: 1.71 V to 5.5 V
• Operating Temperature range: -40 °C to +85 °C
• Flexible on-chip memory
• Four Clock Sources
• Programmable pin configurations
• Versatile Analog functions
• Full-Speed USB
• For more, see pdf

PSoC^® Functional Overview

The PSoC family consists of on-chip controller devices, which are designed to replace multiple traditional microcontroller unit (MCU)-based components with one, low cost single-chip programmable component. A PSoC device includes configurable analog and digital blocks, and programmable interconnect. This architecture allows the user to create customized peripheral configurations, to match the requirements of each individual application.  

Architecture:

PSoC 3/PSoC 5/PSoC 5LP has total of 24 UDBs. Each UDB mainly consists of: 8 macrocells, PLA (which can implement 16 Product terms), 1 datapath cell, 1 Control cell and 1 Status cell.

Altera MAXV 570ZM device has a total of 570 Logic elements. Each logic element consists of: One 4-input LUT and One register (D flip-flop).

Lattice MACHXO2 256HC device has a total of 128 slices. Each slice consists of: Two 4-input LUTs and Two registers (D flip-flop).

Xilinx XC2C384 consists of 24 Function blocks. Each function block consists of 16 Macrocells and a PLA (which can implement 56 Pterms).

Conclusion:

Data from the above table shows that the PSoC 3/PSoC 5/PSoC 5LP UDB utilization is comparable to:

Mid to higher end CPLDs from Altera MAXV series

Mid to higher end CPLDs from Xilinx Cool runner series

Lower end to mid range FPGAs from Lattice’s MACHXO2 series

The following table indicates the PSoC devices, PSoC Creator versions, compilers, and development kits that will work with this application note project:

Refer to Migrating CY8CKIT-001 DVK project to CY8CKIT 030/ 050.

The architecture TRM contains complete and detailed information about how to use and design with the IP blocks that construct a PSoC device. This document describes the analog and digital architecture to give the designer a better understanding of features and limitations.

The registers TRM covers the registers of the device. The document lists all the registers in mapping tables, in address order.

The programming specifications documents explain the hardware connections, programming protocol, programming vectors, and the timing information for developing programming solutions for a PSoC device.

NOTE: As stated above, the purpose of this kit is to get you acquainted with the PSoC 3 architecture and software tools. For full development and evaluation purposes, we recommend you use one of our full development kits: PSoC 3 Development Kit (CY8CKIT-030) or PSoC Development Kit (CY8CKIT-001).

Kit Contents:

• PSoC 3 FirstTouch Board
• USB Cable
• 9V Battery
• Proximity Wire (for use as a Proximity Detection Antenna)
• Quick Start Guide
• Kit CD, which includes: PSoC Creator™, Kit Projects, and Documentation

For PSoC training, please visit http://www.cypress.com/go/training.

Software Title	Description	Link
PSoC Creator	This kit requires PSoC Creator for development
PSoC Programmer	This kit requires PSoC Programmer for programming

Note: The installation file will install the sample projects onto your system

Kit Contents:

• PSoC® CY8C38 Family Processor Module
• Kit CD, which includes: PSoC Creator™, PSoC Programmer, and Documentation

For PSoC training, please visit http://www.cypress.com/go/training.
 

Software Title	Description	Link
PSoC Creator	This kit requires PSoC Creator for development
PSoC Programmer	This kit requires PSoC Programmer for programming

Note: The installation file will install the sample projects onto your system

Kit Upgrade: Now it’s time to make the upgrade to PSoC® 5LP Processor Module and take advantage of all that PSoC has to offer.

These upgrades are FREE to our valued customers. Log on to http://www.cypress.com/go/psockitupgrade to know more details. Cypress appreciates your business and continued loyalty.

Kit Contents:

• PSoC Development Board 
• PSoC 1 CY8C28 Family Processor Module
• PSoC 3 CY8C38 Family Processor Module
• PSoC 5 CY8C58LP Family Processor Module
• MiniProg3 Program/Debug Device
• Program/Debug Ribbon Cable
• USB Cable
• 12V AC Power Adapter
• Quick Start Guide
• Kit CDs, which includes: PSoC Creator™, PSoC Designer™, PSoC Programmer, Projects, and Documentation

For PSoC training, please visit http://www.cypress.com/go/training.

Software Title	Description	Link
PSoC Creator	This kit requires PSoC Creator for development
PSoC Designer	This kit requires PSoC Designer for development
PSoC Programmer	This kit requires PSoC Programmer for programming

Introduction

PSoC® 3 and PSoC 5LP have a powerful clocking system. This system offers the flexibility and performance to suit the needs of most embedded applications. It is comprised of clock sources and a clock distribution network. The clock sources available are the internal main oscillator (IMO), external crystal oscillators (ECO) and internal low-speed oscillator (ILO). This application note describes the IMO and ILO as well a method to improve their accuracy through run-time calibration.

The following table indicates the PSoC devices, PSoC Creator versions, compilers, and development kits that will work with this application note project:

Notes:

1. Click on AN84741 - PSoC® 5 to PSoC 5LP Migration Guide to learn differences between PSoC 5 and PSoC 5LP.
2. Click on AN77835 - PSoC® 3 to PSoC 5LP Migration Guide to learn differences between PSoC 3 and PSoC 5LP.
3. For PSoC 5 project and related document, please download file AN80248_Archive.zip.

Projects associated with this application note can be downloaded from the 'Related Files' section below. For your convenience, we have provided projects that are compatible with the two most recent versions of PSoC Creator:

• AN80248.zip is used with PSoC Creator 2.1 SP1
• AN80248_Archive.zip is used with PSoC Creator 2.1/2.0

The project’s default settings may not be compatible with your device or kit, and you may need to change your project settings. For more information, see:

See how you can integrate thermal management functions in a single low-cost PSoC 1 device:

1. Closed-loop 4-wire fan control
2. Temperature measurement
3. Fan Speed Control based on temperature measurement
4. Display

Required Hardware

CY8CKIT-001 PSoC Development Kit (sold separately) The CY8CKIT-001 PSoC Development Kit (DVK) allows you to evaluate the PSoC 1, PSoC 3, and PSoC 5 families. Place the Processor Module families (included) on the DVK and program it with the CY8CKIT-016 PSoC Thermal Management kit example project using the MiniProg3 Program device.

CY8CKIT-036 PSoC Thermal Management Expansion Board Kit (sold separately) The CY8CKIT-036 PSoC Thermal Management Expansion Board Kit (EBK) connects to the CY8CKIT-001. Kit Contents: Two 4-wire fans and connectors for two additional 4-wire fans Digital (I2C-based TMP175, One-wire DS1820, PWM output TMP05) and Analog (Diode) temperature sensors I2C/SMBus/PMBus host interface   The EBK connects to the CY8CKIT-001 PSoC Development Kit for operation.

Easy to use Modular Design

The CY8CKIT-001 PSoC 1 Development Kit allows you to evaluate Cypress's PSoC 1, PSoC 3 and PSoC 5 families. The modular design allows you to interface with different types of Expansion Board Kits. In this case the CY8CKIT-036 plugs onto the CY8CKIT-001, which uses the firmware example project of the CY8CKIT-016 to demonstrate Thermal Management functions.

CY8CKIT-001 PSoC DVK	CY8CKIT-036		CY8CKIT-016
PSoC 1 CY8C28 Family Processor Module

Example Project Description

Example firmware provides a quick demonstration of a two-zone Thermal Management system. Zone 1 consists of a 4-wire fan, the I2C temperature sensor and a potentiometer that simulates a diode. Zone 2 consists of the other 4-wire fan, a PWM output temperature sensor and a 1-wire temperature sensor. Fan RPM is controlled based on the weighted average readings of temperature sensors in their zones. Fan RPM zone temperature readings and fan faults are displayed in LCD.
 

PSoC One-chip Solution
 

This Thermal Management solution is used by Tier 1 Customers in Data and Telecom equipment. It can be your solution as well. Options include:

1. Driving up to 8 fans in closed-loop or open-loop
2. Interfacing with Multiple Digital and Analog Sensors
3. Communicating via I2C, SPI, UART or PMBus* and SMBus*

*SMBus and *PMBus with PSoC 1 are under development

To learn more, download these App Notes.

To know more about PSoC 1, click here. To know more about other PSoC 1 kits, click here.
 

Software Title	Description	Link
PSoC Designer	This kit requires PSoC Designer for development
PSoC Programmer	PSoC programmer is required every time the PSoC 1 (CY8C28) Family Processor Module is programmed

Features

• XRES pin to support in-system serial programming (ISSP) and external reset control in CY8C24894
• Powerful Harvard-architecture processor
• Advanced peripherals (PSoC® Blocks)
• Full speed USB (12 Mbps)
• Flexible on-chip memory
• Programmable pin configurations
• Precision, programmable clocking
• Additional system resources
• For more, see pdf

PSoC Functional Overview

The PSoC family consists of many devices with on-chip controllers. These devices are designed to replace multiple traditional MCU-based system components with one low-cost single-chip programmable component. A PSoC device includes configurable blocks of analog and digital logic, and programmable interconnect. This architecture makes it possible for you to create customized peripheral configurations, to match the requirements of each individual application.

现在在中国 !!

今日本語で !!  

Introduction

   Cypress's Programmable System-on-Chip (PSoC®) integrates a microcontroller with programmable analog and digital peripherals. Because you can configure the resources of a PSoC, you can develop a device that is customized and tuned for your application. Moreover, as the needs of the application change during development and in production, you can reconfigure the device to adapt to these new requirements with minimal effort.   
   

Getting Started with PSoC 1 - Part 1 - Architecture and System Resources

Getting Started with PSoC 1 - Part 2 - Digital Subsystem

Getting Started with PSoC 1 - Part 3 - Analog architecture

Getting Started with PSoC 1 - Part 4 - My first PSoC Designer Project

CAN (Controller Area Network) is a serial communication protocol developed by Robert Bosch GmbH in the early 1980s. This protocol was initially developed for automotive applications to communicate between subsystems without a central control. CAN is also being adopted in areas such as embedded systems (CANOpen) and factory automation (DeviceNet). CAN was standardized by ISO in 2003 (ISO 11898-1:2003).

This application note introduces the basic concepts of CAN protocol and demonstrates how CAN bus communication can be implemented using PSoC® 3 and PSoC 5LP (hereafter referred to as PSoC). Four code examples are included with this application note. Examples 1 and 2 together illustrate a simplex communication between two PSoCs. Examples 3 and 4 together demonstrate the Remote Transmission Request (RTR) feature of CAN.

The video talks about how to transmit and receive messages using CAN controller available in PSoC3.

The following table indicates the PSoC devices, PSoC Creator versions, compilers, and development kits that will work with this application note project:

*Refer to Migrating CY8CKIT-001 DVK project to CY8CKIT 030/ 050.

1. Click on AN84741 - PSoC® 5 to PSoC 5LP Migration Guide to learn differences between PSoC 5 and PSoC 5LP.
2. Click on AN77835 - PSoC® 3 to PSoC 5LP Migration Guide to learn differences between PSoC 3 and PSoC 5LP.
3. For PSoC 5 project and related document, please download file AN52701_Archive.zip.

Projects associated with this application note can be downloaded from the ‘Related Files’ section below. For your convenience, we have provided projects that are compatible with the two most recent versions of PSoC Creator:

• AN52701.zip is used with PSoC Creator 2.1 SP1
• AN52701_Archive.zip is used with PSoC Creator 2.1/2.0

The project’s default settings may not be compatible with your device or kit, and you may need to change your project settings. For more information, see:

There are two workarounds in PSoC Designer for this issue:

1. Change the value of the ORDER attribute for the 'Watchdog Enable' resource from '19' to '20' in the StdDevicesBH1.xml device’s description. You can find this file in the PSoC Designer installation path at
   Common\CypressSemiDeviceEditor\Devices\CY8C29000\StdDevicesBH1.xml.


2. Execute the following macro in the project application code:

M8C_EnableWatchdog

AN32200 has more information on Clocks and Global Resources configuration of PSoC® 1 devices in PSoC Designer.

For other technical issues, contact Cypress technical support at www.cypress.com/go/support.

For example, if ‘UART’ is the instance name of the UART component in your project, then write the following function in the main.c file to override Keil’s built-in putchar function:

Then, printf can be used to send data to UART in the following manner (note that the putchar() function should either be defined or declared before the first call to the printf() function for proper execution):

Introduction

The DMA controller (DMAC) in PSoC 3 and PSoC 5LP can transfer data from a source to a destination with no CPU intervention. This allows the CPU to handle other tasks while the DMA does data transfers, thereby achieving a „multiprocessing‟ environment.

The PSoC DMA Controller (DMAC) is highly flexible – it can seamlessly transfer data between memory and on chip peripherals including ADCs, DACs, Filter, USB, UART, and SPI. There are 24 independent DMA channels.

 The following video gives the user a brief description of how to use the DMA on PSoC3 and the different parameters related to it:

The following table indicates the PSoC devices, PSoC Creator versions, compilers, and development kits that will work with this application note project:

 *Refer to Migrating CY8CKIT-001 DVK project to CY8CKIT 030/ 050. 

1. Click on AN84741 - PSoC® 5 to PSoC 5LP Migration Guide to learn differences between PSoC 5 and PSoC 5LP.
2. For PSoC 5 project and related document, please download file AN52705_Archive.zip.

Projects associated with this application note can be downloaded from the ‘Related Files’ section below. For your convenience, we have provided projects that are compatible with the two most recent versions of PSoC Creator:

• AN52705.zip is used with PSoC Creator 2.1 SP1
• AN52705_Archive.zip is used with PSoC Creator 2.1/2.0

The project’s default settings may not be compatible with your device or kit, and you may need to change your project settings. For more information, see:

This processor module must be used in conjunction with the PSoC Development Kit (CY8CKIT-001) to create designs utilizing on-board DVK resources or compatible expansion boards. This kit provides you with an additional processor module to use with different projects.

Kit Contents:

• PSoC® CY8C58LP Family Processor Module
• Kit CD, which includes: PSoC Creator™, PSoC Programmer, and Documentation

For PSoC training, please visit  http://www.cypress.com/go/training .

Software Title	Description	Link
PSoC Creator	This kit requires PSoC Creator for development
PSoC Programmer	This kit requires PSoC Programmer for programming

Note: The installation file will install the sample projects onto your system

• Eliminates unwanted “glitch” pulses on digital input lines
• Programmable filtering length and bypass option
  
   

General Description

Glitch filtering is the process of removing unwanted pulses from a digital input signal that is usually high or low. Glitches frequently occur on lines carrying signals from sources such as RF receivers. Electrical or in some cases even mechanical interference can trigger an unwanted glitch pulse from the receiver.

This design outputs a ‘1’ only when the current and previous N samples are ‘1’, and a ‘0’ only when the current and previous N samples are ‘0’. Otherwise the output is unchanged from its current value.

For more details on glitch filtering please see application note AN60024.

Required Software: PSoC Creator 2.1 Component Pack 4 and above.

• USB Clock for Full-Speed operation – 48 MHz (+0.25% tolerance).
• UART with 8x oversampling, voting enabled, the tolerance for tclock: ±3.9%
• UART with 16x oversampling, voting enabled, he tolerance for tclock: ±4.6%
• The accuracy of CAN CLK_BUS must be at least 1.58% for 125 Kbps and slower bit rates

  For bit rates faster than 125 Kbps, the accuracy of CAN CLK_BUS must be 0.5% or better.

Therefore, the project that uses IMO as clock source with USB/UART/CAN does not work in PSoC Creator 2.0 or later version. You must use an external crystal-base for clocking the device when using USB, CAN, and UART communication. For USB communication, you must use a 24-Mhz external crystal.

Refer to AN54439 - PSoC® 3 and PSoC 5 External Crystal Oscillators for more details on how to configure hardware and firmware for PSoC 3 or PSoC 5 using the integrated oscillator subsystems and external resonators.

If you are new to PSoC Programmer, you must first install it and then set the options you want to use. You then use PSoC programmer to:

• Open a hex file
• Select a communication port
• Select a device
• Set programming parameters
• Program a device
• Verify programming

PSoC® 1 - Getting Started with SPI

PSoC 1, PSoC 3, and PSoC 5LP are all true programmable embedded system-on-chips that integrate configurable analog, programmable digital, memory, and a central processor on a single chip.

PSoC contains a processor, but it is not an MCU. The name PSoC (Programmable-System-on-Chip) defines its true identity. AN54181 introduces the Programmable-System-on-Chip concept with specific emphasis on PSoC 3. Here, you learn about PSoC 3 and what it can do for you and your projects. It also introduces PSoC Creator™, a powerful IDE development tool for PSoC 3 and PSoC 5LP.

The following video gives brief introduction for PSoC3:

The following video guides how to create projects using PSoC3:

The following table indicates the PSoC devices, PSoC Creator versions, compilers, and development kits that will work with this application note project:

*Refer to Migrating CY8CKIT-001 DVK project to CY8CKIT 030/050. 

1. Click on AN84741 - PSoC® 5 to PSoC 5LP Migration Guide to learn differences between PSoC 5 and PSoC 5LP.
2. Click on AN77835 - PSoC® 3 to PSoC 5LP Migration Guide to learn differences between PSoC 3 and PSoC 5LP.
3. For PSoC 5 project and related document, please download file AN54181_Archive.zip.

Projects associated with this application note can be downloaded from the ‘Related Files’ section below. For your convenience, we have provided projects that are compatible with the two most recent versions of PSoC Creator:

• AN54181.zip is used with PSoC Creator 2.1 SP1
• AN54181_Archive.zip is used with PSoC Creator 2.1/2.0.

The project’s default settings may not be compatible with your device or kit, and you may need to change your project settings. For more information, see:

To get introduced to basics of PSoC 3 and PSoC 5LP Bootloader please refer  AN73854 - PSoC® 3 and PSoC 5LP - Introduction to Bootloaders. If you intend to learn how to develop I2C Bootloader for PSoC 3 and PSoC 5LP,  AN60317 - PSoC® 3/PSoC 5LP I2C Bootloader  should get you going. 

Since the projects involve the use of USB component, in case of PSoC 5LP it is mandatory to use an external 24 MHz crystal.

The Bootloader GUI provided with this App Note has been tested to work on full-fledged Windows operating system only.
The GUI is not tested and not guaranteed to work on Virtual machines.
 

*Refer to Migrating CY8CKIT-001 DVK project to CY8CKIT 030/ 050. 

Notes:

1. Click on AN84741 - PSoC® 5 to PSoC 5LP Migration Guide to learn differences between PSoC 5 and PSoC 5LP.
2. Click on AN77835 - PSoC® 3 to PSoC 5LP Migration Guide to learn differences between PSoC 3 and PSoC 5LP.
3. For PSoC 5 project and related document, please download file AN73503_Archive.zip.

Projects associated with this application note can be downloaded from the ‘Related Files’ section below. For your convenience, we have provided projects that are compatible with the two most recent versions of PSoC Creator:

• AN73503.zip is used with PSoC Creator 2.1 SP1
• AN73503_Archive.zip is used with PSoC Creator 2.1/2.0

The project’s default settings may not be compatible with your device or kit, and you may need to change your project settings. For more information, see:

Introduction

System cooling is a critical task in any high performance electronic system. As circuit miniaturization continues, increasing demands are placed on system designers to improve the efficiency of their thermal management designs. Usually thermal management is done by forced convection. In forced convection the heat dissipation is increased by moving the air inside and around the heat source. This can be easily accomplished using Brushless DC (BLDC) based fans. The speed of these fans depends on DC voltage across these fans.

• Asynchronous reset or preset
• Synchronous reset, preset, or both
• Configurable width for array of D Flip Flops

General Description

The D Flip Flop stores a digital value.

Required Software: PSoC Creator v1.0 Beta 5 and above

Features

• Produces a selectable output voltage that is higher than the input voltage
• Input voltage range between 0.5 V and 3.6 V
• Boosted output voltage range between 1.8 V and 5.25 V
• Source up to 75 mA depending on the selected input and output voltage parameter values
• Two modes of operation: Active and Standby for PSoC 3 or Sleep for PSoC 5LP
• Boost Converter component is not supported on PSoC 5

General Description

The Boost Converter (BoostConv) component allows you to configure and control the PSoC boost converter hardware block. The boost converter enables input voltages that are lower than the desired system voltage to be boosted to the desired system voltage level. The converter uses an external inductor to convert the input voltage to the desired output voltage.

Required Software: PSoC Creator v1.0 Beta 5 and above

• Gain steps from -1 to -49
• High input impedance
• Adjustable power settings

General Description

The Inverting Programmable Gain Amplifier (PGA_Inv) component implements an opamp-based inverting amplifier with user-programmable gain. It is derived from the switched capacitor/continuous time (SC/CT) block.

The inverting gain can be between -1.0 (0 dB) and -49.0 (+33.8 dB). The gain can be selected using the configuration window or changed at run time using the provided API. The maximum bandwidth is limited by the gain-bandwidth of the opamp and is reduced as the gain is increased. The input of the PGA_Inv operates from rail to rail, but the maximum input swing (difference between Vin and Vref) is limited to V_DDA/Gain. The output of the PGA_Inv is class A, and is rail to rail for sufficiently high load resistance.

Required Software: PSoC Creator v1.0 Beta 5 and above

• Interfaces to up to 32 DC-DC power converters
• Measures power converter output voltages and load currents using a DelSig-ADC
• Monitors the health of the power converters generating warnings and faults based on user-defined thresholds
• Support for measuring other auxiliary voltages in the system
• Support 3.3V and 5V chip power supply

General Description

Power Converter Voltage Measurements:

For power converter voltage measurements, the ADC can be configured into single-ended mode (0-4.096 V range or 0-2.048 V range). The ADC can also be configurable into differential mode (±2.048 V range) to support remote sensing of voltages where the remote ground reference is returned to PSoC over a PCB trace. In cases where the analog voltage to be monitored equals or exceeds Vdda or the ADC range, external resistor dividers are recommended to scale the monitored voltages down to an appropriate range.

Power Converter Current Measurements:

For power converter load current measurements, the ADC can be configured into differential mode (+/- 64 mV or +/- 128 mV range) to support voltage measurement across a high-side series shunt resistor on the outputs of the power converters. Firmware APIs convert the measured differential voltage into the equivalent current based on the external resistor component value used. The ADC can also be configured into single-ended mode (0-4.096V range or 0-2.048 V range) to support connection to external current sense amplifiers (CSAs) that convert the differential voltage drop across the shunt resistor into a single ended voltage or to support power converters or hot-swap controllers that integrate similar functionality.

Required Software: PSoC Creator 2.0 Component Pack 3 and above

PSoC Creator Power Monitor Component Video
 

• Programmable flicker-free dimming resolution from 2 to 32 bit
• Two pulse density outputs
• Programmable output signal density
• Serial output bit stream
• Continuous run mode
• User-configurable sequence start value
• Standard or custom polynomials provided for all sequence lengths
• Kill input disables pulse density outputs and forces them low
• Enable input provides synchronized operation with other components
• Reset input allows restart at sequence start value for synchronization with other components
• Terminal Count Output for 8-, 16-, 24-, and 32-bit sequence lengths.

General Description

The Precision Illumination Signal Modulation (PrISM) component uses a linear feedback shift register (LFSR) to generate a pseudo random sequence. The sequence outputs a pseudo random bit stream, as well as up to two user-adjustable pseudo random pulse densities. The pulse densities may range from 0 to 100 percent.

Required Software: PSoC Creator v1.0 Beta 5 and above

• 2 to 768 pixels or symbols
• 1/3, 1/4 and 1/5 bias supported
• 10 to 150 Hz refresh rate
• Integrated bias generation between 2.0 V and 5.2 V with up to 128 digitally controlled bias levels for dynamic contrast control
• Supports both type A (standard) and type B (low power) waveforms
• Pixel state of the display may be inverted for negative image
• 256 bytes of display memory (frame buffer)
• User-defined pixel or symbol map with optional 7-, 14-, or 16-segment character; 5x7 or 5x8 dot matrix; and bar graph calculation routines.
• Supports PSoC 3 ES3 silicon revisions and above.

General Description

The Segment LCD (LCD_Seg) component can directly drive a variety of LCD glass at different voltage levels with multiplex ratios up to 16x. This component provides an easy method of configuring the PSoC device to drive your custom or standard glass. 

Required Software: PSoC Creator v1.0 Beta 5 and above

• SMBus Slave mode
• PMBus Slave mode
• SMBALERT# pin support
• 25 ms Timeout
• Fixed Function (FF) and UDB implementations
• Configurable SM/PM Bus commands
   

General Description

The System Management Bus (SMBus) and Power Management Bus (PMBus) Slave component provides a simple way to add an I2C physical layer interface to a PSoC 3 or PSoC 5 design with either SMBus or PMBus protocol running on top of it.

The SMBus is a two-wire interface with various System Management chips that can communicate with the system host. It uses I2C as a physical layer. The SMBus Slave component implements most of the SMBus Slave device specifications and provides options for configuring the slave device parameters. The slave device can communicate with the SMBus Master using the provided APIs.

The PMBus protocol is a specific implementation of the more generic SMBus protocol. With the PMBus, the component presents all the possible PMBus commands and allows you to select which commands are relevant to your application.

Required Software: PSoC Creator 2.1 Component Pack 4 and above.
 

• Conforms to IEC-60958, AES/EBU, AES3 standards for Linear PCM Audio Transmission
• Sample rate support for clock/128 (up to 192 kHz)
• Configurable audio sample length (8/16/24)
• Channel status bits generator for consumer applications
• DMA support
• Independent left and right channel FIFOs or interleaved stereo FIFOs

General Description

The SPDIF_Tx component provides a simple way to add digital audio output to any design. It formats incoming audio data and metadata to create the S/PDIF bit stream appropriate for optical or coaxial digital audio. The component supports interleaved and separated audio.

Required Software: PSoC Creator v1.0 Beta 5 and above

Features

• 3- to 16-bit data width
• Four SPI operating modes
• Bit Rate up to 18 Mbps

General Description

The SPI Master component provides an industry-standard, 4-wire master SPI interface. It can also provide a 3-wire (bidirectional) SPI interface. Both interfaces support all four SPI operating modes, allowing communication with any SPI slave device. In addition to the standard 8-bit word length, the SPI Master supports a configurable 3- to 16-bit word length for communicating with nonstandard SPI word lengths.     

Required Software: PSoC Creator v1.0 Beta 5 and above 

PSoC Creator SPI Master Component video

• Calculation accuracy 0.01 °C for -200 °C to 850 °C temperature range
• Provides simple API function for resistance to temperature conversion
• Displays Error Vs Temperature graph

General Description

The Resistance Temperature Detector (RTD) Calculator component generates a polynomial approximation for calculating the RTD Temperature in terms of RTD resistance for a PT100, PT500 or PT1000 RTD. Calculation error budget is user-selectable, and determines the order of the polynomial that will be used for the calculation (from 1 to 5). A lower calculation error budget will result in a more computation intensive calculation. For example, a fifth order polynomial will give a more accurate temperature calculation than lower order polynomials, but will take more time for execution. After maximum and minimum temperatures and error budget are selected, the component generates the maximum temperature error, and an error vs. temperature graph for all temperatures in the range, along with an estimate of the number of CPU cycles necessary for calculation using the selected polynomial. Selecting the lowest error budget will choose the highest degree polynomial. For the whole RTD temperature range, -200 °C to 850 °C, the component can provide a maximum error of <0.01 °C using a fifth order polynomial.

Required Software: PSoC Creator 2.1 Component Pack 4 and above
 

• Single or differential connections
• Adjustable between 1 and 64 connections for single AMux, 1 and 32 connections for Differential AMux.
• Software controlled
• Connections may be pins or internal sources
• Multiple simultaneous connections
• Bi-directional (passive)

General Description

The analog multiplexer (AMux) component can be used to connect none, one, or more analog signals to a different common analog signal. The ability to connect more than one analog signal at a time provides cross-bar switch support, which is an extension beyond traditional mux functionality.

Required Software: PSoC Creator v1.0 Beta 5 and above

• Single or differential connections
• Adjustable between 1 and 64 connections for single AMux, 1 and 32 connections for Differential AMux
• Software controlled
• Connections may be pins or internal sources
• No simultaneous connections
• Bidirectional (passive)

General Description

The analog multiplexer sequencer (AMuxSeq) component is used to connect one analog signal at a time to a different common analog signal, by breaking and making connections in hookuporder sequence. The AMuxSeq is primarily used for time division multiplexing.

Required Software: PSoC Creator v1.0 Beta 5 and above

Features

• Supports PSoC 5 and PSoC 5LP devices
• 12-bit resolution at up to 1 msps maximum
• Four power modes
• Selectable resolution and sample rate
• Single-ended or differential input

General Description

The ADC Successive Approximation Register (ADC_SAR) component provides medium-speed (maximum 1-msps sampling), medium-resolution (12 bits maximum), analog-to-digital conversion.

Required Software: PSoC Creator v1.0 Beta 5 and above

• Provides an editor to enter the assembler instructions to configure the DFB block and an assembler that converts the assembly instructions to instruction words.
• Supports simulation of the assembly instructions.
• Supports a code optimization option that provides a mechanism to incorporate up to 128 very large instruction words inside the DFB Code RAM.
• Provides hardware signals such as DMA requests, DSI inputs and outputs, and interrupt lines.
• Supports semaphores to interact with the system software and the option to tie the semaphores to hardware signals.

General Description

The digital filter block (DFB) in PSoC 3 and PSoC 5 can be used as mini DSP processor and allows you to configure the DFB using assembly instructions. The component assembles the instructions entered in the editor and generates the corresponding hex code words, which can be loaded into the DFB. It also includes a simulator, which helps the user to simulate and debug the assembly instructions.

The DFB consists of a programmable 24*24 multiplier/accumulator (MAC), an arithmetic logic unit (ALU), shifter, and various program and data memory to store instructions and data. The DFB runs on the bus clock, and can interface with both CPU and DMA. It can be used to offload the CPU and can speed up arithmetic calculations that involve intensive multiply accumulate operations. Typical operations you can use the DFB component to implement include: vector operations, matrix operations, filtering operations, and signal processing.

• Easy user configuration of filters running on the Digital Filter Block (DFB) available in some PSoC 3, PSoC 5 and PSoC5 LP devices.
• Supports two separate filter channels, each one constructed as a cascade of up to four separately designed stages.
• Multiple FIR and IIR (Biquad) filter methods (including user coefficient entry) give great flexibility
• Final coefficient values can be extracted for further analysis

General Description

The customizer for the Filter component allows you to configure digital filters on one or two data streams passed to the Digital Filter Block (DFB), using DMA, interrupts, or polling to manage data flow. The DFB’s 128 data and coefficient locations are shared as needed between the two filter channels. The customizer reports (but does not set) the minimum bus clock frequency required to execute the filtering within the user-declared sample interval.

This component supports a huge number of use cases. If you encounter something unusual when using it, report it (with a good description of what you did to cause it) to psoc_creator_fb@cypress.com so Cypress can investigate. 

Required Software: PSoC Creator v1.0 Beta 5 and above