Features

• Powerful Harvard Architecture Processor
• Flexible On-Chip Memory
• Complete Development Tools
• Precision, Programmable Clocking
• Programmable Pin Configurations
• Additional System Resources
• For more, see pdf
   

Functional Overview

The enCoRe V LV family of devices are designed to replace multiple traditional low voltage microcontroller system components with one, low cost single chip programmable component. Communication peripherals (I2C/SPI), a fast CPU, Flash program memory, SRAM data memory, and configurable I/O are included in a range of convenient pinouts.

In this application note, we use a CY3660 Development Kit (DVK) to demonstrate wireless data exchange between two enCoRe™ V LV devices each using the WirelessUSB™-LP Radio. The CY3660 DVK includes two enCoRe V LV development boards, each with a WirelessUSB-LP radio. With the PSoC® Designer™ projects attached to this application, we configure one board for data transmission and the second board for data reception.

• Supports Serial Peripheral Interconnect (SPI) Master protocol
• Supports SPI clocking modes 0, 1, 2, and 3
• Programmable interrupt on SPI-done condition
• SPI Slave devices can be independently selected
   

The SPIM User Module is a Serial Peripheral Interconnect Master. It performs full duplex synchronous 8- bit data transfers. SCLK phase, SCLK polarity, and LSB First can be specified to accommodate most SPI clocking modes. Controlled by user supplied software, you can configure the slave select signal to control one or more SPI Slave devices.

The SPI User Module also supports two wire serial devices such as optical mouse sensors that employ an SDIO/SCK interface.

• Implements CapSense® capacitive sensing in the CY8C20xx6A family of PSoC® devices using sigma-delta data conversion.
• Configurable system parameters allow tuning to optimize performance in a broad range of applications.
• Supports up to 36 capacitive sensors and 6 sliders.
• Capable of detecting touches as low as 0.1 pF, that is, detecting a finger is possible through up to 15 mm of glass or 5 mm of plastic.
• High immunity to AC mains noise, other EMI, and power supply noise.
• Supports capacitive sensors configured as independent buttons and/or as dependent arrays to form sliders.
• Effective number of slider elements can double the number of dedicated I/O pins using diplexing technique.
• Supports slider resolution greater than physical pitch through interpolation.
• Shield electrode provided for reliable operation with high parasitic capacitance and/or in the presence of water film.
• Guided sensor and pin assignments using the CSD Wizard.
• The CY8C20045 family does not support sliders.

• 8-bit resolution
• Sample rates up to 100 sps
• Input range depends on CPU Clock
   

The SAADC implements a simple ADC which does not require a Digital Block to operate.

Note:  The SAADC has 8 bits of resolution with 1% error if placed in analog column 0. When placed in analog column 1 the error is 4%.

• Provides a global shadow register for a selected port data register
• Generates a set of macros for port pin manipulation
• Prevents corruption of GPIO pin settings during CPU control of GPIO
• Cooperates with other user modules that allocate shadow registers.
   

• Industry standard Philips I2C bus compatible interface.
• Enables you to reprogram a PSoC device using the I2C system bus instead of in-system programming pins.

The I2C Bootloader User Module implements a bootloader that can reprogram the PSoC device over the I2C interface. The PSoC device already gives an in-system serial programming interface (ISSP) that allows downloading new code into the device. However, the bootloader allows a code update to occur through an industry standard communication interface, such as I2C.

Features and Overview

• Protocol stack that implements node functionality to support a wireless star network consisting of one hub and up to 250 nodes
• Provides reliable two way communication between a hub and node
• Dynamic data rate (up to 1 Mbps) and output power according to the channel noise level and packet loss rate
• Operates in the unlicensed worldwide Industrial, Scientific, and Medical (ISM) band (2.400–2.483GHz)

The CyFi™ Star Network Protocol Stack (CYFISNP) User Module is designed to address up to 250 general purpose nodes; it provides reliable two way communication between the hub and node(s). The hub is assumed to be wall powered, while the nodes may be either wall powered or powered by an alkaline (low impedance) or coin-cell (high impedance) battery.

• Industry standard Philips I²C-bus compatible interface (version 2.1)
• Only two pins (SDA and SCL) required to interface several slave I²C devices
• Standard mode data supports rate of 100 kbits/s
• High level API requires minimal user programming
• Low level API provided for flexibility

• Uses the industry standard Hitachi HD44780 LCD display driver chip protocol
• Requires only seven I/O pins
• Routines provided to print RAM or ROM strings
• Routines provided to print numbers
• Routines provided to display horizontal and vertical bar graphs
• Uses a single I/O port
   

The Character LCD User Module is a set of library routines that writes text strings and formatted numbers to a common two- or four-line LCD module. Vertical and horizontal bar graphs are supported, using the character graphics feature of these LCD modules. This module was developed specifically for the industry standard Hitachi HD44780 two-line by 16 character LCD display driver chip, but will work for many other four-line displays. This library uses the 4-bit interface mode to limit the number of I/O pins required.

• Supports Serial Peripheral Interconnect (SPI) Master protocol.
• Supports SPI clocking modes 0, 1, 2, and 3.
• Selectable input sources for clock and MISO.
• Selectable output routing for MOSI and SCLK.
• Programmable interrupt on SPI done condition.
• SPI Slave devices are independently selected.
   

The SPIM User Module is a Serial Peripheral Interconnect Master. It performs full duplex synchronous 8- bit data transfers. SCLK phase, SCLK polarity, and LSB First are available to accommodate most SPI clocking modes. Controlled by user supplied software, the slave select signal is able to control one or more SPI Slave devices. The SPIM PSoC block has selectable routing for the input and output signals and programmable interrupt driven control.

• Supports Serial Peripheral Interconnect (SPI) slave protocol.
• Supports protocol modes 0, 1, 2, and 3.
• Selectable input sources for MOSI, SCLK, and ~SS.
• Selectable output routing for MISO.
• Programmable interrupt on SPI done condition.
• SS may be firmware controlled.
   

The SPIS User Module is a Serial Peripheral Interconnect Slave (SPIS). It performs full duplex synchronous 8 bit data transfers. You can specify SCLK phase, SCLK polarity, and LSB First to accommodate most SPI protocols. The SPIS PSoC block has selectable routing for the input and output signals and programmable interrupt driven control. Application Programming Interface (API) firmware provides a high level programming interface for either assembly or C application software.

• Industry standard Philips I2C bus compatible interface
• Emulates common I2C EEPROM interface
• Only two pins (SDA and SCL) required to interface to I2C bus
• Standard data rate of 100/400 kbps
• High level API requires minimal user programming
   

The EzI2Cs user module implements an I2C register-based slave device. The I2C bus is an industry standard, two wire hardware interface developed by Philips® (now NXP).The master initiates all communication on the I2C bus and supplies the clock for all slave devices. The EzI2Cs user module supports the standard mode with speeds up to 400 kbps. No digital or analog PSoC blocks are consumed with this module. The EzI2Cs user module is compatible with multiple devices on the same bus.

• 8 to 10-bit resolution
• Sample rate up to 11.71 ksps (10-bit resolution)
• Sample rate up to 46.875 ksps (8-bit resolution)
• Input range up to reference voltage
• Internal clock divider
   

The ADCINC User Module is part of the System Performance Controller (SPC). SPC is a modular system for product performance compensation over process, voltage, and temperature variations. The system is based on the M8C microcontroller. The heart of the SPC is the microcontroller core, temperature sensor, and the SPC system bus.
 

• 16-bit programmable countdown timer
• One shot countdown option where the period is not reloaded on Terminal Count
• Interrupt occurs on Terminal Count
• Uses the internal 32 kHz clock or the CPU clock
   

The user module is a 16-bit programmable timer with interrupt call back. It is clocked by the internal 32 kHz clock or the CPU clock.

• Industry standard Philips I2C bus compatible interface
• Slave only operation
• Only two pins (SDA and SCL) required to interface to I2C bus
• Standard data rate of 100/400 kbits/s, also supports 50 kbits/s
• High level API requires minimal user programming
• 7-bit addressing mode
   

The I2C Hardware User Module implements an I2C Slave device in firmware. The I2C bus is an industry standard, two wire hardware interface developed by Philips®. The master initiates all communication on the I2C bus and supplies the clock for all slave devices. The I2CHW User Module supports the standard mode with speeds up to 400 kbits/s and is compatible with other slave devices on the same bus.

Features and Overview

• Full byte-oriented EEPROM emulation
• Abstracts block-oriented Flash architecture
• Efficient use of memory
   

The EEPROM User Module emulates an EEPROM device within the Flash memory of the PSoC device. The EEPROM device can be defined to start at any Flash block boundary, with a byte length from 1 to the remainder of Flash memory space. The API enables the user to read and write 1 to N bytes at a time.

• Full byte-oriented EEPROM emulation
• Abstracts block-oriented flash architecture
• Efficient use of memory

• 12-bit programmable interval timer
• Source clock rates up to 24 MHz
• Automatic reload of period on terminal count

Functional Description

The 12-Bit Programmable Interval Timer User Module provides convenient access to the Programmable Interval Timer feature of the enCoRe II.

• 7/8-bit software serial transmitter
• Data framing consists of start, optional parity, and one or two stop bits
• RS-232 serial-data compatible format with optional parity
   

The TX8SW User Module is an 7- or 8-bit RS-232 data-format compliant serial transmitter. The data transmitted is framed with a leading start bit and a final one or two stop bits. Transmitter firmware is used to start and stop device and control transmission of complex structures like strings, HEX value representations, and so on.

• AutoTuning algorithms optimize the operational parameters at runtime based on the parasitic capacitance of each sensor.
• Scans 1 to 36 capacitive sensors.
• Capable of detecting 0.1 pF touch with parasitic sensor capacitance (Cp) up to 50 pF as long as layout guidelines of are followed.
• Sensing possible through up to a 15 mm glass overlay.
• High immunity to AC mains noise, other EMI, and power supply voltage changes.
• Supports capacitive sensors configured as independent buttons, proximity sensors and/or as dependent arrays to form sliders. Sliders and proximity sensors not fully supported in this beta version.
• Effective number of slider elements can double the number of dedicated IO pins using diplexing technique.
• Supports slider resolution greater than physical pitch through interpolation.
• Touchpads can be implemented as pairs of interwoven orthogonal sliders.
• Shield electrode provides for reliable operation with high parasitic capacitance and/or in the presence of water film.
• Guided sensor and pin assignments using the CSDAUTO Wizard.
• PC GUI application support for raw data monitoring in real-time.
   

The CSDAUTO (Autotuning CapSense® using a Sigma-Delta Modulator) User Module provides capacitance sensing using the switched capacitor technique with a sigma-delta modulator to convert the sensor capacitance into digital code.

Features and Overview

• 12-bit interval timer
• Input clock: enCoRe II TCAPCLK Clock
• Provides a 1 Millisecond interrupt with the TCAPCLK Divider = 6 (24 MHz/6 = 4 MHz)
• Source clock rates up to 24 MHz
• Designed to use with the USB User Module for USB Suspend handling

Functional Description

The MSTIMER User Module provides convenient access to the "1024 microsecond" feature of the enCoRe II.

Features and Overview

• PS/2 Device Interface
• Selectable command sets for mouse or keyboard applications
• Custom feature unlock mechanism
• Integrated with the USB SIE for combo USB-PS/2 applications

Functional Description

The PS/2 Device User Module supports a standard PS/2 keyboard or a standard PS/2 mouse. A PS/2 connector is a 6-pin mini-DIN connector. It can be used for connecting either a keyboard or a mouse with a compatible computer. You must choose to support either a keyboard or a mouse with the PS/2 Device User Module. Choose to support either the keyboard command set or the mouse command set when you select the user module. If you wish to change from one to the other after the user module is selected, right click on the user module icon and select User Module Selection Options. By convention, connectors that support keyboards are color coded purple, and ports that support mice are color coded green. With the addition of the USB Device User Module, you can create a single device that supports a USB and PS/2 combination device.

Features

• enCoRe™ II low-voltage (enCoRe II LV) – enhanced component reduction
  • Internal crystalless oscillator with support for optional external clock or external crystal or resonator
  • Configurable I/O for real world interface without external components
• Enhanced 8-bit microcontroller
  • Harvard architecture
  • M8C CPU speed up to 12 MHz or sourced by an external crystal, resonator, or clock signal
• Internal memory
  • 256 bytes of random access memory (RAM)
  • 8 KB of flash including electrically erasable read only memory (EEROM) emulation
• FOr more, see pdf
   

Introduction

The enCoRe II LV family brings the features and benefits of the enCoRe II to non-USB applications. The enCoRe II family has an integrated oscillator that eliminates the external crystal or resonator, reducing overall cost. Other external components, such as wakeup circuitry, are also integrated into this chip.

Features

• Powerful Harvard-architecture processor
• Configurable peripherals
• Flexible on-chip memory
• Complete development tools
• Precision, programmable clocking
• Programmable pin configurations
• Versatile analog mux
• Additional system resources
• For more, see pdf

enCoRe III Low Voltage Functional Overview

The enCoRe III low voltage (enCoRe III LV) CY7C603xx device is based on the flexible PSoC® architecture. This supports a simple set of peripherals that can be configured to match the needs of each application. Additionally, a fast CPU, flash program memory, SRAM data memory, and configurable IO are included in a range of convenient pinouts.

This application note discusses the necessary information for you to use a WirelessUSB(TM) LP radio in a product intended for the Japanese market. WirelessUSB based systems require a certification to market the product to make certain that it meets international regulations and national laws. This application note serves as a reference point in selecting WirelessUSB LP Radio for your application needs. The use of a Cypress radio chip and its suitability for Japanese product development is demonstrated by providing the compliance data on a reference development kit.

Wireless products are now found in abundance, all around us today, and their usage continues to rapidly expand. This application note introduces the Cypress CYRF8935 device and a sample PCB design. The appendix section guides you on antenna selection process.

When product designers use reference designs as a basis for their own projects, they typically modify or enhance the original designs. Unfortunately, these modifications can cause a considerable decline in performance. This application note describes parameters that can affect WirelessUSB system performance. It also explains how to evaluate these parameters within your own wireless product design.

In-Circuit Emulation (ICE) Pod Kit for Debugging 32-pin QFN enCoRe V (CY7C64343/45) Devices

• One (1) 64345Q Pod
• One (1) Flexcable
• Two (2) 32QFN Feet

• One (1) 60445Q Pod
• One (1) Flexcable
• Two (2) 32QFN Feet

Hardware Description:

The CY3250-60445QFN emulation POD is designed to work with the PSoC ICE Cube (In-Circuit Emulator), which can be purchased separately as a part of the CY3215-DK kit available from the Cypress Online Store at www.cypress.com.

• Two (2) 64315Q Pod

Hardware Description:

The ICE pod provides the interconnection between the CY3215-DK In-Circuit Emulator via a flex cable and the target device in a prototype system or PCB via device-specific pod feet. Pod feet sold separately.

• Two (2) 64345Q Pod

• Two (2) 60445Q Pod

Hardware Description:

The ICE pod provides the interconnection between the CY3215-DK In-Circuit Emulator via a flex cable and the target device in a prototype system or PCB via device-specific pod feet. Pod feet sold separately.

• One (1) 64315Q Pod
• One (1) Flexcable
• Two (2) 16QFN Feet

Hardware Description:

The CY3250-64315QFN emulation POD is designed to work with the PSoC ICE Cube (In-Circuit Emulator), which can be purchased separately as a part of the CY3215-DK kit available from the Cypress Online Store at www.cypress.com.

Replacement In-Circuit Emulation (ICE) Pods (2) for Debugging 48-pin QFN CY7C60455/56 Device




CY3250-60455QFN-POD Kit Contents:

• Two (2) 60455Q Pod
   

Hardware Description:

The ICE pod provides the interconnection between the CY3215-DK In-Circuit Emulator via a flex cable and the target device in a prototype system or PCB via device-specific pod feet. Pod feet sold separately.

• Two (2) 64355Q Pod
   

Hardware Description:

The ICE pod provides the interconnection between the CY3215-DK In-Circuit Emulator via a flex cable and the target device in a prototype system or PCB via device-specific pod feet. Pod feet sold separately.

SAN JOSE, Calif., June 20, 2006 - Cypress Semiconductor Corp. (NYSE: CY) today announced that Darfon Electronics Corporation's new generation of wireless mice will use Cypress's WirelessUSB™ LP 2.4-GHz radio system-on-chip and enCoRe™ II flash microcontrollers. The mice will be marketed under the Elecom and BenQ brands. Darfon employed Cypress's WirelessUSB LS and enCoRe USB devices for its previous generation of wireless mice for Elecom and BenQ. 

Darfon's innovative and award-winning wireless mice are recognized for their compact designs that allow users to store the receiver inside a smart storage compartment of the mouse while not in use. Darfon's newest wireless mice leverage WirelessUSB LP's low-power consumption for longer battery life and its robust interference immunity for excellent performance.

"The WirelessUSB LP device helped us deliver new mice with robust 2.4-GHz connectivity and low power consumption for extended battery life," said Josh Tsai, product marketing director at Darfon. "In addition, Cypress's whole product one-stop shop provided a complete reference design, development tools, and outstanding applications and technical support, allowing us to reduce the design cycle for these innovative, convenient mice, which are ideal for on-the-go end users."

"We are pleased that Darfon has again selected Cypress's WirelessUSB and enCoRe technologies to deliver end-to-end connectivity for their sleek, high-performance wireless mice," said Matt Branda, senior product marketing manager of Cypress's Human Interface Device Business Unit. "This design win is evidence that WirelessUSB LP offers the right combination of best-in-class interference immunity and low-power for next-generation wireless peripherals."

About WirelessUSB LP
Cypress's WirelessUSB LP offers an unparalleled feature set to enable superior interference immunity, low bill-of-materials (BOM) costs, higher data rate applications, and faster time-to-market for keyboards, mice, gaming devices, presenter tools, and remotes, as well as other simple, multi-point-to-point wireless applications. Featuring a highly integrated radio transceiver plus digital baseband on a single chip, it operates between 1.8 and 3.6 volts, using advanced power-saving techniques to extend battery life in devices such as wireless mice. WirelessUSB LP uses Cypress's patented frequency agile Direct Sequence Spread Spectrum (DSSS) technology to offer best-in-class interference immunity for a 2.4-GHz radio system. This combination of low power consumption, interference immunity and low cost make it ideal for wireless HID applications. A photo of Cypress's WirelessUSB LP can be downloaded at: www.cypress.com/WUSBLPphoto."

About the enCoRe Family
Cypress's enCoRe USB technology features a breakthrough crystal-less oscillator. By integrating the oscillator on-chip, an external crystal or resonator is no longer needed. Cypress has also integrated other external components commonly found in low-speed USB applications, including pull-up resistors, wake-up circuitry, and a 3.3V regulator. This integration results in shorter development cycles and lower system costs. In addition, the enCoRe family offers a Flash-based design that enables storage of wireless binding parameters as well as in-system reprogrammability and EEPROM emulation.

About Darfon
Established in 1997, Darfon Electronics Corporation designs, manufactures and markets human interface devices, power devices, and multi-layer components that enable people to effectively work, play, and communicate in the digital world. Darfon employs 6,600 people supporting customers worldwide. For more information, please visit www.darfon.com.tw.

About Cypress
Cypress solutions perform: consumer, computation, data communications, automotive, industrial, and solar." Leveraging proprietary silicon processes, Cypress's product portfolio includes a broad selection of wired and wireless USB devices, CMOS image sensors, timing solutions, specialty memories, high-bandwidth synchronous and micropower memory products, optical solutions and reconfigurable mixed-signal arrays. Cypress trades on the NYSE under the ticker symbol CY. Visit us at www.cypress.com.

# # #

Cypress and the Cypress logo are registered trademarks of Cypress Semiconductor Corporation. WirelessUSB and enCoRe are trademarks of Cypress.  All other trademarks are the property of their respective owners.

Following is the list of Kits tested and their respective web links

1. CY3655-EXT :Encore-II Development Kit

             weblink: www.cypress.com/go/cy3655-ext

Download CY3655-EXT_Firmware_PSOC_Designer_5_2.zip

2. CY3631 :Wireless Manufacturing Test Kit

             weblink: www.cypress.com/go/cy3631

Download CY3631_WirelessUSB_MTK_Firmware_PSOC_Designer_5_2.zip

3. CY4623:EncoreII Mouse Reference Design

             weblink: www.cypress.com/go/cy4623

Download CY4623_RDK_Firmware_PD_5_2.zip

4. CY4672:PROC Lp Keyboard/Mouse Reference Design

             weblink: www.cypress.com/go/cy4672

Download CY4672_Firmware_Examples_PSOC_Designer_5_2.zip

5.CY4638:VOIP Demo kit

             weblink: www.cypress.com/go/cy4638

Download CY4638_Firmware_Examples_PSOC_Designer_5_2.zip

6.CY3660:Encore V LV Development Kit

             weblink: www.cypress.com/go/cy3660

Download CY3660_Firmware_Examples_PSOC_Designer_5_2.zip

Note:Please download and install PSOC designer 5.2 prior to testing the firmware examples.The weblink to PSoC designer is mentioned on above listed Kit weblinks.

• One (1) 60455Q Pod
• One (1) Flexcable
• Two (2) 48QFN Feet
   

Hardware Description:
The CY3250-60455QFN emulation POD is designed to work with the PSoC ICE Cube (In-Circuit Emulator), which can be purchased separately as a part of the CY3215-DK kit available from the Cypress Online Store at www.cypress.com.

In-Circuit Emulation (ICE) Pod Kit for Debugging 48-pin QFN enCoRe V (CY7C64355/56) Devices




CY3250-64355QFN Kit Contents:

• One (1) 64355Q Pod
• One (1) Flexcable
• Two (2) 48QFN Feet

Hardware Description:

The Modular Programmer features include

• Programming support for some PSoC, enCoRe II, Wireless enCoRe II and enCoRe III devices in PDIP packages.
• Programming support for some PSoC, enCoRe II, Wireless enCoRe II and enCoRe III devices in surface mount packages with purchase of an appropriate surface mount adapter socket (sold separately).
• Support for programming from:
  • ICE-Cube
  • Miniprog1
  • Miniprog3
• Modular Programmer supports many other Cypress devices by obtaining the appropriate adapter card and socket adapter.

The CY3216 Module Programmer Kit is included in the larger CY3655 kit: Click Here

For more information please see the kit documentation listed in the table below.

 If this modified circuit is not desirable and you want to program the PRoC without isolating the RF section, you can use Miniprog 3. Miniprog 3 supports Power cycle programming at 3.3V. Since the RF section is tolerant to voltages below 3.6V, 3.3 V programming by Miniprog 3 is acceptable.

To fix this, please add "ljmp Sleep_ISR" to line 131 of BOOT.ASM, or overwrite the existing BOOT.ASM with the attached one.

Hence, the radio chip needs some check over the current.

Whereas CYWUSB6935 is a Wireless USB LR 2.4-GHz DSSS Radio and needs an external microcontroller which can configure and operate on the radio through an SPI interface.

General note: Typically, these pins are nRESET, nPD, IRQ, nSS, SCK, MOSI, and MISO.

Open file "radio.asm" under directory "...\Firmware\Source Code\RDK Bridge"

1. Find the following string "switch_rx:"
2. Insert the following statement "CALL delay200us" after the CALL SPI_write

Your final firmware patch should similar to:

switch_rx:

MOV A, REG_CONTROL
MOV [reg_addr], A
MOV A, (bRX_ENABLE | bAUTO_SYNTH_COUNT)
MOV [reg_data], A
CALL SPI_write
CALL delay200us

Attached is the entire v1.31 build including this patch to fix read RSSI firmware logic.

Note:  Read RSSI firmware logic issue only applies to v1.3 (and v1.31) builds.

CY4632 WirelessUSB KBM RDK

For enCoRe (USB Controller) development tools:

CY3654        : enCoRe Platform Board - ICE
CY3654-P05  : enCoRe Personality Board

CY3083-07    : 16/18-pin DIP Adapter 
CY3083-08    : 24-pin SOIC Adapter 
CY3083-DP48 : DIP Base HiLo Adapter 
CY3649         : Standalone HiLo Programmer

CY3083-SC28 : 28-pin Base HiLo Adapter

For Windows Software application development tools: Microsoft Visual Studio .NET

A fully high-impedance input requires that the following configuration to be used:

Open Drain configuration (by setting appropriate values in PRTxDM0 and PRTxDM1) along with the corresponding data bit (by setting appropriate value in  PRTxDR ) = 1. This disables both the NMOS and PMOS in the GPIO cell and puts it in a true Hi-Z mode.

For example, the following setting will make the pin P2[5] as high Z:

PRT2DM1 = 0x20;

PRT2DM0 = 0x20;

and PRT2DR = 0x20;

An application uses P0[0] as a sourcing LED output, and P0[1] as a pulled up input for a normally open switch connected to ground. After setting the drive mode registers for port 0, the firmware initializes the LED to off and enables the input with the following C statement.

PRT0DR = 0x02;
 

Without a shadow, register, the firmware toggles the LED by the following C statement.
 

PRT0DR ^= 0x01;
 

On the initial LED toggle operation, the value read from PRT0DR is 0x00 if the switch is closed, and 0x02 if the switch is open. Performing the XOR operation to toggle the LED results in 0x01 (0x00 XOR 0x01) if the switch is closed but 0x03 (0x02 XOR 0x01) if the switch is open when the initial toggle occurs. Toggling the LED when the switch is closed causes P0[1] to be driven to 0V internally. When the switch is opened, the value read from PRT0DR is still 0x01 because the voltage on P0[1] is still 0V. The switch input has been inadvertently disabled.
The solution is to always manipulate the shadow register first, then copy the shadow register value into the port data register. The following C statements initialize the LED output and the switch input:

Port0_Data_Shade = 0x02;
PRT0DR = Port0_Data_Shade;

The following code toggles the LED without affecting the switch input:

Port0_Data_Shade ^= 0x01;
PRT0DR = Port0_Data_Shade;

Regardless of whether the switch is open or closed, 0x03 (0x02 XOR 0x01) is written to the port data register on the initial toggle operation because the logical operation was performed using the shadow register (0x02 regardless of whether button is open or closed) as input rather than the port data register (0x00 when the switch is closed, and 0x02 when the switch is open).

1. All GPIO pins must be set to outputs and driven low except P1.0 and P1.1 .
2. P1.0 and P1.1 should be configured and inputs with pull-ups enabled.
3. Make sure the 32-kHz oscillator clock is not selected as clock source to ITMRCLK, TCAPCLK, and not even as clock output source onto P01_CLKOUT pin.

Advantages

■ Easiest method with highest chance of successful user

experience. True plug-and-play. It just works out of the box

■ Least risk of technical support calls, therefore smallest

support cost

■ No impact to power consumption in battery powered systems

Disadvantages

■ Risk of cross-binding on the manufacturing line

■ May require additional manufacturing steps, which adds

a small amount of time and cost

■ Not suitable for systems where additional devices can be

sold independent of the bridge

Cypress WirelessUSB systems. It is straight forward and easy to use.

Description

Each side of the system (device and bridge) has a specific button used to initiate bind. In this scenario there is no required order in which to press the button. When the user presses the bind button on the bridge it is placed into a listening mode, ready to receive bind requests. When the button is pressed on the device side it begins continuous transmission of bind requests. Both sides have a timeout of about 20 seconds allowing ample time to press both buttons in the case that one is not in an easily accessible location. Furthermore, multiple channels are used to increase the chance of a successful bind. Both the bridge and the device must rotate through the defined subset of channels. A reduced output Power Amplifier (PA) level is used, which slightly limits the range but does not tightly constrain it. When the bridge receives the request it responds with the MID used to seed the network parameters algorithm at which point the sequence is complete.

Advantages

■ Simple system resulting in good user experience. It is reasonably well understood by most users because it is commonly used.

■ Minimal risk of technical support calls

■ Adequate time-out ensures users can get both bind buttons pressed even when one device is not quickly accessible. Buttons can be pressed in any order

Disadvantages

■ Small cost impact for button hardware on both sides

■ Ties up the system when the bind button is pressed due to the timeout required. This can be problematic in the

case of inadvertent bind button presses

■ Inexperienced wireless users may not understand the bind requirements and the need to press buttons before using the device for the first time—small potential for support calls

Description: Every time power is applied to the unit with power-on bind implemented, it will enter a bind sequence. In some cases, such as those when power is infrequently removed, this will not appear substantially different from what has been discussed under 2-way button bind. In cases where it is likely for  power to be cycled frequently this method is either not acceptable or there will have to be some changes to prevent it from becoming intrusive to normal device operation. The likely change is to reduce the timeout as described above. Power-up bind is typically implemented on one side only, with the other side using a button. Generally the timeout will also be kept small. It is possible to use power-up bind with a long timeout if power is rarely cycled. Examples are keyboard and mice for desktop users (Cypress battery life is typically a year or more), sensors in a building control network, or bridges built into some embedded systems. Obviously there are multiple combinations of power-up on one side or the other, or both, and short or long timeouts. The system architect must carefully consider the behavior that the user will encounter to determine if power-up bind choices are acceptable.

Example 1: Power-up bind on USB bridge, button bind on device. The bridge, since it is USB based, will see frequent power cycles when it is removed from the PC, or when the PC shuts down or hibernates, therefore it will have a short timeout of ~1 second. This is generally not noticeable when compared with the USB enumeration process. The device will use a standard button. To bind, the button on the device is pressed first, and then the bridge is inserted into the USB port. A bind channel subset and reduced PA are also used to generally increase robustness.

Example 2: Power-up bind on building sensor, button on bridge Sensors would typically have batteries inserted once every few years. A long timeout on the device side is used so that the basic 2-way button bind behavior is preserved. The long timeout would not be intrusive to the device operation. The user can start the bind process on either side: press the button on the bridge first and then insert batteries into the sensor, or the reverse. A bind channel subset is used for robustness, and a higher PA is used in case the bridge is a substantial distance away.

Example 3: Power-up bind on mouse/keyboard, button on bridge.This is somewhat less likely, but presents an opportunity to save cost by removing the buttons on the mouse and keyboard. Those that are not typically powered down can probably use the method described in Example 2. Others, particularly those intended for laptop users, have on/off switches to prevent inadvertent activation during transit. This power-up bind method employs a very brief bind sequence on power-up of the device (1 second or less) and a standard button on the bridge with a long timeout. For general use the  ~1 second timeout should be short enough that it is not inconvenient when powering up the product, however it does slightly increase the power consumption of the device in cases where power may be cycled frequently. To bind devices the bridge must initiate the bind process, then batteries are inserted into the mouse or keyboard, or the power switch is cycled. If both devices are being bound the process is repeated for each one.

Advantages

■ Using power on to initiate bind on the device side can eliminate the need for one or more buttons, thus saving

cost.

Disadvantages

■ This process is not necessarily intuitive for the user, therefore it needs to be described in user documentation (which users do not always read).

■ There is a slight potential for increased technical support calls for users who do not understand the power-on behavior (Short timeouts require sequencing. Long timeouts make the device appear inoperable until the timeout is

over).

■ It potentially increases power consumption since the process repeats whenever power is cycled

Solution”, but is also activated by ‘kissing’ the units—bringing the device in close proximity to the bridge. Note that KISSBind does not necessarily replace other binding methods. It can coexist with one of the manual bind processes described above, thus providing enhanced functionality.

Description

The bridge can support KISSBind when it is just listening for traffic as part of its normal operation. On the device side there are two situations where it will enter a KISSBind mode. The first is when it is first powered up without ever having been bound. The second is if it has repeatedly failed to get a response from its bridge. If it does not get acknowledgements and cannot locate the bridge on another channel then it will attempt one KISSBind sequence. If that also fails it will go to sleep. When next awakened it will go through the entire process again until it succeeds somewhere along the way.

The first thing to consider is that there is overhead associated with each packet. Exactly how much varies with a number of the configuration options available with WirelessUSB. Once these options are selected, you can expect the overhead to be consistent regardless of the size of the packet. Therefore, it is generally more efficient to transfer larger packets.
The next thing to consider is the impact of bit error rate (BER). In a given environment with a fixed set of configuration options there is a probability that any given bit may be corrupted when it is transmitted. At the lowest level is the probability of a DSSS chip being corrupted. The tolerance thresholds manage this to some extent, but with a set number of chips making up each bit you can still calculate a theoretical probability of an actual data bit being corrupted. This probability is the same for every bit; therefore, the more bits that are sent the greater the probability that any error occurs in the packet.

WirelessUSB LP does employ a CRC mechanism to help detect errors, but there is no a built-in error correction capability. Although error correction could be added in software, there may also be a packet size penalty to pay for that. For the moment, only consider that if an error occurs, it is necessary to retry sending the packet again if accurate delivery of data is essential.
Thus, there is a conflict. Larger packets are more efficient, but they may also be subject to a higher probability of failure and require retransmission, therefore increasing overhead in another way. Finding the critical point where the balance shifts one way or the other may require experimentation under the conditions required for the application.
There is one final consideration when dealing with larger packet sizes. Keep in mind that WirelessUSB LP has a 16 byte data buffer. This is significant particularly for battery powered devices that need to minimize power. For packet lengths up to 16 bytes it is possible to sleep the microcontroller after the packet is initiated because the radio’s Auto Transaction Sequencer (ATS) can manage the transmission without microcontroller intervention. For packets lager than 16 bytes it is necessary for the microcontroller to be awake at least periodically to manage buffer over- or under-flow conditions. Therefore, it might be beneficial to break large packets into chunks less than or equal to 16 bytes

Question: 

Repsonse: Binding is the mechanism by which a network is created or by which new devices are added into an existing network. Binding can be achieved in many different ways. Examples of binding options include:
■ Binding in the manufacturing process, such as through use of special test software/hardware
■ Binding that occurs as a result of a user action, such as pressing buttons
■ Binding that occurs upon the power up sequence of a device
■ Binding that can occur in a dynamic or ad-hoc basis, such as whenever a device comes in proximity of a network
■ Completely manual binding, such as selection of the channel through a switch, or entering parameters via a
software interface.

SAN JOSE, Calif., February 22, 2005 - Cypress Semiconductor Corp. (NYSE:CY), the market share leader in USB, today introduced a new family of low-speed USB microcontrollers targeting PC human input devices, including keyboards, mice and wireless dongles.  Based on Cypress's popular "M8" microcontroller architecture, the enCoRe(TM) II (enhanced Component Reduction) family offers a flash-based design that enables storage of wireless binding parameters as well as in-system reprogrammability. The new family also adds reduced power consumption and enhanced CPU capabilities.

Cypress's enCoRe USB technology features a breakthrough crystalless oscillator. By integrating the oscillator on-chip, an external crystal or resonator is no longer needed. Cypress has also integrated other external components commonly found in low-speed USB applications, including pull-up resistors, wake-up circuitry, and a 3.3V regulator. This integration results in shorter development cycles and lower system costs.

"As the worldwide leader in USB technology, customers expect Cypress to continually deliver value-added solutions," said Trevor Davis, director of marketing for Cypress's Consumer and Computation Division. "The enCoRe II products offer important new features while meeting the low-cost requirements of this competitive market."

The enCoRe-II family includes three lines of products:

·  The CY7C639xx line is the first to bring Cypress's enhanced component reduction technologies to keyboard designs.  The chips are offered in 40-pin PDIP and 28-/48-pin SSOP packages, and priced starting at $1.30 in 100,000-unit quantities.

·  The CY7C638xx line of enCoRe II controllers is targeted for high-end optical mice and wireless dongles.  The devices are offered in PDIP, SOIC and QSOP packages, with pricing starting at $0.90 each in 100,000-unit quantities. 

·  The CY7C633xx products target low-end optical and optomechanical mice.  Available in 16-pin PDIP and SOIC packages, the devices are priced starting at just $0.85 in volume.

All of the devices are sampling now with production availability in April of this year. Cypress is also providing low-cost manufacturing chip-on-board support for high-volume enCoRe II products.  A low voltage, low power non-USB version of the enCoRe-II microcontroller targeting wireless applications will be available later this year.

Cypress is the world's leading supplier of USB controllers with more than one quarter of a billion units shipped worldwide. 

Photo
A high resolution photo of the EncoreII is available on the cypress website at:
http://www.cypress.com/prphoto/encoreII

About Cypress
Cypress Semiconductor Corp." (NYSE: CY) provides high-performance solutions for personal, network access, enterprise, metro switch and core communications system applications. Leveraging its process and system-level expertise, Cypress makes industry-leading physical layer devices, framers and network search engines, along with a broad portfolio of high-bandwidth memories, USB devices, timing technology solutions and reconfigurable mixed-signal arrays. More information about Cypress is accessible online at www.cypress.com."

# # #

Cypress and the Cypress logo are registered trademarks of Cypress Semiconductor Corporation. "enCoRe" is a trademark of Cypress. All other trademarks are the property of their respective owners.

1. Go to www.cypress.com.  On the top right, you will see a “Keyword / Part Number” search box (adjacent to “Contact Us.”) 

2. Select the “Part Number” tab above this text box.

3. Type the exact part number, for example CY8C29466-12PVXE.

4. The part number will be listed in the search results page.

5. Click on the part number link (1st column starting from the left). This will open a new web page.

Moisture Sensitivity Level (MSL) can be found by clicking the “Quality & Pb-free Data” link on the top, or by just scrolling down to the Quality & Pb-free Data” section about half way down the page.

All other Quality information for this part number (e.g., RoHS compliance, Lead/Ball Finish, Qualification Reports, IPC reports) can also be found on this web page. 

In case of any questions, or if the information is not available for a particular part number, please create a support case at www.cypress.com/support

If you do not know the Cypress part number: 

1. Go to www.cypress.com.  Browse the different products (“Products” tab on the top navigation menu) by family.

2. Once you choose the relevant product family (e.g., “Clocks and Buffers->Clock Distribution,” “Memory->FIFOs”), scroll down the particular page to get to the “Parametric Product Selector.”

3. Use this tool to find the part number by function/feature, and click on the part number you are interested in. This will lead you directly to step # 5 above.

1. Deep sleep – Drive Mode Strong – Logic level High
2. Normal Sleep – Drive Mode Strong – Logic level – retains state based on input (depending on toggle, delay off etc.,)
3. Sensor Disabled or Sensor did not pass the Failure Mode Analysis – Drive mode Strong – 5 ms active low pulse on POR and later logic level high (see datasheet for more info)

Add the following line after the radio is initialised. RadioGetRssi() API returns the value of RSSI.

// Insert below code

BYTE rssi;

rssi =  RadioGetRssi();  //get rssi

Display the contents on an LCD. Please find the attached code example which does the same (Look for the above lines in main.c ).

asm (“mov A, 05”);

For more info on inline assembly, refer the ‘C Language User Guide’ in the Help >> Documentation menu in PSoC Designer.

First location at: Tools->Options->Build->Compiler
Second location at: Project->Settings->Build->Compiler

See the attached Hirose20PinDescription.jpg file for the pin description of this connector.

The schematic of CY3250 flex cable can be viewed at this link:- http://www.cypress.com/?docID=2975

These connections can also be verified by checking the continuity between pin nos. 4,5,8,9,12,13,16,17 as all of them are grounded. 

Voltage:-5 to 9V

Current:- 1 to 2 A

Connector:- P5 style jack. 

This problem may be because of slow internet connection.

The workaround is to use ISO file of the Designer, it can be downloaded by clicking on "PSoC Designer" under "Software" from our website.

After downloading the ISO file, burn it on a CD and this CD can be used for installing Designer without the need of internet connection.

Answer: The NSE part decoder is attached below.